ETC TMP90C441N

TOSHIBA
TLCS-90 Series
TMP90C441
CMOS 8–Bit Microcontrollers
(2)
TMP90C441N/TMP90C441F
(3)
(4)
1. Outline and Characteristics
The TMP90C441 is a high-speed advanced 8-bit microcontroller
applicable to a variety of equipment.
With its 8-bit CPU, A/D converter, multi-function timer/
event counter and general-purpose serial interface integrated
into a single CMOS chip, the TMP90C441 allows the expansion
of external memories for programs (up to 64K byte) and data
(1M byte).
The TMP90C441N is a 64-pin shrink DIP product.
(SDIP64-P750)
The TMP90C441F is a 64-pin flat package product.
(QFP64-P1420A)
The characteristics of the TMP90C441 include:
(1)
Powerful instructions: 163 basic instructions, including
Multiplication, division, 16-bit arithmetic operations, bit
manipulation instructions
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
Minimum instruction executing time:
250ns at 16MHz oscillation frequency)
Internal RAM
Memory expansion
External program memory: 64K byte
External data memory: 1M byte
8-bit A/D converter (6 channels)
General-purpose serial interface (1 Channel)
Asynchronous mode, I/O interface mode
Multi-function 16-bit timer/event counter (1 channel)
8-bit timers (4 channels)
Stepping motor control port (2 channels)
Input/Output ports (28 pins)
Interrupt function: 10 internal interrupts and 4 external
interrupts
Micro Direct Memory Access (µDMA) function (11 channels)
Watchdog timer
Standby function (4 HALT modes)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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TMP90C441
Figure 1. TMP90C441 Block Diagram
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TMP90C441
2. Pin Assignment and Functions
The assignment of input/output pins, their names and functions
are described below.
2.1 Pin Assignment
Figure 2.1 (1) shows pin assignment of the TMP90C441N.
Figure 2.1 (1). Pin Assignment
(Shrink Dual Inline Package)
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TMP90C441
Figure 2.1 (2) shows pin assignment of theTMP90C441F.
Figure 1. 1 (2). Pin Assignment (Flat Package)
2.2 Pin Names and Functions
The names of input/output pins and their functions are summarized in Table 2.2.
Table 2.2 Pin Names and Functions (1/2)
Pin Name
4/12
No. of pins
I/O 3 states
Function
D0 ~ D7
8
3 states
Data bus: Also functions as 8-bit bidirectional data bus for external memory
A0 ~ A7
8
Output
Address bus: The lower 8 bits address bus for external memory
A8 ~ A15
8
Output
Address bus: The upper 8 bits address bus for external memory
P30
/RxD
1
Input
P31
/RxD
1
Input
Port 30: 1-bit input port
Receiver Serial Data
Port 31: 1-bit input port
Receiver Serial Data
Port 32: 1-bit input port
P32
/TxD
/RTS
/SCLK
1
P33
/TxD
1
Output
P34
/CTS
1
Input
RD
1
Output
Read: Generates strobe signal for reading external memory
WR
1
Output
Write: Generates strobe signal for writing into external memory
Output
Transmitter Serial Data
Request to send Serial Data
Serial clock output
Port 33: 1-bit output port
Transmitter Serial Data
Port 34: 1-bit input port
Clear to send Serial data
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TMP90C441
Table 2.2 Pin Names and Functions (2/2)
Pin Name
No. of Pins
I/O 3 states
P37
/WAIT
1
Input
P40 ~ P43
/A16 ~ A19
4
Output
P50 ~ P55
/AN0 ~ AN5
6
Input
VREF
1
–
Input of reference voltage to A/D converter
AGND
1
–
Ground pin for A/D converter
P60 ~ P63
/M00 ~ M03
/TO1
I/O
Port 6: 4-bit I/O port that allows I/O selection on bit basis
4
Output
P70 ~ P73
/M10 ~ M13
/TO3
Function
Port 37: 1-bit input port
Wait: Input pin for connecting slow speed memory or peripheral LSI
Port 4: 4-bit output port that allows selection of Port/Address Bus on bit basis
Output
I/O
4
Output
Output
Address bus: Also functions as address bus for external memory
(4 bits of bank address)
Port 5: 6-bit input port
Analog input: 6 analog input to A/D converter
Stepping motor control port 0
Timer output 1: Output of Timer 0 or 1
Port 7: 4-bit I/O port that allows I/O selection on bit basis
Stepping motor control port 1
Timer output 3: Output of timer 2 or 3
Port 80: 1-bit input port
P80
/INTO
1
Input
Interrupt request pin 0: Interrupt request pin (Level/rising edge is
programmable)
Port 81: 1-bit input port
P81
/INT1
/TI4
1
Input
Interrupt request pin 1: Interrupt request pin (Rising/falling edge is
programmable)
Timer input 4: Counter/capture trigger signal for Timer 4
Port 82: 1-bit input port
P82
/INT2
/TI5
1
P82
/TO3/T04
1
Output
NMI
1
Input
CLK
1
Output
Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is
Pulled up internally during resetting.
EA
1
Input
External access: Connects with GND pin in the TMP90C441 with no internal
ROM.
RESET
1
Input
Reset: Initializes the TMP 90C441. (Built-in pull-up resister)
X1/X2
2
Input/
Output
Pin for quartz crystal or ceramic resonator
VCC
1
–
Power supply (+5V)
VSS (GND)
1
–
Ground (0V)
Input
Interrupt request pin 2: rising edge interrupt request pin
Timer input 5: capture trigger signal for Timer 4
Port 83: 1-bit output port
Timer output 3/4: Output of Timer 2, 3 or 4
Non-maskable interrupt request pin: Falling edge interrupt request pin
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TMP90C441
3. Operation
(1)
The following explains the TMP90C441 functions and basic
operations. The CPU functions and internal I/O functions of
the TMP90C441 are the same as the TMP90C840A.
Refer to the “TMP90C840A” section concerning functions
which are not explained the following.
The TMP90C441 internally contains a 4K byte RAM,
which is allocated to the address space from FBC0H
to FFBFH. The CPU allows the access to a certain
RAM area (FF00H to FFBFH, 192 bytes) by a short
operation code (opcode) in a “direct addressing
mode”.
The addresses from FF10H to FF7FH in this RAM area
can be used as parameter area for micro DMA processing
(and for any other purposes when the micro DMA
function is not used).
3.1 CPU
The TMP90C441 has an internal high-performance 8-bit CPU.
Refer to the “TLCS-90 CPU” section concerning CPU
operation.
3.2 Memory Map
The TMP90C441 supports a program memory of up to 64K
bytes and a data memory of maximum 1M bytes.
The program memory may be assigned to the address
space from 00000H to 0FFFFH, while the data memory can
be allocated to any address from 00000H to FFFFFH.
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Internal RAM
(2)
Internal I/O
The TMP90C441 provides a 48-byte address space
as an internal I/O area, whose addressess range from
FFC0H to FFEFH. This I/O area can be accessed by
the CPU using a short opcode in the “direct addressing
mode”.
Figure 3.1 is a memory map indicating the areas
accessible by the CPU in the respective addressing mode.
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TMP90C441
Figure 3.2. Memory Map
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TMP90C441
4. Electrical Characteristics
TMP90C441N/TMP90C441F
4.1 Absolute Maximum Ratings
Symbol
Parameter
VCC
Supply voltage
VIN
Input voltage
Unit
-0.5 ~ + 6.5
V
-0.5 ~ VCC + 0.5
V
F 500
Power dissipation (Ta = 70°C)
PD
Rating
mW
N 600
260
°C
TSTG
Storage temperature
-65 ~ 150
°C
TOPR
Operating temperature
-20 ~ 70
°C
TSOLDER
Soldering temperature (10s)
4.2 DC Characteristics
TA = -20 ~ 70°C Vcc = 5V ± 10%
Typical Values are for TA = 25°C and VCC = 5V.
Symbol
Parameter
Min
Max
Unit
Test Conditions
VIL
Input Low Voltage (D0 ~ D7)
-0.3
0.8
V
–
VIL1
P3, P5, P6, P7, P8
-0.3
0.3VCC
V
–
VIL2
RESET, INT0, NMI
-0.3
0.25VCC
V
–
VIL4
X1
-0.3
0.2VCC
V
–
VIH
Input Low Voltage (D0 ~ D7)
2.2
VCC + 0.3
V
–
VIH1
P3, P5, P6, P7, P8
0.7VCC
VCC + 0.3
V
–
VIH2
RESET, INT0, NMI
0.75VCC
VCC + 0.3
V
–
VIH4
X1
0.8VCC
VCC + 0.3
V
VOL
Output Low Voltage
–
0.45
V
IOL = 1.6mA
VOH
VOH1
VOH2
Output High Voltage
2.4
0.75VCC
0.9VCC
–
V
V
V
IOH = -400µA
IOH = -100µA
IOH = -20µA
IDAR
Darlington Drive Current
(8 I/O pins)
-1.0
-3.5
mA
VEXT = 1.5V
REXT = 1.1kΩ
–
ILI
Input Leakage Current
0.02 (Typ)
±5
µA
0.0 ≤ Vin ≤ VCC
ILO
Output Leakage Current
0.05 (Typ)
± 10
µA
0.2 ≤ Vin ≤ VCC - 0.2
19 (Typ)
1.6 (Typ)
9 (Typ)
30
6
15
mA
mA
mA
tosc = 16MHz
ICC
Operating Current (RUN)
Idle 1
Idle 2
0.2 (Typ)
50
10
µA
µA
0.2 ≤ Vin ≤ VCC - 0.2
STOP (TA = -20 ~ 70°C)
STOP (TA = 0 ~ 50°C)
RRST
RESET Pull Up Register
50
150
KΩ
CIO
Pin Capacitance
–
10
pF
VTH
Schmitt width RESET, NMI, INT0
0.4
1.0 (Typ)
V
–
testfreq = 1MHz
–
Note: IDAR is guaranteed for a total of up to 8 optional ports.
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TMP90C441
4.3 AC Characteristics
TA = -20 ~ 70°CVCC = 5V ± 10%
CL = 50pF
Variable
Symbol
10MHz Clock
16MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
80
1000
100
–
82.5
–
ns
ns
tOSC
OSC. Period = x
tCYC
CLK Period
4x
4x
400
–
250
–
tWL
CLK Low width
2x - 40
–
160
–
85
–
ns
tWH
CLK High width
2x - 40
–
160
–
85
–
ns
tAC
Address Setup to RD, WR
x - 45
–
55
–
17
–
ns
tRR
RD Low width
2.5x - 40
–
210
–
115
–
ns
tCA
Address Hold Time After RD, WR
0.5x - 30
–
20
–
5
–
ns
tAD
Address to Valid Data In
–
3.5x - 95
–
255
–
124
ns
tRD
RD to Valid Data In
–
2.5x - 80
–
170
–
77
ns
tHR
Input Data Hold After RD
0
–
0
–
0
–
ns
tWW
WR Low width
tDW
Data Setup to WR
2.5x - 40
–
210
–
115
–
ns
2x - 50
–
150
–
75
–
ns
tWD
Data Hold After WR
20
70
20
70
20
70
ns
tCWA
RD, WR to Valid WAIT
–
1.5x - 80
–
70
–
14
ns
tAWA
Address to Valid WAIT
–
2.5x - 130
–
120
–
27
ns
tWAS
WAIT Setup to CLK
50
–
50
–
50
–
ns
tWAH
WAIT Hold After CLK
0
–
0
–
0
–
ns
tRV
RD/WR Recovery Time
1.5x - 35
–
115
–
58
–
ns
tCPW
CLK to Port Data Output
–
x + 200
–
300
–
263
ns
tPRC
Port Data Setup to CLK
200
–
200
–
200
–
ns
tCPR
Port Data Hold After CLK
100
–
100
–
100
–
ns
tCHCL
RD/WR Hold After CLK
x - 60
–
40
–
10
–
ns
tCLC
RD/WR Setup to CLK
1.5x - 25
–
125
–
68
–
ns
tCLHA
Address Hold After CLK
1.5x - 80
–
70
–
13
–
ns
tACL
Address Setup to CLK
2.5x - 80
–
170
–
76
–
ns
tCLD
Data Setup to CLK
x - 50
–
50
–
12
–
ns
• AC output level High 2.2V/Low 0.8V
• AC input level High 2.4V/Low 0.45V (D0 – D7)
High 0.8VCC/Low 0.2VCC (excluding D0 – D7)
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TMP90C441
4.4 A/D Conversion Characteristics
TA = -20 ~ 70°C VCC = 5V ± 10%
Symbol
Parameter
Min
Typ
Max
VREF
Analog reference voltage
VCC - 1.5
VCC
VCC
AGND
Analog reference voltage
VSS
VSS
VSS
VAIN
Allowable analog input voltage
VSS
–
VCC
IREF
Supply current for analog reference voltage
–
0.5
1.0
Total error
(TA = 25°C, VCC = VREF = 5.0V)
–
–
Total error
–
–
Total error
(TA = 25°C, VCC = VREF = 5.0V)
–
–
Total error
–
–
Error
(1M ≤ fc ≤ 12.5MHz)
Error
(12.5M ≤ fc ≤ 16MHz)
Unit
V
mA
1.0
LSB
2.5
2.0
LSB
3.5
4.5 Zero-Cross Characteristics
TA = -20 ~ 70°C VCC = 5V ± 10%
Symbol
Parameter
VZX
Zero-cross detection input
AZX
Zero-cross accuracy
FZX
Zero-cross detection input frequency
Condition
Min
Max
Unit
AC coupling C = 0.1µF
1
1.8
VAC p - p
50/60Hz sine wave
–
135
mV
–
0.04
1
kHz
4.6 Serial Channel Timing-I/O Interface Mode
TA = -20 ~ 70°C VCC = 5V ± 10%
CL = 50pF
Variable
Symbol
10MHz Clock
16MHz Clock
Parameter
tSCY
Serial Port Clock Cycle Time
Unit
Min
Max
Min
Max
Min
Max
8x
–
800
–
500
–
ns
ns
tOSS
Output Data Setup SCLK Rising Edge
6x - 150
–
450
–
225
–
tOHS
Output Data Hold After SCLK Rising Edge
2x - 120
–
80
–
45
–
ns
tHSR
Input Data Hold After SCLK Rising Edge
0
–
0
–
0
–
ns
tSRD
SCLK Rising Edge to Input DATA Valid
–
6x - 150
–
450
–
225
ns
4.7 16-bit Event Counter
TA = -20 ~ 70°C VCC = 5V ± 10%
Variable
Symbol
10MHz Clock
16MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
tVCK
TI4 clock cycle
8x + 100
–
900
–
600
–
ns
tVCKL
TI4 Low clock pulse width
4x + 40
–
440
–
290
–
ns
tVCKH
TI4 High clock pulse width
4x + 40
–
440
–
290
–
ns
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TMP90C441
4.8 Interrupt Operation
TA = -20 ~ 70°C VCC = 5V ± 10%
Variable
Symbol
10MHz Clock
16MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
4x
–
400
–
250
–
ns
4x
–
400
–
250
–
ns
8x + 100
–
900
–
600
–
ns
8x + 100
–
900
–
600
–
ns
NMI, INT0 Low level pulse width
tINTAL
NMI, INT0 High level pulse width
tINTAH
INT1, INT2 Low level pulse width
tINTBL
INT1, INT2 High level pulse width
tINTBH
(Reference) Definition of IDAR
4.9 I/O Interface Mode Timing Chart
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TMP90C441
4.10 Timing Chart
TMP90C441 Special Function Register Address Table
Address
Symbol
Address
Symbol
Address
FFC0
Reserved
FFC1
Reserved
FFC2
FFC3
Symbol
FFD0
P8
FEC0
TREG4L
FFD1
P8CR
FEC1
TREG4H
IRFL (Note 1)
FFD2
WDMOD
FEC2
TREG5L
IRFH
FFD3
WDCR
FEC3
TREG5H
FFC4
Reserved
FFD4
TREG0
FEC4
T4MOD
FFC5
Reserved
FFD5
TREG1
FEC5
T4FFCR
FFC6
P3 (Note 2)
FFD6
TREG2
FEC6
INTEL
FFC7
P3CR
FFD7
TREG2
FEC7
INTEH (DMAEL)
FFC8
P4
FFD8
TCLK
FEC8
DMAEH
SCHMOD
FFC9
P4CR
FFD9
TFFCR
FEC9
FFCA
SMMOD
FFDA
TMOD
FECA
SCCR
FFCB
P5
FFDB
TRUN
FECB
SCBUF
FFCC
P6
FFDC
CAP1L
FECC
BX
FFCD
P7
FFDD
CAP1H
FECD
BY
FFCE
P67CR
FFDE
CAP2L
FECE
ADREG
FFCF
SMCR
FFDF
CAP2H
FECF
ADMOD
Note 1) You can’t use except for bit 4, 5, and 6 in Address (FFC2H)
Note 2) You can’t use except for bit 0, 1, 2, 3, 4, 5, 7 in Address (FFC6H)
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