NTB10N40 Preferred Device Product Preview TMOS 7 E-FET Power Field Effect Transistor N–Channel Enhancement–Mode Silicon Gate http://onsemi.com TMOS POWER FET 10 AMPERES 400 VOLTS RDS(on) = 0.5 Ω This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. N–Channel D New Features of TMOS 7 • Ultra Low On–Resistance Provides Higher Efficiency • Reduced Gate Charge Features Common to TMOS 7 and TMOS E–FETS • • • Avalanche Energy Specified Diode Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature G S MARKING DIAGRAMS MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage — Continuous — Non–Repetitive (tp 10 ms) v Drain — Continuous — Continuous @ 100°C — Single Pulse (tp 10 µs) v Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range Single Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 10 A, L = 10 mH, RG = 25 Ω) Thermal Resistance — Junction–to–Case — Junction–to–Ambient — Junction–to–Ambient (Note 1.) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol Value Unit VDSS VDGR 400 Vdc 400 Vdc "20 "40 Vdc 10 7.5 35 Adc 142 1.14 Watts W/°C – 55 to 150 °C VGS VGSM ID ID IDM PD TJ, Tstg EAS 500 mJ D2PAK CASE 418B STYLE 2 2 NTB10N40 YWW YY, Y = Year WW, W = Work Week PIN ASSIGNMENT 1 Gate 2 Drain 3 Source 4 Drain °C/W RθJC RθJA RθJA TL ORDERING INFORMATION 0.88 62.5 50 Device °C 260 This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. June, 2000 – Rev. 0 1 3 1. When surface mounted to an FR4 board using the minimum recommended pad size. Semiconductor Components Industries, LLC, 2000 4 1 Package Shipping NTB10N40 D2PAK 50 Units/Rail NTB10N40T4 D2PAK 800 Tape & Reel Preferred devices are recommended choices for future use and best overall value. Publication Order Number: NTB10N40/D NTB10N40 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 400 — — 475 — — — — — — 10 100 — — — — 100 100 2.0 — 2.5 6.5 4.0 — mV/°C — 0.35 0.5 Ohm — — — — 6.0 5.3 gFS 2.0 7.0 — Mhos Ciss — 1440 2020 pF Coss — 360 500 Crss — 15 30 td(on) — 10 20 tr — 20 40 td(off) — 33 70 tf — 24 50 QT — 24 30 Q1 — 6.0 — Q2 — 7.0 — Q3 — 12 — — — 0.9 0.8 1.1 — trr — 305 — ta — 155 — tb — 150 — QRR — 2.5 — — — 3.5 4.5 — — — 7.5 — OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Collector Current (VDS = 400 Vdc, VGS = 0 Vdc) (VDS = 400 Vdc, VGS = 0 Vdc, TJ =125°C) Vdc µAdc IDSS Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS(f) IGSS(r) mV/°C nAdc ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage ID = 0.25 mA, VDS = VGS Temperature Coefficient (Negative) VGS(th) Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 5.0 Adc) RDS(on) Drain–to–Source On–Voltage (VGS = 10 Vdc, ID = 10 Adc) (VGS = 10 Vdc, ID = 5.0 Adc, TJ = 125°C) VDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) Vdc Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2.) Turn–On Delay Time (VDD = 200 Vdc, ID = 10 Adc, VGS = 10 Vdc Vdc, RG = 9.1 Ω) Rise Time Turn–Off Delay Time Fall Time Gate Charge ((VDS = 320 Vdc, ID = 10 Adc, VGS = 10 Vdc) ns nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (Note 1.) VSD (IS = 10 Adc, VGS = 0 Vdc) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 10 Adc Adc, VGS = 0 Vdc Vdc, dIS/dt = 100 A/µs) Reverse Recovery Stored Charge Vdc ns µC INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS 1. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. 2. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 nH NTB10N40 PACKAGE DIMENSIONS D2PAK CASE 418B–03 ISSUE D C E V –B– NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 4 A 1 2 S 3 –T– SEATING PLANE K J G D H M T B INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 STYLE 2: PIN 1. 2. 3. 4. 3 PL 0.13 (0.005) DIM A B C D E G H J K S V M http://onsemi.com 3 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40 NTB10N40 E–FET is a trademark of Semiconductor Components Industries, LLC. TMOS is a registered trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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