ETC TMP90C051F

TOSHIBA
TLCS-90 Series
TMP90C051
CMOS 8–Bit Microprocessor
TMP90C051F
1. Overview and Features
The TMP90C051F is a high-speed 8-bit CMOS microprocessor with advanced functions and was developed for application in various types of device control.
The TMP90C051F is a single-chip, 8-bit CMOS microprocessor that integrates peripheral functions such as DMA, DRAM
controller, serial interface, timer/event counter and real time
clock with an 8-bit CPU (TLCS90) core. Memory area can also
be extended up to 8M bytes depending on the MMU.
The TMP90C051F features are as follows.
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(10)
(1)
(2)
(3)
(4)
Highly efficient instruction group
Number of basic instructions: 167
Multiplication and division instructions, 16-bit arithmetic
operation instructions and bit operation instructions.
Minimum instruction execution times: 250ns (at
16.0MHz)
Memory extension capability
Address space: 8M byte (max)
DMA (2 channels)
Maximum transfer speed: 2-byte transfer;
0.88M byte/sec (at 16.0MHz)
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(15)
DRAM controller
General-purpose serial interface (2 channels)
UART (transmit/receive)
I/O interface mode (transmit/receive)
Thermal printer head (transmit)
8-bit timer/event counter (4 channels)
Real time clock: Clock and calendar functions/battery
backup capability.
Stepping motor control pattern generation ports
(2 channels)
Input/output port (31-pin)
Interrupt functions:11 internal, 9 external.
Micro DMA function
Maximum transfer speed: 0.34M byte/s (at 16.0MHz)
Watchdog timer function
Standby function (3 halt modes)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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TMP90C051
Figure 1. TMP90C051F Block Diagram
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TMP90C051
2. Pin Layout and Functions
This section shows the TMP90C051F pin layout diagram, and
describes the input/output pin names and functions.
2.1 Pin Layout Diagram
Figure 2.1 shows the TMP90C051F pin layout.
Figure 2.1. Pin Layout Diagram (80-pin Flat Package) [TOP VIEW]
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TMP90C051
2.2 Pin Names and Functions
Table 2.2 Shows the input/output pin names and functions.
Table 2.2 Pin Names and Functions (1/3)
Pin Name
Number of pins
(pin no.)
Input/output or tristate
Function
AD0 ~ AD7
8
(37 ~ 44)
Input/output or tristate
Lower address/data bus: Used as both the lower 8-bit address bus (output) and
data bus (bi-directional).
A8 ~ A15
8
(45 ~ 52)
Output
The upper 8-bit address bus.
Output
Port 2: A 7-bit output port. Outputs “0” after reset.
Output
Address bus: The extension (upper) address bus. Outputs “0” after reset; therefore, the TMP90C051F address area is 0 - 64K bytes until a value other than
000H is written to EXPA0 and EXPA1 of the MMU register group after a reset;
therefore, A16 - A22 output zeros (0).
When a logical address indicates within the local area (local 0 or local 1) range
when the MMU is started, the physical addresses generated by the MMU are
outputs to A16 - A22.
Zeros (0) are output to A16 - A22 when a logical address indicates within the common
area (common 0 or common 1) range.
When an indirect extension address area is accessed using the CPU index register the address value loaded to the BX or BY register is output to A16 - A22.
When data are transferred using high-speed micro DMA, the address value loaded to
the DMA bank register is output to A16 - A22.
P20 ~ P26
(A16 ~ A22)
7
(54 ~ 60)
RD
1
(62)
Output
Read: The strobe signal output used to read data from external memory.
WR
1
(63)
Output
Write: The strobe signal output used to write data to external memory.
WAIT
1
(65)
Input
Wait: An input pin used to connect memory with slow access time and peripheral LSIs.
NMI
1
(29)
Input
Non-maskable interrupt request pin:
The input pin used to generate interrupt requests on the fall edges
P30
(RAS)
(1)
(61)
Output
P31
(CAS)
1
(64)
Input
Port 30: A 1-bit output port. Outputs “1” after reset.
RAS: Outputs the RAS timing required for refreshing the DRAM of CAS before RAS.
Port 31: A 1-bit output port. Outputs “1” after reset.
CAS: Outputs the CAS timing required for refreshing the DRAM of CAS before RAS.
Port 32: A 1-bit output port. Outputs “1” after reset.
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P32
(CS)
1
(66)
Output
P33
(DACT0)
1
(67)
Output
Chip select: The external memory chip select output pin. When a start address
and area size are loaded to the control register in the dynamic RAM controller,
“0” is output from the CS pin whenever the TMP90C051F accesses that address
range.
Port 33: A 1-bit output port. Outputs “1” after reset.
DMA active 0: Outputs zeros (0) while data are being transferred via high-speed
micro DMA channel 0.
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Table 2.2. Pin Names and Functions (2/3)
Pin Name
Number of pins
(pin no.)
Input/outpu t or tristate
P34
(DACT1)
1
(68)
Output
P35
(WDTOUT)
1
(69)
Output
P36
(INT7)
1
(70)
Input/Output
Input
Port 36: A 1-bit output port. Functions as an input port after reset.
P37
1
(71)
Input/output
Port 37: A 1-bit input/output port. Functions as an input port after reset.
P40 ~ P43
4
(7 ~ 10)
Input/output
4
Input/output
(11 ~ 14)
Output
P50 ~ P53
(M10
~ M03)
Function
Port 34: A 1-bit output port. Outputs “1” after reset.
DMA active 1: Outputs zeros (0) while data are being transferred via high-speed micro DMA
channel 1.
Port 35: A 1-bit output port. Outputs “WDTOUT = 1” after reset.
Output
Watchdog timer output: used as the WDTOUT output pin when watchdog timer mode
register, D1 = 1.
Interrupt request pin 7: The input pin for generating interrupt requests at rise edges.
Port 40 - 43: A 4-bit input/output port. Functions as an input port after reset.
Stepping motor control port 0.
Port 50 - 53: A 4-bit input/output port. Functions as an input port after reset.
Stepping motor control port 1
P60 ~ P63
(INT3
~ INT6)
4
Input/output
(15 ~ 18)
Input
P64
(TI0)
1
(19)
Input/output
P65
(TI2)
1
(20)
Input/output
P66
(TO0/TO1)
1
(22)
Input/output
P67
(TO2/TO3)
1
(23)
Input/output
LATWAIT
RxD0
1
(30)
TPHSD
(TxD0)
1
(31)
Output
TPHCKO
1
Output
After a reset, serial channel 0 enters the TPH mode and outputs “1”. The TPHCK0 pin is used
to output the transmit clock to TPH.
(SCLK0)
(32)
Input/output
When set to the Normal mode by the TPH control register, serial channel 0 operates in the
UART or I/O interface mode.
The control register of serial channel 0 determines whether the UART or I/O interface mode is
used.
In the I/O interface mode, either the external clock from SCLK0 or the transmit/receive clock
from the internal baud rate generator is output. Note: When operating with external clock
inout in the I/O interface mode SCLK0 is output after a reset; therefore, use an open drain
circuit to connect the external clock to the SCLK0 pin.
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Input
Input
Output
Port 60 ~ 63: A 4-bit input/output port. Functions as an input port after reset.
Interrupt request pins 3-6: Input pins for generating interrupt requests at rise edges.
Port 64: A 1-bit input/output port. Functions as an input port after reset.
Timer input 0: The timer 0 clock input pin.
Port 65: A 1-bit input/output port. Functions as an input port after reset
Timer input 2: The timer 2 clock input pin.
Port 66: A 1-bit input/output port. Functions as an input port after reset.
Timer output 0/1: The timer 0 or timer 1 output pin.
Port 67: A 1-bit input/output port. Functions as an input port after reset.
Output
Timer output 2/3: The timer 2 or timer 3 output pin.
Input
Set serial channel 0 to the TPH mode after reset. The wait control input pin used to cause
TPHLAT output to wait.
Used as the receive data input pin when serial channel 0 is set to the Normal mode.
Serial channel 0 enters the TPH mode and outputs “0” after a reset. The TPHSD pin is used
to output transmit data to TPH.
When set to the Normal mode, serial channel 0 functions as the transmit data output pin
TXD0 output immediately after mode is set.
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Table 2.2 Pin Names and Functions (3/3)
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Pin Name
No. of pins
(pin. no.)
Input/output or tristate
TPHCKI
1
Input
Serial channel 0 enters the TPH mode after a reset and functions to input the transmit
clock to TPH.
(RTS0)
(33)
Output
Serial channel 0 is the TPH control register and operates as the RTS output pin when set to the
Normal mode.
TPHLAT
1
Output
After a reset, serial channel 0 enters the TPH mode and the functions as the latch signal
pin for outputs to TPH.
Input
When set to the Normal mode by the TPH control register, serial channel 0 operates as the
CTS0 input pin.
Consequently, since the CTS0 pin outputs after a reset, use an open drain circuit to connect
the CTS0 pin to CTS0 when serial channel 0 is used in the UART mode.
Function
(CTS0)
(34)
RTS1
1
(72)
Output
The serial channel 1 RTS1 output pin.
CTS1
1
(73)
Input
The serial channel 1 CTS1 input pin.
SCLK1
1
(74)
Input/output
TxD1
1
(75)
Output
The serial channel 1 transmit data output pin.
RxD1
1
(76)
Input
The serial channel 1 receive data input pin.
CXIN/CXOUT
2
(1/2)
Input/output
Used to connect the crystal oscillator for the real time clock. A 32.768kHz crystal oscillator
is usually connected.
ALARM
1
(3)
Output
Alarm: The output pin for alarms from the real time clock. Comparator output and either
the 16Hz or 1Hz signal generated by the divider can be output to the ALARM pin using the
alarm select circuit inside the real time clock.
INT0 ~ INT2
3
(4~6)
Input
Interrupt request pins 0 - 2: The input pin used to generate interrupt requests at rise edges.
INT0 is an input pin with a Schmitt circuit.
ALE
1
(35)
Output
Address latch enable signal: AD0 - AD7 addresses are latched on the fall of this signal.
Connected to external memory.
EA
1
(28)
Input
Connect to GND.
CLK
1
(24)
Output
Clock output: Output a clock equal to the oscillation frequency divided by 4. Pulled up
during resets.
RESET
1
(23)
Input
Reset: The reset input pin used to initialize the TMP90C051F. (Built-in pull up register)
X1/X2
2
(26/77)
Input/Output
VCC
2
(36/77)
–
BAKEN
1
(79)
Input
Backup enable: set BUKEN = 1 when the TMP90C051F main power supply Vcc (pins 36/
77) is +5V.
Set to BUKRN = 0 to provide battery backup for the real time clock when the main power
supply Vcc (pins 36/77) is off.
VCC (RTC)
1
(78)
–
The real time clock backup power supply pin. Arrange so that the same power is supplied
to Vcc (RTC) as to Vcc (pins 36/77) when power is being supplied to Vcc (pins 36/77). To
provide battery backup for only the ral time clock, supply + 5V - 2V to Vcc (RTC).
VSS (GND)
3
(25/53/80)
–
GND pin (0V)
Functions as the serial channel 1 transceive clock input or output pin. SCLK1 functions as an
input pin after a reset.
Used to connect the crystal oscillator that generates the TMP90C051 internal system clock.
Main power supply pin (+5V)
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3. Operation
This section explains the functions and basic operations of the
TMP90C051F by block.
3.1 CPU
The TMP90C051F includes a high performance 8 bit CPU. For
the function of the CPU, see the book TLCS 90 Series CPU
Core Architecture. This chapter explains exclusively the functions of the CPU of TMP90C051F which are not described in
the the book.
3.1.1 Reset
Figure 3.1 (1) shows the basic timing for the reset operation.
To reset the TMP90C051F, it is necessary to maintain the
RESET input at “0” for at least 10 system clocks (10 states: 2
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microseconds with a 10MHz system clock) with the power
supply voltage within the operating range and stable internal
oscillator operation.
When a reset is received, the address data bus (AD0 - AD7),
address bus (A8 - A15), P36, P37, port 4 port 5 and port 6 are
all set to input port status (high impedance). Dedicated output
port 2 (A16 - A22) ALE is set to “0”; P30 - P35, RD, WR and
CLK are set to “1”. The other dedicated output ports are all set
to “0” and the dedicated input ports retain their current status.
The CPU registers and external memory are not changed;
however, the program counter PC, interrupt enable/disable
flag IFF, bank registers BX and BY are cleared to “0”. The A register is indeterminate.
When the reset is released, the instruction starts from
address 0000H.
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Figure 3.1 (1). Reset Timing
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3.1.2 EXF (Exchange Flag)
For TMP90C051F, “EXF”, which is inverted when the command
“EXX” is executed to transfer data between the main register
and the auxiliary register, is allocated to the first bit of memory
address FFBFH.
3.1.3 Wait Control
For TMP90C051F, a wait control register P2FR <WAITC0, 1> is
allocated to the 2th and 3th bits of memory address FFDFH.
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3.1.4 Bank Register
For TMP90C051F, BX and BY registers are allocated to memory addresses FFECH (BX register) FFEDH (BY register),
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respectively. In these registers, only the low-order 7 bits are
valid, and the high-order 1 bit are undefined. These undefined
bits become “1” whenever they are read.
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3.2 Memory Map
The TMP90C051F supports a program memory and a data
memory of maximum 8M bytes.
The program and data memory may be assigned to the
address space from 00000H to 7FFFFFH.
3.2.1 Internal I/O
The TMP90C051F provides a 128-byte address space as an
internal I/O area, whose addresses range from FF80H to
FFFFH. This I/O area can be accessed by the CPU using a
short opcode in the “direct addressing mode”.
Figure 3.2 (1) is a memory map indicating the areas
accessible by the CPU in the respective addressing mode.
Figure 3.2 (1). Memory Map
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3.3 Interrupt Functions
The TMP90C051F has a general-purpose interrupt processing routine for responding to both internal and external interrupt requests, a micro DMA processing mode in which the
CPU automatically transfers data, and a high-speed micro
DMA (HDMA) processing mode.
Immediately after a reset is released, all responses to
interrupt requests are set to the general-purpose interrupt
processing mode. The interrupt requests can be set to the
micro DMA processing mode with the DMA enable/disable
register which is described later.
The high-speed DMA processing mode can be set by
loading a vector value to the DMAV 0/1 register.
Figure 3.3 (1) shows the interrupt response flow.
Figure 3.3 (1). Interrupt Response Flow
When an interrupt request is generated, this is reported to
the CPU via the built-in interrupt controller. If the request is for
a non-maskable interrupt or an enabled maskable interrupt,
the CPU starts interrupt processing. If for a disabled maskable
interrupt, the request is ignored and not received.
If the interrupt is received, the CPU first reads the interrupt
vector from the built-in interrupt controller to determine the
source of the interrupt request.
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Next, a check is made as to whether this request is for
general-purpose interrupt processing, micro DMA processing
or high-speed DMA (HDMA) processing, and then the corresponding processing is performed.
The interrupt vector is read in an internal operation cycle
so the bus cycle becomes a dummy cycle.
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3.3.1 General-Purpose Interrupt Processing
Figure 3.3 (2) shows the general-purpose interrupt processing
flow.
The CPU first saves the contents of the program counter
PC and register AF (including the interrupt enable/disable flag
IFF immediately before an interrupt) to the stack and then
resets the interrupt enable/disable flag IFF to “0” (interrupt
disable). Finally, the interrupt vector contents [V] are transferred to
the program counter and a jump is made to the interrupt
processing program.
There is a 20-state overhead from the time when the interrupt is
received until the jump is made to the interrupt processing program.
Figure 3.3 (2). General-Purpose Interrupt Processing Flow
Interrupt processing program is ended with the RETI
instruction for both maskable and non-maskable interrupts.
Executing this instruction restores the program counter
PC and register AF contents from the stack. (Resets the interrupt
enable/disable flag immediately before an interrupt.)
When the CPU reads the interrupt vector, the interrupt
request source confirms that the interrupt has been received
and then clears the interrupt request. Non-maskable interrupts
cannot be disabled by program. Maskable interrupts, however, can be enabled and disabled by program. Bit 5 of CPU reg-
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ister F is an interrupt enable/disable flipflop (IFF). Interrupts are
enabled by setting this bit to “1” with the EI (interrupt enable)
instruction and disabled by resetting this bit to “0” with the DI
(interrupt disable) instruction. IFF is reset to “0” by resetting
and when an interrupt is received (including non-maskable
interrupts).
The EI instruction is actually executed after the next
instruction is executed.
Table 3.3 (1) shows the interrupt sources.
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Table 3.3 (1) Interrupt Sources
Priority
sequence
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Type
Interrupt
function
name
Interrupt
vector
value
Generalpurpose
interrupt
processing
start address
Micro
DMA
support
Micro DMA
processing
parameter start
address
Interrupt sources
Comments
Internal
External
Nonmaskable
SWI
Instruction
NMI
08H
0008H
–
–
O
–
–
10H
0010H
–
–
–
NMI pin
–
Maskable
(HDMA)
INT0
INT1
INT2
INTT0
INTT1
INTT2
INTT3
INTRX0
INTTX0
INTLINE
INTRX1
INTTX1
INTALARM
INT3
INT4
INT5
INT6
INT7
–
18H
20H
28H
30H
38H
40H
48H
50H
58H
60H
68H
70H
78H
80H
88H
90H
98H
A0H
–
0018H
0020H
0028H
0030H
0038H
0040H
0048H
0050H
0058H
0060H
0068H
0070H
0078H
0080H
0088H
0090H
0098H
00A0H
–
O
O
O
O
O
O
O
O
O
O
O
O
–
–
–
–
–
–
–
FF18H
FF20H
FF28H
FF30H
FF38H
FF40H
FF48H
FF50H
FF58H
FF60H
FF68H
FF70H
–
–
–
–
–
–
–
–
–
–
Timer 0
Timer 1
Timer 2
Timer 3
Serial receive end
Serial send end
TPH send
Serial receive end
Serial receive end
Alarm output
–
–
–
–
–
–
INT0 pin
INT1 pin
INT2 pin
–
–
–
–
–
–
–
–
–
–
INT3 pin
INT4 pin
INT5 pin
INT6 pin
INT7 pin
*1
External 0
External 1
External 2
Timer
Timer
Timer
Timer
SIO
SIO
TPH
SIO
SIO
RTC
External 3
External 4
External 5
External 6
External 7
Note: * HDMA supports all maskable interrupts.
The “priority sequence” shown in Table 3.3 (1) indicates
the sequence in which interrupt sources are received by the
CPU when multiple interrupt requests are generated simultaneously.
For example, if interrupt requests with the priority
sequences 4 and 5 are generated simultaneously, the CPU will
receive the interrupt request with priority sequence 4 first.
When processing of the interrupt with priority sequence 4 is
ended with the RETI instruction, the CPU will then receive the
interrupt with priority sequence 5.
If the interrupt processing program for the priority
sequence 4 interrupt is interrupted by executing the EI instruction,
the CPU will receive the priority sequence 5 interrupt request.
When multiple interrupt requests are generated simultaneously, the
built-in interrupt controller only determines the priority
sequence of the interrupt sources received by the CPU. There
is no function to compare the priority sequence of the interrupt
currently being processed and the interrupt currently being
requested.
Another interrupt can be enabled while another interrupt is
being processed by resetting the interrupt enable/disable flag
IFF to enable.
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3.3.2 Micro DMA Processing
Figure 3.3 (3) shows the micro DMA processing flow. The CPU
first loads the parameters (transfer source and destination
addresses, transfer mode) required for transferring data
between memories from the address modified by the interrupt
vector value and then transfers the data between memories in
accordance with those parameters. After that, the revised
parameters are saved to the original location. The transfer
count is then decremented and, if the value is not “0”, micro
DMA processing is ended. If the value is “0”, the general-purpose
interrupt processing described in the previous item is performed.
The transfer count is decremented by “-1” each time the
micro DMA starts up.
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Figure 3.3 (3). Micro DMA Processing Flow
Since most interrupt processing involves only simple data
transfers, micro DMA processing uses only the hardware for
such processing. Consequently, micro DMA processing is
faster than conventional software processing. Naturally, there
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is absolutely no influence on the CPU registers from the micro
DMA processing.
Figure 3.3 (4) shows the functions of the parameters used
in the micro DMA processing.
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Figure 3.3 (4). Micro DMA Processing Parameters
The parameters used for the micro DMA processing are
located in the external RAM area (See Table 3.3 (1) Interrupt
sources). The start address of each micro DMA processing
parameter is [FF00H + interrupt vector value], 6 bytes of which
are used for the parameters. When the micro DMA processing
mode is not used, this area can be used as user memory.
The parameters include transfer count, transfer destination
address, transfer source address and transfer mode. Transfer
count specifies the number of times data will be transferred by
micro DMA processing. Either 1 or 2- bytes of data are trans-
ferred at one time by micro DMA processing. Data are
transferred 256 times with a transfer count of “00H”.
The addresses 0000H - FFFFH are used in micro DMA
processing (at not use MMU function). Bits 0 and 1 specify the
transfer destination or transfer source address change mode.
Bit 2 specifies the length (1 or 2 bytes) of the data handled.
Table 3.3 (2) shows the relationship between the transfer
mode and transfer destination/transfer source address increment/decrement values.
Table 3.3 (2) Micro DMA Processing Address Changes
Transfer
Mode
000
001
010
011
100
101
110
111
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Function
Transfers 1-byte, fixes transfer destination/source addresses.
Transfers 1-byte, increment s transfer destination address.
Transfers 1-byte, increment transfer source address.
Transfers 1-byte, decrement transfer source address.
Transfers 2-bytes , fixes the current destination/source addresses.
Transfers 2-bytes , increment transfer destination address.
Transfers 2-bytes, increment transfer source address.
Transfers 2-bytes, decrements, transfer source address.
Transfer destination
address
Transfer source
address
0
+1
0
0
0
+2
0
0
0
0
+1
-1
0
0
+2
-2
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Data are transferred as shown below in the 2-byte transfer
mode.
(Transfer source address)←(Transfer destination address)
(Transfer source address + 1)←(Transfer destination
address + 1)
Transfers are also performed as shown above in “decrement
transfer source address mode” but address changes are as
shown in Table 3.3.
Address incrementation and decrementation are used for
the memory area but fixed addresses are used for ordinary input/
output addresses. Because of that, micro DMA was designed
taking into consideration input/output to memory and memory
to input/output transfers.
Figure 3.3 (5) shows and example using the micro DMA
processing mode. Built-in serial input/output receive data are
processed in the example.
In the example, 7 frames (1 frame = 1 byte in this example) of
received data are stored to memory address FF00H - FF06H
and when all of the data have been received, the “receive end
processing program” is executed.
Figure 3.3 (5). Micro DMA Processing Example
“Table 3.2 Bus operations for each instruction” above
shows the bus operation for general-purpose interrupt processing and micro DMA processing.
The execution time (when the transfer count is not 0 after
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decrementation) for micro DMA processing is 46 states (9.2
microseconds at 10MHz), regardless of whether the 1-byte or
2-byte transfer mode is used.
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TMP90C051
3.3.3 High-Speed Micro DMA Processing
The TMP90C051F has two built-in DMA channels called
HDMA.
HDMA has three times the processing capacity of µDMA
and is used for high-speed data transfers. HDMA execution
time (decrease the value of transfer number and the value is
not “0” data) is 14 states, regardless of whether the 1-byte
transfer mode or 2-byte transfer mode is used. HDMA and
micro DMA transfer speeds.
Table 3.3 (3) shows the high-speed micro.
Table 3.3 (3) Transfer Speeds
fxtal (MHz)
HDMA
Micro DMA
10
2.8µs
9.2µs
12.5
2.24µs
7.36µs
16
1.75µs
5.75µs
* At 1-byte transfer mode.
Table 3.3 (4) Shows the HDMA function
Number of channels
(1)
2
Transfer speed
14 states (for 1 byte) or 18 states (for 2 bytes)
Start method
By interrupt (all external and internal interrupt sources)
Transfer mode
1 byte transfer or 2 byte transfer
Address output method
Dual address (source/destination)
Access area
0 ~ 8-M byte memory area (64k-byte units)
HDMA Setting Registers
HDMA operation.
The following describes the registers required for
(a) DMAS0, 1: source address register (16-bit)
(b) DMA0, 1: Destination address register (16-bit)
(c) DMAC0, 1: byte count register (16-bit)
Sets the number of bytes to be transferred.
The set value is decremented (–1) for each HDMA
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started. A generation purpose interrupt is when the
value reaches “0”.
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TMP90C051
(d) DMAM0, 1: transfer mode register (8-bit)
This register determines the HDMA transfer mode.
The bits of this register are as shown in the table
above.
The source and destination addresses shown here are
the addresses loaded to DMAS0, 1 and DMAD0, 1
above.
Example 1 : XXX00001
Transfers 1 byte, fixes transfer source
address (DMAS0, 1), and increments the
transfer destination address after each
transfer.
Example 2: The renewal of address at 2
byte transfer mode.
Note:
It is ineffective to set decrement for a destination address when a source address being increment; and to set increment for a destination address
when a source address being decrement.
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TMP90C051
(e) DMASB0, 1: source address bank register
Source address extension register
Used as a pair with the DMAS0, 1 register, this bank
register is specified for addresses for 64k bytes or
more.
This register has no increment or decrement function;
therefore, it is necessary to exercise caution in specifying
variable addresses (increment or decrement) with the
above mode register.
(f) DMADB0, 1: destination address bank register
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Destination address register
Used as a pair with the DMAD0, 1 register. The function
are the same as those of the DMASB0/1.
(g) DMAV0, 1: DMA vector register
HDMA is started by interrupts. Consequently, the vector
address of the interrupt that assigns HDMA start is
loaded to the DMA vector register (DMAV0/1).
HDMA compares the interrupt vector and the contents
of this register. If they match, HDMA operation starts.
It is necessary to set the vector address before generating the interrupt that starts HDMA.
(2)
(a) Internal start factors
• SWI (software)
• All internal I/O interrupts
Assign starting of HDMA channel 0 or channel 1 to the
INT0 - INT7 external interrupts, connect any of the bits
of ports 2 - 6 (output mode) externally to INT0 - INT7
to generate a start interrupt.
Register Loading
(a) DMAS0, 1
DMAD0, 1 Loaded with the LDC instruction.
DMAC0, 1 (*The LDC instruction is a new TLCS-90
1 instruction.)
DMAM0,
(b) External start factors
• NMI pin
• INT0 ~ 7 pin
(4)
(b) DMASB0, 1
DMADB0, 1 Load the input/output address with
the LD instruction.
DMAV0, 1 (See the separate address map
concerning input/output addresses.)
(3)
HDMA Start
HDMA can be started by any of the TMP90C051
maskable interrupt sources.
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HDMA Channel 0 and Channel 1 Priority Sequence
The channel where an interrupt is generated first has
priority.
Note: HDMA, regardless of an interrupt enable flag,
compares the vector and the values of the DMA V0/1
register. If they match in EI mode, the HDMA starts. Do
not write the vector value of the non-maskable interrupt to
the DMA V0/1 register. If doing so, the HDMA does not
operate normally.
To stop the HDMA being started, set DI mode before
generating the interrupt to start the HDMA, or set the
DMA V0/1 register to 00H.
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TMP90C051
(5)
HDMA Operation Flow
Figure 3.3 (6). HDMA Operation Flow
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(6)
HDMA Operation Timing
(a) 1-byte transfer mode
Figure 3.3 (7a). HDMA Operating Timing
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TMP90C051
(b) 2-byte transfer mode
Figure 3.3 (7b). HDMA Operation Timing
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3.3.4 Interrupt Controller
Figure 3.3 (9) shows an abbreviated interrupt circuit diagram.
The left half of this diagram shows the interrupt controller and
the right half shows the CPU interrupt request signal circuit
and hold release circuit.
The interrupt controller has an interrupt request flipflop
and interrupt enable/disable flag for each interrupt channel
(total: 20 channels), and a micro DMA enable/disable flag. The
interrupt request flip-flop latches interrupt requests that arrive
from the periphery. This flipflop is reset to “0” when there is a
reset, when the CPU receives an interrupt and reads the vector of
that interrupt channel, and when an instruction that clears the
interrupt request (writes “vector value/8” to memory address
FFC9H) for that channel is executed.
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LD (0FFC9H), 38H/8
For example, when LD (0FFC9H), 38H / 8 is executed, the
interrupt request flipflop for the interrupt channel [INTT1] with
the vector value 38H is reset to “0” (to clear the flipflop, also
write to address FFC9H when the interrupt request flag is
assigned to FFCAH and FFCBH).
Table 3.3 (5) shows the “interrupt vector value/8” values.
The status of the interrupt request flipflop can be determined
by reading memory address FFC9H, FFCAH or FFCBH. “0”
means no interrupt request and “1” means an interrupt
request. Figure 3.3 (8) shows the bit layout when the interrupt
request flipflop is read.
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TMP90C051
Table 3.3 (5) Interrupt Vector Value/8 Values
Priority
sequence
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Type
Interrupt function
name
Interrupt vector
value
Vector value ÷ 8
Non
Maskable
SWI instruction
NMI
08H
10H
–
Maskable
(HDMA)
INT0
INT1
INT2
INTT0
INTT1
INTT2
INTT3
INTRX0
INTTX0
INTLINE
INTX1
INTTX1
INTALARM
INT3
INT4
INT5
INT6
INT7
–
18H
20H
28H
30H
38H
40H
48H
50H
58H
60H
68H
70H
78H
80H
88H
90H
98H
A0H
–
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
Figure 3.3 (8). Interrupt Request Flipflop Read (1/2)
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Figure 3.3 (8). Interrupt Request Flipflop Read (2/2)
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TMP90C051
Figure 3.3 (9). Interrupt Controller Block
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The interrupt enable/disable flags for each interrupt request
channel are assigned to memory addresses FFCC - FFCEH.
Interrupts are enabled for a channel by setting the flag to “1”.
The flags are reset to “0” by resets.
Disable interrupts (DI) before clearing the interrupt request
flags.
The micro DMA enable/disable flags for each interrupt
request channel are assigned to memory addresses FFCEH or
FFCFH. The interrupt requests for a channel are set to the
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micro DMA processing mode by setting the flag to “1”. The
flags are reset to “0” by resets (“0” is the general-purpose interrupt processing mode).
Figure 3.3 (9) shows the bit layouts for the interrupt
enable/disable flags and micro DMA enable/disable flags.
Disable interrupts (DI) before clearing the interrupt request
flags.
Caution is required in usage because the two following
points are exceptions.
INTRX0, INTRX1
Interrupt request flipflops are cleared only by resets and reading the
serial channel receive buffer. They are not cleared by instructions.
INT0 ~ INT7
INT0 ~ INT7 are all of the edge type.
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TMP90C051
Figure 3.3 (10). Micro DMA Interrupt Enable Flags (1/2)
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Figure 3.3 (10). Micro DMA Interrupt Enable Flags (2/2)
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TMP90C051
Figure 3.3 (11). Overall Interrupt Processing Flow
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DMAS0 and DMAS1; destination address bank register:
DMADB0 and DMADB1).
3.4 MMU
3.4.1 Address Area Extension
The TMP90C051F can access the extended address area
(10000H -7FFFFFH) using the following three methods.
(3)
Address extension method
(1)
Extended data area access using CPU bank registers
BX and BY.
(2)
Extended data area access during HDMA (high-speed
DMA) transfers (source addresses bank register:
Extended program area and extended data area
access by the MMU.
As shown in figure 3.4 (1), the TMP90C051F can also use
CLLAR (common local logical address register) of the MMU to
specify common 0, local 0, common 1 and local 1 areas in the
logical area at address 0000H - FFFFH.
Table 3.4 (1) shows in what areas of the logical address
area the above three methods can be used.
Table 3.4 (1) Address Extensions for Each Area of the Logical Area
Logical area
BX, BY
MMU
DMASB0/1, DMADB0/1
Common 0
O
X
O
Local 0
O
O
O
Local 1
O
O
O
Common 1
O
X
O
Figure 3.4 (1). Logical Area Specification
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TMP90C051
i)
Extended data area access using the CPU bank registers
BX and BY
IX, IY, BX and registers
IX and IY are independent 16-bit registers called index
registers. BX and BY are independent 7-bit registers
called bank registers.
These registers are mainly used to specify memory
Extended data area addressing mode
The TMP90C051F can use up to 8M bytes of data
memory.
Addresses 0000000H - 00FFFFH can be accessed in
the normal addressing mode.
Addresses 010000H - 7FFFFFH are called the
extended data area and are accessed in a special
addressing mode.
To access the extended data area, an addressing
mode (a mode that uses the register indirect addressing
mode register pair IX or IY, or a mode that uses the
index addressing mode register pair IX or IY) that uses
the index addressing mode register pair IX or IY to calculate
the operand address.
Thus, there are four types.
(IX)
(IY)
(IX + d)
(IY + d)
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addresses and to generate 23-bit addresses. The IX
and IY registers are also used as 16-bit addition
instruction registers.
The BX and BY registers are assigned to address
FFECH (BX register) and address FFEDH (BY) in the
built-in input/output register area. Only the lower 7 bits
of these registers are effective; the uppermost bit is
undefined. This undefined bit is always read as “1”.
The lower 7 bits of the BX and BY registers are initialized to
“0” by resets.
In these modes, the 23-bit address required for
accessing the extended data area consists of a 16-bit
offset (address bus A0 - A15) and a 7-bit bank
address (address bus A16 - A22).
The 16-bit offset is the same as the calculated value of
the conventional address.
The 7-bit bank address is specified with bank register
BX or BY. BX is used to form a pair in modes that use
the index register IX. BY is used to form a pair in
modes that us the index register IY.
Note:
When the extended data area addressing
mode is used with the JR or CALL instruction, the value of the bank register that corresponds to that index register must be “0”.
These instruction cannot use in expand memory area
at MMU.
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TMP90C051
Example: LD A, (IX)
Memory data 45H at address 062000H is loaded to the A
register.
In the index addressing mode, carries resulting from
calculation of 16-bit offsets are ignored. There is no effect
on the bank registers.
Example: LD A, (IY + 23H)
Memory data 45H at address 060013H is loaded to the A
register.
In addressing modes (modes that do not use index register IX
or IY to calculate the operand address) that do not access the
extended data area, the 7-bit bank register (address bus A16 - A22)
becomes “0” and the address range 000000H - 00FFFFH can
then be accessed.
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Note:
When this addressing mode is used by the
transfer destination, this write cycle is not performed correctly when the actual address is
bank register address FFECH or FFEDH.
Example: LD (IX), 05H when the IX value is FFECH and
BX value is “0”.
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TMP90C051
ii)
Extended data area access during HDMA transfer
During HDMA transfers, memory addresses are indicated
by the values loaded to the HDMA source address register
(DMAS0 and DMAS1) and destination address register
(DMAD0 and DMAD1). For extended data area access,
memory addresses are indicated by the values loaded to
the source bank register (DMASB0 and DMASB1) and
destination bank register (DMADB0 and DMADB1).
Figure 3.4 (2). Source Address/Destination Address Specification During HDMA Transfer
Figure 3.4 (3). Typical HDMA Data Transfer Between Banks (① ~ ②)
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iii)
Program area and data area expansion using the MMU
function
The TMP90C051 offers program area and data area
expansion, depending on the MMU.
• MMU not used : Program area
0 - 64KB
: Data area
0 - 64KB
: When BX and
BY/HDMA are used 0 - 8MB
3.4.2 MMU Functions
The following register expand the 64KB logical memory
capacity (address 0000H - FFFFH) to a maximum of 8MB
(addresses 000000H - 7FFFFFH).
(1) CLLAR: Common Local Logical Address Register
(14-bit)
(2) EXPA0: Local 0 Expand Register (11-bit)
(3) EXPA1: Local 1 Expand Register (11-bit)
• MMU used
: Program area
: Data area
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0 - 8MB
0 - 8MB
CLLAR is used to specify the logical addresses
0000H-FFFFH in the common 0, local 0, local 1and common
1 areas, as shown in Figure 3.4 (1).
EXPA0 is a bank register used to map the local 0 area logical
addresses specified with CLLAR to the physical address
space.
When the program area or data is indicated as being inside
the local 0 area, the EXPA0 value is added to either the current
program address value or memory address value to generate the
physical addresses.
EXPA1 functions in the same way as EXPA0.
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TMP90C051
Figure 3.4 (4). Address Expansion by MMU (4KB units)
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(1)
CLLAR (Common and Local Logical Address Register)
Figure 3.4 (5). Configuration
As shown in Figure 3.4 (5), CLLAR has a 14-bit configuration (8 lower bits and 6 upper bits).
The start addresses of common 0, local 0, local 1 and
common 1 in the logical address area shown in Figure 3.4 (4)
are specified with CLLAR. That is, up to 4 address areas can
be specified with CLLAR.
When the 16-bit transfer instruction is used, LOCS and
COM1 are the upper addresses and LOC1 and LOC0 are the
lower addresses of the CLLAR setting.
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LOCS and COM1, LOC1 and LOC0 can also be set individually with 8-bit transfer instructions.
CLLAR can be read and written with either 8-bit or 16-bit
transfer instructions.
i)
LOCS (local size)
This register specifies the minimum local 0 and local 1
unit (size).
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TMP90C051
ii)
COM1, LOC1 and LOC0 (common and local start
addresses)
These registers specify the 4 upper bits of the start
addresses of common 1, local 1 and local 0 in the
0000H - FFFFH logical address area.
Since the minimum unit for the COM1, LOC1 and
LOC0 areas is determined by LOCS, the start address
of each area is as shown in Figure 3.4 (6).
After a reset, COM1 = EH, LOC = EH and LOC0 = 0H.
Note:
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Setting example: (The minimum unit : 4K byte)
When LOCS = 00H
LOC0 = 01H
LOC1 = 08H
COM1 = 0FH
The minimum unit for the area size is determined by LOCS, and defined by the start
address of each area.
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Figure 3.4 (6). Local Size (LOCS) and Start Address Specification
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TMP90C051
iii)
Address area specification and types
In the logical address area (0000H - FFFFH), the
address areas are set using the common and local register
(CLADR) as shown below. MMU will not operate correctly
if any combination not shown here is used.
Always set the CLADR register to COM1 ≥ LOC1 ≥
LOC0.
Note: COM1, LOC1 and LOC0 are set to match the local size (LOCS) as shown below.
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(2)
EXPA0 (Expand Register 0) and EXPA1 (Expand Register 1)
Figure 3.4 (7). EXP0, EXPA1 Configuration
EXPA0 is set to map the logical address area in local 0
to the physical address area when the local 0 address
area is accessed by the CPU. All bits are set to “0” by
resets.
EXPA1 is set to map the logical address area in local 1
to the physical address area when the local 1 address
area is accessed by the CPU. All bits are set to “0” by
resets.
For both EXPA0 and EXPA1, the 16-bit transfer
instruction loads the upper address bits to A22 - A20
and the lower address bits to A19 - A12. Loading is
also possible with 8-bit transfer instructions.
Both EXPA0 and EXPA1 can be read and written.
Use the common area (in the logical address area) to
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write overwrite EXPA0 and EXPA1. When loading to
the logical address area, the contents of EXPA0 and
EXPA1 are mapped to the physical address area
immediately after the instruction used to load is executed.
Note: When overwriting EXPA0 and EXPA1 in the physical address area, use caution concerning the
addresses in the physical address area to which
the addresses in the current logical address area
are mapped. This is because the addresses are
mapped to a different physical address area
immediately after the instruction used to overwrite is executed.
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TMP90C051
(3)
Physical Address Area Specification
When a program area is located above 64k bytes
(0000H - FFFFH), the logical address area can be
mapped to the physical address area by accessing the
local 0 and local 1 address area specified with the
common and local address register.
When mapping to the physical area, the address is
indicated by adding the values of the local 0 expand
register (EXPA0), local 1 expand register (EXPA1) and
the logical addresses in the local 0 and local 1 area.
When a program is executed in a common area, zeros
are output to A22 - A20 and the logical address is output
to A12 - A15.
Physical address generation
Figure 3.4 (8). Physical Address Generation Using 4k-byte Units
Figure 3.4 (9). Physical Address Generation Using 8k-byte Units
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Figure 3.4 (10). Physical Address Generation Using 16k-byte Units
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3.4.3 MMU Usage (Software)
(1)
Typical MMU Setting
Figure 3.4 (11). After Reset
Figure 3.4 (12). Typical MMU Settings – 1
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Figure 3.4 (13). MMU Settings –2
Figure 3.4 (14). MMU Settings –3
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3.5 Standby Functions
Executing the HALT instruction sets the TMP90C051 to the
RUN, IDLE1 or STOP mode, depending on the contents of the
halt mode setting register. The features are shown below.
(1)
Run:
Only the CPU halts, power consumption
remains the same.
(2)
IDLE:
Only the internal oscillators operate, all others
internal circuitry halts. Power consumption is
1/10 or less of that during operation.
(3)
STOP: All internal circuitry halts, including the
oscillators. Power consumption is extremely
reduced.
The HALT mode setting WDMOD <HLTM1, 0> is
assigned to bits 2 and 3 memory address FFDDH in the built-in
input/output register area (all other bits are used to control other
block functions). The “00” RUN mode is set by resets.
The halt status is released by interrupt requests and
resets. If interrupts are enabled, the CPU receives non-maskable
and maskable interrupts and starts interrupt processing. If
maskable interrupts are disabled, the CPU restarts execution
from the instruction following the HALT instruction but the
interrupt request flag remains at “1”.
If the halt status is released by reset, however, use caution
since the status in effect before entering the halt status cannot
be maintained. In such cases, it is recommended that interrupt requests be used for releasing.
Figure 3.5 (1). Halt Mode Setting Register
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3.5.1 RUN Mode
Figure 3.5 (2) shows the timing used to release halts using
interrupts in the RUN mode.
In the RUN mode, the system clock in the MCU does not
stop after the HALT instruction is executed; the CPU merely
stops executing instructions. That is, the CPU repeats dummy
cycles until the halt status is released. In the halt status, interrupt
requests are sampled at CLK signal falls.
Figure 3.5 (2). Halt Release Timing Using Interrupts in the RUN Mode
*: Halt status can be released with external interrupts (INT1 - INT7) only in the RUN mode.
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TMP90C051
3.5.2 IDLE Mode
Figure 3.5 (3) shows the timing used to release halts with interrupts
in the IDLE mode.
In the IDLE mode, only the internal oscillator operations,
TMP90C051F system clock stops and the CLK signal is fixed
at “1”.
In the halt mode, interrupt requests are sampled asynchronously with the system clock but sampling is performed synchronously when the halt mode is released.
Note: In this mode, only external interrupt (NMI and INT0)
are enabled during the halt interval.
Figure 3.5 (3). Halt Release Timing Using Interrupts in the IDLE Mode
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3.5.3 STOP Mode
In the STOP mode, all internal circuitry stops, including the
internal oscillator. When the STOP mode is activated, all but
certain pins are isolated from TMP90C051F by being set to
high impedance.
All interrupt requests are disabled during the hat interval in
this mode (leave the external non-maskable interrupt pin (NMI)
at the “1” level). Consequently, this mode can only be released
by resetting. Ports with programmable pull-up resistance
remain pulled up.
Table 3.5 shows the status of each pin in the STOP mode.
The status in effect before the halt continues if WDMOD
<DRIVE> (drive enable: bit 0 of memory address FFDDH) of
the built-in input/output register is set to “1”. This register is
cleared to “0” by resets.
The internal oscillator can also be restarted by inputting
the RESET signal “0” to the CPU; however, operation is sometimes
not correct after power-on due to clock instability immediately
after the internal oscillator restarts. When releasing a halt by
resetting in the STOP mode, it is necessary to keep the
RESET signal at “0” for a sufficient time.
The internal oscillator also restarts by entering the RESET
signal “0” to the CPU; however, the warming up counter does
not operate due to quick power-on operation. Because of
clock instability immediately after restarting the internal oscillator,
the CPU may not operate correctly. When releasing a halt by
resetting in STOP mode, the RESET signal must be kept at “0”
for a sufficient time.
Figure 3.5 (4). Halt Release Timing Using Interrupts in the STOP Mode
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Table 3.5 State of Pin in STOP Mode
IN/OUT
DRZVE = 1
AD0 ~ AD7
3 State
–
–
A8 ~ A15
OUT Pin
–
OUT
P20 ~ P26
OUT Pin
–
OUT
P30 ~ P35
OUT Pin
–
OUT
P36 ~ P37
INPUT Mode
OUTPUT Mode
–
–
IN
OUT
P4
INPUT Mode
OUTPUT Mode
–
OUT
IN
OUT
P5
INPUT Mode
OUTPUT Mode
–
OUT
IN
OUT
P6
INPUT Mode
OUTPUT Mode
–
–
IN
OUT
ALE
OUTPUT Pin
“0”
“0”
CLK
OUTPUT Pin
–
“1”
RESET
INPUT Pin
IN
IN
X1
INPUT Pin
–
–
X2
OUTPUT Pin
“1”
“1”
RD
OUTPUT Pin
–
OUT
WR
OUTPUT Pin
–
OUT
WAIT
INPUT Pin
–
IN
NMI
INPUT Pin
IN
IN
INT0
INPUT Pin
IN
IN
INT1 ~ 2
INPUT Pin
-
IN
LATWAIT/RXD0
INPUT Pin
–
IN
TPHSD/TXD0
OUTPUT Pin
–
OUT
TPHCKO/SCLK0
INPUT Mode
OUTPUT Mode
–
–
IN
OUT
TPHCKI/RTS0
INPUT Mode
OUTPUT Mode
–
–
IN
OUT
TPHLAT/CTS0
INPUT Mode
OUTPUT Mode
–
–
IN
OUT
RXD1
INPUT Pin
–
IN
TXD1
OUTPUT Pin
–
OUT
INPUT Mode
OUTPUT Mode
–
–
IN
OUT
SCLK1
RTS1
OUTPUT Pin
–
OUT
CTS1
INPUT Pin
–
IN
BAKEN
INPUT Pin
IN
IN
CXIN
–
:
IN
:
OUT :
IN :
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DRZVE = 0
IN
IN
CXOUT
OUTPUT Pin
INPUT Pin
OUT
OUT
ALARM
OUTPUT Pin
OUT
OUT
Indicates that input mode/input pin cannot be used for input and
that the output mode/output pin have been set to high
impedance.
The input gate is operating. Fix the input voltage at either “0” or
“1” to prevent the pin floating.
The output status.
The input status.
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3.6 Function of Ports
The TMP90C051F contains a of total 31 bits input/output
ports. These ports function not only for the general-purpose I/
O but also for the input/output of the internal CPU and I/O.
Table 3.6 describes the functions of these ports.
Table 3.6 Functions of Ports
Port
name
Pin name
No. of pins
Direction
Direction set
unit
Pin name for internal
function
Port 2
P20
P21
P22
P23
P24
P25
P26
1
1
1
1
1
1
1
Output
Output
Output
Output
Output
Output
Output
–
–
–
–
–
–
–
A16
A17
A18
A19
A20
A21
A22
Port 3
P30
P31
P32
P33
P34
P35
P36
P37
1
1
1
1
1
1
1
1
Output
Output
Output
Output
Output
Output
I/O
I/O
–
–
–
–
–
–
–
–
RAS
CAS
CS
DACT0
DACT1
WDTOUT
INT7
–
Port 4
P40 ~ P43
4
I/O
bit
M00 ~ M03
Port 5
P50 ~ P53
4
I/O
bit
M10 ~ M113
Port 6
P60
P61
P62
P63
P64
P65
P66
P67
1
1
1
1
1
1
1
1
bit
INT3
INT4
INT5
INT6
TI0
TI2
TO0/TO1
TO2/TO3
I/O
These port pins function as the general-purpose input/
output ports by resetting. The port pins, for which input or output
is programmably selectable, function as input ports by resetting.
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A separate program is required to use them for an internal
function.
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TMP90C051
3.6.1 Port (P20 - P26)
Port 2 is a 7-bit general-purpose output port (P2: memory
address FFB4H).
P20 - P26 are used both as output only ports and as the
expansion address bus (A16 - A22). The control register
P2CR: memory address FFB5H) is used to specify which
mode is to be used. Reset operations clear the P20 - P26 output latch and all control register bits to “0” to set P20 - P26 to
the general-purpose output port mode.
Figure 3.6 (1). Port 2 (P20 - P26)
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Figure 3.6 (2). Register for Port 2
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TMP90C051
3.6.2 Port 3 (P30 - P37)
Port 3 is an 8-bit general-purpose I/O port (P3: memory
address FFB6H). P30 - P35 are output only ports; P36 and
P37 are I/O ports. The control register (P3CR: memory
address FFB7H) is used to set P36 and P37 as input or output
ports.
Reset operations set the P30 - P35 output latch to “1”,
and clear the P36 and P37 output latch and all control register
bits to “0” to set P36 and P37 to the input mode.
In addition to the general-purpose I/O port function, there
are also interrupt request input, chip select (CS) and DMA
active (DACT0, DATC1, RAS, CAS, WD6OUT) output
functions.
(1)
P30 - P34
P30 - P34 are used both as general-purpose output
ports for RAS, CAS, CS, DACT0 and DACT1.
RAS, CAS, CS, DACT0 and DACT1 output is set
using bits 0 - 4 of the port 3 function register (P3FR:
memory address FFB8H).
Figure 3.6 (3). Port 3 (P30 - P34)
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TMP90C051
(2)
P35
P35 is used both as a general-purpose output port for
WDTOUT output. Bit 1 of the watchdog timer mode
register (WDMOD: memory address FFDDH) is used to
set P35 for WDTOUT output.
Figure 3.6 (4) Port 3 (P35)
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TMP90C051
(3)
P36
for external interrupt request input INT7.
P36 is used both as a general-purpose I/O port and
Figure 3.6 (5). Port 3 (P36)
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TMP90C051
(4)
P37
Port 37 is a general-purpose I/O port.
Figure 3.6 (6). Port 3 (P37)
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TMP90C051
Figure 3.6 (7). Registers for Port 3
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TMP90C051
3.6.3 Port 4 (P40 - P43)
Port 4 is a 4-bit general-purpose I/O port (P4: memory
address FFB9H), each bit of which can be set individually for
input or output. The control register (bits 0 - 3 of P45CR: memory
address FFBBH) is used to set the bits for input or output. Reset
operations clear this control register to “0” to set port 4 to the
input mode.
This port is also used as stepping motor control/pattern
generation port 0 (M00 - M03). The function register (bits 0 - 3
of P45FR: memory address FFBCH) is used to select generalpurpose I/O port or stepping motor control/pattern generation
port. Reset operations set port 4 to the general-purpose I/O mode.
Figure 3.6 (8). Port 4
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3.6.4 Port 5 (P50 - P53)
Port 5 is a 4-bit general-purpose I/O port (P5: memory
address FFBAH), each bit of which can be set individually for
input or output. The control register (bits 4 - 7 of P45CR: memory
address FFBBH) is used to set the bits for input or output.
Reset operations clear this control register to “0” to set port 5
to the input mode.
This port is also used as stepping motor control/pattern
generation port 1 (M10 - M13). The function register (bits 4 - 7
of P45FR: memory address FFBCH) is used to select generalpurpose I/O port or stepping motor control/pattern generation
port. Reset operations set port 5 to the general-purpose I/O mode.
Figure 3.6 (9). Port 5
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Figure 3.6 (10). Registers for Port 4, 5
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TMP90C051
3.6.5 Port 6 (P60 - P67)
Port 6 is an 8-bit general-purpose I/O port (P6: memory
address FFBDH), each bit of which can be set individually for
input or output. The control register (P6CR: memory address
FFBEH) is used to set the bits for input or output.
Reset operations clear all bits of the output latch and control
register to “0” to set port 6 to the input mode.
In addition to its general-purpose I/O port function, port 6
also has interrupt request input, time clock input and timer
output functions that can be specified with the port 6 function
register (P6FR: memory address FFBFH).
(1)
P60 - P63
P60 - P63 are also used for external interrupt request
input (INT3 - I NT6).
Figure 3.6 (11). Port 6 (P60 - P63)
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(2)
P64 - P65
P64 and P65 are also used for 8-bit timer clock input.
Figure 3.6 (12). Port 6 (P64 - P65)
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TMP90C051
(3)
P66 - P67
timer output.
P66 and P67 are also used for 8-bit timer 0/1, 2/3
Figure 3.6 (13). Port 6 (P66 - P67)
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Figure 3.6 (14). Register of Port 6
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TMP90C051
3.7 Stepping Motor Control/Pattern Generation Port (P4,
P5)
The TMP90C051F has a built-in, timer-coupled, 4-bit, 2-channel
(M0 and M1) hardware stepping motor control/pattern generation
port (hereafter called SMC). SMC (M0 and M1) is also used as
4-bit input/output ports P4 and P5.
Channel 0 (M0) is coupled to 8-bit timer 0 or timer 1, and
channel 1 (M1) is coupled to 8-bit timer 2 or timer 3, to alter
output.
SMC is controlled by two control registers (P45CR and
P45FR) and is used to select the stepping motor control mode
and pattern generation mode.
3.7.1 Control Registers
(1)
Ports 4 and 5 Function Control Register (P45FR)
This register is used to set ports 4 and 5 for use as
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(3)
Port 4
This is a 4-bit input/output port assigned to address
FFB9.
The 4 lower bits correspond to port 4 and the 4 upper
bits are a shift alternate register P4 <SA43 ~ 40>
used to drive the stepping motor in the pattern generation mode of with 1-2 excitations.
Ports 4 and 5 Input/Output Specification Register
(P45CR)
This register is specifies 4-bit input/output port 5 input
and output in 1-bit units. All P45CR bits are cleared to
“0” by resets, which sets ports 4 and 5 for input. To
use ports 4 and 5 as SMC, set all P45CR bits to “1”
for output.
The P45CR register can only be written, and cannot
be read.
(2)
SMC. To use ports 4 and 5 as SMC, set P45FR
<M0S, M1S> and P45FR4 (M1S) to “1”.
SMC is set to the 8-bit write mode or 4-bit write mode
with P45FR <PAT0> and P45FR <PAT1>. When writing to SMC in the 4-bit write mode, it is only possible
to write to the 4-bit shift alternate register and SMC functions as the pattern generation port.
To use SMC as the stepping motor control port, the
method of excitation is selected with P45FR <M0M>
and P45FR <M1M>; P45FR <CCW0> and P45FR <
CCW1> control the direction of rotation.
(4)
Port 5
This is a 4-bit input/output port assigned to address
FFBA.
The 4 lower bits correspond to port 5, and the 4 upper
bits are a shift alternate register P5 <SA53 ~ 50> used
to drive the stepping motor in the pattern generation mode
of with 1-2 excitations.
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TMP90C051
Figure 3.7 (1). Ports 4, 5 Input/Output Specification Register (P45CR)
Figure 3.7 (2a). Port 4 and 5 Function Control Register (P45FR)
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TMP90C051
Figure 3.7 (2b). Port 4 and 5 Function Control Register (P45FR)
Figure 3.7 (3). Port 4 and 5
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TMP90C051
3.7.2 Pattern Generation Mode
SMC can be set to function as a pattern generation port with
bits 3 and 7 (PAT0 and PAT1) of P45FR. In the mode, the CPU
writes only to the shift alternate register; therefore, during shift
trigger timer interrupt processing, it is possible to write to ports
4 and 5, and to output patterns in real time by coupling with
the timer.
In this mode, it is also necessary to always set P45FR1
and P45FR5 (M0M and M1M) to “1”.
Figure 3.7 (4) shows the mode block diagram.
Figure 3.7 (4). Pattern Generation Mode Block Diagram (Port 4)
In this pattern generation mode, only writing to the output
latch is disabled by the hardware. All other operations are the
same as for 1-2 excitations in the stepping motor control port
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mode. Consequently, after a trigger signal from the timer, it is
always necessary to write data before the next trigger signal is
generated.
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TMP90C051
3.7.3 Stepping Motor Control Mode
(1)
Figure 3.7 (5) and (6) show the channel 0 output waveforms
for 4-phase 1-excitation and 4-phase 2-excitation.
4-Phase 1-Excitation/2-Excitation
Figure 3.7 (5). 4-phase, 1-Excitation Output Waveform (Forward/Reverse)
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TMP90C051
Figure 3.7 (6). 4-Phase, 2-Excitation Output Waveform (Forward)
The following is an explanation of channel 0 operation.
The M0 (also used P4) output latch is shifted and output
to the port at the rise of the trigger signal from the timer.
The shift direction is set with P45FR5 (CCW0). The direction of rotation is forward when CCW0 is “0”, and is reverse
(M00← M01←M02 ←M03) when CCW0 is “1”. Setting only
one bit to “1” when making the port 4 initial setting sets 4-phase,
1-excitation; setting 2 consecutive bits to “1” sets 4-phase, 2excitation.
Figure 3.7 (7) shows the block diagram.
Figure 3.7 (7). 4-Phase, 2-Excitation (Forward) Block Diagram
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(2)
4-Phase, 2-Excitation
Figure 3.7 (8) shows the channel 0 4-phase, 2-excitation output waveform
Figure 3.7 (8). 4-Phase, 1-2 Excitation Output Waveform (Forward/Reverse)
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TMP90C051
The 4-phase, 1-2 excitation settings are as shown below.
Intial value
When the initial value is rearranged as, 3 consecutive bits
are set to “1” and the others to “0” (positive logic).
For example, if b3, b7 and b2 are “1”, the initial value is
10001100 and the waveform shown in Figure 3.7 (8) is
obtained.
To obtain a negative logic output waveform, reverse the
“1s” and “0s” of the initial value. For example, to obtain the
waveform shown in Figure 3.7 (8) with negative logic, the initial
value must be 01110011.
The following is an explanation of channel 0 operation.
The M0 (also used as P4) output latch and stepping motor
control shift alternate register (SA4) is shifted and output to the
port at the rise of the trigger signal from the timer. The shift
direction is set with P45FR <CCW0>.
Figure 3.7 (9) shows the block diagram.
Figure 3.7 (9). 4-Phase, 1-2 Excitation (Forward) Block Diagram
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Setting example:
Setting the registers as shown below
when driving channel 0 (M0) with timer
3.7.4 Timer Trigger Signals
The trigger signals used with SMC are not the same as the
0 at 4-phase, 1-2 excitations.
timer flip-flop (TFF1, 3) inversion trigger signals, but differ as
shown in Table 3.7 (1) depending on the timer operation mode.
Table 3.7 (1) Using 8-bit timers 0 and 1 (same for timers 2 and 3)
TFF1 Inversion
Note:
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SMC shift
8-bit timer mode
Selected with TFFCR0 (FF1IS) when the up counter matches TREG0 or
TREG1.
←
16-bit timer mode
Selected when the up counter matches both TREG0 and TREG1 (up counter
value = TREG*28 + TREG0).
←
PPG output mode
Selected when the up counter matches TREG0 and TREG1, respectively.
Selected when the up counter matches TREG1 (PPG cycle).
PWM output mode
Selected when the up counter matches TREG0.
The SMC shift trigger signal is not generated.
It is necessary to TFFCR1 (FF1IE) to “1” and enable TFF1 inversion when SMC is shifted.
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TMP90C051
3.7.5 SMC and Timer Output Application
As was explained in “3.7.4 Timer Trigger Signal”, SMC shift
and TFF inversion timing differ depending on the timer mode.
The following is a description of a typical application in which
SMC is operated while the 8-bit timer is operated in the PPG
output mode.
When driving a stepping motor, a sync signal at the excitation
switchover timing is often necessary together with each phase
value (SMC output). In view of this, in this application the port 4
is used as the stepping motor control port and the sync clock
is output to TO1 (also used as P61).
4-phase, 1-Excitation Output Waveform
Setting example:
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TMP90C051
3.8 Timers
The TMP90C051F has four 8-bit timers (timers 0, 1, 2 and
3).
These four 8-bit timers can be operated independently
or cascade connected to form two 16-bit timers. These 8-bit
timers have the following four operation modes.
• 8-bit internal timer modes (4) } Can be combined
• 16-bit interval timer modes (2) } (8 bits x 2, 16 bits x 1)
• 8-bit programmable square wave (PPG: variable duty
at fixed interval) (2).
• 8-bit PWM (pulse width modulation: variable duty at
fixed interval) output modes (2)
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Figure 3.8 (1) shows the 8-bit timer (timers 0 and 1)
block diagram.
Timers 2 and 3 have the same circuit configuration as
timers 0 and 1.
The configuration of each interval timer consists of an 8bit up counter.
8-bit comparator and 8-bit timer register. Timer flipflops
(TFF1 and TFF3) are available for the timer 0 and 1 pair, and
the timer 2 and 3 pair. The internal clocks øT1, øT4, øT16
and øT256 used as the input clocks to the interval timers are
obtained from the 9-bit prescaler shown in Figure 3.6 (2).
The operating modes and timer flipflops for the 8-bit timers are controlled by 5 control registers (TO1MOD, T23MOD,
TFFCR, TRUN and TRDC).
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Figure 3.8 (1). Timer Block Diagram (Timers 0 and 1)
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➀ Prescaler
This 9-bit prescaler generates the clocks used for
input to the 8-bit timers and baud rate generator, TPH
serial I/F by further dividing the fundamental clock after
it has been divided by 4 (fc/4)
The four clock øT1, øT4, øT16 and øT256 are used for
the 8-bit timers.
This prescaler can be enabled/disabled with the 5th
bit TRUN <PRRUN> of the timer operation control
register (TRUN). Setting <PRRUN> to “1” starts counting and setting it to “0” clears and stops the timer.
Resets clear <PRRUN> to “0”, so the prescaler is
cleared and stopped.
Figure 3.8 (2). Prescaler
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TMP90C051
➁ Up-counter
➂ Timer register
This is an 8-bit binary counter that counts up in accordance
with the input clock specified with the timer 0 and 1
mode register (T01MOD) and timer 2 and 3 mode register
(T23MOD).
The timer 0/timer 2 input clock can be selected from
external clocks (TI0 and TI2) and the three internal
clocks øT1, øT4 and øT16 by setting the T01MOD/
T23MOD registers.
The timer 1/timer 3 input clock differs depending on
the operating mode. In the 16-bit timer mode, the
timer 0/timer 2 output overflow is used as the input
clock.
In other than the 16-bit timer mode, the input clock is
selected from the internal clocks øT1, øT16 and
øT256 by setting the T01MOD/T23MOD registers, and
the timer 0/timer 1 comparator output (match detection).
These are 8-bit registers used to set interval times.
When the values to which the timer registers (TREG0/
TREG1 and TREG2/TREG3) are set and the up
counter value match, the comparator match detect
signal becomes active. When the setting value is 00H,
the match detect signal becomes active in case of an
up counter overflow.
Timer registers TREG0/TREG2 have a double-buffer
configuration and these registers and buffers are used
as pairs.
The TREG0/TREG2 double buffer is enabled and disabled
with <TR0DE> and <TR2DE> of the timer register
double buffer control register (TRDC). The double
buffer is disabled when <TR0DE>/<TR2DE> = “0” and
enabled when <TR0DE>/<TR2DE> = “1”.
The timing for data transfers from a register buffer to a
timer register when double buffer has been enabled is
determined by compare matching of PWM mode 2n - 1
overflow or PPG mode cycle.
<TR0DE>/<TR2DE> are initialized to “0” by resets,
which disable double buffers. When using a double
buffer, write data to the timer register, set <TR0DE>/
<TR2DE> to “1” and then write the following data to
the register buffer.
Examples: If T01MOD <T10M1, 0> = 01, the timer 0
overflow output is used as the timer 1
input clock (16-bit timer).
If T01MOD <T10M1, 0> = 00, and
T01MOD <T1CLK1, 0> = 01, øT1 (8/fc) is
used as the timer 1 input clock (8-bit
timer).
The operating mode is also set using the T01MOD/
T23MOD registers. <T10M1, 0> and T23M1, 0> are
initialized to “00” by resets. This sets the 8-bit timer
mode.
Concerning the up counters, each interval timer can
be enabled, disabled or cleared with timer operation control register TRUN. All counters are cleared and timers
are stopped by resets.
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Figure 3.8 (3). Timer Register 0, 2 Configuration
Note:
The timer registers and register buffers
are assigned to the same memory
addresses.
When <TR0DE>/<TR2DE> = 0, the same values are
written to the register buffers and timer registers.
When <TR0DE>/<TR2DE> = 1, values are written only
to the register buffers.
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The timer register memory addresses are as follows.
TREG0:
TREG1:
TREG2:
TREG3:
FFC0H
FFC1H
FFC2H
FFC3H
These are write-only registers.
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Figure 3.8 (4). Timer 0/1 Mode Register (T01MOD)
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Figure 3.8 (5). Timer 2/3 Mode Register (T23MOD)
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Figure 3.8 (6). 8-bit Timer Flip-flop Control Register (TFFCR)
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Figure 3.8 (7). Timer Operation Control Register (TRUN)
Figure 3.8 (8). Timer Register Double Buffer Control Register (TRDC)
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➃ Comparator
The following explains the operation of the 8-bit timers.
When a comparison of the up counter value and timer
register values shows a match, the up counter is
cleared to “0” and an interrupt (INTT0-INTT3) is generated. If
timer flip-flop inversion is enabled, the timer flip-flop value
is inverted at the same time.
(1)
8-Bit Timer Mode
The four 8-bit interval timers 0, 1, 2 and 3 can be used
independently. The operation is the same for all and
timer 1 will be used for explanatory purposes.
➄ Timer Flip-flop
➀ When interrupts are generated in a fixed cycle
This flip-flop is inverted by the interval timer match
detect signals (comparator output) and the value can
be output to the timer output pins TO1 (also used a
P66) and TO3 (also used as P67).
One each of these timer flip-flops is provided for the
timer 0/1 pair and the timer 2/3 pair. These timer flipflops are called TFF1 and TFF3. TFF1 outputs to TO1
and TFF3 outputs to TO3.
To use timer 1 for generating interrupts (INTT1) in a
fixed cycle, first stop timer 1 and then load the operation
mode, input clock and cycle to the T01MOD TREG1 registers. Next, enable interrupt INTT1 and then start timer
1 counting.
Example:
Use the following procedure to load the
registers to generate timer 1 interrupts
every 40 microseconds at fc = 16MHz.
Refer to the table below concerning input clock selection
Table 3.8 (1) Interrupt Cycle and Input Clock Selection Using an 8-Bit Timer
Interrupt cycle (@fc = 16MHz)
Resolution
Input clock
0.5µs ~ 128µs
2 µs ~ 512µs
8 µs ~ 2.048ms
128 µs ~ 32.768ms
0.5 µs
2 µs
8 µs
128 µs
øT1 (8/fc)
øT4 (32/fc)
øT16 (8128/fc)
øT256 (2048/fc)
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➁ Outputting a 50% duty square waveform
Invert the timer flipflop at a fixed cycle and output the
timer flipflop value to the timer output pin (TO1).
Example:
Use the following procedure to load the
registers to output a square waveform
from the TO1 pin in a 3.0 microsecond
cycle at fc = 16MHz. Timers 0 and 1 are
used in this case but timer 1 will be used
here for explanatory purposes.
Figure 3.8 (9). Square Waveform (50% Duty) Output Timing Chart
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➂ Starting timer 1 counting with timer 0 match output
output as the timer 1 input clock.
Set the 8-bit timer mode and set the timer 0 comparator
Figure 3.8 (10)
➃ Output inversion with software
The timer flipflop value can be inverted regardless of
timer operation.
Writing 00 to FF1C (bit 3 and 2 of TFFCR at memory
address FFC6) inverts the TFF1 value. Writing 00 to
FF3C (bits 7 and 6 of TFFCR at memory address
FF3C) inverts the TFF3 value.
➄ Timer Flipflop initial setting
The timer flipflop initial value can be set to either “0” or
“1” regardless of timer operation.
For example, write 10 to FF1C (bits 3 and 2 of TFFCR)
at memory address FF1C to set TFF1 to “0” and write
01 to memory address FF1C to set TFF1 to “1”.
Note:
(2)
16-Bit Timer Mode
16-bit interval timers can be created by using timers 0
and 1 as a pair and timers 2 and 3 as a pair.
Timers 0 and 1, and timers 2 and 3 have the same
operation, so timers 0 and 1 are used here for explanatory
purposes.
Cascade connect timers 0 and 1 and set bits 7 and 6
of the timer 0 and 1 mode register T01MOD to “00” to
enable use as a 16-bit interval timer.
When the 16-bit timer mode is set, the timer 0 overflow is used as the timer 1 input clock regardless of the
T1CLK (bits 3 and 2 of T01MOD) setting value. Table
3.8 (2) shows the relationship between timer (interrupt)
cycles and input clock selection.
Timer Flipflop and timer register values cannot
be read.
Table 3.8 (2) 16-Bit Timer (Interrupt) Cycle and Input Clock Selection
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Interrupt cycle (@fc = 16MHz)
Resolution
Input clock
0.5 µs ~ 32.768ms
0.5µs
øT1
2 µs ~ 131.072ms
2 µs
øT4
8 µs ~ 524.288ms
2 µs
øT16
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The timer (interrupt) cycle is set by loading the 8 lower
bits to timer register TREG0 and the 8 upper bits to
timer register TREG1. In this case, always set TREG0
first. (Comparison is temporarily halted by writing data
to TREG0 and comparison is started by writing data to
TREG1.)
Setting example: To generate the interrupt INTT1
every 0.5s at fc = 16MHz, load the
following values to TREG0 and
TREG1.
When counting using øT16 (= 8µs
@16MHz),
0.5s ÷ 8µs = 62500 = F424H
therefore, set TREG1 = F4H,
TREG0 = 24H.
The timer 0 comparator match detect signal is output
each time the time counter UC0 and TREG0 values
match; however, up counter UC0 is not cleared.
When the timer 1 comparator match detect signal is
output at each comparator timing cycle, if up counter
UC1 and TREG1 match, up counters UC0 and UC1
are cleared to “0” when the match detect signals of
both timer 0 and 1 comparator are output at the same
time, and interrupt INTT1 is generated. If inversion is
enabled, the value of the timer flipflop TFF1 is inverted.
Example: When TREG1 = 04H, TREG0 = 80H
Figure 3.8 (11)
(3)
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8-bit PPG (Programmable Square Waveform) Output Mode
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TMP90C051
Timer 0 of timer 2 can be used to output square waveforms of optional frequency and optional duty. The output
pulses can be either low-active or high-active. Timers 0
and 3 cannot be used when this mode is set.
When timer 0 is used, the output goes to TO1 (also
used as P66) and when timer 2 is used, the output
goes to TO3 (also used as P67).
Timer 0 will be used for explanatory purposes. (Operation
is the same with timer 2.)
This mode outputs a programmable square waveform
by inverting the timer output each time the 8-bit up
counter 0 (UC0) matches timer registers (TREG0 and
TREG1.
It is necessary, however, to satisfy the condition
(TREG0 setting value) < (TREG1 setting value).
The timer 1 up counter (UC1) cannot be used in this
mode but timer 1 can be used for counting by setting
TRUN <T1RUN> = 1.
Figure 3.8 (12) shows the block diagram for this mode.
Figure 3.8 (12). 8-Bit PPG Output Mode Block Diagram
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In this mode, the register buffer value is shifted in to
TREG0 by TREG1 and UC0 matching when TREG0 is
enabled as a double buffer.
Example: Outputting a 1/4 duty 50kHz pulse (@fc =
16MHz)
A double buffer facilitates small duties (when changing
the duty).
• Determining timer register setting values
The frequency is set to 50kHz by making
a t = 1/50kHz = 20µs waveform.
When øT1 = 0.5µs (@16MHz) is used 20µs ÷ 0.5µs = 40
therefore, timer register 0 (TREG0) is set to 10 = 0AH.
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(4)
8-bit PWM output mode
Only timers 0 and 2 can be used in this mode. Up to
two 8-bit resolution PWM outputs are possible (PWM0
and PWM2).
When timer 0 is used, the PWM waveform is output to
TO1 (also used as P66) and when timer 2 is used, the
PWM waveform is output to TO3 (also used as P67).
Timer 0 (PWM0) is used for explanatory purposes.
(Operation is the same for timer 2).
Timer output is inverted when the up counter (UC0)
matches the timer register TREG0 value and 2n - 1
(set to n = 6, 7 or 8 with the T01MOD register) counter
overflows. Up counter UC0 is cleared by 2n - 1
counter overflows.
The following conditions must be satisfied when the
PWM mode is used.
(Timer register setting value) < (2n - 1 counter overflow
setting value)
(timer register setting value) ≠ 0
Figure 3.8 (13) shows the block diagram for this mode
Figure 3.8 (13). 8-Bit PWM Output Mode Block Diagram
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In this mode, the register buffer value is shifted in to
TREG0 by 2n - 1 overflow detection when the TREG0 double
Example: Outputting the PWM waveform shown below
to the TO1 pin using timer 0 at fc = 16MHz.
buffer is enabled.
A double buffer facilitates small duties.
Setting a PWM cycle of 63.5 with µs øT1 = 0.5µs (@fc =
16MHz)
63.5µs ÷ 0.5µs = 127 = 27- 1
Thus, n = 7 is set.
The “LOW” level cycle is 36µs; therefore, at øT1 = 0.5µs
36µs ÷ 0.5µs=72 = 48H is loaded to TREG0.
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TMP90C051
Table 3.8 (3) PWM Cycle and Selection of 2n - 1 Counter
PWM cycle
(@fc = 122.5MHz)
øT4
øT16
øT1
øT4
øT16
2 -1
40.3µs
161µs
645µs
31.5µs
126µs
504µs
27 - 1
81.2µs
325µs
1.30ms
63.5µs
254µs
1.01ms
28 - 1
163µs
652µs
2.61ms
127µs
510µs
2.04ms
6
(5)
øT1
PWM cycle (@fc = 16MHz
Table 3.8 (4) Shows the Settings for Each 8-bit Timer Mode
Table 3.8 (4) Setting Register for Each Timer Mode
Register
T01MOD (T23MOD)
TFFCR
Bit Name
T10M
(T23M)
PWM0
(PWM2)
T1CLK (T3CLK)
T0CLK
(T2CLK)
FF1IS
(FF3IS)
Function
Timer mode
PWM cycle
Upper timer input
clock
lower timer
input clock
reverse signal selection
of timer F/F
01
–
–
External, øT1, øT4,
øT16,
(01, 10, 11)
–
External, øT1, øT4,
øT16,
(00, 01, 10, 11)
0: lower timer output
1: upper timer output
16-bit timer mode
8-bit timer x 2ch
8-bit PPG x 1ch
00
–
–
External, øT1, øT4,
øT16,
(00, 01, 10, 11)
10
–
–
–
8-bit PWM x 1ch
11
26 - 1, 27 - 1, 28 - 1
(01, 10, 11)
–
External, øT1, øT4,
øT16,
(00, 01, 10, 11)
–
8-bit timer x 1 ch
11
–
øT1, øT16, øT256,
(01, 10, 11)
–
Output
disenable
(Note) –: Don’t care
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3.9 Serial Channels
The TMP90C051F has two built-in serial input channels (CH0
and CH1) for full-duplex asynchronous communication (UART)
and input/output extension. Operation is the same for both
channels, so channel 0 will be used for explanatory purposes.
The serial channels have the following operation modes.
A parity bit can be added in modes 1 and 2. Mode 3 has
a wake-up function with which the master controller starts the
slave controller with a serial link (multi-controller system).
Figure 3.9 (1) shows the data format (1 frame) for each
mode.
Figure 3.9 (1). Data Formats
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The serial channels have buffer registers for the temporary
storage of transmit and receive data; therefore, transmitting
and receiving can be performed independently (full duplex).
In the input/output interface mode, however, the SCLK
(serial clock) pin is used for both transmitting and receiving, so
only half duplex operation is possible.
The receive buffer register has a double buffer construction
to prevent overflow errors and has a one frame margin until the
CPU reads the received data. That is, one buffer stores the
data already received and the other buffer receives the next
frame data.
In the UART mode, a check function has been added that
prevents the receive operation being started by mistake by the
start bit due to noise. The start bit is sampled three times and
the receive operation is started only when a normal start bit is
detected at least two times.
The INTTX interrupt is generated when the transmit buffer
is empty and a request for the next data to be sent is sent to
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the CPU. The INTRX interrupt is generated when data are
stored in the receive buffer and a read request is sent to the
CPU. The flags (SCCR <OERR, PERR, FERR>) are set when
an overrun error, parity error or framing error occurs during the
receive operation.
In the input/output interface mode, sync signal (SCLK)
input is also possible and data can be sent and received using
an external clock. (Note)
The serial channels have a dedicated built-in baud rate
generator. Any desired baud rate can be set by dividing by 2 - 16
4 clocks (øT0, øT2, øT8, øT32) from the prescaler (also used
for the 8-/16-bit timers).
Note: When transmitting and receiving using serial channel 0
in the input/output interface mode with external clock
input, an external circuit and control are required for
the SCLK0 pin. This circuit and control are shown
below.
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3.9.1 Control Registers
All serial channels are controlled by 4 control registers
(SCMOD, SCCR, BRGCR and P2FR). Transmit and receive
data are stored to the SCBUF register.
Figure 3.9 (2). Serial Channel Mode Register (SCMOD0/1)
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Figure 3.9 (3). Serial Channel Mode Register (SCCR0/1)
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Figure 3.9 (4). Serial Transmit/Receive Buffer Register (SCBUF0/1)
Figure 3.9 (5). Baud Rate Generator Control Register (BRGCR0/1)
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Figure 3.9 (6). Port 2 Function Register (P2FR)
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3.9.2 Configuration
Figure 3.9 (7) shows the serial channel (channel 0) block dia-
gram.
Channels 0 and 1 have the same circuit configuration.
Figure 3.9 (7). Serial Channel (Channel 0) Block Diagram
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➀ Baud rate generator
The relationship to the input clock fundamental clock
(fc) is as follows.
The baud rate generator is a circuit that generates the
transmit/receive clocks that determine the transfer
speed of the serial channels.
øT0 (fc/4), øT2 (fc/16), øT8 (fc/64) and øT32 (fc/256)
from the 9-bit prescaler also used as a timer are used
as the baud rate generator input clocks. The input
clocks are selected by setting bits 5 and 4 (BG1, 0) of
the baud rate generator control register BRGCR.
The baud rate generator has a built-in 4-bit divider.
This divider determines the transfer speed by dividing
by 2 ~ 16.
Next is the method used to calculate the baud rate
when the baud rate generator is used.
øT0 = fc/4
øT2 = fc/16
øT8 = fc/64
øT32= fc/256
Consequently, with a fundamental clock of fc =
12.288MHz, input clock øT2 (fc/16), and divider value
of 5, the UART mode baud rate is as follows.
• UART mode
= 12.288 x 106 ÷ 16 ÷ 5 ÷ 16 = 9600 (bps)
Table 3.9 (1) shows a typical UART mode baud rate.
The serial channel baud rate can also be determined
using the 8-bit timer 2. Table 3.9 (2) shows a typical baud rate
determined using timer 2.
• Input/output interface mode
Table 3.9 (1) Baud Rate Selection (1) (Using the Baud Rate Generator) Unit: Kbps
Input clock
Divide value
øT0
(fc/4)
øT2
(fc/16)
øT8
(fc/64)
øT32
(fc/256)
9.8304MHz
–
2457.6
614.4
153.6
38.4
–
2
76.8
19.2
4.8
1.2
–
4
38.4
9.6
2.4
0.6
–
8
19.2
4.8
1.2
0.3
–
16
9.6
2.4
0.6
0.15
12.288MHz
–
3072.0
786.0
192.0
48.0
–
5
38.4
9.6
2.4
0.6
–
10
19.2
4.8
1.2
0.3
14.7456MHz
–
3686.4
921.6
230.4
57.6
–
3
76.8
19.2
4.8
1.2
–
6
38.4
9.6
2.4
0.6
–
12
19.2
4.8
1.2
0.3
FC
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Table 3.9 (2) Baud Rate Selection (2) (Using Timer: Input CLK øT1) Unit: Kbps
fc
TREG2
12.288
MHz
12
MHz
9.8304
MHz
8
MHz
6.144
MHz
1H
96
–
76.8
62.5
48
2H
48
–
38.4
31.25
24
3H
32
31.25
–
–
16
4H
24
–
19.2
–
12
5H
19.2
–
–
–
9.6
8H
12
–
9.6
–
6
AH
9.6
–
–
–
4.8
10H
6
–
4.8
–
3
14H
4.8
–
–
–
2.4
Baud rate calculation method (using timer 2)
➂ Receive counter
➁ Serial clock generation circuit
The receive counter is a 4-bit binary counter used in
the asynchronous communication (UART) mode and
is counted up by SIOCLK. 16 SIOCLK clocks are
used to receive 1 bit of data and the data are sampled
at the 7th, 8th and 9th clocks.
The receive data are identified by majority logic by
sampling 3 times. For example, if the data 1, 0, 1 are
sampled by the 7th, 8th and 9th clocks, the data is
identified as “1”. If the values 0, 0, 1 are sampled, the
data is identified as “0”.
This circuit generates the basic transmit/receive clock.
➃ Receive control block
1) Input/output interface mode
1) Input/output interface mode
In the SCCR0 <IOC0> = “1” SCLK0 output mode, the
output from the baud rate generator as described
above is divided by 2 to make the basic clock.
In the SCCR0 <IOC0> = “1” SCLK0 input mode,
either the rise or fall edge, as set with the SCCR0
<SCLK0> register, is detected to make the basic
clock.
In the SCCR0 <IOC0> = “0” SCLK0 output mode, the
RxD0 pin is sampled at the rise of the shift clock output to
the SCLK0 pin.
In the SCCR0 <IOC0> = “1” SCLK0 input mode, the
RxD0 pin is sampled at the rise/fall of the SCLK0 input
in accordance with the setting of the SCCR0 <IOC0>
register.
2) Asynchronous communication (UART) mode
2) Asynchronous communication (UART) mode
Either the baud rate generator clock described above,
the internal clock 1 (312.5k-baud @ 10MHz), or the
match detect signal from timer 2 is selected, as determined
by the SCMOD <SC01, 00> register settings, to make
the basic clock (SIOCLK).
The receive control block has a start bit detection circuit
that used majority logic. If “0” is detected twice or
more by sampling three times, the start bit is judged to
be correct and receiving starts.
Receive data are identified by majority logic even while
receiving data.
Input CLK of timer 2
øT1 = fc/8
øT4 = fc/32
øT16 = fc/128
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➄ Receive buffers
The receive buffers have a redundant construction to
prevent overruns. Receive data are stored 1 bit at a
time to receive buffer 1 (shift register type). When 7 or
8 bits of data have been stored, the are shifted to the
other receive buffer (SCBUF0) and interrupt INTRX is
generated. The CPU reads receive buffer 2 (SCBUF0).
The next receive data can be stored to receive buffer 1
even before the CPU reads receive buffer 2 (SCBUF0).
However an overrun error will occur unless receive
buffer 2 (SCBUF0) is read before all bits of the next
data have been received by receive buffer 1. If an overrun
error occurs, the contents of receive buffer 2 and
RB08 are held but the contents of receive buffer 1 are
lost.
In the case of 8-bit UART with parity, the parity bit is
stored to SCCR07 (RB08). In the case of 9-bit UART,
the uppermost bit is stored to SCCR0 <RB08>.
In the case of 9-bit UART, wake-up operation of the
slave controller can be enabled by setting SCMOD0
<WU0> to “1”. After that, interrupt INTRX will be generated only when RB08 = 1.
➅ Transmit counter
The transmit counter is a 4-bit binary counter used in
the asynchronous communication (UART) mode and,
like the receive counter, is counted up by SIOCLK. The
transmit clock TXDCLK is generated every 16 clocks.
➆ Transmit control block
Hand-shake function
1) Input/output interface mode
The TMP90C051F supports a hand-shake function by
the connection of CTS0 and RTS0 of the other
TMP90C051F.
The hand-shake function allows receiving/transmitting
data on a frame basis to prevent overrun errors. This
function is enabled or disabled by the control register
SCMOD0 <CTSE0>.
When the last bit (parity bit or MSB) of 1-frame data is
received by the receiving unit, the RTS0 pin turns to
the “H” level to request the transmission unit to halt
transmission.
When the CTS0 pin turned to the “H” level, the transmission unit halts transmission, after completing the
current data transmission, until the pin turns to the “L”
level. At this time, the interrupt INTTX is generated, to
request the CPU to transfer data. Then the data is written into the transmission buffer, and the transmission
unit is placed in the standby until the CTS0 pin turned
to the “L” level.
When the received data are read by the CPU, the
RTS0 pin returns to the “L” level, requesting that the
transmission is restarted.
In the SCCR0 <IOC0> = “0” SCLK0 output mode, the
transmit buffer data are output to the TxD0 pin one bit
at a time at the rise of the shift clock output to the
SCLK0 pin.
In the SCCR0 <IOC0> = “1” SCLK0 input mode, the
transmit buffer data are output to the TxD0 pin one bit
at a time at the rise/fall of the SCLK0 input in accordance
with the setting of the SCCR01(SCLK0) register.
2) Asynchronous communication (UART) mode
When the CPU writes transmit data to the transmit
buffer, transmitting starts from the next TxDCLK rise
edge to make the transmit shift clock TxDSFT.
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Figure 3.9 (8). Hand-shake Function
Figure 3.9 (9). Timing Chart of RTS (request to send) Signal
Note:
1) A Rise of the CTS0 signal during the data transmission halts the transmission of the next data after the current data transmission.
2) The transmisison is restarted from the first fall of TXDCLK after a fall of the CTS0 signal.
Figure 3.9 (10). Hand-shake by CTS (clear to send) Signal
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⑧ Transmission buffer
The transmission buffer SCBUF shifts out the data
written by the CPU from the LSB as based on the shift
clock TXDSFT (same period as TXDCLK) generated by
the transmission control unit. When all bits are shifted
out, the transmission buffer becomes empty, generating
the interrupt INTTX.
to the receiving buffer 2 (SCBUF0) is compared with
the parity bit received from the RxD terminal. Parity
error occurs if they are not equal.
3) Framing error (SCCR0 <FERR0>)
The stop bit of received data is sampled three times
around the center. If a majority results in zero, framing
error occurs.
⑨ Parity control circuit
11
Setting the serial channel control register SCCR <PE>
to “1” allows the addition of a parity bit in transmitting/
receiving data, only in the 7-bit UART or 8-bit UART
mode. Either even or odd parity can be selected by the
SCCR <EVEN> register.
In the transmission mode, the parity is automatically
generated as based on the data written into the transmission buffer SCBUF, storing into the SCBUF <TB7>
in the 7-bit UART mode or into <TB8> in the 8-bit
UART mode for transmission. <PE> and <EVEN>
should be designated before writing data into the
transmission buffer.
In the receiving mode, the receiving data is shifted into
the receiving buffer 1 and transferred to the receiving
buffer 2 (SUBUF). The parity is generated from the
data in the receiving buffer 2. A parity error is detected
and the SCCR <PERR> flag is set if the parity status
mismatches the SCBUF <RB7> in the 7-bit UART
mode or <RB8> in the 8-bit UART mode.
➉ Error flag
There error flags are prepared to increase the reliability
of received data.
1) Overrun error (SCCR0 <OERR0>)
Overrun error occurs if all the bits of the next data are
received by the receiving buffer 1 while valid data are
still stored in the receiving buffer 2 (SCBUF).
Generation Timing
1) UART mode
Receiving
Mode
9 Bit
8 Bit, 7 Bit + Parity,
7 Bit
Interrupt timing
Center of last bit
(Bit 8)
Center of last bit
(Parity Bit)
Center of Stop bit
Framing error
timing
Center of stop bit
Center of stop bit
↑
Parity error timing
Center of last bit
(Bit 8)
Center of last bit
(Parity Bit)
↑
Over-run error
timing
Center of last bit
(Bit 8)
Center of last bit
(Parity Bit)
↑
Note: The occurrence of a framing error is delayed until after interruption.
Therefore, to check for framing error during interrupt operation, an addition
operation, such as waiting for 1 bit time, becomes necessary.
Transmitting
Mode
Interrupt timing
9-bit
Just before the
stop bit
8-bit + Parity
8-bit, 7-bit + Parity,
7-bit
←
←
2) I/O interface mode
Receiving
2) Parity error (SCCR0 <PERR0>)
Interrupt timing of receiving
The parity generated from the data that is transferred
Interrupt timing of transmitting
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8 Bit + Parity
Just after the last SCLK rising
↑
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3.9.3 Operation
(1)
Mode 0 (input/output interface mode)
This mode is used to increase the number of
TMP90C051F input/output pins. This is done by using
externally connected shift registers to transmit and
receive data.
This mode has an SCLK0 output mode in which the
sync clock (SCLK0) is output and an SCLK0 input
mode in which an external. Sync clock (SCLK0) is
input.
This mode has an SCLK0 output mode in which the
sync clock (SCLK0) is output and SCLK0 input mode
in which an external sync clock (SCLK0) is input.
• Typical SCLK0 output mode connection
Figure 3.9 (11). Input/Output Interface Mode
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➀ Transmitting
In the SCLK0 output mode, each time the CPU writes
data to the transmit buffer, 8 bits of data are output to
the TxD0 pin and the sync clock is output from the
SCLK0 pin.
When all of the data have been output, IRF2 <IRFTX0>
is set and interrupt INTTX0 is generated.
Figure 3.9 (12). Input/Output Interface Mode Transmit Operation (SCLK0 Output Mode)
In the SCLK0 input mode, 8 bits of data are output
from the TxD0 pin when SCLK0 input is active while
data are being written by the CPU to the transmit
buffer.
When all of the data have been output, IRF2 <IRFTX0>
is set and interrupt INTTX0 is generated.
Figure 3.9 (13). Input/Output Interface Mode Transmit Operation (SCLK0 Input Mode)
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➁ Receiving
In the SCLK0 output mode, the sync clock is output
from the SCLK0 pin and the next data are shifted into
receive buffer 1 each time the CPU reads the receive
data and the receive interrupt flag IRFRX0 is cleared.
When 8 bits of data have been received, they are
shifted to receive buffer 2 (SCBUF0), IRF2 <IRFRX0>
is again set and interrupt INTTX0 is generated.
Figure 3.9 (14). Input/Output Interface Mode Receive Operation (SCLK0 Output Mode)
In the SCLK0 input mode, the next data are shifted
into receive buffer 1 when SCKL0 input is active while
the CPU is reading receive data and the receive interrupt
flag IRFRX0 is cleared. When 8 bits of data have been
received, they are shifted to receive buffer 2
(SCBUF0), IRFRX0 is again set and interrupt INTRX0 is
generated.
Figure 3.9 (15). Input/Output Interface Mode Receive Operation (SCLK0 Input Mode)
It is necessary to enable receiving (SCMOD <RXE0> = 1)
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before receiving data.
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(2)
Mode 1 (7-Bit UART Mode)
The 7-bit UART mode is entered by setting serial channel
mode register SCMOD0 <SM01, 00> to 01.
In this mode, a parity bit can be added. The parity bit is
enabled and disabled with serial channel control register
SCCR0 <PE0>. <PE0> = 1 enables parity; <PE> = 0
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disables parity; and even or odd parity is selected
SCCR0 <EVEN0>.
Setting example: The control register settings for
transmitting data in the following
format.
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(3)
Mode 2 (8-Bit UART Mode)
The 8-bit UART mode is entered by setting serial channel
mode register SCMOD0 <SM01, 00> to 10. In this
mode, a parity bit can be added. The parity bit is
enabled and disabled with serial channel control register
SCCR0 <PE0>. <PE0> = 1 enables parity; PE = 0 dis-
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ables parity; and even or odd parity is selected with
SCCR0 <EVEN0>.
Setting example: The control register settings for
receiving data in the following format
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(4)
Mode 3 (9-Bit UART Mode)
Wake-up function
The 9-bit UART mode is entered by setting serial channel
mode register SCMOD0 <SM01, 00> to 11. In this
mode, a parity bit cannot be added.
The uppermost (9th) bit is written to SCMOD0 <TB08>
when transmitting and is stored to SCCR0 <RB08>
when receiving. Always start with the uppermost bit
and proceed toward SCBUF0 when reading or writing
the buffer.
In the 9-bit UART mode, slave controller wake-up
operation is enabled by setting SCMOD0 <WU0> to
“1”. Interrupt INTRX0 is generated when SCCR0
<RB08> = 1.
Caution:
Always set the TxD0 pin of the slave controller to the open drainoutput mode
Figure 3.9 (16). Serial Link Using the Wake-up Function
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Protocol
time, the uppermost bit <TB08> is cleared to “0”.
➀ Set the master and slave controller to the 9-bit
UART mode.
➁ Set the SCMOD0 <WU0> bit of a slave controller to
“1” to enable receiving.
➂ The master controller transmits 1 frame, including
the select code (8 bits) of the slave controller. The
uppermost bit SCMOD0 <TB08> is set to “1” at this
time.
➃ The slave controller receives the frames and, if its
own select code matches the received data, clears
the <WU0> bit to “0”.
➅ Even with <WU0> set to “1”, the slave controller will
neither generate interrupt INTRX0 nor read receive
data as long as <RB08>is cleared to “0”.
When both <WU0> and <RB08> are set to “1”, the
slave controller will always generate interrupt
INTRX0 and read the receive data.
Then, when <WU0> is cleared to “0”, this is
reported to the master controller to inform it that
receiving has ended.
Setting example: Serially linking two slave controllers using internal clock ø1 as
the transfer clock at using ch0.
➄ The master controller transmits data to the specified
slave controller (with <WU0> cleared to “0”). At this
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3.10 TPH Serial Interface
When copying or storing receive data, the TPH (Thermal
Printer Head) serial interface converts the parallel data from
MPU and DMA to serial data and transmits it to the TPH driver.
The TPH serial interface uses SIO channel 0.
Thus, SIO channel 0 has independent control registers for
the serial interface mode, UART mode and input/output interface mode. Any of these three can be selected by program.
The TPH serial interface mode is in effect after a reset.
3.10.1 Features
(1)
Three transmit modes can be selected. An interrupt is
generated after the specified number of bytes has
been sent.
• A4 mode (1728 bits): 216 bytes are sent
• B4 mode (2048 bits): 256 bytes are sent
• A3 mode (2592 bits): 324 bytes are sent
(2)
Either an internal or external can be selected as the
transmit clock.
• In the internal clock mode, fxtal 1/4, 1/8, 1/32, 1/
128 baud rates can be selected. (@ fxtal =
12.5MHz: 3.125MHz/bit sent at 1/4 rate.)
• In the external clock mode, an external 4MHz
(max.) input clock can be used.
(3)
TPH driver and interface pins
•
•
•
•
TPHCKO
TPHSD
TPHLAT
LATWAIT
input pin
• TPHCK1
:transmit clock output pin
:transmit data output pin
:latch output pin
:TPHLAT output wait control
:external clock input pin
These pins are multiplexed internally to function as
TXD0, RXD0, RTS0, CTS0 and SCLK0 when the
input/output interface issued in the UART mode.
For details, see 3.10.3 (6) Operation (pin multiplexing).
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3.10.2 Control Registers
(1)
Transmit Data Write Register
(2)
TPH Control Register
Note: also TMP90C51F can control the wait of TPHLAT output by external pin (LATWAIT).
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(3)
TPH Serial Control Register
(a) The TPH shift register (TPH BUF; Byte Counter) can
be cleared by writing “1” to D7 ~ D1. When TPH
serial interface transmitting has been stopped on
the way, this command must be written again
before writing the next transmit data.
(Note) Write data “1” to <SCR7 ~ 1> before the user
uses firstly TPH serial I/F.
(b) Interrupt generate mode
The <EXINT> bit is set to “0” after a reset.
The <EXINT> bit is used to select the internal interrupt
generation mode (transmit interrupts [INTTX0] are generated only internally) or the external interrupt generation
mode (started by the AND of the start signal from INT3
and the internal transmit interrupt enable status).
<EXINT> = 0: internal interrupt generation mode
<EXINT> = 1: external interrupt generation mode.
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TMP90C051
INTLINE: Generate at the trigger of 1 line data end with
TPHLAT output
Interrupt generation is enabled and disabled by setting
the INTE 1/2 register at address #FFCD/FFCEH. Interrupt
generation is disabled after a reset.
Table 3.10 (1) shows the interrupt generation sources
for SIO channel 0. Set SIO channel 0 interrupts as
shown below in accordance with the mode setting
(operating mode).
3.10.3 Operation
(1)
Clock Selector
• In the internal clock mode, it is possible to output the
transmit clock from TPHCK0 and select a clock rate
of øT0 (fc/4), øT1 (fc/8), T4 (fc/32), T16 (fc/128) from
the internal 9 bit prescaler (Timer Common use) (@
x’tal 12.5MHz: max. 3.125MHz/bit transfer at the 1/4
rate).
• In the external clock mode, the clock input from
TPHCK1 is used for transmit operations (max. 4.0MHz/
bit). If a user uses the internal clock mode, operate the
prescaler.
(2)
a) TPH Serial Interface Mode
Set the mode bit of TPHMOD <SMODE> to “0”.
When controlling the writing of transmit data to the
TPH serial interface from external pin INT3, set the
TPHSCR <EXINT> to “1”. In this case, transmit interrupts are generated in accordance with the AND logic
of the internal transmit shift register status and external
pin INT3 status.
When the TPHSCR <EXINT>is set to “0”, transmit interrupts
are generated in accordance with the internal transmit
register status only.
Byte Counter
Bits TPHMOD <TRM1, 0> (Mode = 0) of the control
register (#FFEAH) are used to specify the number of
bytes to be transferred. The byte counter is reset to “0”
after one line has been transmitted.
(3)
TPHLAT Output
TPHLAT is set to “Low” active when the byte counter
has counted the number of bytes in one line.
(4)
Table 3.10 (1) Serial Channel 0 Interrupt Generation
Sources
Serial channel 0
mode
LATWAIT Input
Wait control by software or from the external pin
(LATWAIT) can be used to wait for the TPHLAT output.
Waits are applied by keeping LATWAIT at low active
from the TPHCK0 fall that transmits the last bit of the
last byte of the transmits data to the next TPHCK0
rise.
TPH mode
Start
External
Internal
External
Internal
INTTX
–
INTTX
INTTX•INT3
INTTX
INTRX
–
INTRX
–
–
INTLINE
–
–
Interrupt source
(b)
(5)
UART, Input/Output
interface mode
INTLINE
UART, I/O Interface Mode
Interrupt Generation
INTTX0: Generate at the trigger of the buffer empty
after TPH I/F transfer the 1 byte data
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Set the TPHMOD <SMODE>to “1” and the
TPHSCR <EXINT> to “0”. Figure 3.10 (1) shows the
SIO channel 0 interrupt generation circuit.
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Figure 3.10 (1). SIO Channel 0 Interrupt Generation Circuit
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(6)
Pin Multiplexing
channel 0 pins.
Table 3.10 (2) shows the multiplexing of the serial
Table 3.10 (2) Pin multiplexing
After reset and in TPH serial
interface mode
Pin name
Pin no.
TPHMOD
UART mode
TPHMOD
Input/
output
Function
<SMODE>
Function
Input/output
<SMODE>
RxD0/LATWAIT
30
LATWAIT
Input
RxD0
Input
TxD0/TPHSD
31
TPHSD
Output
TxD0
Output
SCLK0/TPHCKO
32
TPHCKO
Output
SCLK0
Input/Output
0
1
RTS0/TPHCKI
33
TPHCKI
Input
RTS0
Output
CTS0/TPHLAT
34
TPHLAT
Output
CTS0
Input
Input/output interface mode (1)
Pin name
Pin no.
TPHMOD
Function
Input/output
<SMODE>
RxD0/LATWAIT
30
RxD0
TxD0/TPHSD
31
TxD0
SCLK0/TPHCKO
32
1
Input
Output
SCLK0
Input...in external clock mode
Output...when using the internal baud rate generator
RTS0/TPHCKI
33
RTS0
Output
CTS0/TPHLAT
34
CTS0
Input
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3.10.4 Transmit Operation Timing
Typical transmit operations using the TPH serial interface are
shown below.
(2)
Send Format Example 2
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(1)
Send Format Example 1
: A4 mode transmitting using an internal clock and
external LATWAIT insertion.
: B4 mode transmitting using an external clock.
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TMP90C051
(3)
Send Format Example 3
(4)
Send Format Example 4
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3.10.5 Typical TPH Driver Connections
(1)
Using an External Clock
(2)
Using LATWAIT and an Internal Clock
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(3)
Send Format Example 3
(4)
Send Format Example 4
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3.11 Real Time Clock (RTC)
3.11.1 RTC Function Overview
1) Clock (hour, minute, second, month, day [youbi], date [hinichi],
year, leap year)
2) Auto-calendar
3) Choice of 24-hour clock or 12-hour clock (A.M./P.M.)
4) ±30 seconds correction function (software adjustment)
5) Alarm output (ALARM)
6) Internal interrupt generation by alarm output
3.11.2 RTC Block Diagram
Figure 3.11 (1). RTC Block Diagram
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3.11.3 RTC Input/Output Address Map and Control Registers
Table 3.11 (1) PAGE 0 (timer function) Register
Symbol
I/O
address
D7
D6
D5
D4
D3
D2
D1
D0
SECR
#FFE0H
(Note 1)
–
40
seconds
20
seconds
10
seconds
8
seconds
4
seconds
2
seconds
1
seconds
Second
R/W
MINR
#FFE1H
–
40
minutes
20
minutes
10
minutes
8
minutes
4
minutes
2
minutes
1
minutes
Minute
R/W
HOUR
#FFE2H
–
–
20 hours
(PM/AM)
10 hours
8 hours
4 hours
2 hours
1 hours
Hour
R/W
Setting Contents
Read/Write
DAYR
#FFE3H
–
–
–
–
–
W2
W1
W0
Day
R/W
DATER
#FFE4H
–
–
20 days
10 days
8 days
4 days
2 days
1 days
Date
R/W
MONTHR
#FFE5H
––
–
–
10
months
8
months
4
mnonths
2
months
1
months
Month
R/W
YEARR
#FFE6H
80 years
40 years
20 years
10 years
8 years
4 years
2 years
1 years
Year (last 2 digits)
R/W
PAGER
#FFE7H
–
–
–
ADJUST
TIMER
En/dis
ALARM
EN/dis
–
Page
Page register (Note 2)
R/W
RESTR
#FFE8H
1Hz
dis/En
16Hz
dis/En
TIMER
REST
ALARM
REST
0
0
0
0
Symbol
I/O
address
D7
SECR
#FFE0H
–
–
20 hours
(PM/AM)
Reset register
Write only
Table 3.11 (2) Page 1 (alarm function) Registers
D6
D5
D4
D3
D2
D1
D0
Setting Contents
Read/Write
–
–
–
–
–
–
–
R/W
20
minutes
10
minutes
8
minutes
4
minutes
2
minutes
1
minutes
Alarm minute
R/W
10 hours
8 hours
4 hours
2 hours
1 hours
Alarm hour
R/W
MINR
#FFE1H
–
40
minutes
HOUR
#FFE2H
–
–
DAYR
#FFE3H
–
–
–
–
–
W2
W1
W0
Alarm day
R/W
DATER
#FFE4H
–
–
20 days
10 days
8 days
4 days
2 days
1 day
Alarm date
R/W
MONTHR
#FFE5H
–
–
–
–
–
–
–
24/12
24-hour clock select bit
R/W
YEARR
#FFE6H
–
–
–
–
–
–
LEAP1
LEAP0
Leap year
R/W
PAGER
#FFE7H
–
–
–
–
TIMER
En/dis
ALARM
EN/dis
–
Page
Page register (Note 2)
R/W
RESTR
#FFE8H
1Hz
dis/En
16Hz
dis/En
TIMER
REST
ALARM
REST
0
0
0
0
Reset register (Note 3)
Write only
(Note 1) “–” is ignored when writing but is read as “1”.
(Note 2) Page is specified with the D0 bit (Page) of #FFE7H.
Page = 0 sets PAGE 0
Page = 1 sets PAGE 1
(Note 3) All register bits are not initialized by RESET.
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3.11.4 Register Explanation
The real timer clock (RTC) is not initialized by RESET. RTC
operates with unstable values after power-on; therefore, load
(1)
the time, month, day, date, year and leap year to the registers
before starting operation.
Setting the Second Register (Page 0 only)
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(2)
Setting the Minute Register (Page 0/Page1)
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(3)
Setting the Hour Register (Page 0/Page 1)
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➀ When D0 of FFE5H = 1 (24-hr. clock display)
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➁ When D0 of FFE5H = 0 (12-hr. clock display)
(4)
Setting the Date Register (Page 0/Page 1)
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(5)
Setting the Date Register (Page 0/Page 1)
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(6)
Setting the Month Register (Page 0 only)
(7)
Setting 24-Hour/12-Hour Clock (Page 1 only)
hour/12-hour clock of the timer function.
The MO0 bit of address #FFE5H is used to set the 24-
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(8)
Setting the Year (Last 2 Digits) Register (Page 0 only)
(9)
Setting the Leap Year Register (Page 1 only)
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(10)
Setting the Page Register (Page 0/Page 1)
(11)
Setting the Reset Register (Page 0/Page 1)
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OSC with the divider is output from the ALARM pin.
Set as follows.
3.11.5 Alarms
(1)
ALARM Output Pin
Any one of the following three signals can be selected
with SELECT circuit and output to the ALARM pin.
➀ The ALARM signal output from the comparator
drops to “Low” when the contents of the timer and
alarm register match
Set as follows to output the ALARM signal to the
ALARM pin.
PAGER
<PA2>: ALARM Enable = 1
RESTER
<RE7>: 1Hz Output Disable = 1
PAGER
<PA2>: ALARM DISABLE = 0
RESTER
<RE7>: 1Hz Output enable = 0
<RE6>: 16Hz Output Disable = 1
➂ A 16Hz signal obtained by dividing the 32kHz signal
from OSC with the divider is output from the ALARM
pin. Set as follows.
PAGER
<PA2>: ALARM DISABLE = 0
RESTER
<RE7>: 1Hz Output disable = 1
<RE6>: 16Hz Output enable = 0
<RE6>: 16Hz Output Disable = 1
➁ A 1Hz signal obtained by dividing 32kHz signal from
Figure 3.11 (2). Alarm SELECT Circuit
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(2)
ALARM Reset Cautions
“0” is output to ALARM when the timer and alarm register
contents match for the minute, hour, day and date
items while alarms are enabled.
After an alarm reset, however, items for which nothing
has been written are considered to match, regardless
of the timer contents.
However, the two digits (10’s and units) of the minute,
hour and date items form a single item, so set both
digits when writing.
For example, to output an alarm at the same time
every day, it is only necessary to set the hour (both the
10’s and units digits) and minute (both the 10’s and
units digits) after executing an alarm reset. An alarm
reset clears the contents of the alarm register to “0”.
To compare “0” (to compare “0” for hour and minute,
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for example, 00 hour, 00 minute), however, all items
enter the “don’t care” status when an alarm reset is
executed with alarms enabled and the ALARM signal
is output until an alarm is set. Because of that, it is
necessary to disable alarms before executing an alarm
reset.
(3)
INTALARM (Internal)
As with ALARM signal output, interrupts can be generated
with any of the three following signals. 1) Comparator
output, 2) 1Hz, 3) 16Hz.
Interrupts are generated internally in synchronization
with falls of the ALARM pin output.
INTALARM is reset by system resets (when RESET =
“Low”).
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3.11.6 Typical Programming Sequence
(1)
When Reading Timer Data
➀ Errors are possible when a carry to the next higher
digit of an internal counter occurs while reading timer
data. Thus, use the following method to read the data
correctly.
Figure 3.11 (3). Typical Timer Data Read Sequence
When reading timer data as shown in Figure 3.11 (3),
the timer data are read twice and the contents are
then compared to determine if a carry operation A
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carry operation is indicated when a comparison shows
that the occurred. contents differ, so the data are read
again.
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➁ Reading timer data when ALARM output was used
detecting ALARM = 1 with a 1Hz INTALARM interrupt
routine.
Data can be read at the ALARM output rise edge by
(Note:) This is because an RTC timer carry operation occurs at the 1Hz pulse rise edge when the RTC timer is read after reading ALARM = 1 from a port with
an interrupt routine at *2). When reading timer data, the prescribed timer (timer value) can be read by reading for 0.5 sec. after the carry operation.
Figure 3.11 (4)
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(2)
When Writing Data
➀ Data will not be written correctly if a carry signal
appears while writing a series of data. Use the following method to write the data correctly.
The RTC contains a 15-stage divider that generates
the 1Hz signal from the 32.768kHz signal. Carry operations
are not performed during the 1-s. interval after this
divider is reset. Data are written during this interval.
Figure 3.11 (5). Typical Data Write Sequence
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➁ When disabling the timer
Writing “0” to bit <PA3> of address #FFE7H disables
the timer, disables carry operations and prevents
misoperation due to the CLOCK HOLD circuit.
The CLOCK HOLD circuit holds once only the 1-second carry signal generated by the divider while the
timer is disabled, corrects the time by outputting the carry
signal to the timer after the timer is enabled, and con-
tinues operating. If the timer disable continues for
longer than one second, however, the timer is delayed.
Caution must be exercised here in that the TMP90C051F
system power supply is halted while the timer is disabled. In this case, the timer remains stopped and the
time is delayed; therefore, when a system power-down
is detected while the timer is disabled, always return to
timer enable and then set BAKEN (Back Up Enable) to “0”.
Figure 3.11 (6). Typical Timer Disable Sequence
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3.11.7 Battery Backup
The RTC section has an independent (RTC) Vcc power supply
pin. Operation can be continued in case of loss of Vcc (pins 36/
77), the main power supply, if an external battery backup is
connected to (RTC) Vcc.
The battery backup is activated by setting BUKEN = “0”
when loss of the main power supply, Vcc (pins 36/77), is
detected externally.
A minimum (RTC) Vcc voltage of 2V is guaranteed by the
battery backup.
Use a backup circuit that provides the same potential at
(RTC) Vcc found at Vcc (pins 36/77) when the main power
supply is on.
Figures 3.11 (7) and (8) below show battery backup circuit
configurations.
Figure 3.11 (7). NiCad Battery Backup Circuit Configuration
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Figure 3.11 (8). Lithium Battery Backup Circuit Configuration
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3.12 Dynamic RAM Controller
The TMP90C051F configuration includes a controller circuit
for refreshing the dynamic RAM, an access circuit for reading
and writing, and an address decoder circuit.
Figure 3.12 (1) shows the dynamic RAM controller block
diagram.
Figure 3.12 (1). Dynamic RAM Controller Block Diagram
3.12.1 Refresh Controller Block
The TMP90C051F can drive RAS and CAS outputs used for
DRAM refreshing.
DRAM refresh is easy because the output cycle and output pulse width of the RAS and CAS outputs can be set by
program.
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The refresh controller block has the following features.
1) Refresh method: CAS before RAS interval refresh
2) Refresh interval: 15 ~ 154 states (programmable)
3) Refresh cycle width: 2 ~ 9 states (programmable)
4) Dummy cycles can be generated.
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Figure 3.12 (2) shows typical refresh cycle timing.
Figure 3.12 (2). Typical Refresh Cycle Timing
The method for using the refresh controller block is
described below.
i)
Refresh Method
Refreshing is performed using the CAS and RAS
refresh method using the DRAM built-in refresh
counter.
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ii)
Register Setting Method
With the CAS before RAS refresh method, the refresh
interval and refresh cycle width differ depending on the
DRAM used.
The TMP90C051 sets the RAS and CAS output in
accordance with the system clock and DRAM used by
changing the refresh control register value.
Figure 3.12 (3) shows the bit configuration of the
refresh control register used to control RAS and CAS
output.
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Figure 3.12 (3). Refresh Control Register
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Table 3.12 (3) Refresh Cycle Insertion Intervals
Resfresh cycle
RS2
RS2
RS0
Insertion
interval
(state)
Frequecncy
0
0
0
15
7.5
3.75
0
0
1
31
15.5
7.55
6.2
4.96
4.43
3.88
0
1
0
62
31.0
15.5
12.4
9.92
8.86
7.75
0
1
1
78
39.0
19.5
15.6
12.48
11.14
9.75
1
0
0
97
48.5
24.25
19.4
15.52
13.86
12.13
1
0
1
109
54.5
27.25
21.8
17.44
15.57
13.63
1
1
0
124
62.0
31.0
24.8
19.84
17.72
15.5
15.5
1
1
154
77.0
38.5
30.8
24.7
22.0
19.3
4MHz
8MHz
10MHz
12.5MHz
14MHz
16MHz
3.0
2.4
2.14
1.88
(Unit µs)
The refresh control register (REFCR) is assigned to
address FFD8H and the bits are as follows.
<DM1>:
<RS2 ~ 0>:
Dummy cycle control bit (DMI)
The dummy cycles required fro DRAM
intialization are genrated by setting this bit
to “1” (see Figure 3.12 (4)).
Refresh cycle insertion interval control bits
(RS2 ~ RS0)
These 3 bits are used to
change the system clock used and the
insertion interval.
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Example:
When using the 12.5MHz system clock,
set these bits to “100” to specify a DRAM
refresh cycle of 16 microseconds.
<RW2 ~ 0>:
Refresh cycle width control bits
(RW2 ~ RW0)
These 3 bits are used to
change the refresh cycle width
(RAS, CAS output) (2 ~ 9 states).
<RC>:
Refresh cycle control bit (RC)
This bit is used to control refresh cycle
insertion.
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Figure 3.12 (4). Port 3 Function Registers
iii)
Dynamic RAM Initialize
The dynamic RAM controller generates consecutive
CAS before RAS dummy cycles when using DRAM.
Figure 3.12 (4) shows the CAS before RAS dummy
cycle timing.
Figure 3.12 (5) CAS Before RAS Dummy Cycle Timing
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3.12.2 Read/Write Control Block
The read/write control block outputs the memory access cycle
RAS and CAS signals when the address area set with the
decoder block described in the next section is selected.
Figure 3.12 (6) shows the RAS and CAS output timing
during the memory access cycle.
Figure 3.12 (6). Memory Access Cycle Timing
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i)
Register Setting Method
Figure 3.4 (7) shows the bit configuration of the memory
access control register. The memory access control
register (MACR) is assigned to address FFDBH.
CS output is enabled and disabled by setting
<CSEN>. Additionally, RAS and CAS output during
memory access is enabled and disabled by setting
<MC>. When <CSEN> is set to “0” (CS output disable),
RAS and CAS output during memory access is disabled,
regardless of <MC> value.
Figure 3.12 (7). Memory Access Control Register (MACR)
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3.12.3 Address Decoder Block
The address decoder block enables DRAM access and simultaneously outputs the CS signal when the start address and
mask address are loaded to the register. When a DRAM is not
used, the CS signal can be used as the area select signal.
Figure 3.12 (8). Chip Select (CS) Operation Timing
Figure 3.12 (9). Address Decoder Block Diagram
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ii)
by A15 - A22 and is therefore set every 32K bytes.
In other words, the DRAM start address is set every
32K bytes, starting at 000000H.
Start Address Setting Method
The address decoder outputs the CS signal when the
start address and area size are specified.
As shown in the diagram, the start address is decoded
<Note> The start address is changed to set the value
of MSAMR register.
Figure 3.12 (10). Start Address Setting Locations
iii)
Address Area Setting Method
The address area is specified by setting the start
address mask register (MSAMR).
As can be seen from the address decoder block diagram
(Fig. 3.12 (9), the address area that can output CS is
specified depending on whether or not the A14 - A21
address values are compared.
In other words, it is possible to specify an area of up to
4M bytes in 16K byte units.
(3)
Compare values of the same address bit of MSAMR
and MSAR. (Ex.) Compare values of MSAMR <V15>
and MSAR <S15>.
(4)
If the values of the same address bit are “1”, the bit in
MSAR becomes ineffective and is regarded as “0”.
The start address is changed.
If the values of the same address bit are not matched
by “1”, the set-up is complete. (The specified address
area and start address are decoded.)
iii)
Procedures for Setting Start Address/Address Area
(5)
When the start address is changed correctly, the set-up is
complete. If not so, change the MSAR value.
(1)
Set the memory start address mask register (MSAMR)
(Setting the address area)
(6)
Set MSAR again and compare. (Start from (3).)
(2)
Set the memory start address mask register (MSAR)
(Setting the area start address)
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Set-up example
When address area = 64K bytes, start address = 18000H
(Memory map: 18000H to 27FFFH)
Set
MSAMR = 03H <-> address area: 64K bytes
MSAR = 03H <-> start address: 18000H
*: When values of the same address bit are “1”, the start
address is changed to 10000H.
If not so, change the start address to 20000H.
(Memory map: 20000H to 2FFFFH)
MSAMR =03H
MSAR = 04H
V22 ~ V16 = “0”, so these values of S22 ~ S16 are validness but V15 and V14 = “1”, so these values of S15 and S14
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When the start address is 20000H, the address bits do
not match as “1” and the start address is not changed.
This enables to decode under the start address = 20000H
and the address area = 64K bytes.
(Set-up example 1)
Case of MSAR = 03H and MSAMR = 03H
The output of chip selection is the memory map as below.
are invalidity.
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(Set-up example 2)
V22 ~ V16, V14 = “0”, so these value of S22 ~ S16 and
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Case of MSAR = 03H and MSAMR = 02H
S14 are validness but S15 = “1”, so this value of S15 is invalidity.
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TMP90C051
(Set-up example 3)
MSAMR (partly)
Chip select area by setting value of MSAR and
MSAMR
MSAR
00
01
02
03
00
0000
∫
3FFF
(16K byte)
0000
∫
7FFF
(32K byte)
0000 8000
∫
∫
3FFF 1BFFF
(16K byte x 2)
0000
∫
FFFF
(64K byte)
01
8000
∫
BFFF
(16K byte)
8000
∫
FFFF
(32K byte)
10000 18000
∫
∫
3FFF 1BFFF
(16K byte x 2)
0000
∫
FFFF
(64K byte)
02
10000
∫
13FFF
(16K byte)
10000
∫
17FFF
(32K byte)
10000 18000
∫
∫
13FFF 1BFFF
(16K byte x 2)
10000
∫
1FFFF
(64K byte)
03
18000
∫
1BFFF
(16K byte)
18000
∫
1FFFF
(32K byte)
10000 18000
∫
∫
13FFF 1BFFF
(16K byte x 2)
10000
∫
1FFFF
(64K byte)
MSAMR
MSAR
03
07
0F
1F
04
20000
∫
2FFFF
(64K byte)
20000
∫
3FFFF
(128K byte)
00000
∫
3FFFF
(256K byte)
08
40000
∫
4FFFF
(64K byte)
40000
∫
5FFFF
(128K byte)
40000
∫
7FFFF
(256K byte)
10
80000
∫
8FFFF
(64K byte)
80000
∫
9FFFF
(128K byte)
80000
∫
BFFFF
(256K byte)
80000
∫
FFFF
(512K byte)
20
100000
∫
10FFFF
(64K byte)
100000
∫
11FFFF
(128K byte)
100000
∫
13FFFF
(256K byte)
100000
∫
17FFFF
(512K byte)
100000
∫
1FFFFF
(1M byte)
40
200000
∫
20FFFF
(64K byte)
200000
∫
21FFFF
(128K byte)
200000
∫
23FFFF
(256K byte)
200000
∫
27FFFF
(512K byte)
200000
∫
2FFFF
(1M byte)
200000
∫
3FFFFF
(2M byte)
80
400000
∫
40FFFF
(64K byte)
400000
∫
41FFFF
(128K byte)
400000
∫
43FFFF
(256K byte)
400000
∫
47FFFF
(512K byte)
400000
∫
4FFFFF
(1M byte)
400000
∫
5FFFFF
(2M byte)
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00000
∫
7FFFF
(512K byte)
( ) is area size
3F
00000
∫
FFFFF
(1M byte)
7F
00000
∫
1FFFFF
(2M byte)
FF
00000
∫
3FFFFF
(4M byte)
400000
∫
7FFFFF
(4M byte)
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TMP90C051
Iv)
Register Setting Method
assigned to address FFDAH.
CS output can be enabled and disabled regardless of
the above registers by setting <CSEN> of the memory
access control register (MACR) shown in Figure 3.12
(6).
Figure 3.12 (11) and Figure 3.12 (12) show the bit configurations of the start address register (MSAR) and
start address mask register (MSAMR).
MSAR is assigned to address FFD9H and MSAMR is
Figure 3.12 (11). Memory Start Address Mask Register
The MSAR <S22> ~ <S15> correspond to the A22 ~
A15 of address and the S14 correspond to the A14
(S14 is “0” at default). The MSAMR <V21> ~ <V14>
point to the validness/invalidity of comparison with the
value of the setting MSAR and the address.
The MSAMR <V21> ~ <V14> correspond to the
MSAMR <V21> ~ <V15>, S14 and the MSAMR
<V22> corresponds to the MSAR <S22> (S22 is “0” at
default). The comparison of the A22 and <S22> is
usually validness. The meaning of comparison (validness and invalidity).
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EX.
The case of invalidity at <V15> = 1
The comparison of <S15> value and address (A15) is
invalidity and <S15> value is validity. So the value of
A15 is unrelated ness for “0”/“1”.
The case of validness at <V15> = 0
The comparison of <S15> value and address (A15) is
validness.
When the value of <S15> only agree with address
(A15), CS signal is enabled.
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TMP90C051
3.12.4 Priority Sequence
Since the dynamic RAM refresh cycle is asynchronous with the
CPU operation cycle, it may overlap the read/write cycle in
some cases. In such cases, the dynamic RAM controller gives
priority to the cycle that enters first. When the refresh cycle is
given priority, a waits automatically inserted in the memory
access cycle. Figure 3.12 (13) shows the timing in such cases.
.
Figure 3.12 (13). Timing Chart for When a Memory Access Cycle Enters During a Refresh Cycle
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3.12.5 Typical DRAM Connection
Figure 3.12 (14). Typical DRAM Connection
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