ETC TMP93CM41F

TOSHIBA
TLCS-900 Series
TMP93CM40/TMP93CM41
Low Voltage/Low Power
CMOS 16-bit Microcontrollers
TMP93CM40F/TMP93CM41F
1.
Outline and Device Characteristics
TMP93CM40/M41 are high-speed advanced 16-bit microcontrollers developed for controlling medium to large-scale equipment. The TMP93CM41 does not have a ROM, the
TMP96CM40 has a built-in ROM. Otherwise, the devices function in the same way.
TMP93CM40F/TMP93CM41F are housed in 100-pin
mini flat package. Device characteristics are as follows:
(1) Original 16-bit CPU (900L CPU)
• TLCS-90 instruction mnemonic upward compatible.
• 16M-byte linear address space
• General-purpose registers and register bank system
• 16-bit multiplication/division and bit transfer/arithmetic
instructions
• High-speed micro DMA
- 4 channels (1.6 µs/2 bytes at 20MHz)
(2) Minimum instruction execution time
- 200ns at 20MHz
(3) Internal RAM: 2K byte
Internal ROM:
TMP93CM40
32K-byte ROM
TMP93CM41
None
(4) External memory expansion
• Can be expanded up to 16M bytes (for both programs and
data).
• AM8/16 pin (select the external data bus width).
• Can mix 8- and 16-bit external data buses.
…Dynamic data bus sizing
(5) 8-bit timer: 2 channels
(6) 8-bit PWM timer: 2 channels
(7) 16-bit timer: 2 channels
(8) Pattern generator: 4 bits, 2 channels
(9) Serial interface: 2 channels
(10) 10-bit A/D converter: 4 channels
(11) Watchdog timer
(12) Chip select/wait controller: 3 blocks
(13) Interrupt functions
• 2 CPU interrupts… …SWI instruction, and Illegal instruction
• 14 internal interrupts
7-level priority can be set.
• 6 external interrupts
(14) I/O ports:
79 pins for TMP93CM40 and 61 pins for TMP93CM41
(15) Standby function : 4 halt modes (RUN, IDLE2, IDLE1,
STOP)
(16) Clock Gear Function
• High-frequency clock can be changed fc to fc/16
• Dual clock operation
(17) Wide Operating Voltage
• VCC = 2.7 to 5.5V
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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TMP93CM40/TMP93CM41
Figure 1. TMP93CM40/TMP93CM41 Block Diagram
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TMP93CM40/TMP93CM41
2.
Pin Assignment and Functions
The assignment of input/output pins for TMP93CM40/
TMP93CM41, their name and outline functions are described
below.
2.1 Pin Assignment
Figure 2.1 shows pin assignment of TMP93CM40F/
TMP93CM41F.
Figure 2.1. Pin Assignment (100-pin MFP)
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TMP93CM40/TMP93CM41
2.2 Pin Names and Functions
The names of input/output pins and their functions are described below.
Table 2.2. Pin Names and Functions
Number
of Pins
I/O
P00 to P07
AD0 to AD7
8
I/O
Tri-state
Port 0: I/O port that allows I/O to be selected on a bit basis
Address / data (lower): 0 to 7 for address / data bus
P10 to P17
AD8 to AD15
A8 to A15
8
I/O
Tri-state
Output
Port 1: I/O port that allows I/O to be selected on a bit basis
Address data (upper): 8 to 15 for address / data bus
Address: 8 to 15 for address bus
P20 to P27
A0 to A7
A16 to A23
8
I/O
Output
Output
Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor)
Address: 0 to 7 for address bus
Address: 16 to 23 for address bus
P30
RD
1
Output
Output
Port 30: Output port
Read: Strobe signal for reading external memory
P31
WR
1
Output
Output
Port 31: Output port
Write: Strobe signal for writing data on pins AD0 to7
P32
HWR
1
I/O
Output
Port 32: I/O port (with pull-up resistor)
High write: Strobe signal for writing data on pins AD8 to 15
P33
WAIT
1
I/O
Input
Port 33: I/O port (with pull-up resistor)
Wait: Pin used to request CPU bus wait
P34
BUSRQ
1
I/O
Input
Port 34: I/O port (with pull-up resistor)
Bus request: Signal used to request high impedance for AD0 to 15, A0 to 23, RD, WR, HWR, R/W, RAS, CS0,
CS1, and CS2 pins. (For external DMAC)
P35
BUSAK
1
I/O
Output
Port 35: I/O (with pull-up resistor)
Bus acknowledge: Signal indicating that AD0 to 15, A0 to 23, RD, WR, HWR, R/W, RAS, CS0, CS1, and CS2
pins are at high impedance after receiving BUSRQ. (For external DMAC)
P36
R/W
1
I/O
Output
Port 36: I/O port (with pull-up resistor)
Read/write: 1 represents read or dummy cycle; 0, write cycle.
P37
RAS
1
I/O
Output
Port 37: I/O port (with pull-up resistor)
Row address strobe: Outputs RAS strobe for DRAM.
P40
CS0
CAS0
1
I/O
Output
Output
Port 40: I/O port (with pull-up resistor)
Chip select 0: Outputs 0 when address is within specified address area.
Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area.
Pin Name
Note:
4
Functions
With the external DMA controller, this device’s built-in memory or built-in I/O cannot be accessed using the BUSRQ and BUSAK pins.
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TMP93CM40/TMP93CM41
Number
of Pins
I/O
P41
CS1
CAS1
1
I/O
Output
Output
Port 41: I/O port (with pull-up resistor)
Chip select 1: Outputs 0 if address is within specified address area.
Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area.
P42
CS2
CAS2
1
I/O
Output
Output
Port 42: I/O port (with pull-up resistor)
Chip select 2: Outputs 0 if address is within specified address area.
Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area.
P50 to P53
AN0 to AN3
4
Input
Input
Port 5: Input port
Analog input: Input to A/D converter
VREF
1
Input
Pin for reference voltage input to A/D converter
AGND
Pin Name
Functions
1
Input
Ground pin for A/D converter
P60 to P63
PG00 to PG03
4
I/O
Output
Ports 60 to 63: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)
Pattern generator ports: 00 to 03
P64 to P67
PG10 to PG13
4
I/O
Output
Ports 64 to 67: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)
Pattern generator ports: 10 to 13
P70
TI0
1
I/O
Input
Port 70: I/O port (with pull-up resistor)
Timer input 0: Timer 0 input
P71
T01
1
I/O
Output
Port 71: I/O port (with pull-up resistor)
Timer output 1: Timer 0 or 1 output
P72
T02
1
I/O
Output
Port 72: I/O port (with pull-up resistor)
PWM output 2: 8-bit PWM timer 2 output
P73
T03
1
I/O
Output
Port 73: I/O port (with pull-up resistor)
PWM output 3: 8-bit PWM timer 3 output
P80
TI4
INT4
1
I/O
Input
Input
Port 80: I/O port (with pull-up resistor)
Timer input 4: Timer 4 count/capture trigger signal input
Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge
P81
TI5
INT5
1
I/O
Input
Input
Port 81: I/O port (with pull-up resistor)
Timer input 5: Timer 4 count/capture trigger signal input
Interrupt request pin 5: Interrupt request pin with rising edge
P82
TO4
1
I/O
Output
Port 82: I/O port (with pull-up resistor)
Timer output 4: Timer 4 output pin
P83
TO5
1
I/O
Output
Port 83: I/O port (with pull-up resistor)
Timer output 5: Timer 4 output pin
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5
TMP93CM40/TMP93CM41
Number
of Pins
I/O
P84
TI6
INT6
1
I/O
Input
Input
Port 84: I/O port (with pull-up resistor)
Timer input 6: Timer 5 count/capture trigger signal input
Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge
P85
TI7
INT7
1
I/O
Input
Input
Port 85: I/O port (with pull-up resistor)
Timer input 7: Timer 5 count/capture trigger signal input
Interrupt request pin 7: Interrupt request pin with rising edge
P86
TO6
1
I/O
Output
Port 86: I/O port (with pull-up resistor)
Timer output 6: Timer 5 output pin
P87
INT0
1
I/O
Input
Port 87: I/O port (with pull-up resistor)
Interrupt request pin 0: Interrupt request pin with programmable level/rising edge
P90
TXD0
1
I/O
Output
Port 90: I/O port (with pull-up resistor)
Serial send data 0
P91
RXD0
1
I/O
Input
Port 91: I/O port (with pull-up resistor)
Serial receive data 0
P92
CTS0
SCKL0
1
I/O
Input
I/O
Port 92: I/O port (with pull-up resistor)
Serial data send enable 0 (Clear to Send)
Serial Clock I/O
P93
TXD1
1
I/O
Output
Port 93: I/O port (with pull-up resistor)
Serial send data 1
P94
RXD1
1
I/O
Input
Port 94: I/O port (with pull-up resistor)
Serial receive data 1
P95
SCLK1
1
I/O
I/O
Port 95: I/O port (with pull-up resistor)
Serial clock I/O 1
PA7
SCOUT
1
I/O
Output
WDTOUT
1
Output
Watchdog timer output pin
Pin Name
Port A7: I/O port
System clock output: Outputs system clock or 1/2 oscillation clock for synchronizing to external circuit.
NMI
1
Input
Non-maskable interrupt request pin: Interrupt request pin with falling edge.
Can also be operated at rising edge by program.
CLK
1
Output
Clock output: Outputs System Clock ÷ 2 Clock.
Pulled-up during reset (can be reset to Output Disable for reducing noise).
EA
1
Input
External access: “0” should be input with TMP93CM41
“1” should be input with TMP96CM40.
AM8/16
1
Input
Address mode: Selects external data bus width
For TMP93CM40: “1” should be input. The data bus width for external access is set by Chip Select/WAIT
Control register, Port 1 Control register.
For TMP93CM41: “0” should be input with fixed 16bit bus width or 16bit bus interlarded with 8bit bus.
“1” should be input with fixed 8bit bus width.
ALE
1
Output
Address latch enable. Can be set Output disable for reducing noise.
RESET
1
Input
Reset: Initializes LSI. (With pull-up resistor)
X1/X2
2
I/O
XT1
P96
1
Input
I/O
Low Frequency Oscillator connecting pin
Port 96: I/O port (Open Drain Output)
XT2
P97
1
Output
I/O
Low Frequency Oscillator connecting pin
Port 97: I/O port (Open Drain Output)
TEST1/TEST2
2
Output
Input
TEST1 Should be connected with TEST2 pin
VCC
3
Power supply pin
VSS
3
GND pin (0V)
AVCC
1
Power supply pin for A/D converter
AVSS
1
GND pin for A/D converter (0V)
Note:
6
Functions
Oscillator connecting pin
Pull-up/pull-down resistor can be released from the pin by software.
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TMP93CM40/TMP93CM41
3.
Operation
This section describes in blocks the functions and basic
operations of TMP93CM40A/M41A devices.
Check the [7. Care Points and Restriction] because the
Care Points, etc., are described.
3.1 CPU
TMP93CM40A/M41A devices have a built-in high-performance 16-bit CPU (900L CPU). (For CPU operation, see
TLCS-900 CPU in the previous section).
This section describes CPU functions unique to TMP
93CM40/M41 that are not described in the previous section.
3.1.1 Reset
To reset the TMP93CM40, the RESET input must be kept at
0 for at least 160 system clocks (160 states: 16µs at 20MHz)
within an operating voltage range and with a stable oscillation.
When reset is accepted, the CPU sets as follows:
• Program counter (PC) to 8000H.
PC (7 : 0) → stored data to 8000H
PC (15 : 8) → stored data to 8001H
PC (23 : 16) → stored data to 8002H
Note: Reset Vector address is different with each product.
Set PC (23 : 16) to “00H” and locate Reset Vector
within 64K-byte area for TMP93CM40/M41.
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• Stack pointer (XSP) for system mode to 100H.
• IFF2 to 0 bits of status register to 111. (Sets mask register
to interrupt level 7.)
• MAX bit of status register to 0. (Sets to minimum mode.)
• Bits RFP2 to 0 of status register to 000. (Sets register
banks to 0.)
When reset is released, instruction execution starts
from PC (reset vector). CPU internal registers other than the
above are not changed.
When reset is accepted, processing for built-in I/Os,
ports, and other pins is as follows:
• Initializes built-in I/O registers as per specifications.
• Sets port pins (including pins also used as built-in I/Os) to
general-purpose input/output port mode.
• Sets the WDTOUT pin to 0. (Watchdog timer is set to
enable after reset.)
• Pulls up the CLK pin to 1.
• Sets the ALE pin to 0 (TMP93CM41), to High Impedance
(Hz) (TMP93CM40).
Note:
By resetting, register in the CPU except program counter (PC), status register (SR) and
stack pointer (XSP) and the data in internal
RAM are not changed.
7
TMP93CM40/TMP93CM41
3.2 Memory Map
Figure 3.2 is a memory map of the TMP93CM40/M41.
Figure 3.2. Memory Map
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TMP93CM40/TMP93CM41
3.3 Dual Clock Standby Function
Dual Clock, Standby Control Circuits consist of (1) System
Clock Controller, (2) Prescaler Clock Controller, and (3)
Standby Controller.
The Oscillator operation mode is classified to (a) Single
Clock mode (only X1, X2 pin), and (b) Dual Clock mode (X1,
X2, XT1, XT2 pin).
Figure 3.3.1 shows a transition figure. Figure 3.3.2 shows
the block diagram.
Figure 3.3.3 shows I/O registers.
Figure 3.3.1 (1/2). Transition Figure
The Clock Frequency input from X1, X2 pin is called fc,
and the Clock Frequency input from XT1, XT2 pin is called fs.
The clock frequency selected by SYSCR1 <SYSCK> is called
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system clock fFPH. The divided clock of fFPH is called system
clock fSYS, and the 1 cycle of fSYS is called 1 state.
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TMP93CM40/TMP93CM41
Figure 3.3.1 (2/2). Internal Operation and System Clock
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TMP93CM40/TMP93CM41
Figure 3.3.2. Block Diagram of Dual Clock, Standby Circuits
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TMP93CM40/TMP93CM41
Figure 3.3.3. I/O Register About Dual Clock, Standby
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TMP93CM40/TMP93CM41
(1)
System Clock Controller
The system clock controller generates system clock
(fSYS) for CPU core and internal I/O. It contains two
oscillation circuits and clock gear circuit for high frequency (fc). The register SYSCR1 <SYSCK> changes
system clock to either fc or fs, SYSCR0 <XEN>,
<XTEN> controls enable/disable each oscillator,
SYSCR1 <GEAR 2 : 0> changes high frequency clock
gear either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16),
these functions can reduce the power consumption.
The system clock (fSYS) is set to fc/32 (fc/16 x 1/2)
because of <XEN> = “1”, <XEN> = “0”, <SYSCK> =
“0”, <GEAR 2 : 0> = “100” by resetting.
For example, fSYS is set to 0.5MHz by resetting 16MHz
oscillator is connected to X1, X2 pins.
The high frequency (fc) and low frequency (fs) clocks
can be easily obtained by connecting a resonator to
the X1/X2, XT1/XT2 pins, respectively. Clock input
from an external oscillator is also possible.
The XT1, XT2 pins have also Port 96, 97 function.
Therefore, single clock mode, the XT1, XT2 pins can
be used as I/O port pins.
Figure 3.3.4. Examples of Resonator Connection
* Accurate Adjustment of the Oscillation Frequency
The CLK pin outputs 1/2 clock frequency (fSYS/2) to
monitor the oscillation clock.
With a system requiring adjustment of the oscillation
frequency, the adjusting program must be created
beforehand.
* Clock modes and Warming-up time
When the resonator is connected to X1, X2, or XT1,
XT2 pin, the warming-up timer is used to change the
operation frequency after getting stabilized oscillation.
The warming up time can be selected by WDMOD
<WARM>.
This starting and ending of warming up timer are performed like the following example 1, 2 by program.
Note 1: The warming up timer is also used as a
watchdog timer. So, when it is used as a
warming up timer, the watchdog timer must
be disabled.
Note 2: When using the oscillator (not resonator) with
stabilized oscillation, a warming up timer is
not needed.
Note 3: The warming up timer is operated by an
oscillation clock. Therefore, warming up time
has an error.
Table 3.3.1 Warming Up Time
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TMP93CM40/TMP93CM41
14
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TMP93CM40/TMP93CM41
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TMP93CM40/TMP93CM41
(2)
Prescaler Clock Controller
The 9 bit prescaler provides a clock to 8bit Timer 0, 1,
16bit Timer 4, 5, and Serial Interface 0, 1, and the 5
bit prescaler provides a clock to 8 bit PWM Timer 0,1.
The clock input to the 5 bit prescaler is a clock divided
by 2 which is selected either fFPH, fc/16, or fs by
SYSCR0 <PRCH1 : 0> register.
The clock input to the 9 bit prescaler is a clock
divided by 4 which is selected either fFPH, fc/16, or fs
by SYSCR0 <PRCH1 : 0> register.
<PRCK1 : 0> register is initialized to “00” resetting.
When the IDLE1 mode (operates only oscillator) is
used, set TRUN <PRRUN> to “0” to stop 9, 5 bit
prescaler before “HALT” instruction is executed.
(3)
Standby Controller
When the “HALT” instruction is executed at NORMAL
or SLOW mode, the operating mode changes RUN,
IDLE2, IDLE2, or STOP mode depending on the contents of the HALT mode setting register WDMOD
<HALTM 1 : 0>.
➀ RUN:
The built-in oscillator and the specified I/O
operates.
The power consumption is reduced to 1/3
than that during NORMAL operation.
➂ IDLE1:
Only the built-in oscillator operates, while
all other built-in circuits stop. The power
consumption is reduced to 1/10 or less
than that during NORMAL operation.
➃ STOP:
All internal circuits including the built-in
oscillator stop. This greatly reduces
power consumption.
These HALT states can be released by resetting or
requesting an interrupt. The methods for releasing the
HALT status are shown in Table 3.3 (2).
Either a non-maskable or maskable interrupt with EI
(enable interrupt) condition is acknowledged and
interrupt processing is processed. A maskable interrupt with DI (disable interrupt) condition is also
acknowledged and CPU starts executing an instruction that follows the HALT instruction, but the interrupt
request flag is held at “1”.
Only the CPU halts; power consumption
remains unchanged.
When the halt state is released by a reset, that status
in effect before entering the halt status (including built-
16
➁ IDLE2:
in RAM) is held.
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TMP93CM40/TMP93CM41
➀
RUN mode
Figure 3.3.5 shows the timing for releasing the HALT
state by interrupts in the RUN/IDLE2 mode.
In the RUN mode, the system clock in the MCU continues to operate even after a HALT instruction is exe-
cuted. Only the CPU stops executing the instruction.
Until the HALT state is released, the CPU repeats
dummy cycles. In the HALT state, an interrupt request
is sampled with the rising edge of the “CLK” signal.
The external interrupts (INT4, 5, 6, 7) releases only
RUN and IDLE2 mode.
Figure 3.3.5. Timing Chart for Releasing the HALT State by Interrupt in RUN/IDLE2 Modes
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TMP93CM40/TMP93CM41
➁
IDLE2 mode
Figure 3.3.5 shows the timing for releasing the HALT
state by interrupts in the RUN/IDLE2 mode.
In the IDLE2 mode, the HALT state is released by an
interrupt with the same timing as in the RUN mode,
18
except the internal operation of the MCU. In the RUN
mode, only the CPU stops executing the current
instruction, and the system clock is supplied to all
internal devices. In the IDLE2 mode, however, the system clock is supplied to only specific internal I/O
devices.
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TMP93CM40/TMP93CM41
➂
IDLE1 mode
Figure 3.3.6 illustrates the timing for releasing the HALT
state by interrupts in the IDLE1 mode.
In the IDLE1 mode, only the internal oscillator operates. The system clock in the MCU stops, and the
CLK pin is fixed at the “1” level.
In the HALT state, an interrupt request is sampled
asynchronously with the system clock, however the
HALT release (restart of operation) is performed synchronously with it.
The interrupts except NMI and INT0 are disabled during this mode.
When the IDLE1 mode is used, set TRUN <PRRUN>
to “0” to stop 9, 5 bit prescaler before “HALT” instruction is executed.
Figure 3.3.6. Timing Chart of HALT Released by Interrupts in IDLE1 Mode
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TMP93CM40/TMP93CM41
➃
STOP mode
Figure 3.3.7 is a timing chart for releasing the HALT
state by interrupts in the STOP mode.
The STOP mode is selected to stop all internal circuits
including the internal oscillator. In this mode, all pins
except the special ones are put in the high-impedance
state, independent of the internal operation of the
MCU. Table 3.3 (1) summarizes the state of these pins
in the STOP mode. Note, however, that the pre-halt
state (The status prior to execution of HALT instruction)
of all output pins can be retained by setting the internal
I/O register WDMOD <DRVE> to “1”. The content of
this register in initialized to “0” by resetting.
Warming up
time
Figure 3.3.7. Timing Chart of HALT Released by Interrupt in STOP Mode
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TMP93CM40/TMP93CM41
Only either the NMI, INT0, or RESET can release the
STOP mode.
When the STOP mode is released except by the
RESET, the system clock starts outputting after warming up time to get the stabilized oscillation.
A warming up time can be set using WDMOD
<WARM> bit.
See the example of warming up time in Table 3.3.2.
When the STOP mode is released by RESET, it is necessary to keep the RESET signal at “0” long enough to
release to get the stabilized oscillation because the
warming up counter is ignored.
The warming up counter operates when the STOP
mode is released even when the system which is used
as an external oscillator. As a result, it takes warming
up time from inputting the releasing request to output-
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ting the system clock.
The NORMAL/SLOW mode selection is possible after
released STOP mode.
This is selected by SYSCR0 <RSYSCK> register.
Therefore, setting to <RSYSCK>, <RXEN>, <RXTEN>
is necessary before “HALT” instruction is executed.
Additionally, setting value to <SYSCK>, <XEN>,
<XTEN> are ignored.
(Setting Example)
The STOP mode is entered when the low frequency
(fs) operates, and after that high frequency operates
after releasing by NMI.
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TMP93CM40/TMP93CM41
Table 3.3 (1) Pin States in STOP Mode
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TMP93CM40/TMP93CM41
Table 3.3 (2) Operation During Halt and How to Release the Halt Mode
Note: On the condition that the system allows the interruption to insert during HALT (STOP) operation and
chooses the different clock source before and after
HALT operation, when the system receives the interrupt during HALT (STOP) operation, the oscillation may
be chosen in the frequency the system operates
before HALT operation. If your system avoids this,
match the value <SYSCK> and <RSYSCK> before
HALT operation.
Table 3.3.2 Warming up Time After Releasing the STOP Mode Example
Warming-up time [ms]
Operation clock after the stop
mode
WDMOD <WARM> = 0
WDMOD <WARM> = 1
fc
fc/2
fc/4
fc/8
fc/16
1.024
2.048
4.096
8.192
16.384
4.096
8.192
16.384
32.768
65.536
fc = 16MHz
fs
500
200
fs = 32.768kHz
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Clock
23
TMP93CM40/TMP93CM41
3.4 Interrupts
TLCS-900 interrupts are controlled by the CPU interrupt mask
flip-flop (IFF2 to 0) and the built-in interrupt controller.
TMP93CM40/M41 have altogether the following 22 interrupt sources:
• Interrupts from the CPU…2
(Software interrupts, and Illegal (undefined) instruction execution)
• Interrupts from external pins (NMI, INT0, and INT4 to 7)…6
• Interrupts from built-in I/Os…14
A fixed individual interrupt vector number is assigned to
each interrupt source; six levels of priority (variable) can also be
assigned to each maskable interrupt. Non-maskable interrupts
have a fixed priority of 7.
When an interrupt is generated, the interrupt controller
sends the value of the priority of the interrupt source to the
CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the value of the highest
priority (7 for non-maskable interrupts is the highest) to the
CPU.
The CPU compares the value of the priority sent with the
value in the CPU interrupt mask register (IFF2 to 0). If the value
is greater than that of the CPU interrupt mask register, the
interrupt is accepted. The value in the CPU interrupt mask register (IFF2 to 0) can be changed using the EI instruction (contents of the EI num/IFF <2:0> = num). For example,
programming EI 3 enables acceptance of maskable interrupts
24
with a priority of 3 or greater, and non-maskable interrupts
which are set in the interrupt controller. The DI instruction (IFF
<2 : 0> = 7) operates in the same way as the EI 7 instruction.
Since the priority values for maskable interrupts are 0 to 6, the
DI instruction is used to disable maskable interrupts to be
accepted. The EI instruction becomes effective immediately
after execution. (With the TLCS-90, the EI instruction becomes
effective after execution of the subsequent instruction.)
In addition to the general-purpose interrupt processing
mode described above, there is also a high-speed µDMA processing mode. High-speed µDMA is a mode used by the CPU
to automatically transfer byte or word data. It enables the CPU
to process interrupts such as data saves to built-in I/Os at high
speed.
Figure 3.4 (1) is a flowchart showing overall interrupt
processing.
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TMP93CM40/TMP93CM41
Figure 3.4 (1). Interrupt Processing Flowchart
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25
TMP93CM40/TMP93CM41
3.4.1 General-Purpose Interrupt Processing
When accepting an interrupt, the CPU operates as follows:
(1)
The CPU reads the interrupt vector from the interrupt
controller. When more than one interrupt with the same
level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the
default priority (which is fixed as follows: the smaller
the vector value, the higher the priority), then clears the
interrupt request.
(2)
The CPU pushes the program counter and the status
register to the system stack area (area indicated by the
system mode stack pointer (XSP)).
(3)
The CPU sets a value in the CPU interrupt mask register <IFF2 to 0> that is higher by 1 than the value of the
accepted interrupt level. However, if the value is 7, 7 is
set without an increment.
(4)
The CPU increments the INTNEST (Interrupt Nesting
Counter).
(5)
The CPU jumps to address 8000H + interrupt vector,
then starts the interrupt processing routine.
The following diagram shows all the above processing
state number.
26
Bus Width of
Stack Area
8 bit
16 bit
Bus Width of
Interrupt Vector
Area
Interrupt Processing State Number
MAX mode
MIN mode
8 bit
35
31
16 bit
31
27
16 bit
29
27
8 bit
25
23
To return to the main routine after completion of the interrupt processing, the RETI instruction is usually used. Executing
this instruction restores the contents of the program counter
and the status registers.
Though acceptance of non-maskable interrupts cannot
be disabled by program, acceptance of maskable interrupts
can. A priority can be set for each source of maskable interrupts. The CPU accepts an interrupt request with a priority
higher than the value in the CPU mask register <IFF2 to 0>.
The CPU mask register <IFF2 to 0> is set to a value higher by
1 than the priority of the accepted interrupt. Thus, if an interrupt with a level higher than the interrupt being processed is
generated, the CPU accepts the interrupt with the higher level,
causing interrupt processing to nest.
The interrupt request with a priority higher than the
accepted now interrupt during the CPU is processing above (1)
to (5) is accepted before the 1st instruction in the interrupt processing routine, causing interrupt processing to nest. This is
the overlapped Non-Maskable interrupt (level “7”).) The CPU
does not accept an interrupt of the same level as that of the
interrupt being processed.
Resetting initializes the CPU mask registers <IFF2 to 0>
to 7; therefore, maskable interrupts are disabled.
The addresses 008000H to 0080FFH (256 bytes) of the
TMP93CM40/M41 are assigned for interrupt processing entry
area.
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TMP93CM40/TMP93CM41
Table 3.4 (1) TMP93CM40/M41 Interrupt Table
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27
TMP93CM40/TMP93CM41
3.4.2 High-Speed µDMA
In addition to the conventional interrupt processing, the TLCS900 also has a high-speed µDMA function. When an interrupt
is accepted, in addition to an interrupt vector, the CPU receives
data indicating whether processing is high-speed µDMA mode
or general-purpose interrupt. If high-speed µDMA mode is
requested, the CPU performs high-speed µDMA processing.
The TLCS-900 can process at very high speed compared with the TLCS-90 µDMA because it has transfer parameters in dedicated registers in the CPU. Since those dedicated
registers are assigned as CPU control registers, they can only
be accessed by the LDC instruction.
(1)
High-Speed µDMA Operation
High-speed µDMA operation starts when the accepted
interrupt vector value matches the µDMA start vector
value set in the interrupt controller. The high-speed
µDMA has four channels so that it can be set for up to
four types of interrupt source.
When a high-speed µDMA interrupt is accepted, data
is automatically transferred from the transfer source
address to the transfer destination address set in the
control register, and the transfer counter is decremented. If the value in the counter after decrementing
is other than 0, high-speed µDMA processing is completed. If the value in the counter after decrementing is
28
0, general-purpose interrupt processing is performed.
In read-only mode, which is provided for DRAM
refresh, the value in the counter is ignored and dummy
read is repeated.
32-bit control registers are used for setting transfer
source/destination addresses. However, the TLCS900 has only 24 address pins for output. A 16M-byte
space is available for the high-speed µDMA.
There are two data transfer modes: one-byte mode
and one-word mode. Incrementing, decrementing, and
fixing the transfer source/destination address after
transfer can be done in both modes. Therefore, data
can easily be transferred between I/O and memory
and between I/Os. For details of transfer modes, see
the description of transfer mode registers.
The transfer counter has 16 bits, so up to 65536 transfers (the maximum when the initial value of the transfer
counter is 0000H) can be performed for one interrupt
source by high-speed µDMA processing.
Interrupt sources processed by high-speed µDMA processing are those with the high-speed µDMA start
vectors listed in Table 3.4 (1).
The following timing chart is a high-speed µDMA cycle
of the Transfer Address Increment mode (the other
mode except the Read-only mode is same as this).
(Condition: MIN mode, 16bit Bus width for 16M Byte, 0
wait).
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TMP93CM40/TMP93CM41
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29
TMP93CM40/TMP93CM41
30
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TMP93CM40/TMP93CM41
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31
TMP93CM40/TMP93CM41
(2)
Register Configuration (CPU Control Register)
These Control Registers cannot be set only “LCD cr, r” instruction.
32
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TMP93CM40/TMP93CM41
(3)
Transfer Mode Register Details
Do not use undefined codes for transfer mode control.
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33
TMP93CM40/TMP93CM41
<Example for Usage of read only mode (DRAM refresh)>
➂ Interrupt controller setting
Set the timer interrupt mask higher than the other interrupt mask. Write the above timer interrupt vector value
in the High-Speed µDMA start vector register, DMA0V.
(Operation description)
When the hardware configuration is as follows:
DRAM mapping size:
= 1MB
DRAM data bus size:
= 8 bits
DRAM mapping address range: = 100000H to
1FFFFFH
Set the following registers first; refresh is performed
automatically.
The DRAM data bus is an 8-bit bus and the µDMA is in
read-only mode (4 bytes), so refresh is performed four
times per interrupt.
When a 512 refresh/8ms DRAM is connected, DRAM
refresh is performed sufficiently if the µDMA is started
every 15.625µs x 4 = 62.4µs or less, since the timing is
15.625µs/refresh.
➀ Register initial value setting
(Overhead)
LD
LDC
LD
LDC
XIX, 100000H
DMAS0, XIX
A, 00001010B
DMAM0, A
…
mapping start address
…
read only mode (for
DRAM refresh)
➁ Timer Setting
Set the timers so that interrupts are generated at intervals of 62.5µs or less.
34
Each processing time by the High-Speed µDMA is
1.8µs (18 states) at 20MHz with an 8-bit data bus.
In the above example, the micro DMA is started every
62.5µs, 1.8µs/62.5µs = 0.029; thus, the overhead is
2.88%.
(Note)
When the Bus is released (BUSAK = “0”) which must
wait to accept the interrupt, DRAM refresh is not performed because of the high-speed µDMA is generated
by an interrupt.
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TMP93CM40/TMP93CM41
3.4.3 Interrupt Controller
Figure 3.4.3 (1) is a block diagram of the interrupt circuits. The
left half of the diagram shows the interrupt controller; the right
half includes the CPU interrupt request signal circuit and the
HALT release signal circuit.
Each interrupt channel (total of 20 channels) in the interrupt controller has an interrupt request flip-flop, interrupt priority setting register, and a register for storing the high-speed
µDMA start vector. The interrupt request flip-flop is used to
latch interrupt requests from peripheral devices. The flip-flop is
cleared to 0 at reset, when the CPU reads the interrupt channel vector after the acceptance of interrupt, or when the CPU
executes an instruction that clears the interrupt of that channel
(writes 0 in the clear bit of the interrupt priority setting register).
For example, to clear the INT0 interrupt request, set the
register after the DI instruction as follows.
INTE0AD←---- 0 ---
Zero-clears the INT0 Flip-Flop.
The status of the interrupt request flip-flop is detected by
reading the clear bit. Detects whether there is an interrupt
request for an interrupt channel.
The interrupt priority can be set by writing the priority in
the interrupt priority setting register (e.g., INTE0AD, INTE45,
etc.) provided for each interrupt source. Interrupt levels to be
set are from 1 to 6. Writing 0 or 7 as the interrupt priority disables the corresponding interrupt request. The priority of the
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non-maskable interrupt (NMI pin, watchdog timer, etc.) is fixed
to 7. If interrupt requests with the same interrupt level are generated simultaneously, interrupts are accepted in accordance
with the default priority (the smaller the vector value, the higher
the priority).
The interrupt controller sends the interrupt request with
the highest priority among the simultaneous interrupts and its
vector address to the CPU. The CPU compares the priority
value <IFF2 to 0> set in the Status Register by the interrupt
request signal with the priority value sent; if the latter is higher,
the interrupt is accepted. Then the CPU sets a value higher
than the priority value by 1 in the CPU SR <IFF2 to 0>. Interrupt requests where the priority value equals or is higher than
the set value are accepted simultaneously during the previous
interrupt routine. When interrupt processing is completed (after
execution of the RETI instruction), the CPU restores the priority
value saved in the stack before the interrupt was generated to
the CPU SR <IFF2 to 0>.
The interrupt controller also has four registers used to
store the high-speed µDMA start vector. These are I/O registers; unlike other DMA registers (DMAS, DMAD, DMAM, and
DMAC), they can be accessed in either normal or system
mode. Writing the start vector of the interrupt source for the
µDMA processing (see Table 3.4 (1)), enables the corresponding interrupt to be processed by µDMA processing. The values
must be set in the µDMA parameter registers (e.g., DMAS and
DMAD) prior to the µDMA processing.
35
TMP93CM40/TMP93CM41
Figure 3.4.3 (1). Block Diagram of Interrupt Controller
36
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TMP93CM40/TMP93CM41
(1)
Interrupt Priority Setting Register
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37
TMP93CM40/TMP93CM41
* Note about clearing interrupt request flag
The interrupt request flag of INTAD, INTRX0, INTRX1
are not cleared by writing “00” to IXXC because they
(2)
are level interrupts.
They can be cleared only by resetting or reading
ADREGn/SCBUFn.
External Interrupt Control
Setting of External Interrupt Pin Functions
38
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TMP93CM40/TMP93CM41
(3)
High-Speed µDMA Start Vector
When the CPU reads the interrupt vector after accepting an interrupt, it simultaneously compares the interrupt vector with each channel’s µDMA start vector
(bits 4 to 8 of the interrupt vector). When both match,
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the interrupt is processed in µDMA mode for the
channel whose value matched.
If the interrupt vector matches more than one channel,
the channel with the lower channel number has a
higher priority.
39
TMP93CM40/TMP93CM41
(4)
Notes
The instruction execution unit and the bus interface
unit of this CPU operate independently of each other.
Therefore, if the instruction used to clear an interrupt
request flag of an interrupt is fetched before the interrupt is generated, it is possible that the CPU might
execute the fetched instruction to clear the interrupt
40
request flag while reading the interrupt vector after
accepting the interrupt. If so, the CPU would read the
default vector “0028H” and start the interrupt processing from the address “8028H”.
To avoid this, make sure that the instruction used to
clear the interrupt request flag comes after the DI
instruction.
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TMP93CM40/TMP93CM41
3.5 Functions of Ports
The TMP93CM40/TMP96PM40 has 79 bits for I/O ports. The
TMP93CM41 has 61 bits for I/O ports because Port0, Port1,
P30, and P31 are dedicated pins for AD0 to 7, AD8 to 15, RD,
and WR.
These port pins have I/O functions for the built-in CPU
and internal I/Os as well as general-purpose I/O port functions.
Table 3.5 lists the function of each port pin.
↑ = With programmable pull-up resistor
↓ = WIth programmable pull-down)
(R:
Table 3.5 Functions of Ports
Port Name
Pin Name
Number of
Pins
Direction
Port0
P00 to P07
8
I/O
–
Bit
AD0 to AD7
Port1
P10 to P17
8
I/O
–
Bit
AD8 to AD15/ A8 to A15
Port2
P20 to P27
8
I/O
↓
Bit
A0 to A7/ A16 to A23
Port 3
P30
P31
P32
P33
P34
P35
P36
P37
1
1
1
1
1
1
1
1
Output
Output
I/O
I/O
I/O
I/O
I/O
I/O
–
–
↑
↑
↑
↑
↑
↑
(Fixed)
(Fixed)
Bit
Bit
Bit
Bit
Bit
Bit
Port4
P40
P41
P42
1
1
1
I/O
I/O
I/O
↑
↑
↓
Bit
Bit
Bit
CS0 / CAS0
CS1 / CAS1
CS2 / CAS2
Port5
P50 to P57
8
Input
–
(Fixed)
AN0 to AN7
R
Direction Setting Unit
Pin Name for Built-in Function
RD
WR
HWR
WAIT
BUSRQ
BUSAK
R/W
RAS
Port6
P60 to P67
8
I/O
↑
Bit
PG00 to PG03, PG10 to PG13
Port7
P70
P71
P72
P73
1
1
1
1
I/O
I/O
I/O
I/O
↑
↑
↑
↑
Bit
Bit
Bit
Bit
TI0
TO1
TO2
TO3
Port8
P80
P81
P82
P83
P84
P85
P86
P87
1
1
1
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
↑
↑
↑
↑
↑
↑
↑
↑
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
T14/INT4
T15/INT5
TO4
TO5
TI6 / INT6
TI7 / INT7
TO6
INT0
Port9
P90
P91
P92
P93
P94
P95
P96
P97
1
1
1
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
↑
↑
↑
↑
↑
↑
–
–
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
TXD0
RXD0
CTS0
TXD1
RXD1
SCLK1
XT1
XT2
PortA
PA7 to PA0
8
I/O
–
Bit
SCOUT (PA7)
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TMP93CM40/TMP93CM41
Resetting makes the port pins listed below function as
general-purpose I/O ports.
I/O pins programmable for input or output function as
input ports except P96/XT1, P97/XT2.
To set port pins for built-in functions, a program is
required.
* Notes about the bus release and programmable pullup/down I/O ports:
Since the TMP96C141 has an external ROM, some ports
are permanently assigned to the CPU.
•
•
•
•
P00 to P07
P10 to P17
P30
P31
→
→
→
→
AD0 to AD7
AD8 to AD15
RD
WR
When buses are released (BUSAK = 0), the TMP96C141/
TMP96CM40/TMP96PM40 sets the output buffer for AD0 to
AD15, A0 to A23, and bus control signals (RD, WR, HWR, R/
W, RAS, CS0/CAS0 - CS2/CAS2) to off to set them to high
impedance. The internal programmable pull-up/pull-down
resistors continue to operate. Resistors are programmable only
for operations in input mode; not in output mode.
Pin states at bus release are shown below.
Pin state at bus release
Pin Name
Port mode
P00 to P07
(AD0 to AD7)
P10 to P17
(AD8 to AD15)
The state is not changed
(does not become high-impedance (HZ).)
P30 (RD)
P31 (WR)
becomes high-impedance (HZ)
P32 (HWR)
P37 (RAS)
The output buffer to OFF.
The programmable pull-up resistor is ON only when the
output latch is equal to “1”.
P36 (R/W)
P40 (CS0/CAS0)
P41 (CS1/CAS1)
42
↑
Function mode
becomes high-impedance (HZ)
←
The output buffer to OFF.
The programmable pull-up resistor is ON regardless of the
output latch.
The output buffer to OFF.
The programmable pull-down resistor is undefined.
P42 (CS2/CAS2)
The output buffer to OFF.
The programmable pull-up resistor is ON only when the
output latch is equal to “0”.
The output buffer to OFF.
The programmable pull-down resistor is undefined.
P20 to P27
(A16 to A23)
The state is not changed.
(does not become high-impedance (HZ).)
The output buffer to OFF.
The programmable pull-up resistor is ON only when the
output latch is equal to “0”.
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TMP93CM40/TMP93CM41
The following are the example of the interface circuit of
the above pins when the bus releasing function is used.
When the bus is released, both internal memory and
internal I/O cannot be accessed, but the internal I/O continues
to operate.
So, the watchdog timer also continues to run. Therefore,
be careful about bus releasing time and set the detection time
of WDT.
Example of external bus interface using bus release function.
The above circuit is necessary to fix the signal level when
the bus is released.
Reset sets P30 (RD), P31 (WR) to output, P40 (CS0),
P41 (CS1), P32 (HWR), P36 (R/W), P37 (RAS), and P35
(BUSAK) are set to input mode using a pull-up resistor, P42
(CS2) and P20 to P27 (A16 to 23) to input with pull-down
resistor.
The above circuit is necessary to fix the signal level after
reset because of the external pull-up resistor collisions with the
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internal pull-down resistor.
The value of this external pull-up resistor value must be 3
to 5 kΩ. (The value of the internal pull-down resistor is about
50 to 150kΩ)
P20 to 27 (A16 to 23) also needs a circuit like circuit P42
(CS2) to fix the signal level.
But for the P20 to P27 (A16 to 23) which does not have
the means (“L” is active), add pull down directly like the above
circuit.
43
TMP93CM40/TMP93CM41
3.5.1 Port 0 (P00 to P07)
Port 0 is an 8-bit general-purpose I/O port. I/O can be set on a
bit basis using control register P0CR to 0 and sets Port 0 to
input mode.
In addition to functioning as a general purpose I/O port,
Port 0 also functions as an address data bus (AD0 to 7). To
access external memory, Port 0 functions as an address data
bus (AD 0 to 7) and all bits of the control register P0CR are
cleared to 0.
With the TMP9eCM041, which needs external ROMs,
Port 0 always functions as an address data bus (AD0 to 7)
regardless of the value set in control register P0CR.
Figure 3.5 (1). Port 0
44
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3.5.2 Port 1 (P10 to P17)
Port 1 is an 8-bit general-purpose I/O port. I/O can be set on a
bit basis using control register P1CR and function register
P1FC. Resetting resets all bits of output latch P1, control register P1CR, and function register P1FC to 0 and sets Port 1 to
input mode.
In addition to functioning as a general purpose I/O port,
Port 1 also functions as an address data bus (AD8 to 15) or an
address bus (A8 to 15).
With the TMP93CM41, which needs external ROMs,
Port 1 always functions as an address data bus (AD8 to 15)
(AM8/16 = “0”), as an address bus (A8 to 15) (AM8/16 = “1”)
regardless of the value set in control register P1CR.
Figure 3.5 (2). Port 1
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TMP93CM40/TMP93CM41
Figure 3.5 (3). Registers for Ports 0 and 1
46
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TMP93CM40/TMP93CM41
3.5.3 Port 2 (P20 to P27)
Port 2 is an 8-bit general-purpose I/O port. I/O can be set on
bit basis using the control register P2CR and function register
P2FC. Resetting resets all bits of output latch P2, control register P2CR and function register P2FC to 0. It also sets Port 2 to
input mode and connects a pull-down resistor. To disconnect
the pull-down resistor, write 1 in the output latch.
In addition to functioning as a general-purpose I/O port,
Port 2 also functions as an address data bus (A0 to 7) and an
address bus (A16 to 23).
Figure 3.5 (4). Port 2
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TMP93CM40/TMP93CM41
Figure 3.5 (5). Registers for Port 2
48
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TMP93CM40/TMP93CM41
3.5.4 Port 3 (P30 to P37)
Port 3 is an 8-bit general-purpose I/O port.
I/O can be set on a bit basis, but note that P30 and P31
are used for output only. I/O is set using control register P3CR
and function register P3FC. Resetting resets all bits of output
latch P3, control register P3CR (bits 0 and 1 are unused), and
function register P3FC to 0. Resetting also outputs 1 from P30
and P31, sets P32 to P37 to input mode, and connects a pullup resistor.
In addition to functioning as a general-purpose I/O port,
Port 3 also functions as an I/O for the CPU’s control/status signal.
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With the TMP96C140, when P30 pin is defined as RD
signal output mode (<P30F> = 1), clearing the output latch
register <P30> to 0 outputs the RD strobe (used for the
pseudo static RAM) from the P30 pin even when the internal
address area is accessed.
If the output latch register <P30> remains 1, the RD
strobe signal is output only when the external address area is
accessed.
With the TMP93CM41, which comes with an external
ROM, Port 30 outputs the RD signal; P31, the WR signal,
regardless of the values set in function registers P30F and
P31F.
49
TMP93CM40/TMP93CM41
Figure 3.5 (6). Port 3 (P30, P31, P32, P35, P36, P37)
50
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TMP93CM40/TMP93CM41
Figure 3.5 (7). Port 3 (P33, P34)
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51
TMP93CM40/TMP93CM41
Figure 3.5 (8). Registers for Port 3
52
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TMP93CM40/TMP93CM41
3.5.5 Port 4 (P40 to P42)
Port 4 is a 3-bit general-purpose I/O port. I/O can be set on a
bit basis using control register P4CR and function register
P4FC. Resetting does the following:
In addition to functioning as a general-purpose I/O port,
Port 4 also functions as a chip select output signal (CS0 to
CS2 or CAS0 to CAS2).
- Sets the P40 and P42 output latch registers to 1.
- Resets all bits of the P42 output latch register, the control
register P4CR, and the function register P4FC to 0.
- Sets P40 and P41 to input mode and connects a pull-up
resistor.
- Sets P42 to input mode and connects a pull-down resistor.
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TMP93CM40/TMP93CM41
Figure 3.5 (9). Port 4
54
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TMP93CM40/TMP93CM41
Figure 3.5 (10). Registers for Port 4
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TMP93CM40/TMP93CM41
3.5.6 Port 5 (P50 to P57)
Port 5 is an 8-bit input port, also used as an analog input pin
for the internal A/D Converter.
Figure 3.5 (11). Port 5
Figure 3.5 (12). Registers for Port 5
56
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TMP93CM40/TMP93CM41
3.5.7 Port 6 (P60 to P67)
Port 6 is an 8-bit general-purpose I/O port. I/O can be set on
bit basis. Resetting sets Port 6 as an input port and connects
a pull-up resistor. It also sets all bits of the output latch to 1. In
addition to functioning as a general-purpose I/O port, Port 6
also functions as a pattern generator PG0/PG1 output. PG0 is
assigned to P60 to P63; PG1, to P64 to P67. Writing 1 in the
corresponding bit of the port 6 function register (P6FC)
enables PG output. Resetting resets the function register
P6FC value to 0, and sets all bits to ports.
Figure 3.5 (13). Port 6
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TMP93CM40/TMP93CM41
Figure 3.5 (14). Registers for Port 6
58
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TMP93CM40/TMP93CM41
3.5.8 Port 7 (P70 to P73)
Port 7 is a 4-bit general-purpose I/O port. I/O can be set on bit
basis. Resetting sets Port 7 as an input port and connects a
pull-up resistor. In addition to functioning as a general-purpose
I/O port, Port 70 also functions as an input clock pin TI0; Port
71 as an 8-bit timer output (TO1), Port 72 as a PWM0 output
(TO2), and Port 73 as a PWM1 output (TO3) pin. Writing 1 in
the corresponding bit of the Port 7 function register (P7FC)
enables output of the timer. Resetting resets the function register P7FC value to 0, and sets all bits to ports.
Figure 3.5 (15). Port 7
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TMP93CM40/TMP93CM41
Figure 3.5 (16). Registers for Port 7
60
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TMP93CM40/TMP93CM41
3.5.9 Port 8 (P80 to P83)
Port 8 is an 8-bit general-purpose I/O port. I/O can be set on a
bit basis. Resetting sets Port 8 as an input port and connects
a pull-up resistor. It also sets all bits of the output latch register
P8 to 1. In addition to functioning as a general-purpose I/O
port, Port 8 also functions as an input for 16-bit timer 4 and 5
(1)
clocks, an output for 16-bit timer F/F 4, 5 and 6 output, and an
input for INT0. Writing “1” in the corresponding bit of the Port 8
function register (P8FC) enables those functions. Resetting
resets the function register P8FC value to “0”, and sets all bits
to ports.
P80 to P86
Figure 3.5 (17). Port 8 (P80 to P86)
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TMP93CM40/TMP93CM41
(2)
an INT0 pin for external interrupt request input.
P87 (INT0)
Port 87 is a general-purpose I/O port, and also used as
Figure 3.5 (18). Port 87
62
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TMP93CM40/TMP93CM41
Figure 3.5 (19). Registers for Port 8
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63
TMP93CM40/TMP93CM41
3.5.10 Port 9 (P90 to P95)
• Port 90 to 95
Ports 90 to 95 is a 6-bit general-purpose I/O port. I/Os can be
set on a bit basis.
Resetting sets P90 to 95 to an input port and connects a
pull-up resistor.
It also sets all bits of the output latch register to 1.
In addition to functioning as a general-purpose I/O port,
P90 to 95 can also function as an I/O for serial channels 0 and
1. Writing “1” in the corresponding bit of the port 9 function
register (P9FC) enables this function.
Resetting resets the function register value to “0” and
sets all bits to ports.
• Port 96 to 97
Ports 96 to 97 is a 2-bit general-purpose I/O port. I/Os can be
set on a bit basis.
The output buffer for P96 to 97 to an open drain type
buffer
Resetting sets P96 to 97 to an output port and outputs
high-impedance (HZ) because output latch and control register
are set to “1”.
In addition to functioning as a general-purpose I/O port,
P96 to 97 can also function as a low frequency oscillator pin
fro dual clock mode. The dual clock function can be set by
programming system clock control register SYSCR0, 1.
(1)
Port 90, 93 (TXD0/TXD1)
Ports 90 and 93 also function as serial channel TXD
output pins in addition to I/O ports.
They have a programmable open drain function.
Figure 3.5 (20). Ports 90 and 93
64
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TMP93CM40/TMP93CM41
(2)
Ports 91, 94 (RXD0, 1)
input pins for serial channels.
Ports 91 and 94 are I/O ports, and also used as RXD
Figure 3.5 (21). Ports 91 and 94
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TMP93CM40/TMP93CM41
(3)
Port 92 (CTS)
pin and as a SCLK0 I/O pin for serial channels.
Port 92 is an I/O port, and also used as a CTS input
Figure 3.5 (22). Port 92
66
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TMP93CM40/TMP93CM41
(4)
Port 95 (SCLK)
an SCLK1 I/O pin for serial channel 1.
Port 95 is a general-purpose I/O port. It is also used as
Figure 3.5 (23). Port 95
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TMP93CM40/TMP93CM41
(5)
Port 96 (XT1), 97 (XT2)
used as a low frequency connecting pin.
Port 96, 97 are general-purpose I/O ports. It is also
Figure 3.5 (24). Port 96 to 97
68
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TMP93CM40/TMP93CM41
Figure 3.5 (25). Register for Port 9
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69
TMP93CM40/TMP93CM41
3.5.11 Port A (PA0 to PA7)
Port A is an 8-bit general-purpose I/O port. I/O can be set on a
bit basis by control register PACR.
Resetting sets Port A as an input port by resetting PACR.
It also sets all bits of the output latch register to “1”.
In addition to functioning as a general-purpose I/O port
(only PA7), PA7 can also function as a clock output pin.
The clock output is fFPH or fSYS that is selected oscillator
output clock. It is selected by CKOCR <SCOSEL>.
SCOUT function is enabled by setting PACR <PA7C>
and CKOCR <SCOEN>.
Figure 3.5 (26). Port A0 to A6
70
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TMP93CM40/TMP93CM41
Figure 3.5 (27). Port A7
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71
TMP93CM40/TMP93CM41
Figure 3.5 (28). Registers for Port A
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TMP93CM40/TMP93CM41
3.6 Chip Select/Wait Control, AM8/16 pin
TMP93CM40/M41 has a built-in chip select/wait controller
used to control chip select (CS0 - CS2 pins), wait (WAIT pin),
and data bus size (8 or 16 bits) for any of the three block
address areas, and AM8/16 pin selects external data bus
width for TMP93CM41.
3.6.1 AM8/16 pin
(1)
TMP93CM40
Set this pin to “1”. After reset, the CPU accesses the
internal ROM with 16 bit bus width. When the CPU
access an external bus area, the bus width is set by
Chip Select/Wait Control Register (described at 3.6.2),
P1CR and P1FC (The value “1” of this pin is ignored
and the value set by register is active).
(2)
3.6.2 Control Registers
Table 3.6 (1) shows control registers
One block address areas are controlled by 1-byte CS/
WAIT control registers (B0CS, B1CS, and B2CS). Registers
can be written to only when the CPU is in system mode. (There
are two CPU modes: system and normal.) The reason is that
the settings of these registers have an important effect on the
system.
(1)
Control register bit 7 (B0E, B1E, and B2E) is a master
bit used to specify enable (1)/disable (0) of the setting.
Resetting B0E and B1E to disable (0) and B2E to
enable (1).
(2)
TMP93CM41
(2-2) fixed bit bus width
Set this pin to “1”. Port 1/AD8 to 15/A8 to 15 pins are
then fixed to A8 to 15 function compulsorily and the
value of P1CR, P1FC are ignored. The value of bit 4:
<B0BUS>, <B1BUS>, or <B2BUS> described at
3.6.2 are ignored and the bus width is fixed to 8 bit.
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CS/CAS Waveform select
Control register bit 5 (B0CAS, B1CAS, and B2CAS) is
used to specify waveform mode output from the chip
select pin (CS0/CAS0 - CS2/CAS2). Setting this bit to
0 specifies CS0 to CS2 waveforms; setting it to 1
specifies CAS0 to CAS2 waveforms.
Resetting clears bit 5 to 0.
(2-1) 16 bit bus width interlarded with 8 bit bus width
or fixed 16 bit bus width
Set this pin to “0”. Port 1/AD8 to 15/A8 to 15 pins are
then fixed to A8 to 15 function compulsorily and the
value of P1CR, P1FC are ignored.
When the CPU accesses an external bus area, the bus
width is set by Chip Select/Wait Control Register as
described in section 3.6.2.
However, the bus width program memory only after
reset must be 16 bit bus width.
Enable
(3)
Data bus size select
Bit 4 (B0BUS, B1BUS, and B2BUS) of the control register is used to specify data bus size. Setting this bit to
0 accesses the memory in 16-bit data bus mode; setting it to 1 accesses the memory in 8-bit data bus
mode.
Changing data bus size depending on the access
address is called dynamic bus sizing. Table 3.6 (2)
shows the details of the bus operation.
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TMP93CM40/TMP93CM41
(4)
Wait control
Control register bits 3 and 2 (B0W1, 0; B1W1, 0; B2W1,
0) are used to specify the number of waits. Setting these
bits to 00 inserts a 2-state wait regardless of the WAIT
pin status. Setting them to 01 inserts a 1-state wait
regardless of the WAIT status. Setting them to 10
inserts a 1-state wait and samples the WAIT pin status.
If the pin is low, inserting the wait maintains the bus
cycle until the pin goes high. Setting them to 11 completes the bus cycle without a wait regardless of the
WAIT pin status.
Resetting sets these bits to 00 (2-state wait mode).
(5)
Address area specification
Control register bits 1 and 0 (B0C1, 0; B1C1, 0; B2C1,
0) are used to specify the target address area. Setting
these bits to 00 enables settings (CS output, Wait
state, Bus size, etc.) as follows:
74
* CS0 setting enabled when 7F00H to 7FFFH is
accessed.
* CS1 setting enabled when 880H to 7FFFH is
accessed.
* CS2 setting enabled when 8000H to 3FFFFFFH is
accessed, for the TMP93CM41, which does not have
a built-in ROM.
CS2 setting enabled when 10000H to 3FFFFFH is
accessed for the TMP93CM40, which has built-in
ROM.
Setting bits to 01 enables setting for all CS’s blocks
and outputs a low strobe signal (CS0/CAS0 ~ CS2/
CAS2) from chip select pins when 400000H to
7FFFFFH is accessed. Setting bits to 10 enables them
800000H to BFFFFFH is accessed. Setting bits to 11
enables them when C00000H to FFFFFFH is
accessed.
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TMP93CM40/TMP93CM41
Table 3.6 (1) Chip Select/Wait Control Register
Code
B0CS
B1CS
B2CS
Note:
Name
Block0
CS/WAIT
control
register
Block1
CS/WAIT
control
register
Block2
CS/WAIT
control
register
Address
0068H
0069H
006AH
7
6
5
4
3
2
1
0
B0E
B0CAS
B0BUS
B0W1
B0W0
B0C1
B0C0
W
W
W
W
W
W
W
0
0
0
0
0
0
0
1 : Master bit
of bit 0 to 6
0 : CSO
1 : CAS0
B1E
B1CAS
B1BUS
B1W1
B1W0
B1C1
B1C0
W
W
W
W
W
W
W
0
0
0
0
0
0
0
1 : Master bit
of bit 0 to 6
0 : CS1
1 : CAS1
B2E
B2CAS
B2BUS
B2W1
B2W0
B2C1
B2C0
W
W
W
W
W
W
W
1
0
0
0
0
0
0
1 : Master bit
of bit 0 to 6
0 : CS2
1 : CAS2
00 : 2WAIT
01 : 1WAIT
10 : 1WAIT + n
11 : 0WAIT
0 : 16 bit
Bus
1 : 8 bit
Bus
00 : 2WAIT
01 : 1WAIT
10 : 1WAIT + n
11 : 0WAIT
0 : 16 bit
Bus
1 : 8 bit
Bus
0 : 16 bit
Bus
1 : 8 bit
Bus
00 : 2WAIT
01 : 1WAIT
10 : 1WAIT +n
11 : 0WAIT
00 : 7F00H to 7FFFH
01 : 400000H to
10 : 800000H to
11 : C00000H to
00 : 880H to 7FFFH
01 : 400000H to
10 : 800000H to
11 : C00000H to
00 : 8000H to
01 : 400000H to
10 : 800000H to
11 : C00000H to
Only block 2 is enable (16-bit data bus, 2-wait mode) after reset.
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TMP93CM40/TMP93CM41
Table 3.6 (2) Dynamic Bus Sizing
Operand
Start Address
Memory
Data Size
CPU Address
2n + 0
(even number)
8 bits
8 bits
2n + 1
(odd number)
2n + 0
(even number)
16 bits
2n + 1
(odd number)
2n + 0
(even number)
D15 to D8
D7 to D0
2n + 0
xxxxx
b7 to b0
16 bits
2n + 0
xxxxx
b7 to b0
8 bits
2n + 1
xxxxx
b7 to b0
16 bits
2n + 1
b7 to b0
xxxxx
8 bits
2n + 0
2n + 1
xxxxx
xxxxx
b7 to b0
b15 to b8
16 bits
2n + 0
b15 to b8
b7 to b0
8 bits
2n + 1
2n + 2
xxxxx
xxxxx
b7 to b0
b15 to b8
16 bits
2n + 1
2n + 2
b7 to b0
xxxxx
xxxxx
b15 to b8
2n + 0
2n + 1
2n + 2
2n + 3
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
b15 to b8
b23 to b16
b31 to b24
2n + 0
2n + 2
b15 to b8
b31 to b24
b7 to b0
b23 to b16
2n + 1
2n + 2
2n + 3
2n + 4
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
b15 to b8
b23 to b16
b31 to b24
2n + 1
2n + 2
2n + 4
b7 to b0
b23 to b16
xxxxx
xxxxx
b15 to b8
b31 to b24
8 bits
16 bits
32 bits
2n + 1
(odd number)
8 bits
16 bits
xxxxx:
76
CPU Data
Operand
Data Size
During a read, data input to the bus is ignored. At write, the bus is at high impedance and the write strobe signal remains non-active.
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TMP93CM40/TMP93CM41
3.6.3 Chip Select Image
An image of the actual chip select is shown below. Out of the
whole memory area, address areas that can be specified are
divided into four parts. Addresses from 000000H to 3FFFFFH
are divided differently: 7F00H to 7FFFH is specified for CS0;
880H to 7FFFH, for CS1; and 8000H to 3FFFFFH, for CS2.
The reason is that a device other than ROM (i.e., RAM or I/O)
might be connected externally.
7F00 to 7FFFH (256 bytes) for CS0 are mapped mainly
for possible expansions to external I/O.
880H to 7FFFH (approximately 31K bytes) for CS1 are
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mapped there mainly for possible extensions to external RAM.
8000H to 3FFFFFFH (approximately 4M bytes) for CS2
are mapped mainly for possible extensions to external ROM.
After reset, CS2 is enabled in 16-bit bus and 2-wait. With the
TMP93CM41, which does not have a built-in ROM, the program is externally read at address 8000H in this setting (16-bit
bus, 2-wait). With the TMP93CM40, which has a built-in ROM,
addresses from 8000H to FFFFFH are used as the internal
ROM area; CS2 is disabled in this area. After reset, the CPU
reads the program from the built-in ROM in 16-bit bus, 0-wait
mode.
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TMP93CM40/TMP93CM41
3.6.4 Example of Usage
(1)
Example of Usage - 1
Figure 3.6 (1) is an example in which an external memory is connected to the TMP93CM41. In this example,
a ROM is connected using 16-bit Bus; a RAM is connected using 8-bit Bus.
Figure 3.6 (1). Example of External Memory Connection (ROM = 16 bits, RAM and I/O = 8 bits)
Resetting sets pins CS0 to CS2 to input port mode.
CS0 and CS1 are set high due to an internal pull-up
78
resistor; CS2, low due to an internal pull-down resistor.
The program used to set these pins is as follows:
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TMP93CM40/TMP93CM41
(2)
Example of Usage - 2
Figure 3.6 (2) is an example in which an external mem-
ory is connected to the TMP93CM41. In this example,
a ROM, a RAM, and I/O are connected using 8-bit
bus.
Figure 3.6 (2). Example of External Memory Connection (ROM and RAM and I/O = 8 bits)
Resetting sets pins CS0 to CS2 to input port mode.
CS0 and CS1 are set high due to an internal pull-up
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resistor; CS2, low due to an internal pull-down resistor.
The program used to set these pins is as follows:
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TMP93CM40/TMP93CM41
3.7 8-bit Timers
TMP93CM40/M41 contains two 8-bit timers (timers 0 and 1),
each of which can be operated independently. The cascade
connection allows these timers to be used as 16-bit timer. The
following four operating modes are provided for the 8-bit timers.
• 8-bit interval timer mode (2 timers)
• 16-bit interval timer mode (1 timer)
• 8-bit programmable square wave pulse generation (PPG :
variable duty with variable cycle) output mode (1 timer)
• 8-bit pulse width modulation (PWM: variable duty with con-
80
stant cycle) output mode (1 timer)
Figure 3.7 (1) shows the block diagram of 8-bit timer
(timer 0 and timer 1).
Each interval timer consists of an 8-bit up-counter, 8-bit
comparator, and 8-bit timer register. Besides, one timer flipflop (TFF1) is provided for pair of timer 0 and timer 1.
Among the input clock sources for the interval timers, the
internal clocks of φ T1, φ T4, φT16, and φT256 are obtained
from the 9-bit prescaler shown in Figure 3.7 (2).
The operation modes and timer flip-flops of the 8-bit
timer are controlled by three control registers TMOD, TFFCR,
and TRUN.
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Figure 3.7 (1). Block Diagram of 8-Bit Timers (Timers 0 and 1)
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TMP93CM40/TMP93CM41
➀ Prescaler
Figure 3.7 (2) shows the block digram. Table 3.7 (1)
shows prescaler clock resolution to 8, 16 bit Timer.
There are 9 bit prescaler and prescaler clock selection
register to generate input clock for 8 bit Timer 0, 1, 16
bit Timer 4, 5 and Serial Interface.
Figure 3.7 (2). Prescaler Block Diagram
Table 3.7 (1) Prescaler Clock Resolution to 8, 16 bit Timer
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TMP93CM40/TMP93CM41
The 1/4 times clock selected among fFPH clock is input
to this prescaler. This is selected by prescaler clock
selection register SYSCR0 <PRCK1 : 0>.
Resetting sets <PRCK1 : 0> to “00”, therefore, fFPH /4
clock is input.
The 8 bit Timer 0, 1 uses 4 types of clock: øT1, øT4,
øT16, and øT256 among the prescaler output.
The prescaler can be run or stopped by the timer control register TRUN <PRRUN>. Counting starts when
<PRRUN> is set to “1”, while the prescaler is cleared
to zero and stops operation when <PRRUN> is set to
“0”.
When the IDLE1 mode (operates only oscillator) is
used, set TRUN <PRRUN> to “0” to stop this prescaler
before “HALT” instruction is executed.
The input clock of timer 1 differs depending on the
operation mode. When set to 16-bit timer mode, the
overflow output of timer 0 is used as the input clock.
When set to any other mode than 16-bit timer mode,
the input clock is selected from the internal clocks φ
T1, φ T16, and φT256 as well as the comparator output (match detection signal) of timer 0 according to the
set value of TMOD register.
➁ Up-counter
Operation mode is also set by TMOD register. When
reset, it is initialized to TMOD <T01M1, 0> = 00
whereby the up-counter is placed in the 8-bit timer
mode.
The counting and stop and clear of up-counter can be
controlled for each interval timer by the timer operation
control register TRUN. When reset, all up-counters will
be cleared to stop the timers.
This is an 8-bit binary counter which counts up by the
input clock pulse specified by TMOD.
The input clock of timer 0 is selected from the external
clock from T10 pin and the three internal clocks φ T1, φ
T4, and φT16, according to the set value of TMOD register.
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Example : When TMOD <T10M1,0> = 01, the overflow output of timer 0 becomes the input
clock of timer 1 (16 bit timer mode).
When TMOD <T10M1,0> = 00 and
TMOD <T1CLK1, 0> = 01, φ T1 becomes
the input of timer 1 (8 bit timer mode).
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TMP93CM40/TMP93CM41
➂ Timer register
This is an 8-bit register for setting an interval time.
When the set value of timer registers TREG0, TREG1,
matches the value of up-counter, the comparator
match detect signal becomes active. If the set value is
00H, this signal becomes active when the up-counter
overflows.
Timer register TREG0 is of double buffer structure,
each of which makes a pair with register buffer.
The timer flip-flop control register TFFCR <DBEN> bit
controls whether the double buffer structure in the
TREG0 should be enabled or disabled. It is disabled
when <DBEN> = 0 and enabled when they are set to
1.
In the condition of double buffer enable state, the data
is transferred from the register buffer to the timer register when the 2n - 1 overflow occurs in PWM mode, or
at the PPG cycle in PPG mode. Therefore, during timer
mode, the double buffer cannot be used.
When reset, it will be initialized to <DBEN> = 0 to disable the double buffer. To use the double buffer, write
data in the timer register, set <DBEN> to 1, and write
the following data in the register buffer.
Figure 3.7 (3). Configuration of Timer Register 0
Note : Timer register and the register buffer are allocated to the same memory address. When <DBEN> = 0, the same value is written in the register buffer as
well as the timer register, while when <DBEN> = 1 only the register buffer is written.
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TMP93CM40/TMP93CM41
The memory address of each timer register is as follows.
TREG0: 000022H
TREG1: 000023H
All registers are write-only and cannot be read.
The status of the timer flip-flop is inverted by the match
detect signal (comparator output) of each interval timer
and the value can be output to the timer output pins
TO1 (also used as P71).
A timer F/F is provided for a pair of timer 0 and timer 1
and is called TFF1. TFF1 is output to TO1 pin.
➃ Comparator
A comparator compares the value in the up-counter
with the values to which the timer register is set. When
they match, the up-counter is cleared to zero and an
interrupt signal (INTT0, INTT1) is generated. If the timer
flip-flop inversion is enabled, the timer flip-flop is
inverted at the same time.
⑤ Timer flip-flop (timer F/F: TFF1)
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TMP93CM40/TMP93CM41
Figure 3.7 (4). Timer Operation Control Register/System Clock Control Register
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TMP93CM40/TMP93CM41
Figure 3.7 (5). Timer Mode Control Register (TMOD)
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87
TMP93CM40/TMP93CM41
Figure 3.7 (6). Timer Flip-Flop Control Register (TFFCR)
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TMP93CM40/TMP93CM41
➀ Generating interrupts in a fixed cycle
The operation of 8-bit timers will be described below:
(1) 8-bit timer mode
To generate timer 1 interrupt at constant intervals using
timer 1 (INTT1), first stop timer 1 then set the operation
mode, input clock, and a cycle to TMOD and TREG1
register, respectively. Then, enable interrupt INTT1 and
start the counting of timer 1.
Two interval timers 0, 1, can be used independently as
8-bit interval timer. All interval timers operate in the
same manner, and thus only the operation of timer 1
will be explained below.
Example: To generate timer 1 interrupt every 40
microseconds at fc = 16 MHz, set each
register in the following manner.
Use the following table for selecting the input clock.
Table 3.7 (1) 8-Bit Timer Interrupt Cycle and Input Clock
Input Clock
Resolution
Interrupt Cycle
(at fc = 20MHz)
Resolution
φT1 (8/fc)
0.5µs ~ 128µs
0.5µs
0.4µs ~ 102.4µs
0.4µs
φT4 (32/fc)
2µs ~ 512µs
2µs
1.6µs ~ 409.6µs
1.6µs
φT16 (128/fc)
8µs ~ 2.048ms
8µs
6.4µs ~ 1.638ms
6.4µs
128µs ~ 32.708ms
128µs
102.4µs ~ 2.621ms
128µs
φT256 (2048/fc)
Note:
Interrupt Cycle
(at fc = 16MHz)
The input clock of timer 0 and timer 1 are different from as follows:
Timer 0: TI0 input, φT1, φT4, φT16
Timer 1: Match Output of Timer 0, φT1, φT16, φT256
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TMP93CM40/TMP93CM41
➁ Generating a 50% duty square wave pulse
The timer flip-flop (TFF1) is inverted at constant intervals, and its status is output to timer output pin (TO1).
Example: To output a 3.0µs square wave pulse from
TO1 pin at fc = 16MHz, set each register in
the following procedures. Either timer 0 or
timer 1 may be used, but this example uses
timer 1.
Figure 3.7 (7). Square Wave (50% Duty) Output Timing Chart
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TMP93CM40/TMP93CM41
➂ Making timer 1 count up by match signal from timer
0 comparator
Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1.
Figure 3.7 (8). Timer 1 Count Up by Timer 0
➃ Output inversion with software
The value of timer flip-flop (TFF1) can be inverted, independent of timer operation.
Writing “00” into TFFCR <TFF1C1, 0> (memory
address: 000025h of bit 3 and bit 2) inverts the value of
TFF1.
➄ Initial setting of timer flip-flop (TFF1)
The value of TFF1 can be initialized to “0” or “1”, independent of timer operation.
For example, write “10” in TFFCR <TFF1C1, 0> to
clear TFF1 to “0”, while write “01” in TFFCR <TFF1C1,
0> to set TFF1 to “1”.
(2)
16-bit timer mode
A 16-bit interval timer is configured by using the pair of
timer 0 and timer 1.
To make a 16-bit interval timer by cascade connecting
timer 0 and timer 1, set timer 0/timer 1 mode register
TMOD <T10M1, 0> to “0, 1”.
When set in 16-bit timer mode, the overflow output of
timer 0 will become the input clock of timer 1, regardless of the set value of TMOD <T1CLK1, 0>. Table 3.7
(2) shows the relation between the cycle of timer (interrupt) and the selection of input clock.
Note: The value of timer register cannot be read.
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Table 3.7 (2)
Input Clock
Interrupt Cycle
(at fc = 16MHz)
Interrupt Cycle
(at fc = 20MHz)
Resolution
Resolution
φT1 (8/fc)
0.5µs ~ 32.786ms
0.5µs
0.4µs ~ 26.214ms
0.4µs
φT4 (32/fc)
2µs ~ 131.072ms
2µs
1.6µs ~ 104.857ms
1.6µs
φT16 (128/fc)
8µs ~ 524.288ms
8µs
6.4µs ~ 419.430ms
6.4µs
The lower 8 bits of the timer (interrupt) cycle are set by
the timer register TREG0, and the upper 8 bits are set
by TREG1. Note that TREG0 always must be set first.
(Writing data into TREG0 disables the comparator
temporarily, and the comparator is restarted by writing
data into TREG1.)
When counting with input clock of φ T16 (8µs @ 16MHz)
0.5 sec ÷ 8µs = 62500 = F424H
Therefore, set TREG1 = F4H and TREG0 = 24H, respectively.
The comparator match signal is output from timer 0
each time the up-counter UC0 matches TREG0,
where the up-counter UC0 is not to be cleared.
With the timer 1 comparator, the match detect signal
Setting example:
To generate an interrupt INTT1
every 0.5 seconds at fc = 16MHz,
set the following values for timer
registers TREG0 and TREG1.
is output at each comparator timing when up-counter
UC1 and TREG1 values match. When the match
detect signal is output simultaneously from both comparators of timer 0 and timer 1, the up-counters UC0
and UC1 are cleared to “0”, and the interrupt INTT1 is
generated. If inversion is enabled, the value of the
timer flip-flop TFF1 is inverted.
Example:
When TREG1 = 04H and TREG0 = 80H
Figure 3.7 (9). Output Timer by 16-Bit Timer Mode
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(3)
8-bit PPG (Programmable Pulse Generation) Output
mode
Square wave pulse can be generated at any frequency
and duty by timer 0 and timer 1. The output pulse may
be either low-active or high-active. In this mode, timer
1 cannot be used.
Timer 0 outputs pulse to TO1 pin (also used as P70).
In this mode, a programmable square wave is generated by inverting timer output each time the 8-bit up-
counter (UC0) matches the timer registers TREG0 and
TREG1.
However, it is required that the set value of TREG0 is
smaller than that of TREG1.
Though the up-counter (UC1) of timer 1 is not used in
this mode, UC1 should be set for counting by setting
TRUN <T1RUN> to 1.
Figure 3.7 (11) shows the block diagram for this mode.
Figure 3.7 (10). 8-Bit PPG Output Waveforms
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Figure 3.7 (11). Block Diagram of 8-Bit PPG Output Mode
When the double buffer of TREG0 is enabled in this
mode, the value of register buffer will be shifted in
TREG0 each time TREG1 matches UC0.
Use of the double buffer makes easy handling of low
duty waves (when duty is varied).
Figure 3.7 (12). Operation of Register Buffer
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Example: Generating 1/4 duty 50kHz pulse (at fc =
• Calculate the value to be set for timer register.
To obtain the frequency 50kHz, the pulse cycle t
should be: t = 1/50kHz = 20µs.
Given φ T1 = 0.5µs at 16MHz),
20µs ÷ 0.5µs = 40
Consequently, to set the timer register 1 (TREG1) to
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16MHz)
TREG1 = 40 = 28H and then duty to 1/4, t x 1/4 =
20µs x 1/4 = 5µs
5µs ÷ 0.5µs = 10
Therefore, set timer register 0 (TREG0) to TREG0 = 10
= 0AH.
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(4)
8-bit PWM Output mode
This mode is valid only for timer 0. In this mode, maximum 8-bit resolution of PWM pulse can be output.
PWM pulse is output to TO1 pin (also used as P71)
when using timer 0. Timer 1 can also be used as 8-bit
timer.
Timer output is inverted when up-counter (UC0)
matches the set value of timer register TREG0 or when
2n - 1 (n = 6, 7, or 8; specified by T01MOD <PWM01,
0>) counter overflow occurs. Up-counter UC0 is
cleared when 2n - 1 counter overflow occurs. For
example, when n = 6, 6-bit PWM will be output, while
when n = 7, 7-bit PWM will be output.
To use this PWM mode, the following conditions must
be satisfied.
(Set value of timer register) <(Set value of 2n - 1
counter overflow)
(Set value of timer register ≠ 0)
Figure 3.7 (13). 8-Bit PWM Waveforms
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Figure 3.7 (14) shows the block diagram of this mode.
Figure 3.7 (14). Block Diagram of 8-Bit PWM Mode
In this mode, the value of register buffer will be shifted in
TREG0 if 2n - 1 overflow is detected when the double buffer of
TREG0 is enabled.
Use of the double buffer makes easy the handling of
small duty waves.
Figure 3.7 (15). Operation of Register Buffer
Example: To output the following PWM waves to TO1
pin at fc = 16MHz.
To realize 63.5µs of PWM cycle by φT1 = 0.5µs (@ fc =
16MHz),
63.5µs ÷ 0.5µs = 127 = 27 - 1
Consequently, n should be set to 7.
As the period of low level is 36µs, for φT1 = 0.5µs, set the
following value for TREG0:
36µs ÷ 0.5µs = 72 = 48H
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Table 3.7 (3) PWM Cycle
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(5)
Table 3.7 (4) shows the list of 8-bit timer modes.
Table 3.7 (4) Timer Mode Setting Registers
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3.8 8-Bit PWM Timer
The TMP93CM40/TMP93CM41 has two built-in 8-bit PWM
timers (timers 2 and 3).
They have two operating modes.
• 8-bit PWM (pulse width modulation: variable duty at fixed
interval) output mode
• 8-bit interval timer mode
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Figure 3.8 (1), (2) are block diagrams of the 8-bit PWM
timer (timers 2 and 3).
PWM timers consist of an 8-bit up-counter, 8-bit comparator, and 8-bit timer register. Two timer flip-flops (TFF2 for
timer 2 and TFF3 for timer 3) are provided.
Input clocks φP1, φP4, and φP16 for the PWM timers can
be obtained using the built-in prescaler.
PWM timer operating mode and timer flip-flops are controlled by four control registers (P0MOD, P1MOD, PFFCR, and
TRUN).
PWM timer 0 and 1 can be used independently.
All PWM timers operate in the same manner, thus, only
the operation of PWM timer 0 will be explained below.
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Figure 3.8 (1). Block Diagram of 8-Bit PWM Timer 0 (Timer 2)
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Figure 3.8 (2). Block Diagram of 8-Bit PWM Timer 1 (Timer 3)
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➀ Prescaler
There are 5 bit prescaler and prescaler clock selection
register to generate input clock for 8 bit PWM Timer 0, 1.
Figure 3.8 (3) shows the block diagram. Table 3.8 (1)
shows prescaler clock resolution to 8 bit PWM Timer
0, 1.
Figure 3.8 (3). Prescaler Block Diagram]
Table 3.8 (1) Prescaler Clock Resolution to 8 Bit PWM Timer 0, 1
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The 1/2 times clock selected among fFPH clock, fc/16
clock, and fs clock is input to this prescaler. This is
selected by prescaler clock selection register SYSCR0
<PRCK1 : 0>.
Resetting sets <PRCK1 : 0> to “00”, therefore, fFPH /2
clock is input. The register TRUN <PRRUN> which
controls this prescaler is also used at 9 bit prescaler.
So, this prescaler cannot be operated independently.
The 8 bit Timer 0, 1 uses 3 types of clock: øP1, øP4,
and øP16 among the prescaler outputs.
The prescaler can be run or stopped by TRUN
<PRRUN> described of the 8 bit Timer.
Counting starts when <PRRUN> is set to “1”, while
the prescaler is cleared to zero and stops operation
when <PRRUN> is set to “0”.
When the IDLE1 mode (operates only oscillator) is
used, set TRUN <PRRUN> to “0” to stop this prescaler before “HALT” instruction is executed.
➁ Up-counter
An 8-bit binary counter which counts up using the
input clock specified by PWM mode register P0MOD
<T2CLK1:0>.
The input clock for the PWM0 is selected from the
internal clocks φP1, φP4, and φP16 (PWM dedicated
prescaler output) depending on the <T2CLK1:0>.
Operating mode is also set by P0MOD <PWM0M>. At
reset, they are initialized to “0”, thus, the up-counter is
in PWM mode. In PWM mode, the up-counter is
cleared when a 2n - 1 overflow occurs; in timer mode,
the up-counter is cleared at compare and match.
Count/stop and clear of the up-counter can be controlled for each PWM timer using the timer operation
control register TRUN. Resetting clears all up-counters
and stops timers.
➂ Timer registers
The 8-bit register is used for setting an interval time.
When the value set in the timer register (TREG 2)
matches the value in the up-counter, the match detect
signal of the comparator becomes active.
Timer register TREG2 is paired with register buffer to
make a double buffer structure.
TREG2 is a double buffer enable/disable controlled by
P0MOD <DB2EN> : disabled when <DB2EN> = 0,
enabled when <DB2EN> = 1.
Data is transferred from register buffer to timer when a
2n - 1 overflow occurs in the PWM mode, or when
compare and match occurs in 8-bit timer mode. That
is, with a PWM timer, the timer mode can be operated
in double buffer enable state, unlike timer mode for
timers 0 and 1.
At reset, <DB2EN> is initialized to 0 to disable double
buffer. To use double buffer, write the data in the timer
register at first, then set <DB2EN> to 1, and write the
following data in the register buffer.
Figure 3.8 (4). Structure of Timer Registers 2
Note:
104
The timer register and register buffer are allocated to the same memory address. When <DB2EN> = 0, the same value is written to both register buffer
and timer register. When <DB2EN> = 1, the value is written to the register buffer only.
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Memory addresses of the timer registers are as follows:
TREG2 : 000026H
TREG3 : 000027H
Both timer registers are write only; however, register
buffer values can be read when reading the above
addresses.
➃ Comparator
Compares the value in the up-counter with the value in
the timer register (TREG2). When they match, the
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comparator outputs the match detect signal. A timer
interrupt (INTT2) is generated at compare and match if
the interrupt select bit <PWM0INT> of the mode register (P0MOD) is set to 1. In timer mode, the comparator
clears the up-counter to 0 at compare and match. It
also inverts the value of the timer flip-flop if timer flipflop invert is enabled.
➄ Timer flip-flop
The value of the timer flip-flop is inverted by the match
detect signal (comparator output) of each interval timer
or 2n - 1 overflow. The value can be output to the timer
output pin TO2 (also used as P72).
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Figure 3.8 (5). 8-Bit PWM0 Mode Control Register
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Figure 3.8 (6). 8-Bit PWM1 Mode Control Register
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Figure 3.8 (7). 8-Bit PWM F/F Control Register
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Figure 3.8 (8). Timer Operation Control Register/System Clock Control Register
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The following explains PWM timer operations.
(1)
PWM timer mode
PWM output changes under the following two conditions.
Condition 1:
• TFF2 is cleared to 0 when the value in the upcounter (UC2) and the value set in the TREG2
match.
• TFF2 is set to 1 when a 2n - 1 counter overflow (n
= 6, 7, or 8) occurs.
Condition 2:
• TFF2 is set to 1 when the value in the up-counter
(UC2) and the value set in TREG2 match.
• TFF2 is cleared to 0 when a 2n - 1 counter overflow (n = 6, 7, or 8) occurs.
The up-counter (UC2) is cleared by a 2n - 1 counter
overflow.
The PWM timer can output 0% to 100% duty pulses
because a 2n - 1 counter overflow has a higher priority.
That is, to obtain 0% output (always low), the mode
used to set TFF2 to 0 due to overflow (PFFCR
<FF2TRG1, 0> = 1, 0) must be set and 2n - 1 (value for
overflow) must be set in TREG2. To obtain 100% output (always high), the mode must be changed: PFFCR
<FF2TRG1, 0> = 1,1 then the same operation is
required.
Figure 3.8 (9). Output Waves in PWM Timer Mode
Note:
110
The above waves are obtained in a mode where the F/F is set by a match with the timer register (TREG) and reset by an overflow.
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Figure 3.8 (10) is a block diagram of this mode.
Figure 3.8 (10). Block Diagram of PWM Timer Mode (PWM0)
In this mode, enabling double buffer is very useful. The
register buffer value shifts into TREG2 when a 2n -1 overflow
is detected, when double buffer is enabled.
Using double buffer makes handling small duty waves
easy.
Figure 3.8 (11). Register Buffer Operation
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Example: To output the following PWM waves to TO2
pin using PWM0 at fc = 16MHz.
To implement 31.75µs PWM cycle by φ P1 = 0.25µs (@ fc
= 16MHz)
31.75µs ÷ 0.25µs = 127 = 27 -1.
Consequently, set n to 7.
Since the low level cycle = 15µs; for φ P1 = 0.25µs
15µs ÷ 0.25 = 60 = 3CH
set the 3CH in TREG2.
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Table 3.8 (2) PWM Cycle and 2n -1 Counter Setting
(2)
8-bit timer mode
using PWM0 timer, first stop PWM0, then set the operating mode, input clock, and interval in the P0MOD
and TREG2 registers. Next, enable INTT2 and start
counting PWM0.
Both PWM timers can be used independently as 8-bit
interval timers. Since both timers operate in exactly the
same way, PWM0 (timer 2) is used for the purposes of
explanation.
Example: To generate a timer 2 interrupt every
40µs at fc = 16MHz, set registers as follows:
➀ Generating interrupts at a fixed interval
To generate timer 2 interrupt (INTT2) at a fixed interval
Select an input clock using Table 3.8 (1).
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Note:
To generate interrupts in 8-bit timer mode, bit 5 (interrupt control bit
<PWM0INT> must be set to 1.
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➁ Generating a 50% square wave
Example: To output a 3.0µs square wave at fc = 16MHz from
TO2 pin, set register as follows:
To generate a 50% square wave, invert the timer flipflop at a fixed interval and output the timer flip-flop
value to the timer output pin (TO2).
Figure 3.8 (12). Square Wave (50% Duty) Output Timing Chart
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This mode is as shown in Figure 3.8 (13) below.
Figure 3.8 (13). Block Diagram of 8-Bit Timer Mode
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3.9 16-Bit Timer
TMP93CM40/TMP93CM41 contains two (timer 4 and timer 5)
multifunctional 16-bit timer/event counter with the following
operation modes.
•
•
•
•
•
•
Timer/event counter consists of 16-bit up-counter, two
16-bit timer registers, two 16-bit capture registers (one of them
applies double-buffer), two comparators, capture input controller, and timer flip-flop and the control circuit.
Timer/event counter is controlled by four control registers: T4MOD/T5MOD, T4FFCR/T5FFCR, TRUN and T45CR.
Figure 3.9 (1), (2) show the block diagram of 16-bit timer/
event counter (timer 4 and timer 5).
Timer 4 and 5 can be used independently.
All timers operate in the same manner except the following points, thus, only Timer 4 operation will be explained
below.
16-bit interval timer mode
16-bit event counter mode
16-bit programmable pulse generation (PPG) mode
Frequency measurement mode
Pulse width measurement mode
Time differential measurement mode
Different Points Between Timer 4 and 5
Timer Out Pin
(for upper timer register)
Different Phased Pulse Output Mode
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Timer 4
Timer 5
TO5 pin (TFF5)
–
Exist
Does not exist
(not TO7 pin)
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Figure 3.9 (1). Block Diagram of 16-Bit Timer (Timer 4)
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Figure 3.9 (2). Block Diagram of 16-Bit Timer (Timer 5)
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Figure 3.9 (3). 16-Bit Timer Mode Controller Register (T4MOD) (1/2)
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Figure 3.9 (4). 16-Bit Controller Register (T4MOD) (2/2)
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Figure 3.9 (5). 16-Bit Timer 4 F/F Control (T4FFCR)
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Figure 3.9 (6). 16-Bit Timer Mode Control Register (T5MOD) (1/2)
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Figure 3.9 (7). 16-Bit Timer Control Register (T5MOD) (2/2)
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Figure 3.9 (8). 16-Bit Timer 5 F/F Control (T5FFCR)
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Figure 3.9 (9). 16-Bit Timer (Timer 4, 5) Control Register (T45CR)
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Figure 3.9 (10). Timer Operation Control Register/System Clock Control Register
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➀ Prescaler
There are 9 bit prescaler and prescaler clock selection
register to generate input clock for 8 bit Timer 0, 1, 16
bit Timer 4, 5 and Serial Inteface 0, 1.
Figure 3.9 (11) shows the block diagram. Table 3.7 (1)
shows prescaler clock resolution to 8, 16 bit Timer.
Figure 3.9 (11). Prescaler Block Diagram
Table 3.7 (1) Prescaler Clock Resolution to 8, 16 bit Timer
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The 1/4 times clock selected among 2 times system
clock, fc/16 clock, and fs clock is input to this prescaler. This is selected by prescaler clock selection register SYSCR0 <PRCK1 : 0>.
Resetting sets <PRCK1 : 0> to “00”, therefore, 2 times
system clock is input.
The 16 bit Timer 4, 5 uses 3 types of clock: øT1, øT4,
and øT16 among the prescaler outputs.
The prescaler can be run or stopped by the timer operation control register TRUN <PRRUN>. Counting starts
when <PRRUN> is set to “1”, while the prescaler is
cleared to zero and stops operation when <PRRUN> is
set to “0”.
When the IDLE1 mode (operates only oscillator) is
used, set TRUN <PRRUN> to “0” to stop this prescaler
before “HALT” instruction is executed.
➁ Up-counter
UC4 is a 16-bit binary counter which counts up
according to the input clock specified by T4MOD
<T4CLK1, 0> or T5MOD <T5CLK1, 0> register.
As the input clock, one of the internal clocks φ T1, φ
T4, and φ T16 from 9-bit prescaler (also used for 8-bit
TREG4 timer register is of double buffer structure,
which is paired with register buffer. The timer control
register T45CR <DB4EN> controls whether the double
buffer structure should be enabled or disabled. : disabled when <DB4EN> = 0, while enabled when
<DB4EN> = 1.
When the double buffer is enabled, the timing to transfer data from the register buffer to the timer register is
at the match between the up-counter (UC4) and timer
register TREG5.
When reset, it will be initialized to <DB4EN> = 0,
whereby the double buffer is disabled. To use the double buffer, write data in the timer register, set <DB4EN>
= 1, and then write the following data in the register
buffer.
TREG4, TREG6 and register buffer are allocated to the
128
timer), and external clock from TI4 pin (also used as
P80/INT4 pin) can be selected. When reset, it will be
initialized to <T4CLK1, 0> = 00 to select TI4 input
mode. Counting or stop and clear of the counter is
controlled by timer operation control register TRUN
<T4RUN>.
When clearing is enabled, up-counter UC4/UC5 will be
cleared to zero each time it coincides matches the
timer register TREG5, TREG7. The “clear enable/disable” is set by T4MOD <CLE>.
If clearing is disabled, the counter operates as a freerunning counter.
➂ Timer Registers
These two 16-bit registers are used to set the interval
time. When the value of up-counter UC4 matches the
set value of this timer register, the comparator match
detect signal will be active.
Setting data for timer register (TREG4 and TREG5) is
executed using 2 byte date transfer instruction or using
1 byte date transfer instruction twice for lower 8 bits
and upper 1 bits in order.
same memory addresses 000030H/000031H. When
<DB4EN> = 0, same value will be written in both the
timer register and register buffer. When <DB4EN> = 1,
the value is written into only the register buffer.
➃ Capture Register
These 16-bit registers are used to hold the values of
the up-counter.
Data in the capture registers should be read by a 2byte data load instruction or two 1-byte data load
instruction, from the lower 8 bits followed by the upper
8 bits.
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➄ Capture Input Control
This circuit controls the timing to latch the value of upcounter UC4 into (CAP1, CAP2). The latch timing of
capture register is controlled by register T4MOD
<CAP12M1, 0>.
• When T4MOD <CAP12M1, 0> = 00
Capture function is disabled. Disable is the default on
reset.
• When T4MOD <CAP12M1, 0> = 01
Data is loaded to CAP1 at the rise edge of TI4 pin (also
used as P80/INT4) input, while data is loaded to CAP2
at the rise edge of TI5 pin (also used as P81/INT5)
input. (Time difference measurement)
• When T4MOD <CAP12M1, 0> = 10
Data is loaded to CAP1 at the rise edge of TI4 pin
input, while to CAP2 at the fall edge. Only in this setting, interrupt INT4 occurs at fall edge. (Pulse width
measurement)
• When T4MOD <CAP12M1, 0> = 11
Data is loaded to CAP1 at the rise edge of timer flipflop TFF1, while to CAP2 at the fall edge.
Besides, the value of up-counter can be loaded to
capture registers by software. Whenever “0” is written
in T4MOD <CAPIN>, the current value of up-counter
will be loaded to capture register CAP1. It is necessary
to keep the prescaler in RUN mode (TRUN <PRRUN>
to be “1”).
➅ Comparator
These are 16-bit comparators which compare the upcounter UC4 value with the set value of (TREG4,
TREG5) to detect the match. When a match is
detected, the comparators generate an interrupt (INTT4,
INTT5), respectively. The up-counter UC4 is cleared only
when UC4 matches TREG5. (The clearing of upcounter UC4 can be disabled by setting T4MOD
<CLE> = 0.)
➆ Timer Flip-Flop (TFF4)
This flip-flop is inverted by the match detect signal
from the comparators and the latch signals to the capture registers. Disable/enable of inversion can be set
for each element by T4FFCR <CAP2T4, CAP1T4,
EQ5T4, EQ4T4>. TFF4 will be inverted when “00” is
written in T4FFCR <TFF4C1, 0>. Also it is set to “1”
when “10” is written, and cleared to “0” when “10” is
written. The value of TFF4 can be output to the timer
output pin TO4 (also used as P82).
➇ Timer Flip-Flop (TFF5)
This flip-flop is inverted by the match detect signal
from the comparator and the latch signal to the capture register CAP2. TFF5 will be inverted when “00” is
written in T4FFCR <TFF5C1, 0>. Also it is set to “1”
when “10” is written, and cleared to “0” when “10” is
written. The value of TFF5 can be output to the timer
output pin TO5 (also used as P82).
Note: This flip-flop (TFF5) is contained only in the 16-bit timer 4.
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(1)
16-bit Timer Mode
In this example, the interval time is set in the timer register TREG5 to generate the interrupt INTTR5.
Generating interrupts at fixed intervals:
(2)
16-bit Event Counter Mode
In 16-bit timer mode as described in above, the timer
can be used as an event counter by selecting the
external clock (TI4 pin input) as the input clock. To read
the value of the counter, first perform “software cap-
130
ture” once and read the captured value.
The counter counts at the rise edge of TI4 pin input.
TI4 pin can also be used as P80/INT4.
Since both timers operate in exactly the same way,
timer 4 is used for the purposes of explanation.
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(3)
16-bit Programmable Pulse Generation (PPG) Output
Mode
Since both timers operate in exactly the same way,
timer 4 is used for the purposes of explanation.
The PPG mode is obtained by inversion of the timer
flip-flop TFF4 that is to be enabled by the match of the
up-counter UC4 with the timer register TREG4 or 5
and to be output to TO4 (also used as P82). In this
mode, the following conditions must be satisfied.
(Set value of TREG4) < (Set value of TREG5)
Figure 3.9 (11). Programmable Pulse Generation (PPG) Output Waveforms
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When the double buffer of TREG4 is enabled in this
mode, the value of register buffer 4 will be shifted in TREG4
at match with TREG5. This feature makes easy the handling of
low duty waves.
Figure 3.9 (12). Operation of Register Buffer
Shows the block diagram of this mode.
Figure 3.9 (13). Block Diagram of 16-Bit PPG Mode
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(4)
Application Examples of Capture Function
The loading of up-counter (UC4) values into the capture registers CAP1 and CAP2, the timer flip-flop TFF4
inversion due to the match detection by comparators
CP4 and CP5, and the output of TFF4 status to TO4
pin can be enabled or disabled. Combined with inter-
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rupt function, they can be applied in many ways, for
example:
➀
➁
➂
➃
One-shot pulse output from external trigger pulse
Frequency measurement
Pulse width measurement
Time difference measurement
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➀ One-Shot Pulse Output from External Trigger Pulse
Set the up-counter UC4 in free-running mode with the
internal input clock, input the external trigger pulse
from TI4 pin, and load the value of up-counter into
capture register CAP1 at the rise edge of the TI4 pin.
Then set to T4MOD <CAP12M1, 0> = 01.
When the interrupt INT4 is generated at the rise edge
of TI4 input, set the CAP1 value (c) plus a delay time (d)
to TREG4 (= c + d), and set the above set value (c + d)
plus a one-shot pulse width (p) to TREG5 (= c + d + p).
When the interrupt INT4 occurs the T4FFCR <EQ5T4,
EQ4T4> register should be set that the TFF4 inversion
is enabled only when the up-counter value matches
TREG4 or TREG5. When interrupt INTTR5 occurs, this
inversion will be disabled.
Figure 3.9 (14). One-Shot Pulse Output (with Delay)
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Setting Example:
To output 2ms one-shot pulse with
When delay time is unnecessary, invert timer flip-flop
TFF4 when the up-counter value is loaded into capture
register 1 (CAP1), and set the CAP1 value (c) plus the
one-shot pulse width (p) to TREG5 when the interrupt
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3ms delay to the external trigger pulse to TI4 pin.
INT4 occurs. The TFF4 inversion should be enabled
when the up-counter (UC4) value matches TREG5,
and disabled when generating the interrupt INTTR5.
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Figure 3.9 (15). One-Shot Pulse Output (without Delay)
➁ Frequency Measurement
The frequency of the external clock can be measured
in this mode. The clock is input through the TI4 pin,
and its frequency is measured by the 8-bit timers
(Timer 0 and Timer 1) and the 16-bit timer/event
counter (Timer 4).
The TI4 pin input should be selected for the input clock
of Timer 4. The value of the up-counter is loaded into
the capture register CAP1 at the rise edge of the timer
flip-flop TFF1 of 8-bit timers (Timer 0 and Timer 1), and
into CAP2 at its fall edge.
The frequency is calculated by the difference between
the loaded values in CAP1 and CAP2 when the interrupt (INTT0 or INTT1) is generated by either 8-bit timer.
Figure 3.9 (16). Frequency Measurement
For example, if the value for the level “1” width of TFF1
of the 8-bit timer is set to 0.5 sec. and the difference
136
between CAP1 and CAP2 is 100, the frequency will be
100/0.5 [sec.] = 200 [Hz].
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➂ Pulse Width Measurement
This mode allows measuring the “H” level width of an
external pulse. While keeping the 16-bit timer/event
counter counting (free-running) with the internal clock
input, the external pulse is input through the TI4 pin.
Then the capture function is used to load the UC4 values into CAP1 and CAP2 at the rising edge and falling
edge of the external trigger pulse respectively. The
interrupt INT4 occurs at the falling edge of TI4.
The pulse width is obtained from the difference
between the values of CAP1 and CAP2 and the internal clock cycle.
For example, if the internal clock is 0.8 microseconds
and the difference between CAP1 and CAP2 is 100,
the pulse width will be 100 x 0.8µs = 80µs.
Figure 3.9 (17). Pulse Width Measurement
Note:
Only in this pulse width measuring mode (T4MOD <CAP12M1, 0> = 10), external interrupt INT4 occurs at the falling edge of TI4 pin input. In other
modes, it occurs at the rising edge.
The width of “L” level can be measured from the difference between the first C2 and the second C1 at the
second INT4 interrupt.
➃ Time Difference Measurement
This mode is used to measure the difference in time
between the rising edges of external pulses input
through TI4 and TI5.
Keep the 16-bit timer/event counter (Timer 4) counting
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(free-running) with the internal clock, and load the UC4
value into CAP1 at the rising edge of the input pulse to
TI4. Then the interrupt INT4 is generated.
Similarly, the UC4 value is loaded into CAP2 at the rising edge of the input pulse to TI5, generating the interrupt INT5.
The time difference between these pulses can be
obtained from the difference between the time counts
at which loading the up-counter value into CAP1 and
CAP2 has been done.
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Figure 3.9 (18). Time Difference Measurement
(5)
Different Phased Pulses Output Mode (This mode can
only be used in Timer 4)
In this mode, signals with any different phase can be
output by free-running up-counter UC4.
When the value in up-counter UC4 and the value in
TREG4 (TREG5) match, the value in TFF4 (TFF5) is
inverted and output to TO4 (TO5).
This mode can only be used by 16-bit timer 4.
Figure 3.9 (19). Phase Output
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Cycles (counter overflow time) of the above output waves
are listed below.
Table 3.9 (2) Timer Output Cycle on the Different Phased Pulse Output Mode
xxx : don’t care
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3.10 Stepping Motor Control/Pattern Generation Port
TMP93CM40/M41 has two channels (PG0 and PG1) of 4-bit
hardware stepping motor control/pattern generation (herein
after called PG) which actuate in synchronization with the (8bit/16-bit) timers. The PG (PG0 and PG1) are shared in 8-bit I/
O ports P6.
Channel 0 (PG0) is synchronous with 8-bit timer 0 or
timer 1, 16-bit timer 5, to update the output.
The PG ports are controlled by control registers
(PG01CR) and can select either stepping motor control mode
or pattern generation mode. Each bit of the P6 can be used as
the PG port.
PG0 and PG1 can be used independently.
All PG operate in the same manner except the following
points, and thus only the operation of PG0 will be explained
below.
Different Points Between PG0 and PG1
Trigger Signal
PG0
PG1
from Timer 4
from Timer 5
Figure 3.10 (1). PG Block Diagram
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Figure 3.10 (2a). Pattern Generation Control Register (PG01CR)
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Figure 3.10 (2b). Pattern Generation Control Register (PG01CR)
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Figure 3.10 (3). Pattern Generation 0 Register (PG0REG)
Figure 3.10 (4). Pattern Generation 1 Register (PG1REG)
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Figure 3.10 (5). 16-bit Timer Trigger Control Register (T45CR)
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Figure 3.10 (6). Connection of Timer and Pattern Generator
(1)
Pattern Generation Mode
PG functions as a pattern generation according to the
setting of PG01CR <PAT1>. In this mode, writing from
CPU is executed only on the shifter alternate register.
Writing a new data should be done during the interrupt
operation of the timer for shift trigger, and a pattern
can be output synchronous with the timer.
In this mode, set PG01CR <PG0M> to 1, and
PG01CR <CCW0> to 0.
The output of this pattern generator is output to port 6;
since port and functions can be switched on a bit
basis using port function control register P6FC, any
port pin can be assigned to pattern generator output.
Figure 3.10 (7) shows the block diagram of this mode.
Example of pattern generation mode
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Figure 3.10 (7). Pattern Generation Mode Block Diagram (PG0)
In this pattern generation mode, only writing the output
latch is disabled by hardware, but other functions do the same
operation as 1-2 excitation in stepping motor control port
146
mode. Accordingly, the data shifted by trigger signal from a
timer must be written before the next trigger signal is output.
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(2)
Stepping Motor Control Mode
➀ 4-phase 1-Step/2-Step Excitation
Figure 3.10 (8) and Figure 3.10 (9) show the output
waveforms of 4-phase 1 excitation and 4-phase 2
excitation, respectively when channel 0 (PG0) is
selected.
Figure 3.10 (8). Output Waveforms of 4-Phase 1-Step Excitation (Normal Rotation and Reverse Rotation)
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Figure 3.10 (9). Output Waveforms of 4-Phase 2-Step Excitation (Normal Rotation)
The operation when channel 0 is selected is explained
below.
The output latch of PG0 (also used as P6) is shifted at
the rising edge of the trigger signal from the timer to be
output to the port.
The direction of shift is specified by PG01CR
<CCW0>: Normal rotation (PG00 → PG01 → PG02 →
PG03) when <CCW0> is set to “0”; reverse rotation
(PG00 ← PG01 ← PG02 ← PG03) when “1”. Four-
phase 1-step excitation will be selected when only one
bit is set to “1” during the initialization of PG, while 4phase 2-step excitation will be selected when two consecutive bits are set to “1”.
The value in the shift alternate registers are ignored
when the 4-phase 1-step/2-step excitation mode is
selected.
Figure 3.10 (10) shows the block diagram.
Figure 3.10 (10). Block Diagram of 4-Phase 1-Step Excitation/2-Step Excitation (Normal Rotation)
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➁ 4-Phase 1-2 Step Excitation
phase 1 -2 step excitation when channel 0 is selected.
Figure 3.10 (11) shows the output waveforms of 4-
Figure 3.10 (11). Output Waveforms of 4-Phase 1-2 Step Excitation (Normal Rotation and Reverse Rotation)
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TMP93CM40/TMP93CM41
The initialization for 4-phase 1-2 step excitation is as
follows:
By rearranging the initial value “b7 b6 b5 b4 b3 b2 b1
b0” to “b7 b3 b6 b2 b5 b1 b4 b0”, the consecutive 3
bits are set to “1” and other bits are set to “0” (positive
logic).
For example, if b7, b3, and b6 are set to “1", the initial
value becomes “11001000”, obtaining the output
waveforms as shown in Figure 3.10 (11).
To get an output waveform of negative logic, set values
1s and 0’s of the initial value should be inverted. For
example, to change the output waveform shown in
Figure 3.10 (11) into negative logic, change the initial
value to “00110111”.
The operation will be explained below for channel 0.
The output latch of PG0 (shared by P6) and the shifter
alternate register (SA0) for Pattern Generation are
shifted at the rising edge of trigger signal from the timer
to be output to the port. The direction of shift is set by
PG01CR <CCW0>.
Figure 3.10 (12) shows the block diagram.
Figure 3.10 (12). Block Diagram of 4-Phase 1-2 Step Excitation (Normal Rotation)
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Setting example: To drive channel 0 (PG0) by 4-phase 1-2
step excitation (normal rotation) when
(3)
Trigger Signal From Timer
The trigger signal from the timer which is used by PG is
timer 0 is selected, set each register as
follows:
not equal to the trigger signal of timer flip-flop (TFF1,
TFF4, TFF5, and TFF6) and differs as shown in Table
3.10 (1) depending on the operation mode of the timer.
Table 3.10 (1) Select of Trigger Signal
TFF1 Inversion
Note:
PG Shift
8-bit timer mode
Selected by TFFCR <TFF1IS> when the up-counter value matches
TREG0 or TREG1 value.
16-bit timer mode
When the up-counter value matches with both TREG0 and TREG1
values. (The value of up-counter = TREG1*28 + TREG0)
PPG output mode
When the up-counter value matches with both TREG0 and TREG1.
When the up-counter value matches TREG1 value (PPG cycle).
PWM output mode
When the up-counter value matches TREG0 value and PWM cycle.
Trigger signal for PG is not generated.
To shift PG, TFFCR <TFF1IE> must be set to “1” to enable TFF1 inversion.
Channel 1 of PG can be synchronized with the 16-bit
timer Timer 4/Timer 5. In this case, the PG shift trigger
signal from the 16-bit timer is output only when the upcounter UC4/UC5 value matches TREG5/TREG7.
When using a trigger signal from Timer 4, set either
T4FFCR <EQ5T4> or T4MOD <EQ5T5> to “1” and a
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trigger is generated when the value in UC4 and the
value in TREG5 match. When using a trigger signal
from Timer 5, set T5FFCR <EQ7T6> to 1. Generates a
trigger when the value in UC5 and the value in TREG7
match.
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(4)
Application of PG and Timer Output
As explained in “Trigger signal from timer”, the timing to
shift PG and invert TFF differs depending on the mode
of timer. An application to operate PG while operating
an 8-bit timer in PPG mode will be explained below.
To drive a stepping motor, in addition to the value of
each phase (PG output), synchronizing signal is often
required at the timing when excitation is changed over.
In this application, port 6 is used as a stepping motor
control port to output a synchronizing signal to the TO1
pin (shared by P71).
Figure 3.10 (13). Output Waveforms of 4-Phase 1-Step Excitation
Setting example:
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TMP93CM40/TMP93CM41
3.11 Serial Channel
TMP93CM40/TMP93CM41 contains two serial I/O channels
for full duplex asynchronous transmission (UART) as well as for
I/O extension.
The serial channel has the following operation modes:
●
I/O interface mode
(channel 1 only)
Mode 0: To transmit and receive I/O data as well as
the synchronizing signal SCLK for extending I/O.
●
Asynchronous transmission
(UART) mode (channel 0 and 1)
Mode 1: 7-bit data
Mode 2: 8-bit data
Mode 3: 9-bit data
In mode 1 and mode 2, a parity bit can be added. Mode
3 has wake-up function for making the master controller start
slave controllers in serial link (multi-controller system).
Figure 3.11 (1) shows the data format (for one frame) in
each mode.
Serial Channel 0 and 1 can be used independently.
All channels operate in the same manner except the following points, thus, only the channel 0 will be explained below.
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Different Points Between Channel 0 and Channel 1
Pin Name
Handshake Function
Channel 0
Channel 1
TXD0 (P90), RXD0
(P91), CTS0/SCLK0
(P92)
TXD01 (P93), RXD1
(P94), SCLK1 (P95)
Exist
Does Not Exist
(Not for CTS pin)
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Figure 3.11 (1). Data Formats
The serial channel has a buffer register for transmitting
and receiving operations, in order to temporarily store transmitted or received data, so that transmitting and receiving operations can be done independently (full duplex).
However, in I/O interface mode, SCLK (serial clock) pin is
used for both transmission and receiving, the channel
becomes half-duplex.
The receiving data register is of a double buffer structure
to prevent the occurrence of overrun error and provides one
frame of margin before CPU reads the received data. The
receiving data register stores the already received data while
the buffer register receives the next frame data.
By using CTS and RTS (there is no RTS pin, so any one
port must be controlled by software), it is possible to halt data
send until CPU finishes reading receive data every time a frame
is received (Handshake function).
In the UART mode, a check function is added not to start
154
the receiving operation by error start bits due to noise. The
channel starts receiving data only when the start bit is detected
to be normal at least twice in three samplings.
When the transmission buffer becomes empty and
requests the CPU to send the next transmission data, or when
data is stored in the receiving data register and the CPU is
requested to read the data, INTTX or INTRX interrupt occurs.
Besides, if an overrun error, parity error, or framing error occurs
during receiving operation, flag SC0CR/SC1CR <OERR,
PERR, FERR> will be set.
The serial channel 0/1 includes a special baud rate generator, which can set any baud rate by dividing the frequency
of four clocks (φT0, φT2, φT8, and φT32) from the internal prescaler (shared by 8-bit/16-bit timer) by the value 2 to 16.
In I/O interface mode, it is possible to input synchronous
signals as well as to transmit or receive data by external clock.
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3.11.1 Control Registers
The serial channel is controlled by three control registers
SC0CR, SC0MOD, and BR0CR. Transmitted and received
data is stored in register SC0BUF.
Figure 3.11 (2). Serial Mode Control Register (Channel 0, SC0MOD)
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Figure 3.11 (3). Serial Control Register (Channel, SC0CR)
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Figure 3.11 (4). Serial Channel Control (Channel 0, BR0CR)
Figure 3.11 (5). Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF)
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Figure 3.11 (6). Serial Mode Control Register (Channel 1, SC1MOD)
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Figure 3.11 (7). Serial Control Register (Channel 1, SC1CR)
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Figure 3.11 (8). Baud Rate Generator Control Register (Channel 0, BR0CR)
Figure 3.11 (9). Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF)
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Figure 3.11 (10). Port 9 Function Register (P9FC)
Port 3.11 (11). Port 9 Open Drain Enable Register (ODE)
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3.11.2 Configuration
Figure 3.11 (12) shows the block diagram of the serial channel 0.
Figure 3.11 (12). Block Diagram of the Serial Channel 0
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Figure 3.11 (13) shows the block diagram of the serial channel 1.
Figure 3.11 (13). Block Diagram of the Serial Channel 1
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➀ Prescaler
There are 9 bit prescaler and prescaler clock selection
to generate input clock for 8 bit Timer 0, 1, 16 bit
Timer 4, 5 and Serial Interface 0, 1.
Figure 3.11 (14) shows the block diagram. Table 3.11
(1) shows prescaler clock resolution to the baud generator.
Figure 3.11 (14). Prescaler Block Diagram
Table 3.11 (1) Prescaler Clock Resolution to Baud Rate Generator
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The 1/4 times clock selected among fFPH clock, fc/16
clock, and fs clock is input to this prescaler. This is
selected by prescaler clock selection register SYSCR0
<PRCK1 : 0>.
Resetting sets <PRCK1 : 0> to “00”, therefore, fFPH /4
clock is input.
The Baud Rate Generator uses 4 types of clock: øT0,
øT2, øT8, and øT32 among the prescaler output.
The prescaler can be run or stopped by the timer control register TRUN <PRRUN>. Counting starts when
<PRRUN> is set to “1”, while the prescaler is cleared
to zero and stops operation when <PRRUN> is set to
“0”.
When the IDLE1 mode (operates only oscillator) is
used, set TRUN <PRRUN> to “0” to stop this prescaler
before “HALT” instruction is executed.
●
Baud rate generator comprises a circuit that generates
transmission and receiving clocks to determine the
transfer rate of the serial channel.
The input clock to the baud rate generator, øT0, øT2,
øT8, or øT32 is generated by the 9-bit prescaler which
is shared by the timers. One of these input clocks is
selected by the baud rate generator control register
BR0CR <BR0CK1, 0>.
The baud rate generator includes a 4-bit frequency
divider, which divides frequency by 2 to 16 values to
determine the transfer rate.
How to calculate a transfer rate when the baud rate
generator is used is explained below.
UART mode
Transfer rate =
●
➁ Baud Rate Generator
Input clock of baud rate generator
Frequency divisor of baud rate generator
÷ 16
Input clock of baud rate generator
Frequency divisor of baud rate generator
÷2
I/O interface mode
Transfer rate =
Accordingly, when source clock fc is 12.288 MHz, input clock is φT2 (fc/16), and frequency divisor is 5, the transfer rate
in UART mode becomes as follows:
Transfer rate =
fc/16 ÷ 16
5
= 12.288 x 106/16/5/16 = 9600 (bps)
Table 3.11 (2) shows an example of the transfer rate in UART mode.
Also with 8-bit timer 0, the serial channel can get a transfer rate. Table 3.9 (3) shows an example of baud rate using timer
0.
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Table 3.11 (2) Selection of Transfer Rate (1) (When Baud Rate Generator is Used)
Unit (kbps)
Input Clock
fc [Mhz]
Frequency
Divisor
φT0
(fc/4)
φT2
(fc/16)
φT8
(fc/64)
φT32
(fc/256)
9.830400
2
76.800
19.200
4.800
1.200
↑
4
38.400
9.600
2.400
0.600
↑
8
19.200
4.800
1.200
0.300
↑
0
9.600
2.400
0.600
0.150
12.288000
5
38.400
9.600
2.400
0.600
↑
A
19.200
4.800
1.200
0.300
14.745600
3
76.800
19.200
4.800
1.200
↑
6
38.400
9.600
2.400
0.600
↑
C
19.200
4.800
1.200
0.300
Note 1: Transfer rate in I/O interface mode is 8 times as fast as the values given in the above table.
Note 2: This table is calculated when fc is selected as a system clock, 1 as a clock gear, and system clock as a prescaler clock.
Table 3.11 (3) Selection of Transfer Rate (1) (When Timer 0 (Input Clock φT1) is Used)
Unit (Kbps)
fc
TREG0
12.288MHz
12MHz
9.8304MHz
8MHz
6.144MHz
1H
96
76.8
62.5
48
2H
48
38.4
31.25
24
3H
32
4H
24
5H
19.2
8H
12
AH
9.6
10H
6
14H
4.8
31.25
16
19.2
12
9.6
9.6
6
4.8
4.8
3
2.4
How to calculate the transfer rate (when timer 0 is used):
Transfer rate =
fc
TREG0 x 8 x 16
↑
(When Timer 0 (input clock φT1) is used)
Note 1: Timer 0 match detect signal cannot be used as the transfer clock in I/O interface mode.
Note 2: This table is calculated when fc is selected as a system clock, 1 as a clock gear, and system clock as a prescaler clock.
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TMP93CM40/TMP93CM41
➂ Serial Clock Generation Circuit
This circuit generates the basic clock for transmitting
and receiving data.
<IOC> = “1", RxD0 signal will be sampled at the rising
edge or falling edge of SCLK0 input according to the
setting of SC0CR <SCLKS> register.
2) Asynchronous Communication (UART) mode
1) I/O interface mode (channel 1 only)
When in SCLK output mode with the setting of SC1CR
<IOC> = “0", the basic clock will be generated by
dividing by 2 the output of the baud rate generator as
described before. When in SCLK input mode with the
setting of SC1CR <IOC> = “1", the rising edge or falling edge will be detected according to the setting of
SC1CR <SCLKS> register to generate the basic clock.
2) Asynchronous Communication (UART) mode
According to the setting of SC0CR <SC1, 0>, the
above baud rate generator clock, internal clock φ1
(500 Kbps @ fc = 16 MHz), or the match detect signal
from timer 0 will be selected to generate the basic
clock SIOCLK.
➃ Receiving Counter
The receiving counter is a 4-bit binary counter used in
asynchronous communication (UART) mode and
counts up by SIOCLK clock. Sixteen pulses of SIOCLK
are used for receiving one bit of data, and the data bit
is sampled three times at 7th, 8th and 9th clock.
With the three samples, the received data is evaluated
by the rule of majority.
For example, if the sampled data bit is “1", “0” and “1”
at 7th, 8th and 9th clock respectively, the received
data is evaluated as “1”. The sampled data “0", “0”
and “1” is evaluated that the received data is “0”.
The receiving control has a circuit for detecting the
start bit by the rule of majority. When two or more “0”
are detected during three samples, it is recognized as
start bit and the receiving operation is started.
Data being received is also evaluated by the rule of
majority.
➅ Receiving Buffer
To prevent overrun error, the receiving buffer has a
double buffer structure.
Received data is stored one bit by one bit in the receiving buffer 1 (shift register type). When 7 bits or 8 bits of
data are stored in the receiving buffer 1, the stored
data is transferred to another receiving buffer 2
(SC0BUF), generating an interrupt INTRX0/INTRX1.
The CPU reads only receiving buffer 2 (SC0BUF). Even
before the CPU reads the receiving buffer 2 (SC0BUF),
the received data can be stored in the receiving buffer
1. However, unless the receiving buffer 2 (SC0BUF) is
read before all bits of the next data are received by the
receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of the receiving buffer 1
will be lost, although the contents of the receiving
buffer 2 and SC0CR <RB8> are still preserved.
The parity bit added in 8-bit UART mode and the most
significant bit (MSB) in 9-bit UART mode are stored in
SC0CR <RB8>.
When in 9-bit UART mode, the wake-up function of
the slave controllers is enabled by setting SC0MOD
<WU> to “1", and interrupt INTRX0 occurs only when
SC0CR <RB8> is set to “1”.
➄ Receiving Control
➆ Transmission Counter
1) I/O interface mode (channel 1 only)
When in SCLK0 output mode with the setting of
SC0CR <IOC> = “0", RxD0 signal will be sampled at
the rising edge of shift clock which is output to SCLK0
pin.
When in SCLK0 input mode with the setting SC0CR
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Transmission counter is a 4-bit binary counter which is
used in asynchronous communication (UART) mode
and, like a receiving counter, counts by SIOCLK clock,
generating TxDCLK every 16 clock pulses.
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TMP93CM40/TMP93CM41
Figure 3.11 (15). Generation of Transmission Clock
➇ Transmission Controller
Handshake function
1) I/O interface mode
Serial channel 0 has a CTS0 pin. Using this pin, data
can be sent in units of one frame; thus, overrun errors
can be avoided. The handshake function is enabled/
disabled by SC0MOD <CTSE>.
When the CTS0 pin goes high, after completion of the
current data send, data send is halted until the CTS0
pin goes low again. The INTTX0 Interrupts are generated, requests the next send data to the CPU.
Though there is no RTS pin, a handshake function can
be easily configured by setting any port assigned to the
RTS function. The RTS should be output “High” to
request data send halt after data receive is completed
by a software in the RXD interrupt routine.
In SCLK0 output mode with the setting of SC0CR
<IOC> = “0", the data in the transmission buffer are
output bit by bit to TxD0 pin at the rising edge of shift
clock which is output from SCLK0 pin.
In SCLK0 input mode with the setting SC0CR <IOC> =
“1", the data in the transmission buffer are output bit by
bit to TxD0 pin at the rising edge or falling edge of
SCLK0 input according to the setting of SC0CR
<SCLKS> register.
2) Asynchronous Communication (UART) mode
When transmission data is written in the transmission
buffer sent from the CPU, transmission starts at the rising edge of the next TxDCLK, generating a transmission shift clock TxDSFT.
Figure 3.11 (16). Handshake Function
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Figure 3.11 (17). Timing of CTS (Clear to Send)
➈ Transmission Buffer
Transmission buffer (SC0BUF) shifts to and sends the
transmission data written from the CPU from the least
significant bit (LSB) in order, using transmission shift
clock TxDSFT which is generated by the transmission
control. When all bits are shifted out, the transmission
buffer becomes empty and generates INTTX0 interrupt.
➉ Parity Control Circuit
When serial channel control register SC0CR <PE> is
set to “1", it is possible to transmit and receive data
with parity. However, parity can be added only in 7-bit
UART or 8-bit UART mode. With SC0CR <EVEN> register, even (odd) parity can be selected.
For transmission, parity is automatically generated
according to the data written in the transmission buffer
SCBUF, and data are transmitted after being stored in
SC0BUF <TB7> when in 7-bit UART mode while in
SC0MOD <TB8> when in 8-bit UART mode. <PE>
and <EVEN> must be set before transmission data are
written in the transmission buffer.
For receiving, data is shifted in the receiving buffer 1,
and parity is added after the data is transferred in the
receiving buffer 2 (SC0BUF/SC1BUF), and then compared with SC0BUF <RB7> when in 7-bit UART mode
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and with SC0MOD <RB8> when in 8-bit UART mode.
If they are not equal, a parity error occurs, and SC0CR
<PERR> flag is set
11
Error Flag
Three error flags are provided to increase the reliability
of receiving data.
1. Overrun error <OERR>
If all bits of the next data are received in receiving buffer
1 while valid data is stored in receiving buffer 2
(SCBUF0), an overrun error will occur.
2. Parity error <PERR>
The parity generated for the data shifted in receiving
buffer 2 (SCBUF) is compared with the parity bit
received from RxD pin. If they are not equal, a parity
error occurs.
3. Framing error <FERR>
The stop bit of received data is sampled three times
around the center. If the majority is “0", a framing error
occurs.
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12
Generating Timing
1) UART mode
Receiving
Mode
Interrupt timing
9 Bit
8 Bit + Parity
8 Bit, 7 Bit + Parity, 7 Bit
Center of last bit (Bit 8)
Center of last bit (parity bit)
Center of stop bit
Center of stop bit
Center of stop bit
Center of stop bit
Parity error timing
Center of last bit (Bit 8)
Center of last bit (parity bit)
Center of stop bit
Overrun error timing
Center of last bit (Bit 8)
Center of last bit (parity bit)
Center of stop bit
Framing error timing
Note:
Framing error occurs after an interrupt has occurred. Therefore, to check for framing error during interrupt operation, it is necessary to wait for 1 bit
period of transfer rate.
Transmitting
Mode
Interrupt timing
9 Bit
8 Bit + Parity
8 Bit, 7 Bit + Parity, 7 Bit
Just before last bit is transmitted.
←
←
2) I/O Interface mode
Transmission interrupt timing
SCLK output mode
Immediately after rise of last SCLK signal. (See Figure 3.11 (20) )
SCLK input mode
Immediately after rise of last SCLK signal (rising mode), or immediately after fall in falling mode.
(See Figure 3.11 (21))
SCLK output mode
Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is, immediately after
last SCLK. (See Figure 3.11 (22))
SCLK input mode
Timing used to transfer received data to data receive buffer 2 (SC1BUF); that is, immediately after
SCLK. (See Figure 3.11 (23))
Receiving interrupt timing
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3.11.3 Operational Description
(1)
Mode 0 (I/O interface mode)
This mode is used to increase the number of I/O pins
for transmitting or receiving data to or from the external
shifter register.
This mode includes SCLK output mode to output synchronous clock SCLK and SCLK input mode to input
external synchronous clock SCLK.
Figure 3.11 (18). Example of SCLK Output Mode Connection
Figure 3.11 (19). Example of SCLK Input Mode Connection
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➀ Transmission
In SCLK output mode, 8-bit data and synchronous clock
are output from TxD0 pin and SCLK0 pin, respectively,
each time the CPU writes data in the transmission buffer.
When all data is output, INTES0 <ITX0C0> will be set to
generate INTTX0 interrupt.
Figure 3.11 (20) Transmitting Operation in I/O Interface Mode (SCLK Output Mode) (Channel 1)
In SCLK output mode, 8-bit data are output from TxD0
pin when SCLK0 input becomes active while data are
written in the transmission buffer by CPU.
When all data are output, INTES0 <ITX0C> will be set
to generate INTTX0 interrupt.
Figure 3.11 (21). Transmitting Operation in I/O Interface Mode (SCLK Input Mode) (Channel 1)
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➁ Receiving
In SCLK output mode, synchronous clock is output
from SCLK0 pin and the data is shifted in the receiving
buffer 1 whenever the receive interrupt flag INTES0
<IRX0C> is cleared by reading the received data.
When 8-bit data are received, the data will be transferred in the receiving buffer 2 (SC0BUF) at the timing
shown below, and INTES0 <IRX0C> will be set again
to generate INTRX0 interrupt.
Figure 3.11 (22). Receiving Operation in I/O Interface Mode (SCLK1 Output Mode) (Channel 1)
In SCLK input mode, the data is shifted in the receiving
buffer 1 when SCLK input becomes active, while the
receive interrupt flag INTES0 <IRX0C> is cleared by reading the received data. When 8-bit data is received, the
data will be shifted in the receiving buffer 2 (SC0BUF) at
the timing shown below, and INTES0 <IRX0C> will be set
again to generate INTRX0 interrupt.
Figure 3.11 (23). Receiving Operation in I/O Interface Mode (SCLK Input Mode) (Channel 1)
Note:
For data receiving, the system must be placed in the receive enable state (SC0MOD <RXE> = “1”)
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(2)
Mode 1 (7-bit UART Mode)
The 7-bit mode can be set by setting serial channel
mode register SC0MOD <SM1, 0> to “01”.
In this mode, a parity bit can be added, and the addition of a parity bit can be enabled or disabled by serial
channel control register SC0CR <PE>, and even parity
(3)
Mode 2 (8-bit UART Mode)
The 8-bit UART mode can be specified by setting
SC0MOD <SM1, 0> to “10”. In this mode, parity bit
can be added, the addition of a parity bit is enabled or
disabled by SC0CR <PE>, and even parity or odd par-
174
or odd parity is selected by SC0CR <EVEN> when
<PE> is set to “1” (enable).
Setting example:
When transmitting data with the following format, the control registers
should be set as described below.
Channel 0 is explained here.
ity is selected by SC0CR <EVEN> when <PE> is set to
“1” (enable).
Setting example:
When receiving data with the following format, the control register
should be set as described below.
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TMP93CM40/TMP93CM41
(4)
Mode 3 (9-bit UART Mode)
Wake-up function
The 9-bit UART mode can be specified by setting
SC0MOD <SM1, 0> to “11”. In this mode, parity bit
cannot be added
For transmission, the MSB (9th bit) is written in
SC0M0D <TB8>, while in receiving it is stored in SCCR
<RB8>. For writing and reading the buffer, the MSB is
read or written first, then SC0BUF.
In 9-bit UART mode, the wake-up function of slave
controllers is enabled by setting SC0MOD <WU> to
“1”. The interrupt INTRX0 occurs only when <RB8> =
1.
.
Figure 3.11 (24). Serial Link Using Wake-Up Function
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TMP93CM40/TMP93CM41
Protocol
➀ Select the 9-bit UART mode for master and slave controllers.
to enable data receiving.
➂ The master controller transmits one-frame data including the 8-bit select code for the slave controllers. The
MSB (bit 8) <TB8> is set to “1”.
➁ Set SC0MOD <WU> bit of each slave controller to “1”
176
➃ Each slave controller receives the above frame, and
clears WU bit to “0” if the above select code matches
its own select code.
➄ The master controller transmits data to the specified
slave controller whose SC0MOD <WU> bit is cleared
to “0.” The MSB (bit 8) <TB8> is cleared to “0”.
➅ The other slave controllers (with the <WU> bit remaining at “1”) ignore the receiving data because their
MSBs (bit 8 or <RB8>) are set to “0” to disable the
interrupt INTRX0. The slave controllers (WU = 0) can
transmit data to the master controller, and it is possible to indicate the end of data receiving to the master
controller by this transmission.
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TMP93CM40/TMP93CM41
Setting Example:
To link two slave controllers serially
with the master controller, and use
Since serial channels 0 and 1 operate in exactly the
the internal clock φ1 (fc/2) as the
transfer clock.
same way, channel 0 is used for the purposes of explanation.
• Setting the master controller
• Setting the slave controller 2
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3.12 Analog/Digital Converter
TMP93CM40/M41 contains a high-speed analog/digital converter (A/D converter) with 8-channel analog input that features
10-bit successive approximation.
Figure 3.12 (1) shows the block diagram of the A/D converter. The 8-channel analog input pins (AN7 to AN0) are
shared by input-only P5 and so can be used as input port.
Figure 3.12 (1). Block Diagram of A/D Converter
Note:
178
This A/D converter does not have a built-in sample and hold circuit. Therefore, when A/D converting high-frequency signals, connect a sample and
hold circuit externally.
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TMP93CM40/TMP93CM41
Figure 3.12 (2-1). A/D Control Register
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Figure 3.12 (2-2). A/D Control Register
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TMP93CM40/TMP93CM41
Figure 3.12 (3-1). A/D Conversion Result Register (ADREG04, 15)
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TMP93CM40/TMP93CM41
Figure 3.12 (3-2). A/D Conversion Result Register (ADREG04, 15)
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3.12.1 Operation
(1)
Analog Reference Voltage
High analog reference voltage is applied to the VREFH
pin, and low analog reference voltage is applied to
VREFL pin.
The reference voltage between VREFH and VREFL is
divided by 1024 using ladder resistance, and compared with the analog input voltage for A/D conversion.
The switch between VREFH and VREFL can be cut
(OFF) by writing “0” to <VREFON>.
When the conversion will be started at the <VREFON>
= “0”, write “1” to <VEFRON> before writing “1” to
<ADS>.
(2)
(4)
(6)
A/D Conversion Mode
Both fixed A/D conversion channel mode and A/D
conversion channel scan mode have two conversion
modes, i.e., single and repeat conversion modes.
In fixed channel repeat mode, conversion of specified
one channel is executed repeatedly.
In scan repeat mode, scanning from AN0, … → AN3 is
executed repeatedly.
A/D conversion mode is selected by ADMOD1
<REPET, SCAN>.
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A/D Conversion End and Interrupt
• A/D conversion single mode
ADMOD1 <EOCF> for A/D conversion end will be set
to “1,” ADMOD1 <ADBF> flag will be reset to “0,” and
INTAD interrupt will be enabled when A/D conversion
of specified channel ends in fixed conversion channel
mode or when A/D conversion of the last channel ends
in channel scan mode.
• A/D conversion repeat mode
For both fixed conversion channel mode and conversion channel scan mode, INTAD should be disabled
when in repeat mode. Always set the INTE0AD at
“000”, so that it disables the interrupt request.
Write “0” to ADMOD2 <REPET> to end the repeat
mode. Then, the repeat mode will be exited as soon as
the conversion in progress is completed.
(7)
Storing the A/D Conversion Result
The results of A/D conversion are stored in ADREG04
to ADREG37 registers for each channel.
The result registers are used both as AN0 and AN4,
AN1 and AN5, AN2 and AN6, AN3 and AN7.
However, the current conversion data cannot be
known which channels.
In repeat mode, the registers are updated whenever
conversion ends.
ADREG04 to ADREG37 are read-only registers.
Starting A/D Conversion
A/D conversion starts when A/D conversion register
ADMOD1 <ADS> is written “1". When A/D conversion
starts, A/D conversion busy flag ADMOD1 <ADBF>
which indicates “conversion is in progress” will be set
to “1".
A/D Conversion Speed Selection
There are four A/D conversion speed modes. The
selection is executed by ADMOD2 <SPEED1:0> register.
When reset, ADMOD <SPEED1:0> will be initialized to
“00”, so that high speed conversion mode will be
selected.
Analog Input Channels
Analog input channel is selected by ADMOD
<ADCH2:0>. However, which channel to select
depends on the operation mode of the A/D converter.
In fixed analog input mode, one channel is selected by
ADMOD <ADCH2:0> among four pins: AN0 to AN7.
In analog input channel scan mode, the number of
channels to be scanned from AN0 or AN4 is specified
by <ADCH2:0>, such as AN0 → AN1, AN0 → AN1 →
AN2, AN0 → AN1 → AN2 → AN3, AN4 → AN5, AN4
→ AN5 → AN6, and AN4 → AN5 → AN6 → AN7.
When reset, A/D conversion channel register will be initialized to ADMOD <ADCH2:0> = 00, so that AN0 pin
will be selected.
The pins which are not used as analog input channel
can be used as ordinary input port P5.
(3)
(5)
(8)
Reading the A/D Conversion Result
The results of A/D conversion are stored in ADREG04
to ADREG37 registers.
When the contents of one of ADREG04L, ADREG15L,
ADREG26L, and ADREG37L registers are read,
ADMOD1 <EOCF> will be cleared to “0".
<EOCF> is not cleared to “0" when the contents of
one ADREG04L, ADREG15L, ADREG26L, and
ADREG37L for lower 2-bits is read.
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3.13 Watchdog Timer (Runaway Detecting Timer)
TMP93CM40/M41 contain watchdog timer of Runaway
detecting.
The watchdog timer (WDT) is used to return the CPU to
the normal state when it detects that the CPU has started to
malfunction (runaway) due to causes such as noise. When the
watchdog timer detects a malfunction, it generates a nonmaskable interrupt to notify the CPU of the malfunction, and
outputs “0” externally from watchdog timer out pin WDTOUT
to notify the peripheral devices of the malfunction.
Connecting the watchdog timer output to the reset pin
internally forces a reset.
This binary counter is also used as a warming up timer
for the internal oscillator stabilization. This is used when the
STOP releasing and before changing system clock.
3.13.1 Configuration
Figure 3.13 (1) shows the block diagram of the watchdog timer
(WDT).
Figure 3.13 (1). Block Diagram of Watchdog Timer/Warming Up Timer
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TMP93CM40/TMP93CM41
The watchdog timer is a 22-stage binary counter which
uses φ (fc/2) as the input clock. There are four outputs from the
binary counter: 216/fc, 218/fc, 220/fc, and 222/fc. Selecting one
of the outputs with the WDMOD register generates a watchdog interrupt, and outputs watchdog timer out when an overflow occurs.
Since the watchdog timer out pin (WDTOUT) outputs “0”
due to a watchdog timer overflow, the peripheral devices can
be reset. The watchdog timer out pin is set to “1” after disabling WDT and clearing the watchdog timer (by writing a clear
code 4EH in the WDCR register).
(Example)
LDW
LD
SET
(WDMOD), B100H
(WDCR), 4EH
7, (WDMOD)
;
;
;
disable
write clear code
enable again
In other words, the WDTOUT keeps outputting “0” until
the clear code is written.
The watchdog timer out pin can also be connected to the
reset pin internally. The watchdog timer out pin (WDTOUT) outputs 0 to 8 to 20 states (16 to 40 µs @ fc = 16MHz) and resets
itself.
Figure 3.13 (2). Normal Mode
Figure 3.13 (3). Reset Mode
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TMP93CM40/TMP93CM41
3.13.2 Control Registers
Watchdog timer WDT is controlled by two control registers
WDMOD and WDCR.
(1)
enable the watchdog timer.
To disable, it is necessary to clear this bit to “0” and
write the disable code (B1H) in the watchdog timer
control register WDCR. This makes it difficult for the
watchdog timer to be disabled by runaway.
However, it is possible to return from the disable state
to enable state by merely setting <WDTE> to “1".
Watchdog Timer Mode Register (WDMOD)
➀ Setting the detecting time of watchdog timer
<WDTP>
➂ Watchdog timer out reset connection <RESCR>
This 2-bit register is used to set the watchdog timer
interrupt time for detecting the runaway. This register is
initialized to WDMOD <WDTP1, 0> = 00 when reset,
and therefore 216/fc is set. (The number of states is
approximately 32,768).
The detecting time of WDT is shown in Figure 3.13 (6).
This register is used to connect the output of the
watchdog timer with RESET terminal, internally. Since
WDMOD <RESCR> is initialized to 0 at reset, a reset
by the watchdog timer will not be performed.
(2)
➁ Watchdog timer enable/disable control register
<WDTE>
Watchdog Timer Control Register (WDCR)
This register is used to disable and clear the binary
counter of the watchdog timer function.
When reset, WDMOD <WDTE> is initialized to “1”
• Disable control
• Enable control
Set WDMOD <WDTE> to “1".
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• Watchdog timer clear control
The binary counter can be cleared and resume
counting by writing clear code (4EH) into the WDCR register.
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Figure 3.13 (4). Watchdog Timer Mode Register
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TMP93CM40/TMP93CM41
Figure 3.13 (5). Watchdog Timer Control Register
Figure 3.13 (6). Watchdog Detecting Time
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3.13.3 Operation
The watchdog timer generates interrupt INTWD after the
detecting time set in the WDMOD <WDTP1, 0> register and
outputs a low level signal. The watchdog timer must be zerocleared by software before an INTWD interrupt is generated. If
the CPU malfunctions (runaway) due to causes such as noise,
but does not execute the instruction used to clear the binary
counter, the binary counter overflows and an INTWD interrupt
is generated. The CPU detects malfunction (runaway) due to
the INTWD Interrupt and it is possible to return to normal operation by an anti-malfunction program. By connecting the
190
watchdog timer out pin to peripheral devices’ resets, a CPU
malfunction can also be acknowledged to other devices.
The watchdog timer restarts operation immediately after
resetting is released.
The watchdog timer stops its operation in the IDLE1 and
STOP modes. In the RUN mode, the watchdog timer is
enabled. When the bus is released (BUSAK = “L”), WDT continues counting up.
However, the function can be disabled when entering the
RUN, IDLE2 modes.
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TMP93CM40/TMP93CM41
4.
Electrical Characteristics
4.1 Absolute Maximum (TMP93CM40F/TMP93CM41F)
Symbol
Parameter
Vcc
Power Supply Voltage
V IN
Input Voltage
Σ IOL
Output Current (total)
Rating
Unit
-0.5 to 6.5
V
-0.5 ~ Vcc + 0.5
V
120
mA
Σ IOH
Output Current (total)
-80
mA
PD
Power Dissipation (Ta = 85°C)
600
mW
T SOLDER
Soldering Temperature (10s)
260
°C
T STG
Storage Temperature
-65 to 150
°C
T OPR
Operating Temperature
-40 to 85
°C
4.2 DC Characteristics (1/2)
Symbol
Parameter
Max
Typ.
(Note 1)
Max
Unit
fc = 4 to 16MHz
fs = 30 to 34kHz (Ta = -40 to 85°C)
4.5
Vcc
Power Supply Voltage
5.5
V
2.7
(Note 2)
V IL
V IL1
Port 2 to A (except P87, P5)
0.3 Vcc
RESET, NMI, INT0
0.25 Vcc
V IL3
EA, AM8/16
V IL4
X1, P5
0.2 Vcc
2.2
2.0
V IH1
Port 2 to A (except P87)
0.7 Vcc
RESET, NMI, INT0
0.75 Vcc
V IH3
EA, AM8/16
Vcc - 0.3
X1
V OL
Output Low Voltage
V OH
V OH1
Output High Voltage
I DAR
(note 3)
Darlington Drive Current
(8 Output Pins max.)
VCC ≥ 4.5V
VCC < 4.5V
VCC = 2.7 to 5.5V
0.8 Vcc
0.45
V
I OL = 1.6mA (VCC = 2.7 to 5.5V)
V
I OH = -400µA (VCC = 2.7 to 5.5V)
0.75 Vcc
V
I OH = -100µA (VCC = 5V±10%)
0.9 Vcc
V
I OH = - 20µA (VCC = 5V±10%)
mA
VEXT = 1.5V
REXT = 1.1KΩ (VCC = 5V±10%)
-1.0
-3.5
I LI
Input Leakage Current
0.02 (Typ)
±5
I LO
Output Leakage Current
0.05 (Typ)
±10
(note 1) Typical values are for Ta = 25°C and VCC = 5V unless otherwise.
(note 3) I-DAR is guaranteed for a total of up to 8 ports.
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V
Vcc + 0.3
2.4
V OH2
VCC = 2.7 to 5.5V
0.3
V IH2
V IH4
VCC ≥ 4.5V
VCC < 4.5V
0.8
0.6
Low High Voltage (AD0 to 15)
Low High Voltage (AD0 to 15)
fc = 4 to 20MHz
fs = 30 to 34kHz (Ta = -20 to 70°C)
fc = 4 to 10MHz
fs = 30 to 34kHz (Ta = -40 to 85°C)
V IL2
V IH
Test Condition
µA
0.0 ≤ Vin ≤ Vcc
0.2 ≤ Vin ≤ Vcc - 0.2
(note 2) The operation of A/D converter is guaranteed at VCC = 5V± 10%.
(note 4)The condition of measurement of ICC (Normal/Slow).
Operates only CPU, output ports are open and input ports fixed.
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(2/2)
4.2 DC Characteristics (1/2)
Symbol
Parameter
Max
Typ.
(Note 1)
Max
Unit
Test Condition
V STOP
Power Down Voltage
(at STOP, RAM Back up)
2.0
6.0
R RST
RESET Pull Up Register
50
80
150
200
KΩ
VCC = 5V±10%
VCC = 3V±10%
10
pF
tosc = 1MHz
VIL2 = 0.2Vcc,
VIH2 = 0.8Vcc
C IO
Pin Capacitance
V TH
Schmitt Width
RESET, NMI, INTO (P87)
0.4
R KL
Programmable Pull Down Register
10
30
80
150
KΩ
VCC = 5V±10%
VCC = 3V±10%
R KH
Programmable Pull Up Register
50
100
150
300
KΩ
VCC = 5V±10%
VCC = 3V±10%
I cc
1.0
V
Operating Current (NORMAL)
RUN
IDLE2
IDLE1
16
14
8.0
1.0
25
25
15
5
Operating Current (NORMAL)
RUN
IDLE2
IDLE1
6.0
5.0
3.0
0.4
8
7
4
1.1
Operating Current (SLOW)
RUN
IDLE2
IDLE1
30
28
20
15
35
30
20
15
µA
VCC = 3V±10%
fs = 32.768kHz
(Typ.: VCC = 3.0V)
STOP
0.2
10
µA
VCC = 2.7 to 5.5V
(note 1) Typical values are for Ta = 25°C and VCC = 5V unless otherwise.
(note 3) I-DAR is guaranteed for a total of up to 8 ports.
192
V
VCC = 5V±10%
fc = 20MHz
mA
VCC = 3V±10%
fc = 10MHz
(Typ.: VCC = 3.0V)
(note 2) The operation of A/D converter is guaranteed at VCC = 5V± 10%.
(note 4)The condition of measurement of ICC (Normal/Slow).
Operates only CPU, output ports are open and input ports fixed.
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4.3 AC Electrical Characteristics
(1) Vcc = 5V±10%
Variable
No.
Symbol
16MHz
20MHz
Parameter
Unit
Min
1
tOSC
Osc. Period (= x)
2
tCLK
CLK width
3
tAK
4
tKA
5
tAL
A0-15 Valid→ALE fall
6
tLA
ALE fall→A0 - 15 Hold
7
tLL
ALE High width
x - 40
8
tLC
ALE fall→RD/WR fall
9
tCL
RD/WR rise→ALE rise
10
tACL
11
12
Max
Min
Max
50
ns
2x - 40
85
60
ns
A0 - 23 Valid→CLK Hold
0.5x - 20
11
5
ns
CLK Valid→A0 - 23 Hold
1.5x - 70
24
5
ns
0.5x - 15
16
10
ns
0.5x - 15
11
5
ns
23
10
ns
0.5x - 30
6
0
ns
0.5x - 20
11
5
ns
A0 - 15 Valid→RD/WR fall
x - 25
38
25
ns
tACH
A0 - 23 Valid→RD/WR fall
1.5x - 50
44
25
ns
tCA
RD/WR rise→A0 - 23 Hold
0.5x - 25
6
0
ns
13
tADL
A0 - 15 Valid→D0 - 15 input
3.0x - 55
143
95
ns
14
tADH
A0 - 23 Valid→D0 - 15 input
3.5x - 65
154
110
ns
15
tRD
RD fall→D0 - 15 input
2.0x - 60
75
40
ns
16
tRR
RD Low width
tHR
RD rise→D0 - 15 Hold
18
tRAE
RD rise→A0 - 15 output
250
Min
62.5
17
50
Max
2.0x - 40
0
x - 15
85
60.0
ns
0
0.0
ns
48
35.0
ns
19
tWW
WR Low width
2.0x - 40
85
60
ns
20
tDW
D0 - 15 Valid→WR rise
2.0x - 55
70
45
ns
21
tWD
WR rise→D0 - 15 Hold
0.5x - 15
16
10
ns
22
tAEH
A0 - 23 Valid→WAIT input (1WAIT + n mode)
3.5x - 90
129
85
ns
23
tAWL
A0 - 15 Valid→WAIT input (1WAIT + n mode)
3.0x - 80
108
70
ns
24
tCW
RD/WR fall→WAIT Hold (1WAIT + n mode)
25
tAPH
A0 - 23 Valid→PORT input
26
tAPH2
A0 - 23 Valid→PORT Hold
2.0x + 0
125
2.5x - 120
2.5x + 50
WR rise→PORT Valid
100.0
36
206
200
ns
5
175.0
200
ns
ns
200
ns
27
tCP
28
tASRH
A0 - 23 Valid→RAS fall
1.0x - 40
23
10
ns
29
tASRL
A0 - 15 Valid→RAS fall
0.5x - 15
16
10
ns
30
tRAC
RAS fall→D0 - 15 input
31
tRAH
RAS fall→A0 - 15 Hold
0.5x - 15
16
10
ns
32
tRAS
RAS Low width
2.0x - 40
85
60
ns
33
tRP
RAS High width
2.0x - 40
85
60
ns
34
tRSH
CAS fall→RAS rise
1.0x - 35
23
10
ns
35
tRSC
RAS rise→CAS rise
0.5x - 25
6
0
ns
36
tRCD
RAS fall→CAS fall
1.0x - 40
37
tCAC
CAS fall→D0 - 15 input
38
tCAS
CAS Low width
2.5x - 70
86
23
1.5x - 65
1.5x - 30
55
10
29
64
ns
10
40
ns
ns
ns
AC Measuring Conditions
• Output Level:
High 2.2V
/Low 0.8V, CL50pF
(However CL = 100pF for AD0 ~ AD15, AD0 to AD23, ALE, RD, WR, HWR, R/W, CLK, RAS, CAS0 to CAS2)
• Input Level:
High 2.4V
/Low 0.45V (AD0 to AD15)
High 0.8Vcc /Low 0.2Vcc (Except for AD0 to AD15)
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(2)
Vcc = 3V±10% (TMP93CM40/M41F are guaranteed up to 10MHz operation)
Variable
No.
Symbol
10MHz
Parameter
1
tOSC
Osc. Period (= x)
2
tCLK
CLK width
3
tAK
A0 - 23 Valid→CLK Hold
Unit
Min
Max
Min
Max
80
250
100
ns
2x - 40
160
ns
0.5x - 30
20
ns
4
tKA
CLK Valid→A0 - 23 Hold
1.5x - 80
70
ns
5
tAL
A0-15 Valid→ALE fall
0.5x - 35
15
ns
6
tLA
ALE fall→A0 - 15 Hold
0.5x - 35
15
ns
7
tLL
ALE High width
x - 60
40
ns
8
tLC
ALE fall→RD/WR fall
0.5x - 40
10
ns
9
tCL
RD/WR rise→ALE rise
0.5x - 40
10
ns
10
tACL
A0 - 15 Valid→RD/WR fall
x - 50
50
ns
11
tACH
A0 - 23 Valid→RD/WR fall
1.5x - 50
10
ns
12
tCA
RD/WR rise→A0 - 23 Hold
0.5x - 40
30
ns
13
tADL
A0 - 15 Valid→D0 - 15 input
3.0x - 110
100
ns
14
tADH
A0 - 23 Valid→D0 - 15 input
3.5x - 125
225
ns
15
tRD
RD fall→D0 - 15 input
16
tRR
RD Low width
17
tHR
RD rise→D0 - 15 Hold
18
tRAE
RD rise→A0 - 15 output
19
tWW
WR Low width
20
tDW
21
22
23
2.0x - 115
2.0x - 40
0
85
ns
1600
ns
0
ns
x - 25
75
ns
2.0x - 40
160
ns
D0 - 15 Valid→WR rise
2.0x - 120
80
ns
tWD
WR rise→D0 - 15 Hold
0.5x - 40
tAEH
A0 - 23 Valid→WAIT input (1WAIT + n mode)
3.5x - 130
220
ns
tAWL
A0 - 15 Valid→WAIT input (1WAIT + n mode)
3.0x - 100
200
ns
130
ns
200
ns
10
2.0x + 0
ns
24
tCW
RD/WR fall→WAIT Hold (1WAIT + n mode)
25
tAPH
A0 - 23 Valid→PORT input
200
26
tAPH2
A0 - 23 Valid→PORT Hold
27
tCP
28
tASRH
A0 - 23 Valid→RAS fall
1.0x - 60
29
tASRL
A0 - 15 Valid→RAS fall
0.5x - 40
30
tRAC
RAS fall→D0 - 15 input
31
tRAH
RAS fall→A0 - 15 Hold
0.5x - 25
25
ns
2.5x - 120
2.5x + 50
WR rise→PORT Valid
ns
300
200
ns
40
ns
10
2.5x - 90
ns
160
ns
32
tRAS
RAS Low width
2.0x - 40
160
ns
33
tRP
RAS High width
2.0x - 40
160
ns
34
tRSH
CAS fall→RAS rise
1.0x - 55
45
ns
35
tRSC
RAS rise→CAS rise
0.5x - 25
25
ns
36
tRCD
RAS fall→CAS fall
1.0x - 40
60
ns
37
tCAC
CAS fall→D0 - 15 input
38
tCAS
CAS Low width
1.5x - 120
1.5x - 30
30
1200
ns
ns
AC Measuring Conditions
• Output Level:
High 2.2V
/Low 0.8V, CL50pF
(However CL = 100pF for AD0 ~ AD15, AD0 ~ AD23, ALE, RD, WR, HWR, R/W, CLK, RAS, CAS0 ~ CAS2)
• Input Level:
High 2.4V
/Low 0.45V (AD0 ~ AD15)
High 0.8Vcc /Low 0.2Vcc (Except for AD0 ~ AD15)
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(1)
Read Cycle
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(2)
196
Write Cycle
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4.4 A/D Conversion Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VREF
Analog reference voltage
Vcc - 0.2V
Vcc
Vcc
AGND
Analog reference voltage
Vss
Vss
Vss + 0.2V
VAIN
Analog input voltage range
Vss
IREF (VREFL = 0V)
V
Vcc
Analog current for analog reference voltage
VCC = 5V±10% <VREFON> = 1
0.5
1.5
mA
±3.0
±6
LSB
VCC = 5V±10% <VREFON> = 0
Error
VCC = 5V±10%
4.5 Serial Channel Timing - I/O Interface Mode
(1) SCLK Input Mode
Variable
Symbol
10MHz
20MHz
Parameter
Unit
Min
tSCY
SCLK cycle
Max
Min
Max
Min
Max
16x
1.6
0.8
µs
tOSS
Output Data→rising edge of SCLK
tSCY/2 - 5x - 50
250
100
ns
tOHS
SCLK rising edge→output data hold
5x - 100
400
150
ns
tHSR
SCLK rising edge→input data hold
0
0
0
ns
tSRD
SCLK rising edge→effective data input
tSCY - 5x - 100
1000
450
ns
(2) SCLK Output Mode
Variable
Symbol
10MHz
20MHz
Parameter
tSCY
SCLK cycle (programmable)
tOSS
Output Data→rising edge of SCLK
tOHS
tHSR
tSRD
SCLK rising edge→effective data input
Unit
Min
Max
Min
Max
Min
Max
16x
8192x
1.6
819.2
0.8
409.6
µs
tSCY - 2x - 150
1250
550
SCLK rising edge→output data hold
2x - 80
120
20
ns
SCLK rising edge→input data hold
0
0
0
ns
tSCY - 2x - 150
ns
1250
550
ns
4.6 Timer/Counter Input Clock (TI0, TI4, TI5, TI6, TI7)
Variable
Symbol
10MHz
20MHz
Parameter
Unit
Min
Max
Min
Max
Min
Max
tVCK
Clock cycle
8x + 100
900
500
ns
tVCKL
Low level clock pulse width
4x + 40
440
240
ns
tVCKH
High level clock pulse width
4x + 40
440
240
ns
4.7 Interrupt Operation
Variable
Symbol
10MHz
20MHz
Parameter
Unit
Min
Max
Min
Max
Min
Max
tINTAL
NMI, INT0 Low level pulse width
4x
400
200
ns
tINTAH
NMI, INT0 High level pulse width
4x
400
200
ns
tINTBL
INT4 ~ INT7 Low level pulse width
8x + 100
900
500
ns
tINTBH
INT4 ~ INT7 High level pulse width
8x + 100
900
500
ns
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4.8 SCOUT Pin Characteristics
Variable
Symbol
20MHz
Unit
Min
High level pulse width
VCC = 5V±10%
↑
VCC = 3V±10%
Low level pulse width
VCC = 5V±10%
↑
VCC = 3V±10%
198
10MHz
Parameter
Max
Min
Max
Min
5x - 10
40
15
5x - 20
30
–
5x - 10
40
15
5x - 20
30
–
Max
ns
–
ns
–
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4.9 Timing Chart for I/O Interface Mode
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4.10 Timing Chart for Bus Request (BUSRQ)/BUS Acknowledge (BUSAK)
Variable
Symbol
10MHz
20MHz
Parameter
Unit
Min
Max
Max
120
Min
Max
tBRC
BUSRQ setup time for CLK
tCBAL
CLK→BUSAK falling edge
tCBAH
CLK→BUSAK rising edge
65
ns
tABA
Output buffer is off to BUSAK
0
80
0
80
0
80
ns
tBAA
BUSAK
0
80
0
80
0
80
ns
output buffer is on.
120
Min
1.5x + 120
120
270
0.5x + 40
ns
195
90
ns
Note 1: The Bus will be released after the WAIT request is inactive, when the BUSRQ is set to “0” during “Wait” cycle.
Note 2: This line only shows the output buffer is off-states. They don’t indicate the signal levels are fixed. After the bus is released, the signal level is kept
dynamically before the bus is released by the external capacitance. Therefore, to fix the signal level by an external resistance under the bus is releasing,
the design must be carefully because of the level-fix will be delayed. The internal programmable pull-up/pull-down resistance is switched active by the
internal signal.
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5.
Table of Special Function Registers
(SFRs)
(SFR; Special Function Register)
The special function registers (SFRs) include the I/O ports and
peripheral control registers allocated to the 128-byte
addresses from 000000H to 00007FH.
(1) I/O port
(2) I/O port control
(3) Timer control
(4) Pattern Generator control
(5) Watch Dog Timer control
(6) Serial Channel control
(7) A/D converter control
(8) Interrupt control
(9) Chip Select/Wait Control
(10) Clock Control
Configuration of the table
Note:
“Prohibit “RMW” in table means that you cannot use RMW instructions to these registers.
(Example) Setting only the bit0 of register P0CR, do not use “Set 0, (0002H)”.
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Table 5 I/O Register Address Map
202
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(1)
I/O Port
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(2)
204
I/O Port Control (1/2)
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(2)
I/O Port Control (2/2)
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205
TMP93CM40/TMP93CM41
(3)
206
Timer Control (1/3)
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(3)
Timer Control (2/3)
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207
TMP93CM40/TMP93CM41
(3)
208
Timer Control (3/3)
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TMP93CM40/TMP93CM41
(4)
Pattern Generator
(5)
Watch Dog Timer
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TMP93CM40/TMP93CM41
(6)
210
Serial Channel
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(7)
A/D Converter Control
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211
TMP93CM40/TMP93CM41
(8)
212
Interrupt Control (1/2)
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(8)
Interrupt Control (2/2)
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213
TMP93CM40/TMP93CM41
(9)
214
Chip Select/Controller
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(10)
Clock Control
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TMP93CM40/TMP93CM41
6. Port Section Equivalent Circuit Diagram
• Reading The Circuit Diagram
Basically, the gate singles written are the same as
those used for the standard CMOS logic IC [74HCXX]
series.
The dedicated signal is described below.
STOP: This signal becomes active “1” when the hold mode
setting register is set to the STOP mode and the CPU
executes the HALT instruction. When the drive enable
bit [DRIVE] is set to “1”, however, STP remains at “0”.
• The input protection resistor ranges from several tens of
ohms to several hundreds of ohms.
• PO (AD0 to AD7), P1 (AD8 to 15, A8 to 15), P2 (A16 to 23, A0 to 7)
• P30 (RD), P31 (WR)
• P32 to 37, P40 to 41, P6, P7, P80 to 86, P91 to 92, P94 to 95, PA
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• P42 (CS2, CAS2)
• P5 (AN0 to 7)
• P87 (INT0)
• P90 (TXD0), P93 (TXD1)
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• P96 (XT1), P97 (XT2)
• NMI
• WDTOUT
• CLK
• EA, AM8/16
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• ALE
• RESET
• X1, X2
• VREF, AGND
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TMP93CM40/TMP93CM41
7. Care Points and Restriction
➃ Standby Mode (IDLE1)
(1)
When IDEL1 mode (operates only as an oscillator) is
used, set TRUN <PRRUN> to “0” to stop prescaler
before “HALT” instruction is executed.
Special Expression
➀ Explanation of a built-in I/O register: Register
Symbol
<Bit Symbol>
ex) TRUN <T0RUN> . . . Bit T0RUN of Register TRUN
➁ Read, Modify and Write Instruction
An instruction which CPU executes following by one
instruction.
1. CPU reads data of the memory.
2. CPU modifies the data.
3. CPU writes the data to the same memory.
ex1) SET 3, (TRUN) . . . set bit3 of TRUN
ex2) INC1, (100H) increment the data of 100H
• The representative Read, Modify and Write
Instruction in the TLCS-900
SET
imm, mem,
RES
imm, mem
CHG
imm, mem,
TSET
imm, mem
INC
imm, mem,
DEC
imm, mem
RLD
A, mem,
ADD
imm, reg
The warming-up counter operates when the STOP
mode. is released even the system which is used an
external oscillator. As a result, it takes warming up time
from inputting the releasing request to outputting the
system clock.
➅ High Speed µDMA (DRAM refresh mode)
When the bus is released (BUSAK = “0”) for waiting to
accept the interrupt, DRAM refresh is not performed
because of the high speed µDMA is generated by an
interrupt.
⑦ Programmable Pull Up/Down Resistance
The programmable pull up/down resistors can be
selected ON/OFF by program when they are used as
the input ports. The case of they are used as the output ports, they cannot be selected ON/OFF by program.
➂ 1 state
⑧ Bus Releasing Function
1 cycle clock divided by 2 oscillation frequency is
called 1 state
Refer to the “Note about the Bus Release” in 3.5 Functions of Ports because the pin state when the bus is
released is written.
ex) The case of oscillation frequency is 20MHz.
(2)
➄ Warming-up Counter
Care Points
➈ Watch Dog Timer
➀ EA, AM8/16 pin
The watch dog timer starts operation immediately after
the reset is released. When the watch dog timer is not
used, set watch dog timer to disable.
Fix these pins VCC or GND unless changing voltage.
➉ Watch Dog Timer
➁ TEST2, TEST2 pin
When the bus is released, both internal memory and
internal I/O cannot be accessed. But internal I/O continues to operate. So, the watch dog timer continues
to run. Therefore, be careful with the bus releasing time
and set the detection timer of watch dog timer.
Connect TEST1 pin with TEST2 pin.
➂ Reserved Area in Memory Space
The 256 byte memory area for FFFF00H to FFFFFFH
cannot be used because it is a reserved area.
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11
A/D Converter
The ladder resistor between CREFH and VREFL pins
can be cut by program to reduce the power consumption. When the standby mode is used, cut by program
before “HALT” instruction is used.
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CPU (High SpeedµDMA)
Only the “LDC cr, r”, “LDC r, cr” instruction can be
used to access the control register like transfer source
address register (DMASn) in the CPU.
221
TMP93CM40/TMP93CM41
8. TMP93XX40/41 Different Points
222
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