STB36NF02L N-CHANNEL 20V - 0.016 Ω - 36A D2PAK LOW GATE CHARGE STripFET POWER MOSFET PRELIMINARY DATA TYPE STB36NF02L ■ ■ ■ ■ ■ VDSS R DS(on) ID 20 V <0.021 Ω 36 A TYPICAL RDS(on) = 0.016 Ω TYPICAL Qg = 19 nC @ 10V OPTIMAL RDS(on) x Qg TRADE-OFF CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED 3 1 D2PAK TO-263 (suffix“T4”) DESCRIPTION This application specific Power Mosfet is the third generation of STMicroelectronics unique “Single Feature Size ” strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. ADD SUFFIX “T4” FOR ORDERING IN TAPE & REEL INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Drain-source Voltage (VGS = 0) 20 V Drain-gate Voltage (RGS = 20 kΩ) 20 V Gate- source Voltage ±20 V ID Drain Current (continuos) at TC = 25°C 36 A ID Drain Current (continuos) at TC = 100°C 25 A V DS V DGR VGS IDM(•) Drain Current (pulsed) 144 A Ptot Total Dissipation at TC = 25°C Derating Factor 75 W Tstg Storage Temperature Tj Max. Operating Junction Temperature 0.5 W/°C –65 to 175 °C 175 °C (•)Pulse width limited by safe operating area November 2000 This is preliminary data new product in development or undergoing evaluation. Details are subject to change without notice. 1/6 STB36NF02L THERMAL DATA R thj-case Thermal Resistance Junction-case Max Max 2 °C/W R thj-amb Thermal Resistance Junction-ambient Max Max 62.5 °C/W 300 °C Tj Maximum Lead Temperature For Soldering Purpose ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA IDSS Zero Gate Voltage Drain Current (V GS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20 V V(BR)DSS VGS = 0 Min. Typ. Max. 20 Unit V 1 10 µA µA ±100 nA Max. Unit 2.5 V 0.021 0.03 Ω Ω ON (*) Symbol Parameter Test Conditions ID = 250 µA VGS(th) Gate Threshold Voltage VDS = VGS R DS(on) Static Drain-source On Resistance VGS = 10 V VGS = 4.5 V ID(on) On State Drain Current VDS > ID(on) x RDS(on)max VGS = 10V Min. Typ. 1 ID = 18 A I D = 18 A 0.016 0.023 36 A DYNAMIC Symbol gfs (*) C iss Coss Crss 2/6 Parameter Test Conditions Min. Typ. Max. Unit Forward Transconductance VDS > ID(on) x R DS(on)max ID=18 A 20 S Input Capacitance Output Capacitance Reverse Transfer Capacitances VDS = 25V f = 1 MHz VGS = 0 750 270 60 pF pF pF STB36NF02L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 15 V ID = 40 A RG = 4.7 Ω VGS = 4.5 V (see test circuit, Figure 3) 20 270 Qg Qgs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD= 16 V ID= 36 A VGS=10V 19 3 5 21 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions Min. VDD = 15 V ID = 40 A RG = 4.7 Ω VGS = 4.5 V (Resistive Load, see fig.3) 35 60 ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM(•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 36 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD =36 A di/dt = 100 A/µs VDD = 15 V Tj = 150 °C (see test circuit, Figure 5) trr Qrr IRRM Test Conditions Min. Typ. VGS = 0 50 80 2 Max. Unit 36 144 A A 1.5 V ns nC A (*) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limit ed by safe operating area. . . 3/6 STB36NF02L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STB36NF02L D2PAK MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. A 4.4 4.6 0.173 TYP. 0.181 MAX. A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 D1 E 8 10 10.4 0.393 4.88 5.28 0.192 0.208 E1 G 0.368 0.315 8.5 0.334 L 15 15.85 0.590 0.625 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 M 2.4 3.2 0.094 0.126 R V2 0.4 0º 0.015 8º 5/6 STB36NF02L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com 6/6