® OPA689 OPA 689 OPA 689 For most current data sheet and other product information, visit www.burr-brown.com Wideband, High Gain VOLTAGE LIMITING AMPLIFIER FEATURES APPLICATIONS ● HIGH LINEARITY NEAR LIMITING ● FAST RECOVERY FROM OVERDRIVE: 2.4ns ● TRANSIMPEDANCE WITH FAST OVERDRIVE RECOVERY ● FAST LIMITING ADC INPUT DRIVER ● LIMITING VOLTAGE ACCURACY: ±15mV ● –3dB BANDWIDTH (G = +6): 280MHz ● LOW PROP DELAY COMPARATOR ● NON-LINEAR ANALOG SIGNAL PROCESSING ● STABLE FOR G ≥ +4 ● SLEW RATE: 1600V/µs ● DIFFERENCE AMPLIFIER ● IF LIMITING AMPLIFIER ● ±5V AND +5V SUPPLY OPERATION ● LOW GAIN VERSION: OPA688 ● AM SIGNAL GENERATION DESCRIPTION The OPA689 is a wideband, voltage feedback op amp that offers bipolar output voltage limiting, and is stable for gains ≥ +4. Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. This new output limiting architecture holds the limiter offset error to ±15mV. The op amp operates linearly to within 30mV of the limits. The combination of narrow nonlinear range and low limiting offset allows the limiting voltages to be set within 100mV of the desired linear output range. A fast 2.4ns recovery from limiting ensures that overdrive signals will be transparent to the signal channel. Implementing the limiting function at the output, as opposed to the input, gives the specified limiting accuracy for any gain, and allows the OPA689 to be used in all standard op amp applications. Non-linear analog signal processing circuits will benefit from the OPA689’s sharp transition from linear operation to output limiting. The quick recovery time supports high speed applications. The OPA689 is available in an industry-standard pinout in PDIP-8 and SO-8 packages. For lower gain applications requiring output limiting with fast recovery, consider the OPA688. DETAIL OF LIMITED OUTPUT VOLTAGE LIMITED OUTPUT RESPONSE 2.10 2.5 1.5 1.0 VO VIN 0.5 0 –0.5 –1.0 –1.5 G = +6 VH = 2.0V VL = –2.0V 2.05 Input and Output Voltage (V) Input and Output Voltage (V) 2.0 2.00 1.95 VO 1.90 1.85 1.80 1.75 1.70 1.65 –2.0 1.60 –2.5 Time (50ns/div) Time (200ns/div) International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © SBOS076 1997 Burr-Brown Corporation PDS-1409D 1 OPA689 Printed in U.S.A. January, 2000 SPECIFICATIONS — VS = ±5V G = +6, RL = 500Ω, RF = 750Ω, VH = –VL = 2V, (Figure 1 for AC performance only), unless otherwise noted. OPA689U, P GUARANTEED(1) TYP PARAMETER AC PERFORMANCE (see Fig. 1) Small Signal Bandwidth Gain Bandwidth Product (G ≥ +20) Gain Peaking 0.1dB Gain Flatness Bandwidth Large Signal Bandwidth Step Response Slew Rate Rise/Fall Time Settling Time: 0.05% Spurious Free Dynamic Range Differential Gain Differential Phase Input Noise Density Voltage Noise Current Noise DC PERFORMANCE (VCM = 0V) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Drift Input Bias Current(3) Average Drift Input Offset Current Average Drift INPUT Common-Mode Rejection Ratio Common-Mode Input Range(4) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Range Current Output, Sourcing Sinking Closed-Loop Output Impedance POWER SUPPLY Operating Voltage, Specified Maximum Quiescent Current, Maximum Minimum Power Supply Rejection Ratio +PSR (Input Referred) OUTPUT VOLTAGE LIMITERS Default Limit Voltage Minimum Limiter Separation (VH – VL) Maximum Limit Voltage Limiter Input Bias Current Magnitude(5) Maximum Minimum Average Drift Limiter Input Impedance Limiter Feedthrough(6) DC Performance in Limit Mode Limiter Offset Voltage Op Amp Input Bias Current Shift(3) CONDITIONS +25°C +25°C 0°C to +70°C –40°C to +85°C UNITS VO < 0.5Vp-p G = +6 G = +12 G = –6 VO < 0.5Vp-p VO < 0.5Vp-p, G = +4 VO < 0.5Vp-p VO = 2Vp-p 280 90 220 720 8 110 290 220 — — 490 — — 185 210 — — 460 — — 175 200 — — 430 — — 170 MHz MHz MHz MHz dB MHz MHz Min Typ Typ Min Typ Typ Min B C C B C C B 2V Step 0.5V Step 2V Step f = 5MHz, VO = 2Vp-p NTSC, PAL, RL = 500Ω NTSC, PAL, RL = 500Ω 1600 1.2 7 61 0.02 0.01 1300 1.8 — 57 — — 1250 1.9 — 53 — — 950 2.4 — 48 — — V/µs ns ns dB % ° Min Max Typ Min Typ Typ B B C B C C f ≥ 1MHz f ≥ 1MHz 4.6 2.0 5.3 2.5 6.0 2.9 6.1 3.6 nV/√Hz pA/√Hz Max Max B B VO = ±0.5V 56 ±1 — +8 — ±0.3 — 50 ±12 — 48 ±6 ±14 ±13 –60 ±3 ±10 47 ±7 ±14 ±20 –90 ±4 ±10 dB mV µV/°C µA nA/°C µA nA/°C Min Max Max Max Max Max Max A A B A B A B 60 ±3.3 53 ±3.2 52 ±3.2 50 ±3.1 dB V Min Min A A 0.4 || 1 1 || 1 — — — — — — MΩ || pF MΩ || pF Typ Typ C C ±4.1 105 –85 0.8 ±3.9 ±3.9 85 –65 — ±3.8 80 –60 — V mA mA Ω Min Min Min Typ A A A C 17 14 — ±6 19 12.8 — ±6 20 11 V V mA mA Typ Max Max Min C A A A 65 58 57 55 dB Min A ±3.3 200 — ±3.0 200 ±4.3 ±3.0 200 ±4.3 ±2.9 200 ±4.3 V mV V Min Min Max A B B 54 54 — 2 || 1 –60 65 35 — — — 68 34 40 — — 70 31 45 — — µA µA nA/°C MΩ || pF dB Max Min Max Typ Typ A A B C C ±15 3 ±35 ±40 — ±40 — mV µA Max Typ A C Input Referred, VCM = ±0.5V VH = –VL = 4.3V RL ≥ 500Ω G = +4, f < 100kHz ±5 — 15.8 15.8 — — ±2 90 –70 — — ±6 +VS = 4.5V to 5.5V Limiter Pins Open VO = 0 f = 5MHz VIN = ±0.7V (VO – VH) or (VO – VL) ® OPA689 ±5 MIN/ TEST MAX LEVEL(2) 2 — SPECIFICATIONS — VS = ±5V (cont.) G = +6, RL = 500Ω, RF = 750Ω, VH = –VL = 2V, (Figure 1 for AC performance only), unless otherwise noted. OPA689U, P GUARANTEED(1) TYP PARAMETER OUTPUT VOLTAGE LIMITERS (CONT) AC Performance in Limit Mode Limiter Small Signal Bandwidth Limiter Slew Rate(7) Limited Step Response Overshoot Recovery Time Linearity Guardband(8) THERMAL CHARACTERISTICS Temperature Range Thermal Resistance P 8-Pin DIP U 8-Pin SO-8 CONDITIONS +25°C +25°C 0°C to +70°C –40°C to +85°C UNITS VIN = ±0.7V, VO < 0.02Vp-p 450 100 — — — — — — MHz V/µs Typ Typ C C VIN = 0 to ±0.7V Step VIN = ±0.7V to 0 Step f = 5MHz, VO = 2Vp-p 250 2.4 30 — 2.8 — — 3.0 — — 3.2 — mV ns mV Typ Max Typ C B C Specification: P, U –40 to +85 — — — °C Typ C 100 125 — — — — — — °C/W °C/W Typ Typ C C MIN/ TEST MAX LEVEL(2) NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25°C guaranteed specifications. Junction Temperature = Ambient Temperature + 23°C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (5) I VH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3 and Figures 1 and 7. (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V H (or VL) when VIN = 0. (7) VH slew rate conditions are: V IN = +0.7V, G = +6, VL = –2V, VH = step between 2V and 0V. VL slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 1MHz, VO = 2Vpp) centered between the limiter levels (VH and VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8). The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA689 SPECIFICATIONS — VS = +5V G = +6, RF = 750Ω, RL = 500Ω tied to VCM = 2.5V, VL = VCM –1.2V, VH = VCM +1.2V, (Figure 2 for AC performance only), unless otherwise noted. OPA689U, P GUARANTEED(1) TYP PARAMETER AC PERFORMANCE (see Fig. 2) Small Signal Bandwidth Gain Bandwidth Product (G ≥ +20) Gain Peaking 0.1dB Gain Flatness Bandwidth Large Signal Bandwidth Step Response Slew Rate Rise/Fall Time Settling Time: 0.05% Spurious Free Dynamic Range Input Noise Voltage Noise Density Current Noise Density DC PERFORMANCE Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Drift Input Bias Current(3) Average Drift Input Offset Current Average Drift INPUT Common-Mode Rejection Ratio Common-Mode Input Range(4) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Range Current Output, Sourcing Sinking Closed-Loop Output Impedance POWER SUPPLY Operating Voltage, Specified Maximum Quiescent Current, Maximum Minimum Power Supply Rejection Ratio +PSR (Input Referred) OUTPUT VOLTAGE LIMITERS Default Limiter Voltage Minimum Limiter Separation (VH – VL) Maximum Limit Voltage Limiter Input Bias Current Magnitude(5) Maximum Minimum Average Drift Limiter Input Impedance Limiter Isolation(6) DC Performance in Limit Mode Limiter Voltage Accuracy Op Amp Bias Current Shift(3) AC Performance in Limit Mode Limiter Small Signal Bandwidth Limiter Slew Rate(7) Limited Step Response Overshoot Recovery Time Linearity Guardband(8) CONDITIONS +25°C +25°C 0°C to +70°C –40°C to +85°C UNITS VO < 0.5Vp-p G = +6 G = +12 G = –6 VO < 0.5Vp-p VO < 0.5Vp-p, G = +4 VO < 0.5Vp-p VO = 2Vp-p 210 70 180 440 4 35 175 180 — — 330 — — 150 160 — — 310 — — 140 150 — — 300 — — 125 MHz MHz MHz MHz dB MHz MHz Min Typ Typ Min Typ Typ Min B C C B B C B 2V Step 0.5V Step 2V Step f = 5MHz, VO = 2Vp-p 1600 1.9 7 59 1300 2.1 — 55 1250 2.2 — 51 950 2.6 — 46 V/µs ns ns dB Min Max Typ Min B B C B f ≥ 1MHz f ≥ 1MHz 4.6 2.0 5.3 2.5 6.0 2.9 6.1 3.6 nV/√Hz pA/√Hz Max Max B B VO = ±0.5V 56 ±1 — +8 — ±0.3 — 50 ±12 — 48 ±6 ±14 ±13 –60 ±3 ±10 47 ±8 ±14 ±20 –90 ±4 ±10 dB mV µV/°C µA nA/°C µA nA/°C Min Max Max Max Max Max Max A A B A B A B 58 VCM ±0.8 51 VCM ±0.7 50 VCM ±0.7 48 VCM ±0.6 dB V Min Min A A 0.4 || 1 1 || 1 — — — — — — MΩ || pF MΩ || pF Typ Typ C C VCM ±1.6 70 –60 0.8 VCM ±1.4 60 –50 — VCM ±1.4 55 –45 — VCM ±1.3 50 –40 — V mA mA Ω Min Min Min Typ A A A C 5 — 13 13 — 12 15 11 — 12 15 10 — 12 16 9 V V mA mA Typ Max Max Min C A A A 65 — — — dB Typ C VCM ±0.9 200 — VCM ±0.6 200 VCM ±1.8 VCM ±0.6 200 VCM ±1.8 VCM ±0.6 200 VCM ±1.8 V mV V Min Min Max A B B 35 35 — 2 || 1 –60 65 0 — — — 75 0 30 — — 85 0 50 — — µA µA nA/°C MΩ || pF dB Max Min Max Typ Typ A A B C C ±15 5 ±35 — ±40 — ±40 — mV µA Max Typ A C VIN = ±0.4V, VO < 0.02Vp-p 300 20 — — — — — — MHz V/µs Typ Typ C C VIN = VCM to VCM ±0.4V Step VIN = VCM ±0.4V to VCM Step f = 5MHz, VO = 2Vp-p 55 15 30 — — — — — — — — — mV ns mV Typ Typ Typ C C C Input Referred, VCM ±0.5V VH = VCM + 1.8V, VL = VCM – 1.8V RL ≥ 500Ω G = +4, f < 100kHz — — ±2 VS = 4.5V to 5.5V Limiter Pins Open VO = 2.5V f = 5MHz VIN = VCM ±0.4V (VO – VH) or (VO – VL) ® OPA689 ±5 MIN/ TEST MAX LEVEL(2) 4 SPECIFICATIONS — VS = +5V (cont.) G = +6, RF = 750Ω, RL = 500Ω tied to VCM = 2.5V, VL = VCM –1.2V, VH = VCM +1.2V, (Figure 2 for AC performance only), unless otherwise noted. OPA689U, P GUARANTEED(1) TYP CONDITIONS +25°C +25°C 0°C to +70°C –40°C to +85°C UNITS Specification: P, U –40 to +85 — — — °C Typ C 100 125 — — — — — — °C/W °C/W Typ Typ C C PARAMETER THERMAL CHARACTERISTICS Temperature Range Thermal Resistance P 8-Pin DIP U 8-Pin SO-8 MIN/ TEST MAX LEVEL(2) NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25°C guaranteed specifications. Junction Temperature = Ambient Temperature + 23°C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (5) I VH (VH bias current) is negative, and IVL (VL bias current) is positive, under these conditions. See Note 3 and Figures 2 and 7. (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V H (or VL) when VIN = 0. (7) VH slew rate conditions are: VIN = VCM +0.4V, G = +6, VL = VCM –1.2V, VH = step between VCM +1.2V and VCM. VL slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 5MHz, VO = VCM ±1Vp-p) centered between the limiter levels (VH and VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8). ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY Supply Voltage ................................................................................. ±6.5V Internal Power Dissipation ........................... See Thermal Characteristics Input Voltage Range ............................................................................ ±VS Differential Input Voltage ..................................................................... ±VS Limiter Voltage Range ........................................................... ±(VS – 0.7V) Storage Temperature Range: P, U ................................ –40°C to +125°C Lead Temperature (DIP, soldering, 10s) ...................................... +300°C (SO-8, soldering, 3s) ...................................... +260°C Junction Temperature .................................................................... +175°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS Top View DIP-8, SO-8 NC 1 8 VH Inverting Input 2 7 +VS Non-Inverting Input 3 6 Output –VS 4 5 VL PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER OPA689P OPA689U DIP-8 SO-8 Surface Mount 006 182 –40°C to +85°C –40°C to +85°C OPA689P OPA689U " " " " " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA OPA689P OPA689U OPA689U/2K5 Rails Rails Tape and Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA689U/2K5” will get a single 2500-piece Tape and Reel. ® 5 OPA689 TYPICAL PERFORMANCE CURVES— VS = ±5V G = +6, RL = 500Ω, RF = 750Ω, VH = –VL = 2V, (Figure 1 for AC performance only), unless otherwise noted. INVERTING SMALL-SIGNAL FREQUENCY RESPONSE NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 9 3 0 –3 –6 –9 G = +12 –12 –15 0 –3 –9 G = –12 –12 –15 –21 –24 –21 1M 10M 100M 1G 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) LARGE-SIGNAL PULSE RESPONSE SMALL-SIGNAL PULSE RESPONSE 2.5 0.5 VO = 0.5Vp-p 0.4 VO = 2Vp-p 2.0 1.5 Output Voltage (V) 0.3 Output Voltage (V) G = –6 –6 –18 G = +20 –18 0.2 0.1 0 –0.1 –0.2 1.0 0.5 0 –0.5 –1.0 –0.3 –1.5 –0.4 –2.0 –2.5 –0.5 Time (5ns/div) Time (5ns/div) VH—LIMITED PULSE RESPONSE 2.5 VL—LIMITED PULSE RESPONSE 2.5 VO 2.0 2.0 Input and Output Voltages (V) Input and Output Voltages (V) G = –4 VO = 0.5Vp-p 3 G = +6 Normalized Gain (dB) Normalized Gain (dB) 6 G = +4 VO = 0.5Vp-p 6 1.5 1.0 VIN 0.5 0 –0.5 –1.0 VH = +2V G = +6 –1.5 1.5 1.0 0.5 0 –0.5 –1.0 –2.0 –2.5 –2.5 VO Time (20ns/div) ® OPA689 VIN –1.5 –2.0 Time (20ns/div) VL = –2V G = +6 6 TYPICAL PERFORMANCE CURVES— VS = ±5V (cont.) G = +6, RL = 500Ω, RF = 750Ω, VH = –VL = 2V, (Figure 1 for AC performance only), unless otherwise noted. HARMONIC DISTORTION NEAR LIMIT VOLTAGES 2nd and 3rd Harmonic Distortion (dBc) 2nd and 3rd Harmonic Distortion (dBc) HARMONIC DISTORTION vs FREQUENCY –40 VO = 2Vp-p RL = 500Ω –45 –50 HD2 –55 –60 –65 –70 HD3 –75 –80 –85 –90 1M 10M –40 VO = 0VDC ±1Vp f1 = 5MHz RL = 500Ω –45 –50 –55 HD2 –60 –65 –70 –75 –80 HD3 –85 –90 0.9 20M 1.0 1.1 1.2 1.3 Frequency (Hz) 2ND HARMONIC DISTORTION vs OUTPUT SWING 1.7 1.8 1.9 2.0 3RD HARMONIC DISTORTION vs OUTPUT SWING –40 RL = 500Ω –45 f1 = 10MHz –55 –60 –65 f1 = 5MHz –70 f1 = 2MHz –75 –80 RL = 500Ω –45 f1 = 20MHz –50 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) 1.5 1.6 ± Limit Voltage (V) –40 f1 = 1MHz –85 –50 f1 = 20MHz –55 f1 = 10MHz –60 –65 f1 = 5MHz –70 f1 = 2MHz –75 –80 f1 = 1MHz –85 –90 –90 0.1 1.0 5.0 0.1 Output Swing (Vp-p) 1.0 5.0 Output Swing (Vp-p) LARGE SIGNAL FREQUENCY RESPONSE HARMONIC DISTORTION vs LOAD RESISTANCE 21.6 –40 VO = 2Vp-p f1 = 5MHz –45 –50 2Vp-p 15.6 HD2 –55 12.6 –60 9.6 –65 G = +6 18.6 Gain (dB) 2nd and 3rd Harmonic Distortion (dBc) 1.4 HD3 –70 ≤ 0.5Vp-p 6.6 3.6 –75 0.6 –80 –2.4 –85 –5.4 –8.4 –90 50 100 0.1 1000 10M 100M 1G Frequency (Hz) Load Resistance (Ω) ® 7 OPA689 TYPICAL PERFORMANCE CURVES— VS = ±5V (cont.) G = +6, RL = 500Ω, RF = 750Ω, VH = –VL = 2V, (Figure 1 for AC performance only), unless otherwise noted. FREQUENCY RESPONSE vs CAPACITIVE LOAD RS vs CAPACITIVE LOAD 21.6 45 18.6 Gain to Capacitive Load (dB) 50 40 RS (Ω) 35 30 25 20 15 10 6.6 125Ω VIN RS VO OPA689 0.6 750Ω 150Ω –8.4 1000 1kΩ is optional 0.1 10M Capacitive Load (pF) 40 –60 Phase 30 –90 20 –120 VO = 0.5Vp-p 10 –150 0 –180 –10 –210 –20 –240 1G 10M 100M Input Voltage Noise Density (nV/√Hz) Input Current Noise Density (pA/√Hz) –30 Gain Open-Loop Phase (deg) 50 Open-Loop Gain (dB) 100 0 1M Voltage Noise 10 4.6nV/√Hz Current Noise 2.0pA/√Hz 1 100 LIMITER SMALL-SIGNAL FREQUENCY RESPONSE 10k 100k 1M 10M LIMITER FEEDTHROUGH 6 –30 VO = 0.02Vp-p 3 –35 0 –40 –3 –45 –6 Feedthrough (dB) Limiter Gain (dB) 1k Frequency (Hz) Frequency (Hz) –9 1G INPUT NOISE DENSITY OPEN-LOOP FREQUENCY RESPONSE 100k 100M Frequency (Hz) 60 10k CL 1kΩ –2.4 –5.4 100 CL = 1000pF 9.6 3.6 CL = 10pF CL = 100pF 12.6 0 10 CL = 0 15.6 5 1 VO = 0.5Vp-p VH = 0.02Vp-p + 2.0VDC 125Ω 0.7VDC 8 –12 VO –15 750Ω –18 –50 VH = 0.02Vp-p + 2VDC 125Ω –55 8 –60 VO –65 750Ω –70 150Ω –21 150Ω –75 –24 –80 1M 10M 100M 1G 1M Frequency (Hz) ® OPA689 10M Frequency (Hz) 8 50M TYPICAL PERFORMANCE CURVES— VS = ±5V (cont.) G = +6, RL = 500Ω, RF = 750Ω, VH = –VL = 2V, (Figure 1 for AC performance only), unless otherwise noted. CLOSED-LOOP OUTPUT IMPEDANCE LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE 100 100 Maximum Over Temperature 75 Limter Input Bias Current (µA) Output Impedance (Ω) G = +4 VO = 0.5Vp-p 10 1 50 25 Minimum Over Temperature 0 –25 Limiter Headroom = +VS – VH = VL – (–VS) Current = IVH or –IVL –50 –75 0.1 100k 1M 10M 100M –100 1G 0.0 0.5 1.0 Frequency (Hz) Output Current, Sourcing 160 Supply Current 14 140 | Output Current, Sinking | 12 PSR and CMR, Input Referred (dB) 180 120 10 0 25 3.0 3.5 4.0 4.5 5.0 100 Output Current (mA) 18 50 90 PSR– 85 PSRR 80 75 PSR+ 70 65 CMRR 60 55 50 100 100 75 95 –50 –25 0 25 50 75 100 Ambient Temperature (°C) Ambient Temperature (°C) VOLTAGE RANGES vs TEMPERATURE 5.0 VH = –VL = 4.3V ± Voltage Range (V) Supply Current (mA) 200 –25 2.5 PSR AND CMR vs TEMPERATURE SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE –50 2.0 Limiter Headroom (V) 20 16 1.5 4.5 Output Voltage Range 4.0 3.5 Common-Mode Input Range 3.0 –50 –25 0 25 50 75 100 Ambient Temperature (°C) ® 9 OPA689 TYPICAL PERFORMANCE CURVES— VS = +5V G = +6, RF = 402Ω, RL = 500Ω tied to VCM = 2.5V, VL = VCM –1.2V, VH = VCM +1.2V, (Figure 2 for AC performance only), unless otherwise noted. NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 9 6 VO = 0.5Vp-p VO = 0.5Vp-p 3 3 0 G = +4 G = +6 –3 Normalized Gain (dB) Normalized Gain (dB) 6 –6 G = +20 –9 G = +12 –12 –3 G = –12 –6 G = –6 –9 –12 –15 –15 –18 –18 –21 –21 G = –4 0 –24 1M 10M 100M 1G 1M 10M Frequency (Hz) LARGE-SIGNAL FREQUENCY RESPONSE 18.6 4.5 ≤ 0.5Vp-p Input and Output Voltages (V) 5.0 15.6 Gain (dB) 1G VH AND VH—LIMITED PULSE RESPONSE 21.6 12.6 100M Frequency (Hz) 2Vp-p 9.6 6.6 3.6 0.6 –2.4 –5.4 VH = VCM +1.2V VL = VCM –1.2V 4.0 VO 3.5 3.0 VIN 2.5 2.0 1.5 VIN VCM = 2.5V VO 1.0 0.5 –8.4 0 0.1 10M 100M 1G Time (20ns/div) Frequency (Hz) HARMONIC DISTORTION NEAR LIMIT VOLTAGES 2nd and 3rd Harmonic Distortion (dBc) 2nd and 3rd Harmonic Distortion (dBc) HARMONIC DISTORTION vs FREQUENCY –40 VO = 2Vp-p RL = 500Ω –45 –50 HD2 –55 –60 HD3 –65 –70 –75 –80 –85 –40 VO = 2.5VDC ±1Vp f1 = 5MHz RL = 500Ω –45 –50 HD2 –55 –60 –65 –70 HD3 –75 –80 –85 –90 –90 1M 10M 0.9 20M ® OPA689 1.0 1.1 1.2 1.3 1.4 1.5 | Limit Voltages – 2.5VDC | Frequency (Hz) 10 1.6 1.7 1.8 TYPICAL APPLICATIONS characterization of the OPA689, with a 50Ω source, which it matches, and a 500Ω load. The power supply bypass capacitors are shown explicitly in Figures 1 and 2, but will be assumed in the other figures. The limiter voltages (VH and VL ) and their bias currents (IVH and IVL ) have the polarities shown. Notice that the single supply circuit can use 3 resistors to set VH and VL, where the dual supply circuit usually uses 4 to reference the limit voltages to ground. DUAL SUPPLY, NON-INVERTING AMPLIFIER Figure 1 shows a non-inverting gain amplifier for dual supply operation. This circuit was used for AC characterization of the OPA689, with a 50Ω source, which it matches, and a 500Ω load. The power supply bypass capacitors are shown explicitly in Figures 1 and 2, but will be assumed in the other figures. The limiter voltages (VH and VL) and their bias currents (IVH and IVL) have the polarities shown. LOW DISTORTION, ADC INPUT DRIVER SINGLE SUPPLY, NON-INVERTING AMPLIFIER The circuit in Figure 3 shows an inverting, low distortion ADC driver that operates on single supply. The converter’s internal references bias the op amp input. The 4.0pF and 18pF capacitors form a compensation network that allows Figure 2 shows an AC coupled, non-inverting gain amplifier for single supply operation. This circuit was used for AC 3.01kΩ 1.91kΩ +VS = +5V + 2.2µF VS = +5V 0.1µF 0.1µF + VH = +2V 100Ω 8 49.9Ω OPA689 2 VH = 3.7V IVH 1.50kΩ 6 0.1µF VO 5 IVH 7 3 VIN 53.6Ω 1.50kΩ 0.1µF 6 OPA689 2 500Ω IVL RF 750Ω 0.1µF VL = –2V + VO 5 4 0.1µF 976Ω 8 500Ω IVL 4 RF 750Ω RG 150Ω 523Ω 0.1µF 7 3 VIN 0.1µF 2.2µF 0.1µF RG 150Ω 2.2µF 3.01kΩ 1.91kΩ VL = 1.3V 523Ω 0.1µF –VS = –5V FIGURE 1. DC-Coupled, Dual Supply Amplifier. FIGURE 2. AC-Coupled, Single Supply Amplifier. VS = +5V 787Ω 4.0pF 0.1µF 0.1µF VH = +3.6V 750Ω 374Ω VS = +5V 100Ω VIN +3.5V VS = +5V 18pF REFT 2 RSEL +VS 7 8 OPA689 6 24.9Ω 5 3 ADS822 10-Bit 40MSPS IN 100pF 10-Bit Data 4 REFB 0.1µF 1.40kΩ INT/EXT GND +1.5V 100Ω 0.1µF 1.40kΩ VL = +1.4V +2.5V 787Ω FIGURE 3. Low Distortion, Limiting ADC Input Driver. ® 11 OPA689 the OPA689 to have a flat frequency response at a gain of – 2. This increases the loop gain of the op amp feedback network, which reduces the distortion products below their specified values. CF 1.0pF 4.32kΩ λ VO PRECISION HALF WAVE RECTIFIER CD 5.0pF ID Figure 4 shows a half wave rectifier with outstanding precision and speed. VH will default to a voltage between 3.1 and 3.8V if left open, while the negative limit is set to ground. +VS = +5V 3 7 NC –VB 8 OPA689 4 +VS = +5V 0.1µF 6 5 2 NC 4.32kΩ –VS = –5V 124Ω 7 2 NC VIN 8 OPA689 FIGURE 6. Transimpedance Amplifier. 6 VO 5 3 DESIGN-IN TOOLS 4 150Ω APPLICATIONS SUPPORT The Burr-Brown Applications Department is available for design assistance at phone number 1-800-548-6132 (US/Canada only). The Burr-Brown Internet web page (http://www.burr-brown.com) has the latest data sheets and other design aids. 750Ω –VS = –5V FIGURE 4. Precision Half Wave Rectifier. VERY HIGH SPEED COMPARATOR DEMONSTRATION BOARDS Figure 5 shows a very high speed comparator with hysterisis. The output level are precisely defined, and the recovery time is exceptional. The output voltage swings between 0.5V and 3.5V to provide a logic level output that switches as VIN crosses VREF. Two PC boards are available to assist in the initial evaluation of circuit performance of the OPA689 in both package styles. These will be available as an unpopulated PCB with descriptive documentation. See the board literature for more information. The summary information for these boards is shown below: +VS = +5V 100Ω VO 3 PRODUCT PACKAGE BOARD PART NUMBER OPA689P OPA689U 8-Pin DIP 8-Pin SO-8 DEM-OPA68xP DEM-OPA68xU 604Ω 2.00kΩ 0.1µF 7 LITERATURE REQUEST NUMBER MKT-350 MKT-351 8 95.3Ω VIN OPA689 2 6 1.21kΩ Contact the Burr-Brown Applications Department for availability of these boards. 0.1µF 5 4 200kΩ SPICE MODELS Computer simulation of circuit performance using SPICE is often useful when analyzing analog circuit or system performance. This is particularly true for high speed amplifier circuits where parasitic capacitance and inductance can have a major effect on frequency response. –VS = –5V FIGURE 5. Very High Speed Comparator. TRANSIMPEDANCE AMPLIFIER SPICE models are available through the Burr-Brown web site (www.burr-brown.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion, temperature effects, or different gain and phase characteristics. These models do not distinquish between the AC performance of different package types. Figure 6 shows a transimpedance amplifier that has exceptional overdrive characteristics. The feedback capacitor (CF) stabilizes the circuit for the assumed diode capacitance (CD). ® OPA689 12 OPERATING INFORMATION e) Choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel capacitance. Good metal film or surface mount resistors have approximately 0.2pF parasitic parallel capacitance. For resistors > 1.5kΩ, this adds a pole and/or zero below 500MHz. THEORY OF OPERATION The OPA689 is a voltage feedback op amp that is stable for gains ≥ +4. The output voltage is limited to a range set by the limiter pins (5 and 8). When the input tries to overdrive the output, the limiters take control of the output buffer. This avoids saturating any parts in the signal path, gives quick overdrive recovery, and gives consistent limiter accuracy for any gain. Make sure that the output loading is not too heavy. The recommended 750Ω feedback resistor is a good starting point in your design. f) Use short direct traces to other wideband devices on the board. Short traces act as a lumped capacitive load. Wide traces (50 to 100 mils) should be used. Estimate the total capacitive load at the output, and use the series isolation resistor recommended in the RS vs Capacitive Load plot. Parasitic loads < 2pF may not need the isolation resistor. This part is de-compensated (stable for gains ≥ +4). This gives greater bandwidth, higher slew rate, and lower noise than the unity gain stable companion part OPA688. The limiters have a very sharp transition from the linear region of operation to output limiting. This allows the limiter voltages to be set very near (<100 mV) the desired signal range. The distortion performance is also very good near the limiter voltages. g) When long traces are necessary, use transmission line design techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω transmission line is not required on board—a higher characteristic impedance will help reduce output loading. Use a matching series resistor at the output of the op amp to drive a transmission line, and a matched load resistor at the other end to make the line appear as a resistor. If the 6dB of attenuation that the matched load produces is not acceptable, and the line is not too long, use the series resistor at the source only. This will isolate the op amp output from the reactive load presented by the line, but the frequency response will be degraded. CIRCUIT LAYOUT Achieving optimum performance with the high frequency OPA689 requires careful attention to layout design and component selection. Recommended PCB layout techniques and component selection criteria are: a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Open a window in the ground and power planes around the signal I/O pins, and leave the ground and power planes unbroken elsewhere. Multiple destination devices are best handled as separate transmission lines, each with its own series source and shunt load terminations. Any parasitic impedances acting on the terminating resistors will alter the transmission line match, and can cause unwanted signal reflections and reactive loading. b) Provide a high quality power supply. Use linear regulators, ground plane, and power planes, to provide power. Place high frequency 0.1µF decoupling capacitors < 0.2" away from each power supply pin. Use wide, short traces to connect to these capacitors to the ground and power planes. Also use larger (2.2µF to 6.8µF) high frequency decoupling capacitors to bypass lower frequencies. They may be somewhat further from the device, and be shared among several adjacent devices. h) Do not use sockets for high speed parts like the OPA689. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network. Best results are obtained by soldering the part onto the board. If socketing for DIP prototypes is desired, high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results. c) Place external components close to the OPA689. This minimizes inductance, ground loops, transmission line effects and propagation delay problems. Be extra careful with the feedback (RF), input and output resistors. POWER SUPPLIES d) Use high frequency components to minimize parasitic elements. Resistors should be a very low reactance type. Surface mount resistors work best and allow a tighter layout. Metal film or carbon composition axially-leaded resistors can also provide good performance when their leads are as short as possible. Never use wire-wound resistors for high frequency applications. Remember that most potentiometers have large parasitic capacitances and inductances. The OPA689 is nominally specified for operation using either ±5V supplies or a single +5V supply. The maximum specified total supply voltage of 13V allows reasonable tolerances on the supplies. Higher supply voltages can break down internal junctions, possibly leading to catastrophic failure. Single supply operation is possible as long as common mode voltage constraints are observed. The common mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow design of non-standard or single supply operation circuits. Figure 2 shows one approach to single-supply operation. Multilayer ceramic chip capacitors work best and take up little space. Monolithic ceramic capacitors also work very well. Use RF type capacitors with low ESR and ESL. The large power pin bypass capacitors (2.2µF to 6.8µF) should be tantalum for better high frequency and pulse performance. ® 13 OPA689 ESD PROTECTION When the limiter voltages need to be within 2.1V of the supplies (VL ≤ –VS + 2.1V or VH ≥ +VS – 2.1V), use low impedance voltage sources to set VH and VL to minimize errors due to bias current uncertainty. This will typically be the case for single supply operation (VS = +5V). Figure 2 runs 2.5mA through the resistive divider that sets VH and VL. This keeps errors due to IVH and IVL < ±1% of the target limit voltages. ESD damage is known to damage MOSFET devices, but any semiconductor device is vulnerable to ESD damage. This is particularly true for very high speed, fine geometry processes. ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, ESD handling precautions are required when handling the OPA689. The limiters’ DC accuracy depends on attention to detail. The two dominant error sources can be improved as follows: • Power supplies, when used to drive resistive dividers that set VH and VL, can contribute large errors (e.g., (5%). Using a more accurate source, or bypassing pins 5 and 8 with good capacitors, will improve limiter PSRR. OUTPUT LIMITERS The output voltage is linearly dependent on the input(s) when it is between the limiter voltages VH (pin 8) and VL (pin 5). When the output tries to exceed VH or VL, the corresponding limiter buffer takes control of the output voltage and holds it at VH or VL. • The resistor tolerances in the resistive divider can also dominate. Use 1% resistors. Because the limiters act on the output, their accuracy does not change with gain. The transition from the linear region of operation to output limiting is sharp—the desired output signal can safely come to within 30mV of VH or VL. Distortion performance is also good over the same range. Other error sources also contribute, but should have little impact on the limiters’ DC accuracy: The limiter voltages can be set to within 0.7V of the supplies (VL ≥ –VS + 0.7V, VH ≤ +VS – 0.7V). They must also be at least 200mV apart (VH – VL ≥ 0.2V). • Consider the signal path DC errors as contributing to the uncertainty in the useable output range. • Reduce offsets caused by the Limiter Input Bias Currents. Select the resistors in the resistive divider(s) as described above. • The Limiter Offset Voltage only slightly degrades the limiter accuracy. When pins 5 and 8 are left open, VH and VL go to the Default Voltage Limit; the minimum values are in the spec table. Looking at Figure 7 for the zero bias current case will show the expected range of (VS – default limit voltages) = headroom). Figure 8 shows how the limiters affect distortion performance. Virtually no degradation in linearity is observed for output voltages swinging right up to the limiter voltages. When the limiter voltages are more than 2.1V from the supplies (VL ≥ –VS + 2.1V or VH ≤ +VS – 2.1V), you can use simple resistor dividers to set V H and VL (see Figure 1). Make sure you include the Limiter Input Bias Currents (Figure 7) in the calculations (i.e., IVL ≈ –50µA out of pin 5, and IVH ≈ +50µA out of pin 8). For good limiter voltage accuracy, run at least 1mA quiescent bias current through these resistors. 2nd and 3rd Harmonic Distortion (dBc) HARMONIC DISTORTION NEAR LIMIT VOLTAGES LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE 100 Limter Input Bias Current (µA) Maximum Over Temperature 75 50 –40 VO = 0VDC ±1Vp f1 = 5MHz RL = 500Ω –45 –50 –55 HD2 –60 –65 –70 –75 –80 HD3 –85 –90 0.9 25 1.0 1.1 1.2 1.3 1.4 1.5 1.6 ± Limit Voltage (V) Minimum Over Temperature 0 –25 –75 –100 FIGURE 8. Linearity Guardband. Limiter Headroom = +VS – VH = VL – (–VS) Current = IVH or –IVL –50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Limiter Headroom (V) FIGURE 7. Limiter Bias Current vs Limiter Voltage. ® OPA689 14 1.7 1.8 1.9 2.0 OFFSET VOLTAGE ADJUSTMENT The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and the additional power dissipated in the output stage (PDL) while delivering load power. PDQ is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signals and loads. For a grounded resistive load, and equal bipolar supplies, it is at a maximum when the output is at 1/2 either supply voltage. In this condition, PDL = VS2/(4RL) where RL includes the feedback network loading. Note that it is the power in the output stage, and not in the load, that determines internal power dissipation. The circuit in Figure 9 allows offset adjustment without degrading offset drift with temperature. Use this circuit with caution since power supply noise can inadvertently couple into the op amp. Remember that additional offset errors can be created by the amplifier’s input bias currents. Whenever possible, match the resistance seen by both DC Input Bias Currents by using R3. This minimizes the output offset voltage caused by the Input Bias Currents. +VS The operating junction temperature is: TJ = TA + PD θJA, where TA is the ambient temperature. R2 For example, the maximum TJ for a OPA689U with G = +6, RFB = 750Ω, RL = 100Ω, and ±VS = ±5V at the maximum TA = +85°C is calculated this way: RTRIM 47kΩ OPA689 VO P DQ = (10V • 20mA ) = 200mW –VS 0.1µF R1 P DL = R3 = R1 || R2 ( 5V )2 4 • (100Ω || 850Ω ) P D = 200mW + 70mW = 270mW T J = 85° C + 270mW •125° C/ W = 119° C VIN or Ground CAPACITIVE LOADS NOTES: (1) R3 is optional and minimizes output offset due to input bias currents. (2) Set R1 << RTRIM. Capacitive loads, such as flash A/D converters, will decrease the amplifier’s phase margin, which may cause peaking or oscillations. Capacitive loads ≥ 1pF should be isolated by connecting a small resistor in series with the output as shown in Figure 10. Increasing the gain from +6 will improve the capacitive drive capabilities due to increased phase margin. FIGURE 9. Offset Voltage Trim. OUTPUT DRIVE The OPA689 has been optimized to drive 500Ω loads, such as A/D converters. It still performs very well driving 100Ω loads. This makes the OPA689 an ideal choice for a wide range of high frequency applications. RISO Many high speed applications, such as driving A/D converters, require op amps with low output impedance. As shown in the Output Impedance vs Frequency performance curve, the OPA689 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain decreases with frequency. VO OPA689 RL CL RL is optional FIGURE 10. Driving Capacitive Loads. THERMAL CONSIDERATIONS The OPA689 will not require heat-sinking under most operating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. In general, capacitive loads should be minimized for optimum high frequency performance. The capacitance of coax cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable, or transmission line, is terminated in its characteristic impedance. ® 15 OPA689 FREQUENCY RESPONSE COMPENSATION recommended RS in the RS vs Capacitive Load plot. Extremely fine scale settling (0.01%) requires close attention to ground return current in the supply decoupling capacitors. The OPA689 is internally compensated to be stable at a gain of +4, and has a nominal phase margin of 60° at a gain of +6. Phase margin and peaking improve at higher gains. Recall that an inverting gain of –5 is equivalent to a gain of +6 for bandwidth purposes (i.e., noise gain = 6). The pulse settling characteristics when recovering from overdrive are very good. Standard external compensation techniques work with this device. For example, in the inverting configuration, the bandwidth may be limited without modifying the inverting gain by placing a series RC network to ground on the inverting node. This has the effect of increasing the noise gain at high frequencies, which limits the bandwidth. DISTORTION The OPA689’s distortion performance is specified for a 500Ω load, such as an A/D converter. Driving loads with smaller resistance will increase the distortion as illustrated in Figure 11. Remember to include the feedback network in the load resistance calculations. To maintain a large bandwidth at high gains, cascade several op amps. In applications where a large feedback resistor is required, such as photodiode transimpedance amplifier, the parasitic capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this effect, connect a small capacitor in parallel with the feedback resistor. The bandwidth will be limited by the pole that the feedback resistor and this capacitor create. In other high gain applications, use a three resistor “Tee” network to reduce the RC time constants set by the parasitic capacitances. Be careful to not increase the noise generated by this feedback network too much. 2nd and 3rd Harmonic Distortion (dBc) HARMONIC DISTORTION vs LOAD RESISTANCE PULSE SETTLING TIME The OPA689 is capable of an extremely fast settling time in response to a pulse input. Frequency response flatness and phase linearity are needed to obtain the best settling times. For capacitive loads, such as an A/D converter, use the VO = 2Vp-p f1 = 5MHz –45 –50 HD2 –55 –60 –65 HD3 –70 –75 –80 –85 –90 50 100 1000 Load Resistance (Ω) FIGURE 11. 5MHz Harmonic Distortion vs Load Resistance. ® OPA689 –40 16 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. 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