TI OPA698M

OPA698M
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SGLS287A – MAY 2005 – REVISED MARCH 2006
UNITY-GAIN STABLE WIDEBAND VOLTAGE LIMITING AMPLIFIER
FEATURES
•
•
•
•
•
•
•
JD PACKAGE
(TOP VIEW)
High Linearity Near Limiting
Fast Recovery from Overdrive: 1 ns
Limiting Voltage Accuracy: ±15 mV
-3-dB Bandwidth (G = +1): 450 MHz
Slew Rate: 1100 V/ms
±5-V and 5-V Supply Operation
Unity Gain Version of the OPA699
NC
INVERTING INPUT
NONINVERTING INPUT
-V S
1
8
2
7
3
6
4
5
VH
+VS
OUTPUT
VL
NC - No internal connection
P0013-01
APPLICATIONS
•
•
•
•
•
•
•
•
Fast Limiting ADC Input Buffers
CCD Pixel Clock Stripping
Video Sync Stripping
HF Mixers
IF Limiting Amplifiers
AM Signal Generation
Non-Linear Analog Signal Processing
OPA688M Replacement
DESCRIPTION
The OPA698 is a wideband, unity gain stable voltage-feedback op amp that offers bipolar output voltage limiting.
Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. This new
output limiting architecture holds the limiter offset error to ±15 mV. The op amp operates linearly to within 30 mV
of the output limit voltages.
The combination of narrow nonlinear range and low limiting offset allows the limiting voltages to be set within
100 mV of the desired linear output range. A fast 1-ns recovery from limiting ensures that overdrive signals will
be transparent to the signal channel. Implementing the limiting function at the output, as opposed to the input,
gives the specified limiting accuracy for any gain and allows the OPA698 to be used in all standard op amp
applications.
Non-linear analog signal processing benefits from the ability of the OPA698 to sharply transition from linear
operation to output limiting. The quick recovery time supports high-speed applications.
The OPA698M is available in an industry standard pinout CDIP-8 package. For higher gain or transimpedance
applications requiring output limiting with fast recovery, consider the OPA699M.
ORDERING INFORMATION (1)
TA
–55°C to 125°C
(1)
PACKAGE
CDIP – JD
Tube
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
OPA698MJD
OPA698MJD
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
OPA698M
www.ti.com
SGLS287A – MAY 2005 – REVISED MARCH 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Power supply
±6.5 V
VICM
Common-mode input voltage
±VS
VID
Differential input voltage
±VS
Limiter voltage range
±(VS - 0.7 V)
TA
Operating free-air temperature range
-55°C to 125°C
Tstg
Storage temperature range
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
TJ
Junction temperature
θJC
Package thermal impedance (2) (JD Package)
(1)
(2)
300°C
150°C
14.5°C/W
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The package thermal impedance is measured per MIL-STD-883, Method 1012.1.
RECOMMENDED OPERATING CONDITIONS
MIN
Operating voltage
Split-rail operation
Single-supply operation
Operating free-air temperature
NOM
MAX
±5
±6
5
12
–55
UNIT
V
125
°C
MAX
UNIT
ELECTRICAL CHARACTERISTICS
VS = ±5 V, VICM = 0 V, RL = 500 Ω, limiter pins open (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
AC PERFORMANCE (see Figure 47)
Small signal bandwidth
VO < 0.2 Vp-p, G = +1, RF = 25 Ω
450
VO < 0.2 Vp-p, G = +2
215
MHz
VO < 0.2 Vp-p, G = –1
215
Gain-bandwidth product (G ≥ 5)
VO < 0.2 Vp-p
250
MHz
Bandwidth for 0.1-dB gain flatness
VO = 0.2 V
30
MHz
Gain peaking
VO < 0.2 Vp-p, G = +1, RF = 25 Ω
Large signal bandwidth
VO = 4 Vp-p, VH = –VL = 2.5 V
Slew rate
4 V step, VH = –VL = 2.5 V
Rise and fall time
0.2 V step
Settling time to 0.05%
2 V step
Second harmonic distortion
5
dB
160
MHz
1100
V/µs
1.6
ns
8
ns
VO = 2 Vp-p, f = 5 MHz
–74
dB
Third harmonic distortion
VO = 2 Vp-p, f = 5 MHz
–87
dB
Differential gain
RL = 500 Ω, NTSC, PAL
0.012%
Differential phase
RL = 500 Ω, NTSC, PAL
0.008
Input noise, voltage noise density
f ≥ 1 MHz
5.6
nV/√Hz
Input noise, current noise density
f ≥ 1 MHz
2.2
pA/√Hz
(1)
2
All typical limits are at TA = 25°C unless otherwise specified.
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SGLS287A – MAY 2005 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)
VS = ±5 V, VICM = 0 V, RL = 500 Ω, limiter pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
TA = 25°C
52
58
TA = Full range
43
MAX
UNIT
DC PERFORMANCE
Open-loop voltage gain (AVOL)
VO = ±0.5 V
TA = 25°C
Input offset voltage (VIO)
±2
TA = Full range
±3
TA = Full range
mV
±10
µA
±18
TA = 25°C
Input offset current (IIO)
±8
±12
TA = 25°C
Input bias current (IIB) (2)
dB
±0.3
TA = Full range
±3
µA
±4
INPUT
Common-mode rejection ratio (CMRR)
VICM = ±0.5 V, Input referred
Common-mode input voltage range (VICR) (3)
TA = 25°C
52
TA = Full range
47
TA = 25°C
±3.2
TA = Full range
±3.1
Input impedance, differential mode
Input impedance, common mode
58
dB
±3.3
MΩ
pF
0.32
1
MΩ
pF
3.5
1
MΩ
pF
OUTPUT
Output voltage range (VOH, VOL)
VH = 4.3 V, VL = –4.3 V,
RL≥ 500 Ω
TA = 25°C
±3.9
TA = Full range
±3.7
Current output, sourcing (IOH)
VH = 4.3 V, VL = –4.3 V,
RL = 20 Ω
TA = 25°C
110
TA = Full range
100
Current output, sinking (IOL)
VH = 4.3 V, VL = –4.3 V,
RL = 20 Ω
TA = 25°C
–90
TA = Full range
–80
Closed-loop output impedance
G = +1, RF = 25 Ω, f < 100 kHz
±4
V
165
mA
–130
mA
Ω
0.2
POWER SUPPLY
Operating voltage (VS)
TA = 25°C
Quiescent current (IS)
Power supply rejection ratio (PSRR)
TA = Full range
Input referred,
VS = ±4.5 V to ±5.5 V
15
±5
±6
15.5
16
13.5
TA = 25°C
65
TA = Full range
60
18
V
mA
76
dB
dB
OUTPUT VOLTAGE LIMITERS (pins 5 and 8)
Default output limited voltage
Limiter pins open
Limiter output offset voltage
(VO – VH) or (VO – VL)
Limiter input bias current magnitude (4)
VO = 0 V
TA = 25°C
TA = Full range
±3.3
TA = Full range
TA = 25°C
40
TA = Full range
35
±15
±50
55
65
f = 5 MHz
mV
µA
70
MΩ
pF
–68
Maximum limiter voltage
dB
±4.3
Minimum limiter voltage separation
400
Op amp bias current shift (2)
(2)
(3)
(4)
(5)
V
3.4
1
Limiter input impedance
Limiter feedthrough (5)
±3.6
±3
V
mV
3
µA
Current is considered positive out of node.
CMIR tested as < 3-dB degradation from minimum CMRR at specified limits.
IVH (VH bias current) is positive and IVL (VL bias current) is negative under these conditions. See Note 2, Figure 47 and Figure 66.
Limiter feedthrough is the ratio of the output magnitude to the sine wave added to VH (or VL) when VIN = 0.
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SGLS287A – MAY 2005 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)
VS = ±5 V, VICM = 0 V, RL = 500 Ω, limiter pins open (unless otherwise noted)
PARAMETER
Limiter small signal bandwidth
TEST CONDITIONS
MIN
VI = ±2 V, VO < 0.02 Vp-p
Limiter slew rate (6)
Limiter step response, overshoot
VI = ±2 V
Limiter step response, recovery time
VI = ±2 V
Linearity guardband (7)
VO = 2 Vp-p, f = 5 MHz
(6)
(7)
TYP
MAX
UNIT
600
MHz
125
V/µs
250
mV
1
ns
30
mV
VH slew rate conditions are: VIN = +2 V, G = +2, VL = -2 V, VH = step between 2 V and 0 V. VL slew rate conditions are similar.
Linearity Guardband is defined for an output sinusoid (f = 5 MHz, VO = 0 VDC ±1 VP-P) centered between the limiter levels (VH and VL).
It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3 dB (see Figure 67).
ELECTRICAL CHARACTERISTICS
VS = 5 V, VICM = 2.5 V, RL = 500 Ω, limiter pins open (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE (see Figure 48)
VO < 0.2 Vp-p, G = +1, RF = 25 Ω
375
VO < 0.2 Vp-p, G = +2
200
VO < 0.2 Vp-p, G = –1
200
Gain-bandwidth product (G ≥ +5)
VO < 0.2 Vp-p
230
Gain peaking
VO < 0.2 Vp-p, G = +1, RF = 25 Ω
Bandwidth for 0.1-dB gain flatness
VO < 0.2 Vp-p
Large signal bandwidth
VO = 2 Vp-p
Slew rate
2 V step
820
V/µs
Rise and fall time
0.2 V step
1.9
ns
Settling time to 0.05%
1 V step
12
ns
Spurious free dynamic range
VO = 2 Vp-p, f = 5 MHz
64
dB
Input noise, voltage noise density
f > 1 MHz
5.7
nV/√Hz
Input noise, current noise density
f > 1 MHz
2.3
pA/√Hz
Small signal bandwidth
MHz
MHz
7
dB
30
MHz
200
MHz
DC PERFORMANCE
Open-loop voltage gain (AVOL)
VO = ±0.4 V
TA = 25°C
52
TA = Full range
43
TA = 25°C
Input offset voltage (VIO)
57
±4
TA = Full range
±3
TA = Full range
±10
±15
TA = 25°C
Input offset current (IIO)
±8
±12
TA = 25°C
Input bias current (IIB) (2)
dB
±0.4
TA = Full range
±3
±4
mV
µA
µA
INPUT
Common-mode rejection ratio (CMRR)
VICM = ±0.5 V, Input referred
Common-mode input voltage range
(VICR) (3)
TA = 25°C
50
TA = Full range
45
TA = 25°C
VICM
±0.7
TA = Full range
VICM
±0.6
4
VICM
±0.8
0.32
1
Input impedance, differential mode
(1)
(2)
(3)
57
All typical limits are at TA = 25°C unless otherwise specified.
Current is considered positive out of node.
CMIR tested as < 3-dB degradation from minimum CMRR at specified limits.
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V
MΩ
pF
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SGLS287A – MAY 2005 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)
VS = 5 V, VICM = 2.5 V, RL = 500 Ω, limiter pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.5
1
Input impedance, common mode
UNIT
MΩ
pF
OUTPUT
Output voltage range (VOH, VOL)
VH = VICM + 1.8 V,
VL = VICM– 1.8 V, RL≥ 500 Ω
Current output, sourcing (IOH)
VS = ±2.5 V, RL = 20 Ω
Current output, sinking (IOL)
VS = ±2.5 V, RL = 20 Ω
Closed-loop output impedance
G = +1, RF = 25 Ω, f < 100 kHz
TA = 25°C
VICM
±1.4
TA = Full range
VICM
±1.3
TA = 25°C
70
TA = Full range
60
TA = 25°C
–60
TA = Full range
–50
VICM
±1.6
V
105
mA
–90
mA
Ω
0.2
POWER SUPPLY
Operating voltage (VS)
TA = 25°C
Quiescent current (IS)
Power supply rejection ratio (PSRR)
Input referred, VS = 4 V to 6 V
13.5
5
12
14.3
15
16.5
V
mA
TA = Full range
12
TA = Full range
58
72
dB
TA = 25°C
VICM
±0.8
VICM
±1.1
V
TA = Full range
VICM
±0.6
OUTPUT VOLTAGE LIMITERS (pins 5 and 8)
Default output limited voltage
Limiter output offset voltage
Limiter input bias current magnitude (4)
Limiter pins open
(VO – VH) or (VO – VL)
VO = 2.5 V
TA = Full range
TA = 25°C
40
TA = Full range
35
V
±15
±50
50
65
70
mV
µA
Limiter input bias current drift
30
nA/°C
Limiter input impedance
3.4
1
MΩ
pF
Limiter feedthrough (5)
f = 5 MHz
–60
Maximum limiter voltage
Minimum limiter voltage separation
400
Op amp bias current shift (2)
Limiter small signal bandwidth
dB
VICM
±1.8
mV
5
VI = VICM ± 1.2 V, VO < 0.02 Vp-p
Limter slew rate (6)
V
µA
450
MHz
100
V/µA
Limiter step response, overshoot
VI = VICM ± 1.2 V
55
mV
Limiter step response, recovery time
VI = VICM ± 1.2 V
3
ns
30
mV
Linearity
(4)
(5)
(6)
(7)
guardband (7)
VO = 2 Vp-p, f = 5 MHz
IVH(VH bias current) is positive and IVL (VL bias current) is negative under these conditions. See Note 2, Figure 47 and Figure 66.
Limiter feedthrough is the ratio of the output magnitude to the sine wave added to VH (or VL) when VIN = 0.
VH slew rate conditions are: VIN = VICM +4 V, G = +2, VL = VICM – 2 V, VH = stepped between VICM + 1.2 V and VICM. VL slew rate
conditions are similar.
Linearity Guardband is defined for an output sinusoid (f = 5 MHz, VO = 0 VDC ±1 VP-P) centered between the limiter levels (VH and VL).
It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3 dB (see Figure 67).
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SGLS287A – MAY 2005 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS — VS = ±5 V
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
6
0
-3
VIN
VO
OPA698
RC
-6
RF
-9
VO = 0.2VPP
RF = 402Ω, RG Adjusted
G = -1
0
G = +1, RF = 25Ω, RC = 175Ω
Normalized Gain (dB)
Normalized Gain (dB)
3
G = +1, RF = 25Ω, RC = ∞
VO = 0.2VPP
3
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
G = +2, RC = ∞
G = -2
-3
G = -5
-6
-9
RG
G = +5, RC = ∞
See Figure 49
-12
-12
1
10
100
Frequency (MHz)
800
1
10
Frequency (MHz)
100
500
G001
Figure 1.
Figure 2.
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
9
9
VO = 1VPP
G = -2V/V, RF = 402Ω
VO =
2VPP
6
Normalized Gain (dB)
6
Normalized Gain (dB)
G002
VO = 4VPP
3
VO = 7VPP
0
-3
VO = 4VPP
3
VO = 7VPP
0
VO = 1VPP
-3
VO = 2VPP
See Figure 47
See Figure 49
-6
-6
1
10
Frequency (MHz)
100
400
1
10
Frequency (MHz)
100
G003
G004
Figure 3.
Figure 4.
VH–LIMITER SMALL-SIGNAL
FREQUENCY RESPONSE
Vl–LIMITER SMALL-SIGNAL
FREQUENCY RESPONSE
3
3
G = +2
VO = 0.02VPP
G = +2
VO = 0.02VPP
0
Limiter Gain (dB)
Limiter Gain (dB)
0
0.02VPP + 2VDC
-3
2VDC
VH
VO
OPA698
402Ω
-6
402Ω
-2VDC
VH Open
VO
OPA698
-3
VL
0.02VPP - 2VDC
402Ω
-6
VL Open
402Ω
-9
-9
1M
10M
100M
Frequency (Hz)
1G
1M
G005
Figure 5.
6
400
10M
100M
Frequency (Hz)
Figure 6.
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1G
G006
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SGLS287A – MAY 2005 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS — VS = ±5 V (continued)
SMALL-SIGNAL PULSE RESPONSE
0.25
2.5
VO = 0.2VPP
0.15
1.5
0.10
1.0
0.05
0.5
0.00
-0.05
0
-0.5
-0.10
-1.0
-0.15
-1.5
-0.20
VO = 4VPP
VH = -VL = 2.5V
2.0
VOUT (V)
VOUT (V)
0.20
LARGE-SIGNAL PULSE RESPONSE
-2.0
See Figure 47
See Figure 47
-2.5
-0.25
Time (5ns/div)
Time (5ns/div)
G007
Figure 7.
Figure 8.
VH–LIMITER PULSE RESPONSE
VL–LIMITER PULSE RESPONSE (20 MHz)
2.5
2.5
2.0
2.0
1.5
1.5
VOUT
1.0
VIN
0
-0.5
-1.0
-1.5
-2.0
VIN = 0 → -2V
G = +2
VL = -2V
1.0
0.5
VOUT (V)
VOUT (V)
G008
0.5
VIN
0
-0.5
-1.0
G = +2
VIN = 0 → +2V
VH = +2V
VOUT
-1.5
-2.0
-2.5
-2.5
Time (5ns/div)
Time (5ns/div)
G010
G009
Figure 9.
Figure 10.
LIMITED OUTPUT RESPONSE
DETAIL OF LIMITED OUTPUT VOLTAGE
2.10
2.5
2.0
1.5
1.95
1.0
0.5
0
VIN
-0.5
1.90
1.85
1.80
1.75
-1.0
1.70
-1.5
-2.0
VO
2.00
VOUT (V)
VIN and VOUT (V)
2.05
VOUT
VH = -VL = 2V
G = +2
1.65
1.60
-2.5
Time (50ns/div)
Time (200ns/div)
G012
G011
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS — VS = ±5 V (continued)
5 MHz HARMONIC DISTORTION
vs LOAD RESISTANCE
5 MHz HARMONIC DISTORTION
vs SUPPLY VOLTAGE
-55
-45
VO = 2VPP
f = 5MHz
2nd-Harmonic
-65
-70
-75
3rd-Harmonic
-80
-85
-60
2nd-Harmonic
-65
-70
-75
3rd-Harmonic
-80
See Figure 47
-90
1k
100
Load Resistance (Ω)
2.5
4.0
4.5
5.0
5.5
Figure 14.
HARMONIC DISTORTION
vs FREQUENCY
5 MHz HARMONIC DISTORTION
vs OUTPUT VOLTAGE
-50
RL = 500Ω
VH = -VL = VOPP /2 + 0.5V
f = 5MHz
Harmonic Distortion (dBc)
-55
2nd-Harmonic
-70
-80
-90
-100
See Figure 47
6.0
G014
Figure 13.
-60
-65
-70
2nd-Harmonic
-75
3rd-Harmonic
-80
-85
-90
3rd-Harmonic
-110
See Figure 47
-95
0.5
1
20
10
Frequency (MHz)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
Output Voltage (VPP)
G015
G016
Figure 15.
Figure 16.
HARMONIC DISTORTION
vs NONINVERTING GAIN
HARMONIC DISTORTION
vs INVERTING GAIN
-60
VO = 2VPP
RL = 500Ω
f = 5MHz
2nd-Harmonic
-70
Harmonic Distortion (dBc)
-60
-80
3rd-Harmonic
-90
-100
-65
VO = 2VPP
RL = 500Ω
f = 5MHz
2nd-Harmonic
-70
-75
3rd-Harmonic
-80
-85
-90
1
2
3
4
5
6
Gain (V/V)
7
8
9
10
-1
G017
Figure 17.
8
3.5
G013
VO = 2VPP
RL = 500Ω
-60
3.0
± Supply Voltage (V)
-50
Harmonic Distortion (dBc)
-55
-85
See Figure 47
-90
Harmonic Distortion (dBc)
VO = 2VPP
RL = 500Ω
-50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
-2
-3
-4
-5
-6
Gain (V/V)
Figure 18.
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-7
-8
-9
-10
G018
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SGLS287A – MAY 2005 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS — VS = ±5 V (continued)
2-TONE, 3RD-ORDER INTERMODULATION
INTERCEPT ±5 V 500 Ω
HARMONIC DISTORTION NEAR
LIMITING VOLTAGES
50
VO = 0VDC ± 1VP
f = 5MHz
RL = 500Ω
-50
G = +2V/V
45
Intercept Point (dBm)
Harmonic Distortion (dBc)
-40
-60
2nd-Harmonic
-70
-80
40
PI
35
PO
50Ω OPA698
30
500Ω
402Ω
25
402Ω
3rd-Harmonic
20
-90
0.9 1.0 1.1
1.2
1.3 1.4
1.5
1.6
1.7 1.8 1.9
0
2.0
± Limit Voltage (V)
10
20
30
50
40
Frequency (MHz)
G019
G020
Figure 19.
Figure 20.
RECOMMENDED RS
vs CAPACITIVE LOAD
FREQUENCY RESPONSE
vs CAPACITIVE LOAD
9
140
VO = 0.2VPP
Gain to Capacitive Load (dB)
120
Resistance (Ω)
100
80
60
40
20
6
CL = 100pF
CL = 10pF
3
CL = 22pF
VIN
RS
0
OPA698
402Ω
1kΩ(1)
CL = 47pF
CL
-3
402Ω
NOTE: (1) 1kΩ is optional.
0
-6
100
10
Capacitive Load (pF)
1M
10M
G021
Figure 21.
G022
Figure 22.
INPUT VOLTAGE AND CURRENT NOISE DENSITY
OPEN-LOOP FREQUENCY RESPONSE
70
100
0
VO = 0.5VPP
Gain
Open-Loop Gain (dB)
60
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
1G
100M
Frequency (Hz)
Voltage Noise (5.6nV/√Hz)
10
Current Noise (2.2pA/√Hz)
-30
50
-60
40
-90
Phase
30
-120
20
-150
10
-180
0
-210
-10
1
100
1k
10k
100k
Frequency (Hz)
1M
10M
Open-Loop Phase (°)
1
-240
10k
100k
1M
10M
Frequency (Hz)
G023
Figure 23.
100M
1G
G024
Figure 24.
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TYPICAL CHARACTERISTICS — VS = ±5 V (continued)
VOLTAGE RANGE vs TEMPERATURE
LIMITED VOLTAGE RANGE vs TEMPERATURE
5.0
3.8
VH = -VL = 4.3V
VH and VL left open
4.5
± Voltage Range (V)
Output Voltage Range
4.0
3.5
VH
3.4
VL
3.0
3.2
-50
-25
0
25
50
100
75
Ambient Temperature (°C)
-50
-25
G025
25
50
100
75
G026
Figure 25.
Figure 26.
LIMITED INPUT BIAS CURRENT vs BIAS VOLTAGE
SUPPLY AND OUTPUT CURRENTS
vs TEMPERATURE
20
100
Output Current, Sinking
75
18
Supply Current (mA)
Minimum Over Temperature
25
0
Limiter Headroom = +VS − VH
= VL − (−VS)
Current = IVH or − IVL
−25
−50
98
Output Current, Sourcing
16
96
Supply Current
14
94
12
Output Currents (mA)
Maximum Over Temperature
50
92
−75
−100
10
0
0.5
1.0 1.5
2.0
2.5
3.0
3.5
4.0
4.5 5.0
Limiter Headroom (V)
-50
-25
0
25
50
75
G028
Figure 27.
Figure 28.
CMMR AND POWER-SUPPLY REJECTION
vs FREQUENCY
TYPICAL DC DRIFT OVER TEMPERATURE
4.5
Input Bias and Offset Current (µA)
-PSRR
70
CMRR
60
+PSRR
50
40
30
20
10
1.0
Input Bias Current (IB)
4.0
0.9
3.5
0.8
3.0
0.7
2.5
0.6
Input Offset Voltage (VOS)
2.0
0.5
1.5
0.4
1.0
0.3
0.5
0.2
Input Offset Current (IOS)
0
0.1
-0.5
0
10k
90
100
Ambient Temperature (°C)
G027
80
100k
1M
Frequency (Hz)
10M
100M
-50
-25
0
25
50
Ambient Temperature (°C)
G029
Figure 29.
10
0
Ambient Temperature (°C)
100
Limiter Input Bias Current (∝A)
3.5
3.3
Common-Mode Input Range
CMRR, PSRR (dB)
3.6
Figure 30.
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0
100
G030
Input Offset Voltage (mV)
± Voltage Range (V)
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TYPICAL CHARACTERISTICS — VS = ±5 V (continued)
LIMITER FEEDTHROUGH
CLOSED-LOOP OUTPUT IMPEDANCE
-45
100
G = +1
RF = 25Ω
VO = 0.2VPP
-50
10
Output Impedance (Ω)
Feedthrough (dB)
-55
-60
-65
0.02VPP + 2VDC
-70
VH
VO
-75
OPA698
-80
VL 402Ω
-85
0.1
0.01
402Ω
Open
-90
-95
0.001
1
100
10
Frequency (MHz)
1M
10M
1G
100M
Frequency (Hz)
G031
G032
Figure 31.
Figure 32.
±PSRR AND CMRR vs TEMPERATURE
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
90
5
85
4
+PSRR
VH = -VL = 4.3V
1W Internal
Power Limit
3
80
Output Voltage (V)
PSRR and CMRR, Input Referred (dB)
1
-PSRR
75
70
65
CMRR
60
2
1
0
RL = 25Ω
-1
RL = 50Ω
-2
RL = 100Ω
-3
55
1W Internal
Power Limit
-4
50
-50
-25
0
25
50
75
Ambient Temperature (°C)
-5
-400
100
-300
-200
-100
0
100
200
300
400
Output Current (mA)
G033
Figure 33.
G034
Figure 34.
TYPICAL CHARACTERISTICS — VS = +5 V
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
9
VO = 0.2VPP
3
G = +1, RF = 25Ω, RC = ∞
3
0
0
-3
G = +2, RC = ∞
-6
G = -1
VO = 0.2VPP
G = +1, RF = 25Ω,
RC = 175Ω
Normalized Gain (dB)
Normalized Gain (dB)
6
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
G = +5, RC = ∞
-9
G = -2
RF = 402Ω, RG Adjusted
-3
G = -5
-6
-9
-12
-12
See Figure 48
-15
-15
1
10
Frequency (MHz)
100
500
1
10
Frequency (MHz)
G035
Figure 35.
100
400
G036
Figure 36.
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TYPICAL CHARACTERISTICS — VS = +5 V (continued)
LARGE-SIGNAL FREQUENCY RESPONSE
2.70
VO = 1VPP, VH = VCM + 1.2V,
VL = VCM - 1.2V
G = +2
2.65
6
2.60
VO = 2VPP, VH = VCM + 1.5V,
VL = VCM - 1.5V
2.55
3
VOUT (V)
Normalized Gain (dB)
9
SMALL-SIGNAL PULSE RESPONSE
0
See Figure 48
2.35
2.30
-6
1
10
Frequency (MHz)
2.45
2.40
VO = 3VPP
VH = VCM + 2V
VL = VCM - 2V
-3
2.50
100
400
Time (5ns/div)
G038
G037
Figure 37.
Figure 38.
LARGE-SIGNAL PULSE RESPONSE
VH AND VL– LIMITED PULSE RESPONSE
4.0
4.0
3.5
Input and Output Voltage (V)
VO = 2VPP
VH = VCM + 1.2V
VL = VCM - 1.2V
VOUT (V)
3.0
2.5
2.0
1.5
1.0
VH = VCM + 1.2V
VL = VCM - 1.2V
3.5
VIN
3.0
VOUT
2.5
2.0
1.5
1.0
Time (5ns/div)
Time (5ns/div)
G039
G040
Figure 39.
Figure 40.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs FREQUENCY
-45
-50
VO = 2VPP
f = 5MHz
-55
VO = 2VPP
RL = 500Ω
-55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
2nd-Harmonic
-60
-65
3rd-Harmonic
-70
-75
-60
-65
2nd-Harmonic
-70
-75
-80
3rd-Harmonic
-85
See Figure 48
See Figure 48
-80
-90
1k
100
Load Resistance (Ω)
0.5
G041
Figure 41.
12
1
10
Frequency (MHz)
Figure 42.
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TYPICAL CHARACTERISTICS — VS = +5 V (continued)
2-TONE, 3RD ORDER
INTERMODULATION INTERCEPT
HARMONIC DISTORTION vs OUTPUT VOLTAGE
45
−65
G = +2V/V
40
−70
Intercept Point (+dBM)
Harmonic Distortion (dBc)
2nd−Harmonic
−75
3rd−Harmonic
−80
RL = 500 Ω to VS/2
f = 5 MHz
VH = VCPP/2 + VCM + 0.5 V
VL = VCPP/2 + VCM + 0.5 V
−85
+2.5V
35
PI
+VS
PO
OPA698
50Ω
30
−VS
500Ω
−2.5V
402Ω
25
402Ω
20
−90
0.5
1.0
1.5
2.0
010
2.5
20
HARMONIC DISTORTION NEAR LIMITING VOLTAGES
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
Limiter Input Bias Current (∝A)
Harmonic Distortion (dBc)
-50
-55
-60
-65
2nd-Harmonic
-70
3rd-Harmonic
-75
75
Maximum Over Temperature
50
25
0
Minimum
Over Temperature
−25
−50
Limiter Headroom = +VS − VH
= VL − (−VS)
Current = IVH or − IVL
−75
−100
-80
1.2
1.3
1.4
G044
100
VO = VCM ±1VP
f = 5MHz
RL = 500Ω
-45
1.1
50
Figure 44.
-40
1.0
30
G043
Figure 43.
0.9
40
Frequency (MHz)
Output Voltage Swing (V PP)
1.5
1.6
1.7
Limit Voltages - 2.5V
0
1.8
0.5
1
1.5
2
2.5
Limiter Headroom (V)
G046
G045
Figure 45.
Figure 46.
TYPICAL APPLICATIONS
Wideband Voltage Limiting Operation
The OPA698 is a voltage feedback amplifier that combines features of a wideband, high slew rate amplifier with
output voltage limiters. Its output can swing up to 1 V from each rail and can deliver up to 120 mA. These
capabilities make it an ideal interface to drive ADC, while adding overdrive protection for the ADC inputs.
Figure 47 shows the dc-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the ±5-V
Electrical Characteristics and Typical Characteristics. For test purposes, the input impedance is set to 50 Ω with
a resistor to ground and the output impedance is set to 500 Ω. Voltage swings reported in the specifications are
taken directly at the input and output pins. For the circuit of Figure 47, the total output load is 500 Ω || 804 Ω =
308 Ω. The voltage limiting pins are set to ±2 V through a voltage divider network between the +VS and ground
for VH and between –VS and ground for VL. These limiter voltages are adequately bypassed with a 0.1-µF
ceramic capacitor to ground. The limiter voltages (VH and VL) and the respective bias currents (IVH and IVL) have
the polarities shown. One additional component is included in Figure 47. An additional resistor (174 Ω) is
included in series with the noninverting input. Combined with the 25-Ω dc-source resistance looking back towards
the signal generator, this gives an input bias current-cancelling resistance that matches the 200-Ω source
resistance seen at the inverting input (see the dc accuracy and offset control section). The power-supply bypass
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TYPICAL APPLICATIONS (continued)
for each supply consists of two capacitors: one electrolytic 2.2 µF and one ceramic 0.1 µF. The supply bypass
capacitors are shown explicitly in Figure 47 and Figure 48, but is assumed in the other figures. An additional
0.01-µF power-supply decoupling capacitor (not shown here) can be included between the two power-supply
pins. In practical PC board layouts; this optional-added capacitor typically improves the 2nd harmonic distortion
performance by 3 dB to 6 dB.
3.01kΩ
1.91kΩ
+VS = +5V
+
2.2µF
0.1µF
0.1µF
VH = +2V
174Ω
7
3
VIN
8
49.9Ω
OPA698
2
RG
402Ω
5
IVH
6
VO
IVL
500Ω
4
RF
402Ω
0.1µF
0.1µF
VL = -2V
+
2.2µF
3.01kΩ
1.91kΩ
-VS = -5V
S0035-01
Figure 47. DC-Coupled, Dual-Supply Amplifier
VS = +5V
+
0.1µF
2.2µF
523Ω
0.1µF
VH = 3.7V
806Ω
0.1µF
3
IVH
7
VIN
8
57.6Ω
806Ω
OPA698
2
976Ω
0.1µF
6
VO
5
500Ω
IVL
4
RF
402Ω
0.1µF
RG
402Ω
0.1µF
VL = 1.3V
523Ω
S0036-01
Figure 48. AC-Coupled, Single-Supply Amplifier
Single Supply, Noninverting Amplifier
Figure 48 shows an ac-coupled, noninverting gain amplifier for single +5-V supply operation. This circuit was
used for ac characterization of the OPA698, with a 50-Ω source (which it matches) and a 500-Ω load. The
14
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TYPICAL APPLICATIONS (continued)
mid-point reference on the noninverting input is set by two 806-Ω resistors. This gives an input bias
current-canceling resistance that matches the 402-Ω dc-source resistance seen at the inverting input (see the dc
accuracy and offset control section). The power-supply bypass for the supply consists of two capacitors: one
electrolytic 2.2 µF and one ceramic 0.1 µF. The power-supply bypass capacitors are shown explicitly in Figure 47
and Figure 48, but is assumed in the other figures. The limiter voltages (VH and VL) and the respective bias
currents (IVH and IVL) have the polarities shown. These limiter voltages are adequately bypassed with a 0.1 µF
ceramic capacitor to ground. Notice that the single-supply circuit can use three resistors to set VH and VL, where
the dual-supply circuit usually uses four to reference the limit voltages to ground. While this circuit shows +5-V
operation, the same circuit may be used for single supplies up to +12 V.
Wideband Inverting Operation
Operating the OPA698 as an inverting amplifier has several benefits and is particularly useful when a matched
50-Ω source and input impedance are required. Figure 49 shows the inverting gain of –2 circuit used as the basis
of the inverting mode typical characteristics.
+5V
0.1µF
RT
147Ω
+2V
VH
OPA698
VO
VL
500Ω
-5V
50Ω Source
200Ω
-2V
402Ω
VI
RM
66.5Ω
S0037-01
Figure 49. Inverting G = –2 Specifications and Test Circuit
In the inverting case, only the feedback resistor appears as part of the total output load in parallel with the actual
load. For a 500-Ω load used in the typical characteristics, this gives a total load of 222 Ω in this inverting
configuration. The gain resistor is set to get the desired gain (in this case, 200 Ω for a gain of –2); while an
additional input resistor (RM) can be used to set the total input impedance equal to the source, if desired. In this
case, RM = 66.5 Ω in parallel with the 200-Ω gain setting resistor gives a matched input impedance of 50 W. This
matching is only needed when the input needs to be matched to a source impedance, as in the characterization
testing done using the circuit of Figure 49.
For bias current-cancellation matching, the noninverting input requires a 147-Ω resistor to ground. The
calculation for this resistor includes a dc-coupled 50-Ω source impedance along with RG and RM. Although this
resistor provides cancellation for the bias current, it must be well decoupled (0.1 µF in Figure 49) to filter the
noise contribution of the resistor and the input current noise.
As the required RG resistor approaches 50 Ω at higher gains, the bandwidth for the circuit in Figure 49 far
exceeds the bandwidth at that same gain magnitude for the noninverting circuit of Figure 47. This occurs due to
the lower noise gain for the circuit of Figure 49 when the 50-Ω source impedance is included in the analysis. For
instance, at a signal gain of –8 (RG = 50 Ω, RM = open, RF = 402 Ω) the noise gain for the circuit of Figure 49 will
be 1 + 402 Ω/(50 Ω + 50 Ω) = 5 due to the addition of the 50-Ω source in the noise gain equation. This approach
gives considerably higher bandwidth than the noninverting gain of +8. Using the 250-MHz gain bandwidth
product for the OPA698, an inverting gain of –8 from a 50-Ω source to a 50 Ω RG gives 52-MHz bandwidth,
whereas the noninverting gain of +8 gives 28 MHz, as shown in Figure 50.
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TYPICAL APPLICATIONS (continued)
21
G = —8
Gain (dB)
18
15
12
G = +8
9
6
0.1
1
10k
Frequency (MHz)
100k
G047
Figure 50. G = +8 and –8 Frequency Response
Limited Output, ADC Input Driver
Figure 51 shows a simple ADC driver that operates on a single supply, and gives excellent distortion
performance. The limit voltages track the input range of the converter, completely protecting against input
overdrive. Note that the limiting voltages have been set 100 mV above/below the corresponding reference
voltage from the converter.
VS = +5V
562Ω
VH = +3.6V
VS = +5V
0.1∝F
715Ω
102Ω
+3.5V
VS = +5V
REFT
0.1∝F
3
VIN
RSEL
+VCC
7
8
OPA698
6
24.9Ω
5
2
ADS822
10-Bit
40MSPS
IN
10−Bit
Data
100pF
4
715Ω
REFB
402Ω
INT/EXT GND
+1.5V
102Ω
402Ω
0.1∝F
VL = +1.4V
0.1∝F
562Ω
S0038−01
Figure 51. Single Supply, Limiting ADC Input Driver
Limited Output, Differential ADC Input Driver
Figure 52 shows a differential ADC driver that takes advantage of the OPA698 limiters to protect the input of the
ADC.
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TYPICAL APPLICATIONS (continued)
Two OPA698s are used. The first one is an inverting configuration at a gain of –2. The second one is in a
noninverting configuration at a gain of +2. Each amplifier is swinging 2 VPP providing a 4-VPP differential signal to
drive the input of the ADC. Limiters have been set 100 mV away from the magnitude of each amplifier's
maximum signal to provide input protection for the ADC, while maintaining an acceptable distortion level.
+5V
+1.1V
OPA698
-1.1V
-5V
200Ω
100Ω
10pF
24.9Ω 0.01µF
IN
1kΩ
+5V
VCM
4VPP
+1.1V
VIN = 1VPP
ADC
24.9Ω 0.01µF
1kΩ
IN
OPA698
100Ω
10pF
-1.1V
-5V
200Ω
200Ω
S0040-01
Figure 52. Single-to-Differential AC-Coupled, Output Limited ADC Driver
Precision Half-Wave Rectifier
Figure 53 shows a half-wave rectifier with outstanding precision and speed. VH (pin 8) defaults to a voltage
between 3.1 V and 3.8 V if left open, while the negative limit is set to ground.
+VS = +5V
200Ω
2
7
NC
VIN
8
OPA698
6
VO
5
3
4
402Ω
402Ω
-VS = -5V
S0039-01
Figure 53. Precision Half-Wave Rectifier
The gain for the circuit in Figure 53 is set at +2. Figure 54 shows a 100-MHz sine-wave amplifier, with a gain of
+2 and rectified.
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TYPICAL APPLICATIONS (continued)
2.0
Output
Output Voltage (V)
1.5
1.0
0.5
0
-0.5
Input
-1.0
-1.5
Time (2ns/div)
G048
Figure 54. 100-MHz Sine Wave Rectified
High-Speed Full-Wave Rectifier
There are two methods shown here to build a high-speed full-wave rectifier with a limiting amplifier: use the
half-wave rectifier described previously with another amplifier to obtain the full-wave rectified, or use the input to
set the limiting voltage.
High-Speed Full-Wave Rectifier #1
The circuit shown in Figure 55 uses only one amplifier, in an inverting gain of –1 configuration. The upper limiting
voltage is left open, resulting in an upper limiting voltage of +3.5 V. The lower limiting voltage is connected to the
input signal, resulting in the following behavior. When the input voltage is negative, the amplifier is not limiting,
resulting in the inversion of the input sine wave to the output. During the positive excursion of the input signal,
the output signal is being driven by the limiting input pin. Since the output is driven from the limiter input pin from
positive inputs, the lower slew rate in the input path restricts the application of this approach to lower amplitude
and/or frequencies. A 2-MHz fully rectified sine wave is shown in Figure 56.
In order to reach higher frequencies, a second method is recommended.
200Ω
VH
OPA698
VL
50Ω
Source
402Ω
VO
500Ω
402Ω
57.2Ω
S0041-01
Figure 55. High-Speed Full-Wave Rectifier #1
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TYPICAL APPLICATIONS (continued)
0.6
Output Voltage (V)
0.4
0.2
0
-0.2
-0.4
-0.6
Time (50ns/div)
G049
Figure 56. 2-MHz Sinewave Rectified
High-Speed Full-Wave Rectifier #2
The circuit shown in Figure 57 combines a half-wave rectifier driving the OPA693 in an inverting configuration,
while the input signal drives the noninverting input of the fixed gain amplifier OPA693, resulting in a full-wave
rectifier function. Results are shown in Figure 58.
700MHz
Internal
Gain Set
75Ω
50Ω 50Ω Load
75Ω
VH
OPA693
300Ω
OPA698
VL
300Ω
200Ω
200Ω
S0042-01
Figure 57. High-Speed Full-Wave Rectifier #2
Input and Output Voltage (V)
0.8
VOUT
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
VIN
-0.8
Time (10ns/div)
G050
Figure 58. 10-MHz Sinewave Rectified
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TYPICAL APPLICATIONS (continued)
If the negative excursion of the rectified signal is not desired, it can easily be removed by replacing the OPA693
with the OPA698 configured as a difference amplifier with VL connected to ground and VH left floating.
Soft-Clipping (Compression) Circuit
Figure 59 shows a soft-clipping circuit. As soon as the input voltage exceeds either VCH or VCL, the limiting
voltages are driven by Equation 1 and Equation 2.
R2 V
R1 V
CH
IN
V H
R1 R2
(1)
V L
R4 V
R3 V
CL
IN
R3 R4
(2)
As the amplifier is operating in the limiting mode, the output voltage is compressed with a gain of R1+R2/R1 for
the positive excursion above VCH and by a gain of R3+R4/R3 for the negative excursion below VCL. Figure 60
shows a 5 VPP on the input being compressed above ±1 V with a compression gain of one third.
R1
1kΩ
VCH
+1V
R2
2kΩ
VIN
V
R3
1kΩ
VCL
-1V
R4
2kΩ
OPA698 VHL
VOUT
24.9Ω
S0043-01
Figure 59. Soft-Clipping Circuit
3
Input and Output Voltage (V)
VIN
2
1
VOUT
0
-1
-2
-3
Time (100ns/div)
G051
Figure 60. Soft-Clipping With A Gain of 1/3 Above the Clamp Level (±1 V)
High-Speed Schmitt Trigger
Figure 61 shows a high-speed Schmitt Trigger. The output levels are precisely defined and the switching time is
exceptional. The output voltage swings between VH and VL.
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TYPICAL APPLICATIONS (continued)
The circuit operates as follow. When the input voltage is less than VHL then the output is limiting at VH. When the
input is greater than VHH then the output is limiting at VL, with VHL and VHH defined as the following:
R1 R2 R3
R1 R2 R3
V
V
V
HL,HH
REF
OUT
R1
R2
(3)
Due to the inverting function realized by the Schmitt Trigger, VHL corresponds to VOUT = VH and VHH corresponds
to VOUT = VL.
R2
402Ω
R1
200Ω
+2V
VREF
R3
200Ω
VH
OPA698
VOUT
VL
VIN
-2V
S0044-01
Figure 61. High-Speed Schmitt Trigger
Figure 62 shows the Schmitt Trigger operating with VREF = +5 V. This gives us VHH = 2.4 V and VHL = 1.6 V. The
propagation delay for the OPA698 in a Schmitt Trigger configuration is 6 ns from high-to-low and 5 ns from
low-to-high.
Input and Output Voltage (V)
4
3
2
1
0
VOUT
-1
VIN
-2
-3
-4
Time (10ns/div)
G052
Figure 62. Schmitt Trigger Time Domain Response for a 10-MHz Sinewave
Unity-Gain Buffer
Figure 63 shows a unity-gain voltage buffer using the OPA698. The feedback resistor (RF) isolates the output
from the input capacitance at the inverting input. RF = 24.9 Ω is recommended for unity-gain buffer applications.
RC is an optional compensation resistor that reduces the peaking typically seen at G = +1. Choosing RC = RS +
RF gives a unity-gain buffer with approximately the G = +2 frequency response. The frequency response for this
circuit is shown in the electrical characteristics curves.
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TYPICAL APPLICATIONS (continued)
RS
VO
OPA698
VS
RC
RF
24.9Ω
S0045-01
Figure 63. Unity-Gain Buffer
DC Restorer
Figure 64 shows a dc-restore circuit using the OPA698 and OPA660. The buffer element of the OPA660 is used
to buffer the input signal, while the transconductance element is used to restore the dc level after the decoupling
capacitor C1. The dc level is set using R1 and R2. The OPA698 is configured at a gain of two to compensate for
the 75-Ω series into a 75-Ω load. The OPA698 also limits the output to ground.
C1
20µF
U1
200Ω
VIN
5
+1
VH = Open
20Ω
6
D1
1
RQ
250Ω
R1
19.6kΩ
75Ω
8
R2
1kΩ
OPA698
VO
5
D2
VL
75Ω
Load
402Ω
U1
C
CCII
402Ω
B
3
E
2
R3
200Ω
U1 = OPA660
RQ = 250Ω (sets IQ for U1)
D1, D2 = 1N4148
S0047-01
Figure 64. DC Restore to Ground
Video Sync Stripper
Figure 65 shows a sync stripper using two OPA698 output-limiting op amps. One OPA698 is configured as a
limiting inverting comparator. Referring to the input, the negative excursions lower than –0.2 V are clipped to
ground and all excursions greater than –0.2 V generate an output voltage set by the default limiting value (–3.5
V). The second OPA698 is using this waveform to effectively remove the sync pulse from the video signal.
22
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TYPICAL APPLICATIONS (continued)
Open
VIN
R1
75Ω
R4
75Ω
VH
R2
402Ω
VOUT
OPA698
VL
R3
402Ω
OPA698
VH
VL
-0.2V
Open
S0046-01
Figure 65. Sync Stripper Circuit
DESIGN-IN TOOLS
Applications Support
The Texas Instruments Applications Department is available for design assistance at 1-972-644-5580. The Texas
Instruments web site (www.ti.com) has the latest product data sheets and other design aids.
Demonstrations Boards
A PC board is available to assist in the initial evaluation of circuit performance of the OPA698ID. It is available as
an unpopulated PCB with descriptive documentation. See the demonstration board literature for more
information. The summary information for this board is shown in Table 1.
Table 1. Demo Board Summary Information
PRODUCT
PACKAGE
BOARD
PART NO.
LITERATURE
REQUEST NO.
OPA698ID
SO-8
DEM-OPA-SO-1A
SBOU009
This board can be requested through the Texas Instruments web site.
OPERATING SUGGESTIONS
Theory of Operation
The OPA698 is a voltage-feedback op amp that is unity-gain stable. The output voltage is limited to a range set
by the voltage on the limiter pins (5 and 8). When the input tries to overdrive the output, the limiters take control
of the output buffer. This action from the limiters avoids saturating any part of the signal path, giving quick
overdrive recovery and excellent limiter accuracy at any signal gain. The limiters have a sharp transition from the
linear region of operation to output limiting. This transition allows the limiter voltages to be set near (<100 mV)
the desired signal range. The distortion performance is also good near the limiter voltages.
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Output Limiters
The output voltage is linearly dependent on the input(s) when it is between the limiter voltages VH (pin 8) and VL
(pin 5). When the output tries to exceed VH or VL, the corresponding limiter buffer takes control of the output
voltage and holds it at VH or VL. Because the limiters act on the output, their accuracy does not change with gain.
The transition from the linear region of operation to output limiting is sharp-the desired output signal can safely
come to within 30 mV of VH or VL with no onset of non-linearity. The limiter voltages can be set to within 0.7 V of
the supplies (VL≥– VS + 0.7 V, VH≤ +VS– 0.7 V). They must also be at least 400 mV apart (VH– VL≥ 0.4 V). When
pins 5 and 8 are left open, VH and VL go to the default voltage limit; the minimum values are given in the
electrical specifications. Looking at Figure 66 for the zero bias current case shows the expected range of (VS–
default limit voltages) = headroom.
Limiter Input Bias Current (∝A)
100
75
Maximum Over Temperature
50
25
0
Minimum
Over Temperature
−25
−50
Limiter Headroom = +VS − VH
= VL − (−VS)
Current = IVH or − IVL
−75
−100
0
0.5
1
1.5
2
2.5
Limiter Headroom (V)
G046
Figure 66. Limiter Bias Current vs Bias Voltage
When the limiter voltages are more than 2.1 V from the supplies (VL≥– VS + 2.1 V or VH≤ +VS– 2.1 V), you can
use simple resistor dividers to set VH and VL (see Figure 47). Make sure to include the limiter input bias currents
(see Figure 54) in the calculations (that is, IVL = –50 µA out of pin 5 and IVH = +50 µA out of pin 8). For good
limiter voltage accuracy, run at least 1-mA quiescent bias current through these resistors. When the limiter
voltages need to be within 2.1 V of the supplies (VL≤– VS + 2.1 V or VH≥ +VS– 2.1 V), consider using low
impedance buffers to set VH and VL to minimize errors due to bias current uncertainty. This condition is typically
the case for single-supply operation (VS = +5 V). Figure 48 runs 2.5 mA through the resistive divider that sets VH
and VL. This limits errors due to IVH and IVL < ±1% of the target limit voltages. The limiters' dc accuracy depends
on attention to detail. The two dominant error sources can be improved as follows:
•
•
•
•
•
•
24
Power supplies, when used to drive resistive dividers that set VH and VL, can contribute large errors (for example, ±5%).
Using a more accurate source and bypassing pins 5 and 8 with good capacitors improves limiter PSRR.
The resistor tolerances in the resistive divider can also dominate. Use 1% resistors.
Other error sources also contribute, but should have little impact on the limiters' dc accuracy:
Reduce offsets caused by the limiter input bias currents. Select the resistors in the resistive divider(s) as described
above.
Consider the signal path dc errors as contributing to uncertainty in the usable output swing.
The limiter offset voltage only slightly degrades limiter accuracy. Figure 67 shows how the limiters affect distortion
performance. Virtually no degradation in linearity is observed for output voltage swinging right up to the limiter voltages.
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Harmonic Distortion (dBc)
-40
VO = 0VDC ± 1VP
f = 5MHz
RL = 500Ω
-50
-60
2nd-Harmonic
-70
-80
3rd-Harmonic
-90
0.9 1.0 1.1
1.2
1.3 1.4
1.5
1.6
1.7 1.8 1.9
± Limit Voltage (V)
2.0
G019
Figure 67. Harmonic Distortion Near Limit Voltages
Output Drive
The OPA698 has been optimized to drive 500-Ω loads, such as ADCs. It still performs well driving 100-Ω loads;
the specifications are shown for the 500-Ω load. This makes the OPA698 an ideal choice for a wide range of
high-frequency applications.
Many high-speed applications, such as driving ADCs, require op amps with low output impedance. As shown in
the typical performance curve Output Impedance vs Frequency, the OPA698 maintains low closed-loop output
impedance over frequency. Closed-loop output impedance increases with frequency, since loop gain decreases
with frequency.
Thermal Considerations
The OPA698 does not require heat sinking under most operating conditions. Maximum desired junction
temperature sets a maximum allowed internal power dissipation as described below. In no case should the
maximum junction temperature be allowed to exceed 150°C.
The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and the additional power dissipated
in the output stage (PDL), while delivering load power. PDQ is simply the specified no-load supply current times
the total supply voltage across the part. PDL depends on the required output signals and loads. For a grounded
resistive load, and equal bipolar supplies, it is at maximum when the output is at 1/2 either supply voltage. In this
condition, PDL = VS2/(4RL) where RL includes the feedback network loading. Note that it is the power in the output
stage and not in the load, that determines internal power dissipation.
The operating junction temperature is: TJ = TA + PD x θJA, where TA is the ambient temperature. For example, the
maximum TJ for a OPA698ID with G = +2, RF = 402 Ω, RL = 100 Ω, and ±VS = ±5 V at TA = +85°C is calculated
as:
P
(10 V 15.5 mA) 155 mW
DO
(5V)2
P
70 mW
DL
4 (100 804 )
P
D
155 mW 70 mW 225 mW
T 85oC 225 mW 125 oCW 113 oC
J
(4)
This would be the maximum TJ from VO = ±2.5 VDC. Most applications will be at a lower output stage power and
have a lower TJ. Care must be taken when operating at higher ambient temperatures.
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Capacitive Loads
Capacitive loads, such as the input to ADCs, decreases the amplifier phase margin, which may cause
high-frequency peaking or oscillations. Capacitive loads ≥2 pF should be isolated by connecting a small resistor
in series with the output, as shown in Figure 68. Increasing the gain from +2 improves the capacitive drive
capabilities due to increased phase margin.
RG
RF
RS
VO
OPA698
RL
RT
CL
RL is optional
S0048-01
Figure 68. Driving Capacitive Loads
In general, capacitive loads should be minimized for optimum high-frequency performance. The capacitance of
coax cable (29 pF/ft for RG-58) will not load the amplifier when the coaxial cable, or transmission line, is
terminated in its characteristic impedance.
Frequency Response Compensation
The OPA698 is internally compensated to be unity-gain stable, and has a nominal phase margin of 60° at a gain
of +2. Phase margin and peaking improve at higher gains. Recall that an inverting gain of –1 is equivalent to a
gain of +2 for bandwidth purposes (that is, noise gain = 2). Standard external compensation techniques work with
this device. For example, in the inverting configuration, the bandwidth may be limited without modifying the
inverting gain by placing a series RC network to ground on the inverting node. This has the effect of increasing
the noise gain at high frequencies, which limits the bandwidth.
To maintain a wide bandwidth at high gains, cascade several op amps, or use the high-gain optimized OPA699.
In applications where a large feedback resistor is required, such as photodiode transimpedance amplifier, the
parasitic capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this
effect, connect a small capacitor in parallel with the feedback resistor. The bandwidth will be limited by the pole
that the feedback resistor and this capacitor create. In other high-gain applications, use a three resistor Tee
network to reduce the RC time constants set by the parasitic capacitances. Be careful not to increase the noise
generated by this feedback network too much.
Pulse Settling Time
The OPA698 is capable of an extremely fast settling time in response to a pulse input. Frequency response
flatness and phase linearity are needed to obtain the best settling times. For capacitive loads, such as an ADC,
use the recommended RS in the typical performance curve RS vs Capacitive Load. Extremely fine-scale settling
(0.01%) requires close attention to ground return current in the supply decoupling capacitors.
The pulse settling characteristics, when recovering from overdrive, are good.
Distortion
The OPA698 distortion performance is specified for a 500-Ω load, such as an ADC. Driving loads with smaller
resistance increases the distortion, as illustrated in Figure 69. Remember to include the feedback network in the
load resistance calculations.
26
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2nd- and 3rd-Harmonic Distortion (dBc)
SGLS287A – MAY 2005 – REVISED MARCH 2006
-40
VO = 2VPP
f1 = 5MHz
-45
-50
HD2
-55
-60
-65
HD3
-70
-75
-80
-85
-90
50
100
1000
Load Resistance (Ω)
G053
Figure 69. 5-MHz Harmonic Distortion vs Load Resistance
Noise Performance
High slew rate, unity-gain stable, voltage feedback op amps usually achieve their slew rate at the expense of a
higher input noise voltage. The 5.6-nV/√Hz input voltage noise for the OPA698, however, is much lower than
comparable amplifiers. The input-referred voltage noise and the two input-referred current noise terms combine
to give low output noise under a wide variety of operating conditions. Figure 70 shows the op amp noise analysis
model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current
density terms in either nV/√Hz or pA/√Hz.
ENI
EO
OPA698
RS
IBN
ERS
RF
4kTRS
4kT
RG
4kTRF
IBI
RG
4kT = 1.6E -20J
at 290 K
S0049-01
Figure 70. 5-MHz Harmonic Distortion vs Load Resistance
The total output spot noise voltage can be computed as the square root of the sum of all squared output noise
voltage contributors. Equation 5 shows the general form for the output noise voltage using the terms shown in
Figure 70.
E
O
E
2
NI
BNRS
I
2
4kTR
S
BIRF
NG 2 I
2
4kTR NG
F
(5)
Dividing this expression by the noise gain [NG = (1+RF/RG)] gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in Equation 6.
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E
N
E
2
NI
BNRS
2
I
4kTR S
I R
BI F
NG
2
4kTR
F
NG
(6)
Evaluating these two equations for the OPA698 circuit and component values (see Figure 47) gives a total output
spot noise voltage of 11.9 nV/√Hz and a total equivalent input spot noise voltage of 6 nV/√Hz. This total
input-referred spot noise voltage is only slightly higher than the 5.6 nV/√Hz specification for the op amp voltage
noise alone. This is the case as long as the impedances appearing at each op amp input is limited to a maximum
value of 300 Ω. Keeping both (RF || RG) and the noninverting input source impedance less than 300 Ω satisfies
both noise and frequency response flatness considerations. Since the resistor-induced noise is relatively
negligible, additional capacitive decoupling across the bias current cancellation resistor (RT) for the inverting op
amp configuration of Figure 49 is not required, but is still desirable.
DC Accuracy and Offset Control
The balanced input stage of a wideband voltage feedback op amp allows good output dc accuracy in a large
variety of applications. The power-supply current trim for the OPA698 gives even tighter control than comparable
products. Although the high-speed input stage does require relatively high input bias current (typically ±8 µA at
each input terminal), the close matching between them may be used to reduce the output dc error caused by this
current. The total output offset voltage may be considerably reduced by matching the dc source resistances
appearing at the two inputs. This reduces the output dc error due to the input bias currents to the offset current
times the feedback resistor. Evaluating the configuration of Figure 47, using a worst-case +25°C input offset
voltage and current specifications, gives a worst-case output offset voltage equal to:
– (NG = noninverting signal gain)
± (NG × VIO(MAX)) ± [RF x IIO(MAX)]
= ±(2 × 8 mV) ± (402 Ω × 3 µA)
= ±17.2 mV
A fine-scale output offset null or dc operating point adjustment is often required. Numerous techniques are
available for introducing dc offset control into an op amp circuit. Most of these techniques eventually reduce to
adding a dc current through the feedback resistor. In selecting an offset trim method, one key consideration is
the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the
offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the
signal path is intended to be inverting, applying the offset control to the noninverting input may be considered.
However, the dc offset voltage on the summing junction sets up a dc current back into the source which must be
considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and
frequency response flatness. For a dc-coupled inverting amplifier, Figure 71 shows one example of an offset
adjustment technique that has minimal impact on the signal frequency response. In this case, the dc offsetting
current is brought into the inverting input node through resistor values that are much larger than the signal path
resistors. This insures that the adjustment circuit has minimal effect on the loop gain as well as the frequency
response.
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+5V
Supply Decoupling
Not Shown
0.1µF
328Ω
OPA698
VO
-5V
RG
500Ω
+5V
5kΩ
RF
1kΩ
VI
20kΩ
±200mV Output Adjustment
10kΩ
0.1µF
5kΩ
VO
VI
=-
RF
RG
= -2
S0050-01
-5V
Figure 71. DC-Coupled, Inverting Gain of -2, With Offset Adjustment
Board Layout Guidelines
Achieving optimum performance with the high-frequency OPA698 requires careful attention to layout design and
component selection. Recommended PCB layout techniques and component selection criteria are:
1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Open a window in the ground and
power planes around the signal I/O pins and leave the ground and power planes unbroken elsewhere.
2. Provide a high quality power supply. Use linear regulators, ground plane and power planes to provide power. Place
high frequency 0.1-µF decoupling capacitors < 0.2" away from each power-supply pin. Use wide, short traces to connect
to these capacitors to the ground and power planes. Also use larger (2.2 µF to 6.8 µF) high-frequency decoupling
capacitors to bypass lower frequencies. They may be somewhat further from the device, and be shared among several
adjacent devices.
3. Place external components close to the OPA698. This minimizes inductance, ground loops, transmission line effects
and propagation delay problems. Be extra careful with the feedback (RF), input and output resistors.
4. Use high-frequency components to minimize parasitic elements. Resistors should be a low reactance type.
Surface-mount resistors work best and allow a tighter layout. Metal film or carbon composition axially-leaded resistors
can also provide good performance when their leads are as short as possible. Never use wire-wound resistors for
high-frequency applications. Remember that most potentiometers have large parasitic capacitances and inductances.
Multilayer ceramic chip capacitors work best and take up little space. Monolithic ceramic capacitors also work well. Use
RF type capacitors with low ESR and ESL. The large power pin bypass capacitors (2.2 µF to 6.8 µF) should be tantalum
for better high frequency and pulse performance.
5. Choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel capacitance.
Good metal film or surface mount resistors have approximately 0.2-pF parasitic parallel capacitance. For resistors
> 1.5 kΩ, this adds a pole and/or zero below 500 MHz. Make sure that the output loading is not too heavy. The
recommended 402-Ω feedback resistor is a good starting point in most designs.
6. Use short direct traces to other wideband devices on the board. Short traces act as a lumped capacitive load. Wide
traces (50 to 100 mils) should be used. Estimate the total capacitive load at the output, and use the series isolation
resistor recommended in the typical performance curve, RS vs Capacitive Load. Parasitic loads < 2 pF may not need the
isolation resistor.
7. When long traces are necessary, use transmission line design techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50-Ω transmission line is not required on board—higher characteristic
impedance helps reduce output loading. Use a matching series resistor at the output of the op amp to drive a
transmission line and a matched load resistor at the other end to make the line appear as a resistor. If the 6 dB of
attenuation that the matched load produces is not acceptable and the line is not too long, use the series resistor at the
source only. This isolates the source from the reactive load presented by the line, but the frequency response is
degraded. Multiple destination devices are best handled as separate transmission lines, each with its own series source
and shunt load terminations. Any parasitic impedances acting on the terminating resistors alters the transmission line
match and can cause unwanted signal reflections and reactive loading.
8. Do not use sockets for high-speed parts like the OPA698. The additional lead length and pin-to-pin capacitance
introduced by the socket creates an extremely troublesome parasitic network. Best results are obtained by soldering the
part onto the board.
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Power Supplies
The OPA698 is nominally specified for operation using either ±5-V supplies or a single +5-V supply. The
maximum specified total supply voltage of 12 V allows reasonable tolerances on the supplies. Higher supply
voltages can break down internal junctions, possibly leading to catastrophic failure. Single-supply operation is
possible as long as common-mode voltage constraints are observed. The common-mode input and output
voltage specifications can be interpreted as required headroom to the supply voltage. Observing this input and
output headroom requirement allows design of non-standard or single-supply operation circuits. Figure 48 shows
one approach to single-supply operation.
Input and ESD Protection
ESD damage has been known to damage MOSFET devices, but any semiconductor device is vulnerable to ESD
damage. This is particularly true for high-speed, fine geometry processes. ESD damage can cause subtle
changes in amplifier input characteristics without necessarily destroying the device. In precision operational
amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, ESD handling
precautions are required when handling the OPA698.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
OPA698MJD
ACTIVE
CDIP SB
JD
Pins Package Eco Plan (2)
Qty
8
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA698M :
• Catalog: OPA698
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
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