芟Ι1≡ IΠ 天 △ 塬
Ⅱ
=纽 =口
毛兴武
摘 要 :与 传 统 两 级∷
PFc变 换 器 比较 ,单 级PFc Ac~DC变 换 器 只 采 用△ 个
开 关 和 一 个控 制 器 。单 级 PFc技 术 在 低 功 率 电 源 中 的 应 用 已 成 为 目前研
究的课 题 。
关键 词 :单 级 ,功 率 因数 校 正 ,电 路 拓 朴
,∷
1、
制 电路 ,同 时 实 现 功 率 因 数 校 正 和 对 输 出 电压
引言
的调 节 。
为减 少 办 公 白动 化 设 备 、 计 算 机 和 家 用 电器
等 内部 开 关 电源 对 电 网 的 污 染 ,国 际 电 工 委 员 会
和 — 些 国 家 与 地 区 推 出 了 |EC1000-3-2不 □
EN61O00-3-2等
标准
,对
电流 皆 波 作 出 了 限 量
规 定 。 为 满 足 输 人 电流 谐 波 限 制 要 求
单 级 PFC变 换 器 基 本 电 路 拓 朴
2、
1单 级 PFC变 换 器 基本 电路
2■
单 级 PFC变 换 器 通 常 由升 压 型PFC级 和 DC-
,最 有 效 的
DC变 换 器 组 合 而 成 。 其 中 的 DC-DC变 换 器 又
技 术 手 段 就 有 源 功 率 因数 校 正 (有 源 PFC)。
分正 激 式和 反 激 式 两 种 类 型 。 图2所 示 为基 本 的
目 前 被 广 为 采 用 的 有 源 PFC技 术 是 两 级 方
,如
图 1所 示 。
单 级 隔 离 型 正 激 式 升 压 PFC电 路 。 两 部 分 电路
共 用 — 个 开 关 (O1),通 过 =极 管 D1白 勺电流 为
PFC变 换 器 使 用 两 个 开 关 (通 常 为
MOSFET)和 两 个 控 制 器 ,即 一 个 功 率 因 数 控 制
储 能 电容 C1充 电 ,D2在 O1关 断 时 防 止 电流 倒
流 。通 过 控 制 O1白 勺通 断 ,电 路 同时完成 对AC输
器 和 一 个 PWM控 制 器 。 只 有 在 采 用 PFC/PWM组
C时 ,才 能 使 用 — 个 控 制 器 ,但 仍 需 用
合控 制器 丨
入 电流 的整 形和 对输 出 电压 的调 节 。
两 个 开 关 。 两 级 PFC在 技 术 上 十 分 成 熟
已获
路 ,瞬 时 输 入 功 率 是 随 时 变化 的 ,欲 得 到 稳 定
,但 该 方 案 存 在 电路 拓 朴 复 杂 和 成 本
的功 率 输 出 ,要 依 靠 储 能 电容 实 现 功 率 平 衡 。
案
,即
有 源 PFC升 压 变 换 器 +DC-DC变 换 器
两级
得广泛应用
,早
由于 全 波 桥 式 整 流 电路 输 入 连 接 AC供 电线
(CCM)
较 高等缺 点 。
对 于 DC-DC变 换 器 ,通 常在 连 续模 式
单 级 PFC AC— DC变 换 器 中 的 PFC级 和 DCDC级 共 用 一 个 开 关 管 ‘
不□采 用 PWM方 式 的 — 套 控
,占 空 因 数 不 随 负 载 变化 。 而 全 桥 整 流
输 出 电压 与 负 载 大 小 无 关 ,当 负 载 减 轻 时 ,输
下工作
出功 率减 小
f『
鞲
辗
琳赢 黠‰ 镒
姆
糨踔
D
蚋
∶昏:淄蠛鑫
,但 PFC级 输 入 功 率 同 重 载 时 一
脱辘风
曩
狂
图1
螂
螂
螂
蚋
螂
蚋
螂
卿
裰
两 级 PFc变 换 器 电路 级 成 框 图
41
样
,使 充 入 C|的 能 量 等 于 从 C|抽 取 的 能 量 ,引 起
直 流 总 线 电压 明 显 上 升 ,C|上 的 电压 应 力往 往 达
100O∨ 以 上 ,对 开 关器 件 的耐 压 要 求 非 常 高 。 由
于 开 关 器 件 的 电压 高 ,电 流 应 力 大 ,开 关 损 耗
大 ,并 且 功 率 从 输 入 到输 出要 经 两 次 变换 ,故 效
2改 进 型 单级 PFC变 换 器 电路
为 降低 储 能 电容 上 的高压 和 变换 器 效 率 ,必
须 对 图2所 示 的单 级 PFC基 本 电路拓 朴 进行 改进 。
—种 用 变压 器 双 线组 实现 负反
馈 的单 级
PFC变 换 器 电路 如 图3所 示 。 N1和 N2绕 组 为 变压
器T1的 耦 合 绕 组 。
当 开 关 O1导 通 时 ,电 压 ∨c1施 加 到 T1初 级 绕
数 ,增 加 电流 谐 波含 量 。如 果 在 D2与 N1之 间加
入 — 个 电感 ,使 输 入 电流 工 作 在 CCM,C1上 的
电 压 还 可 以 降 低 。 在 图 3中 。 要 求 N1+N2(
NP。
关 。在 输 入 电流 过 零 附近 ,o2导 通 ,使 附加 绕
组 N1短 路 当输 入 电压 大于 某 — 值 时 ,O2关 断 。
由于 O2在 输 入 电压 很 小 时 才 会 导 通 ,其 余 的 时
间 阻 断 ,流 过 O2白 勺电流 很 小 ,o2白 勺功 率 损耗 也
就 很 小 。 这种 电路拓 朴 与 图3电 路 比 较 ,减 小 了
器 L1上 才 会 有 电 流 通 过 。 当 O1截 止 时
,加 在
L1上 的 反 向 电压 为∨c1与 N2上 的 电压 ∨N2之 和 减 去
,提 供
了负反馈 电压 ,减 轻 了C1上 的 电压 应 力 ,提 高 了
输 入 电压 。 N1和 N2两 个 耦 合 线 圈 的 加 入
噼
率 ,降 低 了 电容
图5所 示 为 带 有 源 钳 位 和 软 开 关 的单 级 隔 离
式 PFC变 换 器 电路 。 图 中 ,O1为 主 开 关 ,O2为
辅助开关
,C1为
Cr为 o1、
o2和 电路 中寄 生 电容 之 和 。 电路 的升
鹅5
G2
:∶
∶
∶
|丨
基 本 的 单 级 隔 离式升 压 型PFC电 路
带低 频 辅 助 开 关的CCM单 级 PFc变 换 器
中囝 咆 滋 博 览
钳 位 电容
孛
;詈
;∶
,
罾L2∶
D磷
|
20O6每 叫苇 1、 2期
,C2为
压 级 工 作 在 DCM,从 而 保 证 有 较 高 的 功 率 因
i}}}∶
图4
储 能 电容
龠
勰 啻 山
妤磉
图2
,提 高 了 功 率 因 数 和 效
(C1)上 的 电压 。
输 入 电流 的 谐 波 含 量
组 。 当经 整 的 电压 大于 N1上 的 电压 时 ,升 压 电感
摒戚爨漉
鞲巍
,加 入 N1和 N2后 ,会 降 低 功 率 因
图 4示 出 了 带 低 频 辅 助 开 关 的 CCM单 级
PFC变 换 器 电 路 。 o1为 主 开 关 ,O2为 辅 助 开
率低 。
2■
效 率 。但 是
图3
G重
瞅L
用 双 绕 组 实现 页反 馈 的 单 级 PFc变 换 器
图5带 有 源 箱 位 和 软 开 关 的 单 级 隔 离式 PFC
变换 器
数 。反激 式 变换 器 级 设计 工 作 在 CCM,从 而 避 免
in波 形 为 直 角 三 角 形
输 入 电流 丨
了产 生 较 高 的 电流 应 力 。 电路 采 用 有 源钳 位 和 软
丨
in(avg)为
〓
DzoR ⑴
硕⒛
⒆
妾
壬・
开 关技 术 来 限制 开 关 MOSFET白 勺电压 应 力 。存 储
在 变压 器 漏感 中 的再 生 能量 ,为 主 开 关O1和 辅 助
开 关 O2提 供 了 软 开 关 条 件
,从 而 减 少 了开 关 损
—
耗 ,提 高 了 变换 器 效 率 。 O1不 口O2采 用 同 控 制
在 升 压 电 感 状 态 ,当 |∨ m㈦ )(∨ C1-∨ O)
时 ,T1相 当 于 — 个 升 压 电感 。 在 一 个 开 关 周 期
电路和 驱 动 电路 ,从 而使 拓 朴 结 构 简 化 。
3、
基 于 F|yboost模 块 的 单 级 PFC
内 ,当 o1导 通 时 ,T1初 级 绕 组 电感 LP经 D5充 电
AC-
器 电路 如 图 6所 示 。 该 变换 器 建 立 在 反 激 式 升 压
可表 示 为
拓 朴 基 础 上 ,工 作 状 态 分 反 激 式 变压 器 状 态 和 升
压 状 态 两 个 工 作 状 态 。 若 ∨in(t)为 Ac输 入 电压 的
D2・
yc1{l/U叫
飞・
2.助 .(yc卜
(1)和 (2)可 知 ,在 两 种 工 作 状 态
下 ,平 均 输 入 电流 均 与 输 入 电压 成 正 比 ,从 而
从式
)((∨ c1-n∨ O),
D6不 能 导通 ,储 存在T1中 的能量 全部传 送 到输 出
实 现 功 率 因 数 校 正 。 C1上 的 电 压 被 钳 位 在
端 。在 这 种 工 作 状 态 ,全 桥 整 流 输 出端 的 变换 器
(∨ in(peak)+n=∨
・Iin
V
块 |
O)电
引
基 于Flyboost模 块 的 单 级 PFc
平 上
,通
常 不超 过
i2
D8
图6
u叫
(2)
)
式 中 :D为 开 关5空 比 ,Ts为 开 关周 期 。
;
| F丨 yboost模
:
Iin(avg)=
瞬 时值 ,∨ c1为 储 能 电容 C1上 的 电压 ,n为 变压 器
T1的 电压 比 ,在 反激 式 变压 器 状 态 的 — 个 开 关 周
当O1截 止 时 , 由 I(∨ in㈦
的储 能 向
—
般 升 压 电感 型 单 级
作情况与
C1放 电 ,工
PFC变 换 器 相 同 。 在 此 状 态 下 ,平 均 输 入 电流
AC-DC变 换
期 内 ,当 开 关o1导 通 时 ,T1被 充 电 ,储 存 能量
;当 o1关 断 时 ,D6导 通 ,在 LP中
储能
DC变 换 器
基 于 F|ybOOst模 块 的 单 级 PFC
,平 均 输 入 电流
:
L1
Ac— DC变 换 器
中池咆源博 览
2006每 二.苇 1、 2期
4O0∨ 。 此 电路 拓 朴 的 功 率 因 数 — 般 可 达 0.95以
C1,对 C1进 行 充 电。
在 AC线 路 输 入 的 半 周 期 内 ,两 个 电 感 器
上 ,效 率超 过 80%。
(L1和
4、
基于
:iW2202的 数 字 单 级 PFC电 路
图 7所 示 为 基 于 数 字 控 制 器 iw2202的 单 级
PFC变 换 器 电路 。 |w2202与 本 刊 20O5年 第 11期
—
《 种 全 数 字 高 效 率 开 关 电源 》 一 文 中 介 绍 的
LP)储 存 的 能 量 平 均 值 相 等 ,从 而 使
C1上 的 电压 保 持 不 变 。 用 iw2202作 为 控 制器
,
解 决 了储 能 电容 上 电压 应 力 过 高 的 问题 。 在 通
常情 况 下
,C1上
的 电压 不 会 超 过 400∨ ,从 而
iw22O1一 样 ,采 用 了脉 冲 串 (pu|seTainTM)专
C1可 选 用 400∨ 白
勺标 准 电容 器 。 基 于 iw2202的
全 数 字 SMPS,可 以 实 现 单 位 功 率 因 数 (即
有 技 术 和 实 时 波 形 分 析 及 智 能 跳 越
PF=1)和 小 于 5%的 总谐 波 失真 (THD)。
(SmartSkip)技
术 。但是
,iw2201不
具 有
PFC功 能 ,而 iw2202集 成 了 单 级 PFC变 换 器 控 制
5、
功能。
单 级 PFC变 换 器 电路 简 单 ,但 PFC和 对 输 入
结束 语
图7所 示 的 电路桥 式 整 流 后 边 拓 朴 ,为 PFC升
电流 谐 波 抑 制 的效 果 不 如 两 级 PFC变 换 器 。 基
压 与 反 激 式 整 流 器 相 结 合 捕巳量 储 存 /DC_DC
于 全 数 字 控 制 器 iw2202白 勺单 级 全 数 字 PFC变 换
( Boost integrated vvit h F|yback
器 ,可 以 实 现 接 近 于 |的 功 率 因 数 ,输 入 电流 达
Rectifier/Energy StOrage/DC-DC'简 写 为
B丨 FRED)拓 朴 ,利 用 不 连 续 模 式 (DCM)升 压
到低 失真 指 标 :满 足 |EC1000-3-2规 定 限值 。◇
变换 器 实现 功 率 因数校 正 。 变压 器 初 级 绕 组
参考文献
[1]李 意 ,尹 华 杰 ,单 级 功 率 因数校 正 研 究
的新进展 ,电 源技 术应 用 ,⒛ 03(5)
[2]毛 兴 武 ,一 种 全数 字 高 效 率 开 关 电源
中国 电源博 览 ,⒛ 05(11),39-41
(WP)串 联 的储 能 电容 C1,用 作 驱 动 反 激 式 变
换 器 。 电路 的 工 作 原 理 如 下
:
当开 关 O1导 通 时 ,来 白AC线 路 的 能 量 被 储
存 在 升压 电感器 L1中 。 与 此 同时 ,来 白C1白 勺能 量
:
,
被 储 存在 反激 式 变压 器 T1的 初 级绕 组 中。
当O1关 断 时 ,在 T1初 级储 存 的能量 传 送 到输
出。 同时 ,在 升 压 电感 器 L1中 的能量 传 输 到 电容
85-265V
50-60Hz
lW2202
R1|
ΨD1 1
c4节 WAUx
图7
中囝 咆 源 博 览
2O06每 二.苇 1、 2期
基 于数 字控 制 器iw2202的 单 级 PFc变 换 器
iW2202
Digital SMPS Controller
Preliminary Data
1 Application
4 Description
Blue-Angel-compliant PFC-controlled switch-mode
power supplies up to 150 watts.
The iW2202 is a digital switching mode power supply
controller for PFC applications. Its is typically used
with the PFC-corrected BIFRED (Boost Integrated with
Flyback Rectifier/Energy storage DC/DC) topology,
shown in Figure 1. The BIFRED topology is a singlestage, single-switch topology that combines a boost
converter with an isolated flyback converter, achieving
power-factor correction with a low parts count.
2 Features
PulseTrain regulation allows voltage, current
and PFC to be controlled independently
Primary-only feedback eliminates optoisolators
and simplifies design
No loop compensation components required
±1% regulation over a 100:1 load variation
Built-in soft-start
Adaptive pulseTrain regulation keeps the bulk
capacitor voltage below 400V
Operates in critical discontinuous conduction
mode (CDCM)
Low start-up and supply current
Reduced EMI noise
SO-8 package
3 Benefits
Ideal for single-stage, single-switch power factor
correction (PFC)
Enables 97% power factor correction resulting in
EN6100-3-2 compliance
SmartSkip mode provides low standby dissipation
of the power supply enabling Blue Angel
Compliance
Efficiency greater than 85% across line and load
variation
Universal input (85-270V, 50-60 Hz)
Low parts count
Reduced design time due to the elimination of
loop compensation design
Revision 1.0
An iW2202-based power supply looks like a resistor to
the AC line. Unlike attempts to control the BIFRED
topology with analog controllers, the all-digital
iW2202 provides a near-unity power factor without
placing high voltage stresses on the bulk capacitor.
The iW2202 uses a proprietary new digital control
technology called pulseTrain to achieve efficiencies
in excess of 85% across a wide load range, and across
the universal input range of 85-270VAC, 50-60 Hz.
Internally, the iW2202 uses real-time waveform analysis
to determine crucial circuit parameters. The reflected
secondary voltage of the flyback transformer is sensed
at precisely calculated times to determine the
secondary voltage, the transformer reset time, and the
ideal zero-voltage switching point Measurements are
performed during the OFF time of every cycle, and the
results determine what is done on the next cycle. The
dynamic response time of the circuit is less than half a
cycle.
Boost Inductor
Auxiliary
Winding
85-270 V,
50-60 Hz
Output
AC
Input
Switch
iW2202
Flyback
Winding
Current
Sense
+
Vout
Boost
(Bulk)
Capacitor
GND
Figure 1. iW2202 system concept
Page 1
iW2202 Data Sheet
Preliminary Data
5 Pin Description
VCC
1
8
OUTPUT
VSENSE
2
7
PGND
VIN
3
6
GND
VAUX
4
5
ISENSE
iW2202
Pin #
Name
Type
Pin Description
1
VCC
Power Input
Power supply for control logic and voltage sense for power-on reset circuitry
2
VSENSE
Analog Input
Secondary voltage sense (when used with optional secondary opto-isolator feedback).
Tied to VAUX in normal configuration
3
VIN
Analog Input
Line voltage sense. Used to monitor rectified line voltage for PFC control
4
VAUX
Analog Input
Feedback voltage from auxilary winding. Used to monitor output voltage waveform
5
ISENSE
Analog Input
Primary current sense. Used for cycle-by-cycle peak-current control
6
GND
Signal Ground
Analog/digital ground
7
PGND
Power Ground
Power ground
8
OUTPUT
Digital Output
Gate driver for external MOSFET switch.
6 Absolute Maximum Ratings
PARAMETER
MIN
MAX
UNITS
Supply voltage
0
15
V
-0.3
6.3
V
800
mW
150
°C
300
°C
Input voltage on VSENSE, VIN, VAUX, ISENSE
Power dissipation at TA ≤ 25° C
Storage temperature (TSTG)
Lead temperature, while soldering for ≤ 10 seconds
Revision 1.0
-65
Page 2
iW2202 Data Sheet
Preliminary Data
7 Electrical Characteristics
Unless otherwise specified, these specifications apply for VCC = 12V, TA ≤ 70 °C. (See Note 1.)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
5
V
0.1
1
µA
1.182
1.2
1.218
V
4.75
5
FEEDBACK / AUXILIARY / PFC SECTION (Pins 2, 3, and 4)
VIR
Input voltage range
IIR
Input current range
VREF
0
Internal voltage reference (Note 2)
ISENSE SECTION (Pin 5)
ISENSE buffer gain
Input voltage
0
Input current
VSD
0.1
Output shutdown voltage (Note 3)
1.5
5.25
V/V
5
V
2
µA
5
V
OUTPUT SECTION (Pin 8)
VOL
VOH
Output low level
Output high level
ISINK = 200mA
0.5
1
V
ISINK = 20mA
0.2
0.4
V
ISOURCE = 200mA
10
11
V
ISOURCE = 20mA
10
11
V
tR
Rise time (Note 4)
TA = 25 °C, CL = 1500pF
30
50
nS
tF
Fall time (Note 4)
TA = 25 °C, CL = 1500pF
30
50
nS
5.1
6
6.9
µS
Start-up threshold (Note 1)
13.5
14
14.5
V
Min operating voltage after turn-on
9.5
10
10.5
V
1
mA
tON_MAX
Maximum switch ON time (Note 5)
START-UP SECTION (Pin 1)
VSU
SUPPLY VOLTAGE SECTION (Pin 1)
ISU
Start-up current
VCC = 13V
0.5
ICC
Supply current (operating)
10 ≤ VCC ≤ 13.2
12
VUVP
Under-voltage protection
VOVP
Over-voltage protection
7
7.8
mA
8.6
V
VSU+1.0
V
Notes:
1.
VCC must be brought aboe the start-up threshold before setting to its operating value (nominally 12V).
2.
VREF is the internal voltage reference. It is not brought out to a pin.
3.
When the voltage on the ISENSE pin exceeds VSD, all gate pulses are suppressed.
4.
Not tested, but guaranteed by design.
5.
The switch will be turned off after this amount of ON time if IPEAK has not been reached, placing a lower limit on
switching frequency.
Revision 1.0
Page 3
iW2202 Data Sheet
Preliminary Data
8 Application Example
Flyback
Windings
D6
L1
Blocking
Diode
Boost Inductor
Output Rectifier,
Filter Capacitor
T1
Snubber
D5
D4
VOUT
C2
1 Vcc
Line
Voltage
Sense
AC
Input
Auxiliary
Voltage
from Chip
Power
100-250 V,
50-60 Hz
BR1
C3
Q1
Switch
Output 8
iW2202
R1
GND 6
4 Vaux
D2
Isense 5
iWatt 2202 Digital
SMPS Controller
D1
R2
R5
R8
Bulk
Capacitor
Chip
Power
VCC
2 Vsense PGND 7
3 Vin
C1
Startup
R3
R7
D3
C4
Auxiliary
Winding
Current
Sense
R4
R6
PGND
GND
Item
Description
Q1
MOSFET switch.
L1, C1, D6
Boost converter section of the BIFRED boost/flyback system. The capacitor C1 provides the
energy for the flyback transformer. See sections 11.4 and 12.7.
T1
The flyback winding provides power to the load. The reflected voltage on the auxiliary winding is
used by the real-time waveform analysis circuit. The auxiliary winding also provides power for
the iW2202.
D1, C4, Startup
Chip power supply.
R1, R2
Voltage divider to scale the auxiliary voltage to the appropriate value. Clamping diode D2
minimizes negative voltage on the Vaux pin. See section 12.6.
R7, R8
Voltage divider for the line voltage sense circuit. Fixed values: R7= 500K, R8=1K.
R4, R5, R6
Current sense circuit. Resistor values set the peak current. See section 12.3.1.
Figure 2. iW2202 -based power supply with single-stage, single-switch active PFC
Revision 1.0
Page 4
iW2202 Data Sheet
Preliminary Data
9 Block Diagram
V CC
PowerOn
Reset
Voltage
Reg.
Waveform
Analyzer
Control Logic
ISENSE
Primary Current
Sense
VAUX
Reflected Voltage
Waveform Detect
VSENSE
(Opt.) Secondary
Voltage Sense
VIN
PFC Line Voltage
Sense
Cycle Selection
• Power
• Sense
• Skip
Cycle Timing
• Rising Edge (ZVS)
• Falling Edge (Constant Ipeak)
Driver
Output
PGND
GND
Figure 3. Conceptual block diagram of the iW2202
PulseTrain
State
Switch
State
Cycle n
Cycle n+1
Cycle n+2
Cycle n+3
Power Cycle
Sense Cycle
Power Cycle
Sense Cycle
ON
OFF
ON
tn
OFF
ON
OFF
ON
tn+2
tn+1
OFF
tn+3
VAUXThreshold
VAUX
High
Low
High
Low
The voltage on the auxiliary winding, VAUX, is measured at a point near the end of the OFF period. This voltage is compared to
the VAUX threshold. If it is higher, the next cycle is a sense cycle. Otherwise, the next cycle is a power cycle.
Figure 4. Power pulses, sense pulses, and the reflected secondary voltage on the auxiliary winding
Revision 1.0
Page 5
iW2202 Data Sheet
Preliminary Data
10 PulseTrain Regulation
Rather than using pulse-width or pulse frequency
modulation to achieve output voltage regulation,
pulseTrain controls output voltage through the
presence or absence of power pulses. If the output
voltage is below the desired level, power pulses are
emitted continuously until the desired level is
reached. If the output voltage is higher than the
desired level, sense pulses are sent instead of power
pulses. A sense pulse has a much shorter ON time
than a power pulse, and transfers much less energy.
See Figure 4.
It is important to recognize that pulseTrain does not
depend on the precise width of the pulses to
maintain regulation. If the output voltage is lower
than the desired level, the next cycle will contain a
power pulse. If the output voltage is above the
desired limit, the next cycle will contain a sense
pulse. The pulseTrain controller will optimize the
ratio of power pulses to sense pulses to keep the
output voltage constant. The frequency and duty
cycle of the pulses can change, but this does not
affect voltage regulation.
A sense cycle has the same period as the preceding
power cycle, but the ON time is set to one-fourth
that of the power cycle. Since primary current ramps
linearly with ON time, the peak current of a sense
pulse is also only one-fourth that of a power pulse.
Thus, a sense cycle only transfers one-sixteenth as
much energy as a power cycle.
This situation is very different from the situation
with analog technologies, such as PWM/PFM-based
controllers, which are forced to attempt to meet all
their goals through the adjustment of pulse
geometry, which forces unwanted trade-offs.
Under most load conditions, regulation is achieved
through a mix of power cycles and sense cycles.
Under extremely low-load conditions, no power
pulses are sent. Instead, sense cycles alternate with
skip cycles.
As will be shown in the next section, pulseTrain
modulation takes full advantage of its ability to
pursue multiple simultaneous goals, combining the
flexibility of pulseTrain regulation with the
precision of real-time waveform analysis, resulting
in ultra-fast dynamic response and simplified circuit
design.
11 Real-Time Waveform Analysis
Figure 5 shows the effect of a sense pulse on the
transformer’s primary winding, measured at Vdrain.
As you can see, this waveform contains quite a bit of
ringing. This ringing is highly organized, consistent
from cycle to cycle, and its onset pinpoints
important events in the cycle.
Real-time waveform analysis uses the information in
the reflected voltage to extract secondary voltage
and transformer reset time. These voltage
measurements are made on every cycle, and each
cycle’s measurement determines the next cycle’s
pulse type.
In a flyback system, the reflected voltage seen
during the switch’s OFF time reveals the secondary
voltage, plus additional circuit information,
including leakage inductance, transformer reset
time, resonant frequency, and secondary diode
characteristics. All this information is easily read on
an auxiliary winding. This information renders
secondary feedback unnecessary.
Traditional voltage regulators use space-average
sensing, averaging the voltage over multiple cycles.
This causes the loss of a great deal of information
and introduces delays, slowing the response of the
controller and raising the issue of loop instability.
Real-time waveform analysis, on the other hand,
does not perform averaging, but determines the next
cycle’s switching decisions from the current cycle
alone. The time delay between measurement and
correction (dynamic response) is thus extremely
short, being less than the OFF time of a single cycle.
The system is inherently stable. There is no need for
loop compensation.
The choice between reading the reflected voltage on
the primary winding or on an auxiliary winding is
somewhat arbitrary. If taken from the primary, the
voltage centers around Vin (the instantaneous line
voltage). If taken from an auxiliary winding, the
voltage centers around zero. The auxiliary winding
can also provide power for the device.
Revision 1.0
Page 6
iW2202 Data Sheet
Switch
State
Preliminary Data
ON
OFF
Ringing due to leakage
inductance. The OFF time of a
sense pulse must be wider than
the decay time of this waveform.
Voltage is
measured
here
VDRAIN = VIN+(VOUT+∆V)*NPRI/NSEC
∆T
The slope of this reflected voltage
represents the voltage-current
characteristics of the secondary side.
If the voltage is read at a consistent
time before the transformer is fully
discharged, this ∆V is a constant, and
we achieve a very accurate reading of
the secondary output voltage.
TCDS
VDRAIN
VIN
0
TCDS is the OFF-time that will
achieve critically discontinuous
conduction mode and zerovoltage switching. In iWatt
products, this time is measured
with every sense pulse.
Secondary
Diode Current
This ringing is due to the
resonance of the
magnetizing inductance and
switch capacitance, and
TRES/2
indicates a fully reset
transformer. Resonance is
easily detected when voltage
TRES/4
excursions cross VIN. Two
successive crossings give
TRES/2. Very consistent from
cycle to cycle.
If the transistor is switched back on at
this point, we will come very close to
∆T
true zero-voltage switching. In addition,
we will achieve critically discontinuous
conduction mode; that is, we will
eliminate dead time between cycles
while guaranteeing that we remain in
discontinuous mode.
This value of ID2
will always be the
same, given a
constant ∆T.
Figure 5. Information available to waveform analysis
Revision 1.0
Page 7
iW2202 Data Sheet
Preliminary Data
11.1 Zero-Voltage Switching
traditional technologies, resulting in lower core
losses and thus higher efficiencies.
PulseTrain achieves zero-voltage switching (ZVS) by
using the resonance (ringing) that occurs in
discontinuous-mode flyback circuits. This resonance
occurs after the secondary current falls to zero,
indicating the transition from power transfer to
open-circuit conditions.
Because the waveform is being monitored in real
time, critically discontinuous conduction mode is
maintained across all variations in line and load
conditions. In addition, this method of extracting
maximum performance from the inductor is
insensitive to component variations, since the circuit
behavior is measured, not assumed.
Post-Conduction
Resonance
Vaux = Vout*Nsec/Naux
Vaux=0
t1
t2
Vaux = -Vin*Npri/Naux
ZVS Algorithm (Power Cycles):
1. Wait for Vaux < 0
2. Wait an additional tZVS
3. Turn on switch
tZVS = (t2-t1)/2
tZVS is measured on
sense cycles
Figure 6. Auxiliary voltage and zero-voltage switching
As shown in Figure 5, post-conduction resonance is
a damped oscillation that falls very close to zero
volts on its first cycle. Zero-voltage switching can be
achieved very easily, simply by measuring the
resonant period on a sense cycle, and switching the
output transistor when the voltage is closest to zero
on subsequent power cycles.
The algorithm for ZVS is shown in Figure 6. On each
power cycle, pulseTrain waits for the primary
voltage to drop below VIN, (on the auxiliary
winding, this occurs when the voltage goes
negative). This indicates that we are in the postconduction resonance. After this event, the
controller waits an additional ∆T that will take us to
the minimum voltage, then turns on the switch for
the next power or sense cycle. The time between the
zero-crossing on the auxiliary winding and the
minimum primary voltage is estimated as being
one-half the time between the negative-going zero
crossing and the positive-going zero-crossing, as
shown in Figure 6. Given the geometry of the
resonant signal, this estimate is extremely accurate.
By achieving zero-voltage switching, we also
achieve critically discontinuous conduction mode,
because we have turned the transistor back on
immediately after the transformer’s magnetic field
has reset. This eliminates dead time between cycles,
fully utilizing the output transformer. As a result,
the transformer operates at lower flux levels than
Revision 1.0
11.2 Primary-Only Feedback
PulseTrain uses primary-only feedback, measuring
the secondary voltage by analyzing its reflected
voltage as seen by an auxiliary winding. This
reflection reveals what is happening at the
transformer secondary. However, the voltage at the
load differs from the secondary voltage by a diode
drop and IR losses. The diode drop is a function of
current, as are IR losses. Thus, if the secondary
voltage is always read at a constant secondary
current, the difference between the output voltage
and the secondary voltage will be a fixed ∆V.
Furthermore, if the voltage can be read when the
secondary current is small, the ∆V will also be small.
As shown in Figure 5, secondary current has a linear
ramp down to zero. Zero secondary current is
signaled (on the reflected voltage waveform) by the
beginning of post-conduction resonance. Using
resonance as a marker, is a simple matter to
calculate a fixed ∆T that will pinpoint a time where
secondary diode current is still flowing, but is very
small. The exact value of ∆T is not crucial, so long as
it places the measurement at a point where current
is still nonzero. ∆T is recalculated on sense cycles.
Measuring voltage on sense cycles uses the same ∆T
as on power cycles. Because the slope of the
secondary current ramp is independent of ON time,
the current at a fixed ∆T is the same, regardless of
whether the cycle is a sense cycle or a power cycle.
11.3 Constant Peak Current
Like the decision to turn the transistor on, the
decision to turn the transistor off is controlled by
real-time waveform analysis -- this time in the
current domain. The maximum desirable primary
current, Ipeak, is set with external resistors.
On every power cycle, the power transistor is kept
on until the primary current ramps up to Ipeak.
When this level is reached, the transistor is turned
Page 8
iW2202 Data Sheet
Preliminary Data
off. Thus, the point at which the transistor is turned
off is controlled by the current waveform, while the
point at which it is turned on is controlled by the
voltage waveform.
If the line voltage is very high, the current will ramp
up quickly, and the ON time of the switch will be
short. If the line voltage is very low, the current will
ramp slowly, and the ON time will be long.
ON
OFF
ON
OFF
ON
OFF
Vdrain
Iswitch
Isec
Low line voltage results in longer ON times before peak
current is reached, resulting in long cycle times (and
relatively low switching frequencies). Critically discontinuous
mode is maintained.
components and the design time they represent are
eliminated.
11.4 Power Factor Correction
One very welcome result of the pulseTrain
methodology is that topologies that have proven
problematical with PWM/PFM controllers work
smoothly with pulseTrain.
For example, the iW2202 is ideal for use in the
inherently PFC-corrected BIFRED (Boost Integrated
with Flyback Rectifier/Energy Storage/DC-DC)
topology. The basic BIFRED topology uses a
discontinuous mode boost converter to achieve PFC.
The capacitor of the boost converter is used as a bulk
capacitor to drive a flyback converter. BIFRED uses
a single switch. See Figure 8.
Flyback
Windings
L1
T1
D5
Boost Inductor
C2
ON
OFF
ON
OFF
ON
VOUT
OFF
Vdrain
Q1
Switch
C1
Bulk
Capacitor
Iswitch
Isec
High line voltage results in shorter ON times, because peak
current is reached more quickly. Short ON times lead to
short cycle times (high switching frequency). Critically
discontinuous mode is maintained.
Figure 8. BIFRED circuit
Figure 7. Constant peak current switching
The circuit operates as follows:
Because of this, the output frequency of the
pulseTrain regulator varies to accommodate
changing line voltage.
Switch on: Energy derived from the AC line is stored
in the boost inductor. At the same time, energy
derived from the bulk capacitor is stored in the
primary of the flyback transformer.
The dynamic response to changing load conditions
is very fast. The time between measurement and
action is only a fraction of a power cycle. The
voltage measurement comes during the switch OFF
time of every cycle, and controls the ON time
switching decision for the very next cycle.
PulseTrain therefore reacts almost instantaneously
to changes in load and line conditions.
The mechanism of real-time waveform analysis
provides inherent stability without the need for loop
compensation. The expense of loop compensation
Revision 1.0
Switch off: The energy in the flyback primary is
transferred to the output. At the same time, the
energy in the boost inductor is delivered to the bulk
capacitor, charging it.
If the two inductors store the same amount of
energy, on average, over the course of a half-cycle of
the AC input, the voltage of the bulk capacitor will
remain constant. The iW2202 achieves this goal,
avoiding the problem of high voltage stresses on the
bulk capacitor. With traditional controllers (such as
modified PFM), the bulk capacitor voltages tend to
Page 9
iW2202 Data Sheet
Preliminary Data
become very high under some line and load
conditions. With the iW2202, the voltages remain
under 400V at all times, allowing standard
capacitors to be used. This is a direct benefit of using
pulseTrain technology.
Both the boost stage and the flyback stage operate in
discontinuous mode. This means that both inductors
are fully reset once per switching cycle. The energy
stored in the boost inductor is completely
transferred to the bulk capacitor, and the energy
stored in the flyback transformer is completely
transferred to the load.
this, the device enters SmartSkip mode, when the
circuit alternates between sense pulses and no
pulses at all.
Regulation is still maintained, since each sense pulse
returns a precise measurement of output voltage.
SmartSkip mode is entered automatically when the
sense pulses reveal that the output voltage is
remaining above the desired level, though no power
pulses have been sent recently.
The depth of the SmartSkip mode (the ratio of
skipped cycles to sense pulses) is increased or
decreased, according to voltage and the current
skip-mode depth. The depth of the SmartSkip mode
is reduced automatically as the load increases.
Normal Mode
(Power Pulses and
Sense Pulses)
Input Current
SmartSkip Mode (Sense
Pulses and Skipped Pulses)
Vgate
Input Voltage
Vpri
Figure 9. Power factor correction example
11.5 SmartSkip Mode
Figure 11. Depth of SmartSkip increasing with light load
11.6 Soft-Start and Protection
Vgate
SmartSkip
Sense
Pulses
Power
Pulses
Sense
Pulses
Smart
Skip
Vpri
Figure 10. SmartSkip mode
As has already been mentioned, a sense pulse
delivers one-sixteenth as much energy as a power
pulse. A continuous stream of sense pulses thus
delivers 6.25% of full load. If the load is lighter than
Revision 1.0
In pulseTrain, all output switching occurs as the
result of the pulseTrain logic. If the logic is not up
and running, the output switch is always off. Valid
waveform analysis is available by the second power
pulse. This reduces the problem of soft-start merely
to the requirement that there be a reliable power-on
reset mechanism.
Figure 12 shows what happens on the output at
start-up. The first power pulse shows a clean current
ramp, but the drain voltage reflects the fact that the
transformer does not reset by the time the second
pulse arrives, and thus is operating in continuous
mode. This is also shown in the current on the
second pulse, which starts at a non-zero value.
However, pulseTrain’s automatic peak current
limiting causes the second power pulse to be much
shorter than the first one. By the third cycle, the
initial current has already fallen significantly, due to
Page 10
iW2202 Data Sheet
the second cycle’s shorter ON time. This trend will
continue until, in a few cycles, the initial current is
zero and the transformer is operating in critically
discontinuous mode.
Vgate
Preliminary Data
The nominal VCC voltage of the device is 12 volts. It
requires a start-up voltage that reaches 14
momentarily, initiating a start-up sequence
internally. The device protects itself from overvoltage by shutting itself down if VCC exceeds 15
volts. Its under-voltage lockout circuit will cause it
to shut itself down if the voltage drops below 7.8
volts, and will remain shut down until the start-up
voltage is seen again. Both over- and under-voltage
shutdowns inhibit switching on the OUTPUT pin.
These mechanisms protect the device, while
protecting the rest of the circuit indirectly.
Vdrain
Ipri
Additional protection can be achieved with external
sensors that shut down the iW2202 on a circuit
fault. The best way of shutting down the iW2202 is
to pull the Isense pin above 1.5V. This will inhibit
output pulses.
Figure 12. Example of current limiting during start-up
12 Designing iW2202 -Based Power Supplies
The schematic in Figure 2 shows a typical iW2202
system. Choosing component values is a
straightforward process, as shown in the example
below.
and the highest input voltage for our worst-case
calculation:
Vd_max = Vline_max + N*Vsec
N = (Vd_max – Vline_max)/Vsec
12.1 Description
For this example, we are designing an 70W, 19V
laptop computer power supply. It is a universal
input supply supporting input line voltages of 85265 VRMS, and operating in discontinuous flyback
mode. To keep component costs low, we wish to use
a switch with a maximum Vdrain of no more than
600V.
12.2 Primary Turns Ratio
The voltage across a flyback switch includes the
input voltage plus the reflected secondary voltage:
Vd = Vin + N*Vout.
The turns ratio between the primary and secondary,
N, is constrained by our desire to avoid stressing
the switch. We use the maximum safe value of Vd
Revision 1.0
12.2.1 Example
If we use a 600V switch and derate it by 100V as a
safety margin, we are left with 500V as our
maximum drain voltage, Vd_max.
N = (500V-380V)/19.7V = 6.09 ≈ 6.
12.3 Ipeak Selection
We next need to calculate the peak current value we
need to support worst-case operation. The constant
peak current circuitry will keep the output switch on
until this value is reached on every power cycle.
Iin is the average input current to the converter:
Iin = Po/(Vin*η)
Where η is the efficiency of the converter. Vsec is the
secondary voltage. It differs from the output voltage,
Page 11
iW2202 Data Sheet
Preliminary Data
Vout, by a fixed ∆V, where ∆V is the secondary
diode drop. We will use 0.7V for ∆V, and thus a
Vsec of 19.7V in our example.
Resistors R4, R5, and R6 are chosen to scale the
voltage accordingly.
The maximum input current we must support
occurs at minimum supported line voltage:
Example
Iin = Po/(Vin_min* η)
Vin_min = Vline_min*1.4142
Vline_min is the lowest supported RMS line voltage.
Full-load efficiency can be taken as a (slightly
conservative) 0.80 for design purposes.
We need to convert the average input current Iin
into a peak input current Ipeak. This depends on the
duty cycle, D, of the switch and the shape of the
primary current waveform (a triangle wave with a
peak value of twice the average value):
Ipeak = 2*Iin/D
At low line voltage, D is:
D_ll = ton_ll/(ton_ll+toff_ll)
We choose 0.1 Ω for R6.
The voltage across R6 at Ipeak is:
0.1*2.94 = 0.294 V.
We need the voltage at the Isense pin, Vc_pk, to be
1.2/5 or 0.24 when Ipeak is reached. If we choose R4
to be 2.2 K Ω, then
R5 = R4*(Ipeak*R6*gain – Vref)/Vref = 495
12.4 Primary Inductance
The inductance of the primary winding is based on
the lowest supported line voltage, the longest ON
time, and the peak current:
Lp = Vin_min * Ton_max/Ipeak
Ton_ll is the maximum on time, which we will set to
5.5 µs. (The device will limit the ON time to 6 µs if
Ipeak is not reached.)
Example
Since, in a critically discontinuous-mode flyback
converter, the net transformer volt-seconds are zero:
Lp = 120.21 * 5.5x10-6 / 2.94 = 225 µH
Vpri*ton = N*Vsec*toff,
12.5 Auxiliary Turns Ratio
We can solve for toff:
Our design calls for an Lp of
toff_ll = Vin_min*ton_ll/(N*Vsec)
The turns ratio between secondary and auxiliary
winding is set to give 12V output plus a 0.6V diode
drop to provide power to the chip:
Example
Naux/Nsec = 12.6/Vout
Vin_min = 85*1.4142 = 120.21 V
toff_ll = 120.21*5.5x10-6/(6*19.7) = 5.6x10-6s
Iin = 70/(120.21*0.80) = 0.728 A
D_ll = 5.5x10-6s/(5.5x10-6s+5.6x10-6s) = 0.495
f_sw = 1/(5.5x10-6s+5.6x10-6s) = 90 Khz
Ipeak = 2*0.728/0.495 = 2.94 A
12.6 Vaux Resistors
The output voltage is set by the resistor divider, R1
and R2, across the auxiliary winding voltage
(Vauxw). The divided voltage is fed into the Vaux
pin. A Schottky diode, D2, is used as a clamping
diode in parallel with R2, to minimize negative
voltages on the Vaux pin.
12.3.1 Ipeak Resistors
Vsec = Vauxw * (Nsec/Naux)
The Ipeak resistors consist of a sense resistor (R6)
and a voltage divider (R4 and R5). The Isense pin is
a voltage amplifier with a gain of 5.0 that compares
the amplified voltage to a reference of 1.2V.
Voltage regulation is controlled by the resistor
divider and the iW2202’s internal voltage reference,
which is fixed at 1.2V. The voltage on the Vaux pin
is compared with the reference by the real-time
waveform analysis circuitry. If it is above this level,
Revision 1.0
Page 12
iW2202 Data Sheet
the next cycle will be a sense cycle. If it is below this
level, the next cycle will be a power cycle:
Vauxw = Vref * (R1+R2)/R2
Vsec = 1.2* (( R1+R2)/R2 * (Nsec/Naux))
Preliminary Data
Other implementations of the BIFRED technology
operate at elevated capacitor voltages, but this does
not occur with a pulseTrain controller.
The size of the bulk capacitor is based on ripple
voltage requirements. We have used 2µf per watt of
output power as a starting point.
Example
Continuing our example, we see that Nsec/Naux =
19.7/12.6.
Example
In our design:
To find R1 and R2, we first note that:
L1 = 0.80*225µH/2 = 90 µH
Vauxw = Vref(1 + R1/R2) ,
C1 = 2.0*70 = 140 µF
R1 = (Vauxw –Vref)*R2/Vref
If we arbitrarily set R2 to 1.1 kΩ, we have:
R1 = (12.6 - 1.2)*1100/1.2 = 10.45 kΩ
12.7 PFC Choke and Capacitor
12.8 Vin Resistors
The pin sensing line voltage uses a fixed resistor
divider consisting of R7 and R8. R7 = 500 KΩ; R8 = 1
KΩ.
In the BIFRED topology used in this design, there is
a definite relationship between the flyback primary
inductance (Lp), the boost inductance (L1), and the
boost capacitor (C1) voltage:
12.9 Conclusion
L1 = (η *Vin_rms2*L2)/Vc12
In particular, note the complete absence of loop
compensation, eliminating the time and costs
associated with loop compensation design.
We would like the bulk capacitor voltage to be no
more than the peak input voltage:
Vc1 = Vin_rms* 2
By substituting Vin_rms* 2 for Vc1, we get:
L1 = η *Lp/2
Revision 1.0
This example shows the simplicity of designing a
power supply with an iWatt pulseTrain controller.
We have also eliminated optoisolators and their
associated feedback circuitry, reducing costs and PC
board area.
Finally, PFC features have been added with a
minimum of cost and design effort.
Page 13
iW2202 Data Sheet
Preliminary Data
13 Physical Dimensions
Figure 13. Physical dimensions, SO-8 package
14 About iWatt
iWatt Inc. is a fabless semiconductor company that
develops power management ICs for computer,
communication, and consumer markets. The
company’s patented pulseTrain ™ technology, the
industry’s first truly digital approach to power
system regulation, is revolutionizing power supply
design.
Trademark Information
iWatt and pulseTrain are trademarks of iWatt, Inc.
Contact Information
Web: http://www.iwatt.com
E-mail: [email protected]
Phone: 408-374-4200
Fax: 408-341-0455
iWatt Corporation
90 Albright Way
Los Gatos CA 95032
Revision 1.0
Disclaimer
iWatt reserves the right to make changes to its
products and to discontinue products without
notice.
Certain applications using semiconductor products
may involve potential risks of death, personal injury,
or severe property or environmental damage
("Critical Applications").
IWATT SEMICONDUCTOR PRODUCTS ARE NOT
DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS, OR OTHER CRITICAL APPLICATIONS.
Inclusion of iWatt products in critical applications is
understood to be fully at the risk of the customer.
Questions concerning potential risk applications
should be directed to iWatt through an iWatt sales
office.
iWatt semiconductors are typically used in power
supplies in which high voltages are present during
operation. High-voltage safety precautions should
be observed in design and operation to minimize the
chance of injury.
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