TI TLC5973DR

TLC5973
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SBVS225A – MARCH 2013 – REVISED MAY 2013
3-Channel, 12-Bit, PWM Constant-Current LED Driver
with Single-Wire Interface ( EasySet™)
Check for Samples: TLC5973
FEATURES
APPLICATIONS
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23
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Three Constant Sink Current Channels
Current Capability:
– 2 mA to 35 mA per Channel (VCC ≤ 4.0 V)
– 2 mA to 50 mA per Channel (VCC > 4.0 V)
Grayscale (GS) Control with PWM:
– 12-Bit (4096 Steps)
Single-Wire Interface (EasySet)
Power-Supply (VCC) Voltage Range:
– 3 V to 6 V
OUT Terminals Maximum Voltage: Up to 21 V
Integrated Shunt Regulator
Data Transfer Maximum Rate:
– Bits per Second (bps): 3 Mbps
Internal GS Clock Oscillator: 12 MHz (typ)
Display Repeat Rate: 2.9 kHz (typ)
Output Delay Switching to Prevent Inrush
Current
Unlimited Device Cascading
Operating Temperature: –40°C to +85°C
RGB LED Cluster Lamp Display
DESCRIPTION
The TLC5973 is an easy-to-use, 3-channel, 50-mA
constant sink current LED driver. The single-wire, 3Mbps serial interface (EasySet) provides a solution
for minimizing wiring cost. The LED driver provides 8bit pulse width modulation (PWM) resolution. The
display repeat rate is achieved at 2.9 kHz (typ) with
an integrated 12-MHz grayscale (GS) clock oscillator.
The driver also provides unlimited cascading
capability.
All output sink constant currents can be set by an
external resistor. The TLC5973 has an internal shunt
regulator that can be used for higher VCC powersupply voltage applications.
VCC
Power
Supply
(5 V)
GND
GND
VCC
IREF
OUT0
RIREF
Device
OUT1
GND
VCC
IREF
OUT0
RIREF
Device
OUT2
Controller
SDI
SDO
OUT1
OUT2
SDI
SDO
Figure 1. Typical Application Circuit Example 1 (No Internal Shunt Regulator Mode)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EasySet is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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TLC5973
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DESCRIPTION (CONTINUED)
LED
Lamp
Power
Supply
VLED
Device and
Controller
Power
Supply
VCC
GND
GND
VCC
IREF
OUT0
RIREF
Device
Optional
GND
VCC
IREF
OUT0
RIREF
OUT1
Device
SDI
OUT1
OUT2
OUT2
Controller
Optional
SDI
SDO
SDO
Figure 2. Typical Application Circuit Example 2 (No Internal Shunt Regulator Mode)
VLED
Power
Supply
GND
+5 V
RVCC
RVCC
CVCC
CVCC
GND
VCC
IREF
OUT0
RIREF
Device
OUT1
Optional
GND
VCC
IREF
OUT0
RIREF
Device
OUT2
Controller
SDI
Optional
OUT1
OUT2
SDI
SDO
SDO
Figure 3. Typical Application Circuit Example 3 (Internal Shunt Regulator Mode)
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
TLC5973
(1)
SO-8
ORDERING
NUMBER
TRANSPORT MEDIA
TLC5973DR
Tape and Reel
TLC5973D
Tube
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
Voltage (2)
MAX
UNIT
Supply, VCC
VCC
–0.3
+7.0
V
Input range, VIN
SDI
–0.3
VCC + 1.2
V
OUT0 to OUT2
–0.3
+21
V
SDO
–0.3
+7.0
V
Output range, VOUT
Current
Output (dc), IOUT
Temperature
Electrostatic discharge (ESD) ratings:
(1)
(2)
OUT0 to OUT2
MIN
0
+60
mA
Operating junction, TJ
–40
+150
°C
Storage, Tstg
–55
+150
°C
Human body model (HBM)
8000
V
Charged device model (CDM)
2000
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
THERMAL INFORMATION
TLC5973
THERMAL METRIC
(1)
D
(SO)
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance
134.6
θJCtop
Junction-to-case (top) thermal resistance
88.6
θJB
Junction-to-board thermal resistance
75.3
ψJT
Junction-to-top characterization parameter
37.7
ψJB
Junction-to-board characterization parameter
74.8
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
3.0
5.0
UNIT
DC CHARACTERISTICS
5.5
V
Internal shunt regulator mode
6.0
V
Voltage applied to output
OUT0 to OUT2
21
V
VIH
High-level input voltage
SDI
0.7 × VCC
VCC
V
VIL
Low-level input voltage
SDI
GND
0.3 × VCC
V
VIHYST
Input voltage hysteresis
SDI
IOH
High-level output current
SDO
–2
mA
SDO
2
mA
VCC
Supply voltage
VO
IOL
Low-level output current
No internal shunt regulator mode
0.2 × VCC
V
OUT0 to OUT2 (VCC ≤ 4.0 V)
2
35
mA
OUT0 to OUT2 (VCC > 4.0 V)
2
50
mA
IREG
Shunt regulator sink current
20
mA
TA
Operating free-air temperature range
VCC
–40
+85
°C
TJ
Operating junction temperature range
–40
+125
°C
kHz
AC CHARACTERISTICS
fCLK
Data transfer rate
SDI
100
3000
tSDI
SDI input pulse duration
SDI
60
0.5 / fCLK
tWH
Pulse duration, high
SDI
14
tWL
Pulse duration, low
SDI
14
tH0
Hold time: end of sequence (EOS)
SDI↑ to SDI↑
3.5 / fCLK
tH1
Hold time: data latch (GSLAT)
SDI↑ to SDI↑
8 / fCLK
4
(SDI)
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ns
ns
ns
5.5 / fCLK
µs
µs
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ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, VCC = 3 V to 6.0 V, and CVCC = 0.1 µF. Typical values at TA = +25°C and VCC = 5.0 V, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage (SDO)
IOH = –2 mA
VOL
Low-level output voltage (SDO)
IOL = 2 mA
VIREF
Reference voltage output
RIREF = 1.5 kΩ
VR
Shunt regulator output voltage (VCC)
ICC = 1 mA, SDI = low
MAX
UNIT
VCC – 0.4
MIN
VCC
V
0
0.4
V
1.23
V
1.18
TYP
1.20
5.9
V
ICC0
VCC = 3.0 V to 5.5 V , SDI = low, all grayscale (GSn) =
FFFh, VOUTn = 1 V, SDO = 15 pF, RIREF = 27 kΩ
(IOUTn = 2-mA target)
3
6
mA
ICC1
VCC = 3.0 V to 5.5 V, SDI = low, all grayscale (GSn) =
FFFh, VOUTn = 1 V, SDO = 15 pF, RIREF = 3 kΩ
(IOUTn = 17-mA target)
4
7
mA
ICC2
VCC = 3.0 V to 5.5 V, SDI = 5 MHz, all grayscale
(GSn) = FFFh, VOUTn = 1 V, SDO = 15 pF,
RIREF = 3 kΩ (IOUTn = 17-mA target)
5
8
mA
ICC3
VCC = 3.0 V to 5.5 V, SDI = 5 MHz, all grayscale
(GSn) = FFFh, VOUTn = 1 V, SDO = 15 pF,
RIREF = 1.5 kΩ (IOUTn = 34-mA target)
5.5
10
mA
34
37
mA
TJ = –40°C to +85°C
0.1
μA
TJ = +85°C to +125°C
0.2
μA
Supply current (VCC)
IOLC
Constant output current
(OUT0 to OUT2)
All OUTn = on, VOUTn = 1 V, VOUTfix = 1 V,
RIREF = 1.5 kΩ
IOLKG
Output leakage current
(OUT0 to OUT2)
GSn = 000h, VOUTn = 21
V
ΔIOLC0
Constant-current error
(channel-to-channel) (1)
All OUTn = on, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
±0.5%
±3%
ΔIOLC1
Constant-current error
(device-to-device) (2)
All OUTn = on, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
±0.5%
±6%
ΔIOLC2
Line regulation of constant-current
output (3)
All OUTn = on, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
±0.5
±1
%/V
ΔIOLC3
Load regulation of constant-current
output (4)
All OUTn = on, VOUTn = VOUTfix = 1 V, RIREF = 1.5 kΩ
±0.5
±1
%/V
RPD
Internal pull-down resistance (SDI)
At SDI
(1)
31
1
MΩ
The deviation of each output (OUT0 to OUT2) from the constant-current average. Deviation is calculated by the formula:
IOUTn
D (%) =
-1
IOUT0 + IOUT1 + IOUT2
´ 100
3
(2)
where n = 0 to 2.
Deviation of the constant-current average in each color group from the ideal constant-current value. Deviation is calculated by the
formula:
IOUT0 + IOUT1 + IOUT2
D (%) =
3
- Ideal Output Current
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
IOUTn(IDEAL) (mA) = 43.4 ´
(3)
where n = 0 to 2.
Line regulation is calculated by the formula:
D (%/V) =
(4)
1.20
RIREF (W)
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V)
IOUTn at VCC = 3.0 V
´
100
5.5 V - 3.0 V
where n = 0 to 2.
Load regulation is calculated by the equation:
D (%/V) =
(IOUTn at VOUTn = 3.0 V) - (IOUTn at VOUTn = 1.0 V)
IOUTn at VOUTn = 1.0 V
´
100
3.0 V - 1.0 V
where n = 0 to 2.
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SWITCHING CHARACTERISTICS
At TA = –40°C to +85°C, VCC = 3.0 V to 5.5 V, CL = 15 pF, RL = 110 Ω, and VLED = 5.0 V, unless otherwise noted.
Typical values are at TA = +25°C and VCC = 5.0 V.
PARAMETER
MIN
TYP
MAX
2
6
12
ns
200
400
ns
6
12
ns
200
400
ns
SDI↑ to SDO↑
30
50
ns
Propagation delay
OUT0↓ to OUT1↓, OUT1↓to OUT2↓,
OUT0↑ to OUT1↑, OUT1↑to OUT2↑
25
tWO
Shift data output one pulse duration
SDO↑ to SDO↓
fOSC
Internal GS oscillator frequency
tR0
tR1
tF0
tF1
TEST CONDITIONS
SDO
Rise time
OUTn (on → off)
SDO
Fall time
OUTn (off → on)
tD0
tD1
2
UNIT
ns
15
25
45
ns
8
12
16
MHz
PARAMETER MEASUREMENT INFORMATION
PIN-EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
SDI
SDO
GND
GND
Figure 4. SDI
Figure 5. SDO
OUTn
(1)
GND
(1) n = 0 to 2.
Figure 6. OUT0 Through OUT2
6
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TEST CIRCUITS
RL
VCC
VCC
OUTn
IREF
RIREF
VCC
(1)
VLED
(2)
VCC
CL
GND
SDO
IREF
RIREF
GND
(1)
CL
(1) n = 0 to 2.
(1) CL includes measurement probe and jig capacitance.
(2) CL includes measurement probe and jig capacitance.
Figure 7. Rise Time and Fall Time Test Circuit for
OUTn
VCC
Figure 8. Rise Time and Fall Time Test Circuit for
SDO
SDO
VCC
IREF
RIREF
OUTn
GND
(1)
SDO
VOUTfix
VOUTn
(1) n = 0 to 2.
Figure 9. Constant-Current Test Circuit for OUTn
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TIMING DIAGRAMS
tWH, tW L
VCC
SDI
(1)
50%
tW H
tH0, tH1
1st Data of Next Device (tH0 case) or
1st Data of Next Sequence (tH1 case).
48th Data
SDI
GND
tW L
VCC
(1)
50%
GND
tH0, tH1
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 10. Input Timing
tR0, tF0, tD0, tW 0
VCC
(1)
SDI
50%
GND
tD0
tW0
VOH
90%
SDO
50%
10%
tR0
VOL
tF0
tR1, tF1, tD1
VOUTnH
OUTn
50%
VOUTnL
tD1
tD1
VOUTnH
90%
OUTn + 1
50%
10%
VOUTnL
tF1
(1)
tR1
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 11. Output Timing
8
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VCC
1st Device
1st Data (0)
2nd
Data (0)
3rd
Data (1)
4th
Data (1)
5th
Data (1)
48th
Data (0)
2nd Device
1st Data (0)
2nd
Data (0)
1st Device
1st Data (0)
48th
Data (0)
SDI
fCLK(SDI)
fCLK(SDI)
Data Transfer
Period Memory
(Internal in all Devices)
tSDI
tWH
tWL
tH0 (for EOS)
tH1 (for GSLAT)
Data transfer period (t CYCLE) is stored.
Data transfer period (t CYCLE) is stored.
Recognized Data,
SIN Signal
(Internal in 1st Device)
1st Data (0)
2nd Data (0)
3rd Data (1)
4th Data (1)
5th Data (1)
47th
Data
48th Data (0)
1st Data (0)
48th Data (0)
1st Data (0)
48th Data (0)
SCLK Signal
(Internal in 1st Device)
48-Bit Shift Register LSB
(Internal in 1st Device)
1st Data (0)
2nd Data (0)
3rd Data (1)
4th Data (1)
1st Data (0)
2nd Data (0)
3rd Data (1)
5th Data (1)
48-Bit Shift Register LSB+1
(Internal in 1st Device)
4th Data (1)
48-Bit Shift Register MSB-1
(Internal in 1st Device)
47th
Data
48th Data (0)
46th
Data
48th Data (0)
47th Data
47th Data
1st Data (0)
2nd Data (0)
3rd Data (0)
1st Data (0)
2nd Data (0)
2nd Data (0)
48-Bit Shift Register MSB
(Internal in 1st Device)
High = SDI data are output from SDO.
1st Data (0)
OUTEN Signal
(Internal)
Low = SDI data are not output from SDO.
GSLAT Signal
(Internal in 1st Device)
36-Bit GS Data Latch
(Internal in 1st Device)
(All GS data are ‘0’ when VCC powers up.)
New GS Data
tD0
tWO
SDO
tF0
tR0
SCLK Signal
(Internal in 2nd Device)
48-Bit Shift Register LSB
(Internal in 2nd Device)
1st Data (0)
48th Data (0)
tH1
GSLAT Signal
(Internal in 2nd Device)
GS Data Latch
(Internal in 2nd Device)
New GS Data
(All GS data are ‘0’ when VCC powers up.)
(VOUTnH)
OUT0
OFF
ON
tF1
(VOUTnL)
(1)
tR1
OUT1
OUT2
OFF
(1)
ON
tD1
OFF
(1)
ON
tD1
(1) OUTn on-time changes, depending on the data in the 36-bit GS data latch.
Figure 12. Data Write and OUTn Switching Timing
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PIN CONFIGURATION
D PACKAGE
SO-8
(Top View)
1
8
VCC
OUT1 2
7
IREF
OUT2
3
6
SDI
GND
4
5
SDO
OUT0
PIN DESCRIPTIONS
PIN
10
NAME
NO.
I/O
GND
4
—
Power ground
DESCRIPTION
IREF
7
I/O
Output current programming terminal. A resistor connected between IREF and GND sets the current
for each constant-current output. Place the external resistor close to the device.
OUT0
1
O
OUT1
2
O
OUT2
3
O
SDI
6
I
Serial data input. This pin is internally pulled down to GND with a 1-MΩ (typ) resistor.
SDO
5
O
Serial data output
VCC
8
—
Power-supply voltage
Constant sink current driver outputs.
Multiple outputs can be configured in parallel to increase the sink drive current capability.
Different voltages can be applied to each output.
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FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
Shunt
Regulator
reset
UVLO
Pulse
Generator
SDI
outen
SDO
LSB
MSB
sin
Interface
Control
48-Bit Shift Register
sclk
0
47
Upper 8 Bits
Lower 36 Bits
LSB
Command
Decoder (3AAh)
MSB
gslat
36-Bit GS Data Latch
0
Internal
Oscillator
12 MHz
reset
35
GS Clock
Counter
36
12
12-Bit PWM Timing Control
reset
IREF
3
Switching Delay
3
GND
3-Channel Constant Sink Current Driver
OUT0
OUT1
OUT2
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TYPICAL CHARACTERISTICS
At TA = +25°C and VCC = 12 V, unless otherwise noted.
50
100k
45
TA = +25°C
VCC = 5V
RIREF = 1.1k
RIREF = 1.5k
26.0
35
Output Current (mA)
IREF, Reference Resistance (k )
40
10.4
10k
5.21
3.47
RIREF = 2.7k
20
RIREF = 5.1k
10
RIREF = 10k
1.49
1.74
1.16
1.30
1k
10
25
15
2.60
2.08
0
30
20
30
40
5
RIREF = 27k
1.04
0
50
0
C001
Figure 13. REFERENCE RESISTOR vs OUTPUT CURRENT
(OUTn)
12
0.5
1
1.5
2
2.5
3
Output Voltage (V)
IOLC, Output Current (mA)
C002
Figure 14. OUTPUT CURRENT vs OUTPUT VOLTAGE
(OUTn)
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DETAILED DESCRIPTION
CONSTANT SINK CURRENT VALUE
The output current value of each channel (IOLC) is programmed by a single resistor (RIREF) that is placed between
the IREF and GND pins. The current value can be calculated by Equation 1:
RIREF (kW) =
VIREF (V)
IOLC (mA)
´ 43.4
where:
•
•
VIREF = the internal reference voltage on IREF (typically 1.20 V), and
IOLC = 2 mA to 50 mA
(1)
IOLC is the current for each output. Each output sinks IOLC current when it is turned on. RIREF must be between 1
kΩ and 27 kΩ in order to hold IOLC between 50 mA (typ) and 1.93 mA (typ). Otherwise, the output may be
unstable. Refer to Figure 13 and Table 1 for the constant-current sink values for specific external resistor values.
Table 1. Constant-Current Output versus External
Resistor Value
IOLC (mA)
RIREF (kΩ, typ)
50
1.04
45
1.16
40
1.30
35
1.49
30
1.74
25
2.08
20
2.60
15
3.47
10
5.21
5
10.4
2
26.0
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RESISTOR AND CAPACITOR VALUE SETTING FOR SHUNT REGULATOR
The TLC5973 internally integrates a shunt regulator to regulate VCC voltage. Refer to Figure 15 for an application
circuit that uses the internal shunt regulator through a resistor, RVCC. The recommended RVCC value can be
calculated by Equation 2.
VLED (V) - 5.9 V
VLED (V) - 5.9 V
< RVCC <
11 mA
13 mA
(2)
VLED
RVCC
RVCC
CVCC
(0.1 mF)
CVCC
(0.1 mF)
Power
Supply
GND
GND
VCC
IREF
OUT0
RIREF
+5 V
1st Device
GND
VCC
IREF
OUT0
RIREF
OUT1
2nd Device
OUT2
Controller
SDI
Optional
OUT1
OUT2
SDI
SDO
SDO
Figure 15. Internal Shunt Regulator Mode Application Circuit
Table 2 shows the typical resistor value for several VLED voltages. Note that the CVCC value should be 0.1 μF.
Table 2. Resistor Example for Shunt Resistor versus LED Voltage (1)
(1)
VLED (V)
RVCC (Ω)
RESISTOR WATTAGE (W)
9
390
0.03
12
820
0.07
18
1500
0.15
24
2200
0.21
RIREF is at 1.5 kΩ.
GRAYSCALE (GS) FUNCTION (PWM CONTROL)
The TLC5973 can adjust the brightness of each output channel using a pulse width modulation (PWM) control
scheme. The PWM data bit length for each output is 12 bits. The architecture of 12 bits per channel results in
4096 brightness steps, from 0% to 99.98% on-time duty cycle.
The PWM operation for OUTn is controlled by an 12-bit grayscale (GS) counter. The GS counter increments on
each internal GS clock (GSCLK) rising edge. All OUTn are turned on when the GS counter is ‘1’, except when
OUTn are programed to GS data '0' in the 36-bit GS data latch. After turning on, each output is turns off when
the GS counter value exceeds the programmed GS data for the output. The GS counter resets to 00h and all
outputs are forced off when the GS data are written to the 36-bit GS data latch. Afterwards, the GS counter
begins incrementing and PWM control is started from the next internal GS clock.
14
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Table 3 summarizes the GS data values versus the output ideal on-time duty cycle. Furthermore, actual on-time
differs from the ideal on-time because the output drivers and control circuit have some timing delay. When the
device is powered on, all outputs are forced off and remain off until the non-zero GS data are written to the 36-bit
GS data latch.
Table 3. Output Duty Cycle and Total On-Time versus GS Data
GS DATA
DECIMAL
HEX
NO. OF GSCLKs
OUTn TURNS ON
NO. OF GSCLKs
OUTn TURNS OFF
TOTAL IDEAL TIME
(µs)
0
0
Off
Off
0
0
1
1
1
2
0.08
0.02
ON-TIME DUTY (%)
2
2
1
3
0.17
0.05
—
—
—
—
—
—
255
0FE
1
256
21.25
6.23
256
0FF
1
257
21.33
6.25
257
100
1
258
21.42
6.27
—
—
—
—
—
—
511
1FF
1
512
42.58
12.48
512
200
1
513
42.67
12.50
513
201
1
514
42.75
12.52
—
—
—
—
—
—
1023
3FF
1
1024
85.25
24.98
1024
400
1
1025
85.33
25.00
1025
401
1
1026
85.42
25.00
—
—
—
—
—
—
2047
7FF
1
2048
170.6
49.98
2048
800
1
2049
170.7
50.00
2049
801
1
2050
170.8
50.02
—
—
—
—
—
—
4093
FFD
1
4094
341.1
99.93
4094
FFE
1
4095
341.2
99.95
4095
FFF
1
4096
341.3
99.98
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PWM Control
The GS counter keeps track of the number of grayscale reference clocks (GSCLKs) from the internal oscillator.
Each output stays on while the counter is less than or equal to the programmed GS value. Each output turns off
when the GS counter is greater than the GS value in the 36-bit GS data latch. Figure 16 illustrates the PWM
operation timing.
1 2
Grayscale
Reference Clock, GSCLK
(Internal)
OUTn
(GSDATA = 0)
OFF
ON
2047
2048
2049
3 4
4094
1
4095
4096
(VOUTnH)
(VOUTnL)
No driver turns on.
t = GSCLK x 1
OUTn
(GSDATA = 1)
OFF
OUTn
(GSDATA = 2)
OFF
OUTn
(GSDATA = 3)
OFF
OUTn
(GSDATA = 2046)
OFF
OUTn
(GSDATA = 2047)
OFF
OUTn
(GSDATA = 2048)
OFF
OUTn
(GSDATA = 4093)
OFF
OUTn
(GSDATA = 4094)
OFF
OUTn
(GSDATA = 4095)
OFF
ON
t = GSCLK x 2
ON
t = GSCLK x 3
ON
t = GSCLK x 2046
ON
t = GSCLK x 2047
ON
t = GSCLK x 2048
ON
t = GSCLK x 4093
ON
t = GSCLK x 4094
ON
t = GSCLK x 4095
t = GSCLK x 1
ON
(1) Actual on-time differs from the ideal on-time.
Figure 16. PWM Operation
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REGISTER AND DATA LATCH CONFIGURATION
The TLC5973 has a 48-bit shift register and a 36-bit data latch that stores GS data. When the internal GS data
latch pulse is generated and the data of the 12 MSBs in the shift register are 3AAh, the lower 36-bit data in the
48-bit shift register are copied into the 36-bit GS data latch. If the data of the eight MSBs is not 3AAh, the 36-bit
data are not copied into the 36-bit GS data latch. Figure 17 shows the shift register and GS data latch
configurations. Table 4 shows the 48-bit shift register bit assignment.
48-Bit Shift Register
LSB
MSB
Write
Command
Bit 11
47
Write
Command
Bit 0
OUT0
GS Data
Bit 11
36
35
---
---
OUT0
GS Data
Bit 0
OUT1
GS Data
Bit 11
24
23
OUT1
GS Data
Bit 0
OUT2
GS Data
Bit 11
12
11
---
OUT2
GS Data
Bit 0
---
Shift Data (Internal)
Shift Clock (Internal)
0
36 Bits
12 Bits
MSB
35
12-Bit Write
Command
Decoder
The internal latch pulse is generated after 8 tCYCLES without SDI clocking.
36-Bit GS Data Latch
---
OUT0
GS Data
Bit 11
24
23
OUT0
GS Data
Bit 0
OUT1
GS Data
Bit 11
12
11
OUT1
GS Data
Bit 0
OUT2
GS Data
Bit 11
---
---
LSB
0
OUT2
GS Data
Bit 0
GS Data
Latch Pulse
(Internal)
Write Command = 3AAh (00111010b)
36 Bits
To Grayscale Timing
Control Circuit
Figure 17. Common Shift Register and Control Data Latches Configuration
Table 4. 48-Bit Shift Register Data Bit Assignment
BITS
BIT NAME
CONTROLLED CHANNEL/FUNCTIONS
0 to 11
GSOUT2
GS data bits 0 to 11 for OUT2
12 to 23
GSOUT1
GS data bits 0 to 11 for OUT1
24 to 35
GSOUT0
GS data bits 0 to 11 for OUT0
WRTCMD
Data write command (3AAh) for GS data.
The lower 36-bit GS data in the 48-bit shift register are copied to the GS data latch
when the internal GS latch is generated (when these data bits are 3AAh,
001110101010b).
36 to 47
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ONE-WIRE INTERFACE (EasySet) DATA WRITING METHOD
There are four sequences to write GS data into the TLC5973 via a single-wire interface. This section discusses
each sequence in detail.
Data Transfer Rate (tCYCLE) Measurement Sequence
The TLC5973 measures the time between the first and second SDI rising edges either after the device is
powered up or when the GS data latch sequence is executed (as described in the GS Data Latch Sequence
(GSLAT) section) and the time is internally stored as tCYCLE. tCYCLE serves as a base time used to recognize one
complete data write operation, a 48-bit data write operation, and a GS data write operation to the GS data latch.
tCYCLE can be set between 0.33 µs and 10 µs (fCLK(SDI) = 100 kHz to 3000 kHz). In this sequence, two instances
of data ‘0’ are written to the LSB side of the 48-bit shift register. Figure 18 shows the tCYCLE measurement timing.
1st SDI
Rising Edge
2nd SDI
Rising Edge
SDI
tCYCLE
Figure 18. Data Transfer Rate (tCYCLE) Measurement
Data ‘0’ and Data ‘1’ Write Sequence (Data Write Sequence)
When the second SDI rising edge is not input before 50% of tCYCLE elapses from the first SDI rising edge input,
the second rising edge is recognized as data '0'. When the second SDI rising edge is input before 50% of tCYCLE
elapses from the first SDI rising edge input, the second rising edge is recognized as data '1'. This write sequence
must be repeated 46 times after the tCYCLE measurement sequence in order to send the write command to the
lower 10-bit (3AAh) and 48-bit GS data. Figure 19 shows the data ‘0’ and ‘1’ write timing.
Data 0 Writing
Data 1 Writing
First SDI
Rising Edge
First SDI
Rising Edge
Second SDI
Rising Edge
Dotted line waveform
is accepted.
SDI
tSDI = 0.5 x tCYCLE
When the second SDI
rising edge is not input, it
is recognized as ‘0’.
When the second SDI
rising edge is input by
0.5 x tCYCLE, it
is recognized as ‘1’.
tSDI = 0.5 x tCYCLE
This time must be between tCYCLE x 1.0 and tCYCLE x 2.0
Figure 19. Data ‘0’ and ‘1’ Write Operation
18
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One Communication Cycle End of Sequence (EOS)
One communication cycle end of sequence (EOS) must be input after the 48-bit data are written because the
TLC5973 does not count the number of input data. When SDI is held low for the EOS hold time (tH0), the 48-bit
shift register values are locked and a buffered SDI signal is output from SDO to transfer GS data to the next
device. Figure 20 shows the EOS timing.
The first SDI rising edge of the last input data.
SDI
3.5 x tCYCLE (min) to 5.5 x tCYCLE (max)
48-Bit Shift
Register
(Internal)
Shift register data are locked.
GSLATignal
(Internal)
GS data latch signal is not generated.
36-Bit GS
Data Latch
(Internal)
GS data are not changed.
High = pulse signal output from SDO.
OUTEN Signal
(Internal)
Low = pulse signal not
output from SDO.
SDO
Figure 20. End of Sequence (EOS)
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GS Data Latch (GSLAT) Sequence
A GS data latch (GSLAT) sequence must be input after the 48-bit data for all cascaded devices are written.
When SDI is held low for the data latch hold time (tH1), the 48-bit shift register data in all devices are copied to
the GS data latch in each device. Furthermore, PWM control starts with the new GS data at the same time.
Figure 21 shows the GSLAT timing.
The first SDI rising edge of the last input data.
SDI
8 x tCYCLE (min)
48-Bit Shift
Register
(Internal)
Shift register data are
written after GSLAT is input.
GSLAT Signal
(Internal)
GS Data in
36-Bit
Data Latch
(Internal)
New GS Data
High = pulse signal output from SDO.
OUTEN Signal
(Internal)
Low = pulse signal not output from SDO.
SDO
Figure 21. GS Data Latch Sequence (GSLAT)
20
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HOW TO CONTROL DEVICES CONNECTED IN SERIES
The 12-bit write command and 36-bit grayscale (GS) data for OUT0 to OUT2 (for a total of 48 bits of data) must
be written to the device.Figure 22 shows the 48-bit data packet configuration. When multiple devices are
cascaded (as shown in Figure 23), N times the packet must be written into each TLC5973 in order to control all
devices. There is no limit on how many devices can be cascaded, as long as proper VCC voltage is supplied.
The packet for all devices must be written again whenever any GS data changes.
MSB
LSB
Data 0
Data 0
for tCYCLE for tCYCLE
Data
1
Bit 11
Data
1
Data
1
Data
0
Data
101
Data
1
Write Command Data, 12 Bits
(3AAh = 001110101010b)
Data
0
Data
0 or 1
Data
0 or 1
Bit 0
Bit 11
Bit 0
OUT0
GS Data, 12 Bits
Data
0 or 1
Data
0 or 1
Bit 11
Bit 0
OUT1
GS Data, 12 Bits
Data
0 or 1
Data
0 or 1
Bit 11
Bit 0
OUT2
GS Data, 12 Bits
Figure 22. 48-Bit Data Packet Configuration for One TLC5973
VLED
GND
GND
5.0 V
VCC
1st Device
CLK
SDI
CVCC
0.1 µF
RVCC
2nd Device
VCC
VCC
Controller
GND
RVCC
RVCC
SDO
IREF
GND
GND
GND
SDI
RVCC
N-1st Device
SDO
IREF
GND
Nth Device
VCC
VCC
SDO
SDI
IREF
GND
SDI
SDO
IREF
GND
GND
Figure 23. Cascade Connection of N TLC5973 Units (Internal Shunt Regulator Mode)
Refer to Figure 24 for the 48-bit data packet, EOS, and GSLAT input timing of all devices. The function setting
write procedure and display control is as follows:
1. Power-up VCC (VLED); all OUTn are off because GS data are not written yet.
2. Write the 48-bit data packet (MSB-first) for the first device using tCYCLE and the data write sequences
illustrated in Figure 18 and Figure 19. The first 12 bits of the 48-bit data packet are used as the write
command. The write command must be 3AAh (001110101010b); otherwise, the 36-bit GS data in the 48-bit
shift register are not copied to the 36-bit GS data latch.
3. Execute one communication cycle EOS (refer to Figure 20) for the first device.
4. Write the 48-bit data packet for the second TLC5973 as described step 2. However, tCYCLE should be set to
the same timing as the first device.
5. Execute one communication cycle EOS for the second device.
6. Repeat steps 4 and 5 until all devices have GS data.
7. The number of total bits is 48 × N. After all data are written, execute a GSLAT sequence as described in
Figure 21 in order to copy the 36-bit LSBs in the 48-bit shift resister to the 36-bit GS data latch in each
device; PWM control starts with the written GS data at the same time.
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VLED Power
MSB
1st Device SDI
LSB
48-Bit Data Packet
for 1st Device
MSB
EOS
1st Device SDO
LSB
MSB
LSB
MSB
LSB
MSB
48-Bit Data Packet
for 2nd Device
EOS
For 3rd
Device
For
N-1th
EOS
48-Bit Data Packet
for Nth Device
GSLAT
48-Bit Data Packet
for 2nd Device
EOS
For 3rd
Device
For
N-1th
EOS
48-Bit Data Packet
for Nth Device
GSLAT
For 3rd
Device
For
N-1st
EOS
48-Bit Data Packet
for Nth Device
GSLAT
48-Bit Data Packet
for Nth Device
GSLAT
N-2nd Device SDO
N-1st Device SDO
LSB
Next Data Packet
for 1st Device
PWM Control Starts
with new GS Data
OUTn
Figure 24. Data Packet Input Order for N TLC5973 Units
CONNECTOR DESIGN APPLICATION
When the connector pin of the device application printed circuit board (PCB) is connected or disconnected to
other PCBs, the power must be turned off to avoid device malfunction or failure. Furthermore, designing the
connector GND pin to be longer than other pins (as shown in Figure 25) is preferable. This arrangement allows
the GND line to either be connected first or disconnected last, which is imperative for proper device function.
GND
VCC (VLED)
N+1st Device PCB
Nth Device PCB
To N-1st
Device
PCB or
Controller
and Power
Supply
To
N+2nd
Device
PCB
SDI
Connector (Male)
Figure 25. Connector Pin Design Application
22
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2013) to Revision A
Page
•
Changed second paragraph of Grayscale (GS) Function (PWM Control) section ............................................................. 14
•
Updated Figure 17 and Table 4 .......................................................................................................................................... 17
•
Changed tCYCLE setting range in Data Transfer Rate (tCYCLE) Measurement Sequence section ........................................ 18
•
Updated Figure 22 .............................................................................................................................................................. 21
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC5973D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
5973
TLC5973DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
5973
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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