DG485 Vishay Siliconix Octal Analog Switch Array Low Signal Distortion Devices Can Be Chained for System Expansion Reduced Board Space Reduced Switch Errors Reduced Power Supply Requirements Simple Interfacing Audio Switching and Routing Audio Teleconferencing Data Acquisition and Industrial Process Control Battery Powered Remote Systems Automotive, Avionics and ATE Systems Summing Amplifiers Low On-Resistance: 55 Rail-to-Rail Analog Input Range Serial Interface Low-Power—PD: 35 nW TTL and CMOS Compatible Any Combination of 8 SPST to the Output High Speed—tON: 170 ns The DG485 is an analog switch array consisting of eight SPST switches connected to a common output. This device may be used as an 8-channel multiplexer in serial control applications. Any, all or none of the eight switches may be closed at any given time. Combining low on-resistance (rDS(on) 55 , typ.) and fast switching (tON: 170 ns, typ.), the DG485 is ideally suited for data acquisition, process control, communication, and avionic applications. Control data is input serially into the shift register with each clock pulse. The shift register contents can be latched-in (via LD) at any point into an octal latch which in turn controls all switches. RS resets the shift register, forcing all latch inputs to a low condition (all switches off). The serial input (DIN) and serial output (DOUT) allow daisy chaining of multiple arrays for large systems. Built on the Vishay Siliconix high voltage silicon gate process the DG485 has a wide 44-V power supply voltage rating. An epitaxial layer prevents latchup. Each channel conducts equally well in either direction when on and blocks up to rail-to-rail voltages when off. For additional information please refer to application note AN204. VL LD NC RS 3 2 1 20 19 LD 1 18 VL 2 17 S4 3 16 D S4 4 18 D S3 4 15 S5 S3 5 17 S5 S2 6 16 S6 S1 7 15 S7 V+ 8 14 S8 DIN 8 CLK 9 Shift Register Latches 12 S8 11 V– 10 DOUT Shift Register/Latches 9 10 11 12 13 V– 7 13 S7 NC 6 S6 DOUT V+ 14 D IN S1 5 GND CLK S2 RS GND PLCC and LCC Dual-In-Line Top View Top View Document Number: 70065 S-52433—Rev. E, 06-Sep-99 www.vishay.com FaxBack 408-970-5600 5-1 DG485 Vishay Siliconix TRUTH TABLES AND ORDERING INFORMATION TRUTH TABLEĊDUALĆINĆLINE PACKAGE RS DIN D1 Dn 1 0 0 1 1 1 0 CLK* X TRUTH TABLEĊPLCC & LCC PACKAGES LD* Dn Ln SWn Dn-1 0 0 OFF 1 Dn-1 1 1 ON X D1 Dn (No Change) Dn Ln (No Change) X 0 0 *LD Input Level Triggered *CLK Input Edge Triggered ORDERING INFORMATION Temp Range Package Part Number 18-Pin Plastic DIP DG485DJ 20-Pin PLCC DG485DN –40 to 85_C –55 to 125_C LCC-20 DG485AZ/883 ABSOLUTE MAXIMUM RATINGS Voltages Referenced to V– V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Inputsa VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+) + 2 V or 30 mA, whichever occurs first Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Current, S or D (Pulsed 1 ms, 10% duty cycle) . . . . . . . . . . . . . . . . . . 100 mA Storage Temperature (AZ Suffix) . . . . . . . . . . . . . . . . . . –65 to 150_C (DJ, DN Suffix) . . . . . . . . . . . . . . –65 to 125_C www.vishay.com S FaxBack 408-970-5600 5-2 Power Dissipation (Package)b 18-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 20-Pin PLCC, LCCd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW Notes: a. Signals on SX, DX or INX exceeding V+ or V– will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads soldered or welded to PC board. c. Derate 6 mW/_C above 75_C. d. Derate 10 mW/_C above 75_C. Document Number: 70065 S-52433—Rev. E, 06-Sep-99 DG485 Vishay Siliconix Test Conditions Unless Otherwise Specified A Suffix D Suffix –55 to 125_C –40 to 85_C V+ = 15 V, V– = –15 V VL = 5 V, VIN = 2.4 V, 0.8 Vf Tempb V+ = 13.5 V, V– = –13.5 V IS = –5 mA, VD = 10 V Room Full 55 Room 6 Room Full 0.01 –1 –20 1 20 –1 –10 1 10 Room Full 0.1 –10 –200 10 200 –10 –50 10 50 V = 16.5 V VS = VD = 15.5 V One Switch At A Time Room Full 0.11 –20 –500 20 500 –20 –50 20 50 V = 16.5 V, VS = VD = 15.5 V All Switches On Room 0.2 IIL VIN Under Test = 0.8 V All Other = 2.4 V Room Full –0.0001 –1 –5 1 5 –1 –5 1 5 IIH VIN Under Test = 2.4 V All Other = 0.8 V Room Full 0.0001 –1 –5 1 5 –1 –5 1 5 Output Voltage with VIN Low – DOUT VOL IO = 1.6 mA, V+ = 4.5 V Full 0.25 Output Voltage with VIN High – DOUT VOH IO = –80 mA, V+ = 16.5 V VL = 4.75 V Full 4.4 Parameter Symbol Typc Mind Maxd Mind Maxd Unit Analog Switch Analog Signal Rangee Drain-Source On-Resistance Delta Drain-Source On-Resistanceg Switch Off Leakage Current L k C t Channel On L k Leakage Current C t VANALOG rDS(on) Full DrDS(on) IS(off) ID(off) ID(on) V+ = 16.5 V,, V– = –16.5 V VD = 15.5 V, VS = 15.5 15 5 V 15 5 V –15 15 –15 85 125 15 V 85 125 W % nA A Input Input Current with VIN Low Input Current with VIN High mA Serial Data Output 0.4 0.4 V 2.7 2.7 Dynamic Characteristics Turn-On Time tON VS = 10 V See Figures 1, 8 Room Full 170 200 275 200 275 Turn-Off Time tOFF VS = 10 V See Figures 2, 3, 8 Room Full 150 200 275 200 276 Data Setup Time tDS See Figures 4, 8 Room Full 40 60 40 60 Data Hold Time tDH Room Full 40 60 40 60 LOAD Hold Time tLH Room Full 100 150 100 150 RESET Hold Time tRH Room Full 100 150 100 150 Room Full 40 60 40 60 RESET to CLOCK Delay Charge Injection Off Isolatione Maximum Clock Frequency Document Number: 70065 S-52433—Rev. E, 06-Sep-99 S Figures See Fi 5 8 5, tDRC ns Q VS = 0 V, CL = 1,000 pF Any One Channel Room 17 pC OIRR RL = 50 W , CL = 5 pF, f = 1 MHz See Figure 9 Room –75 dB Room 10 MHz fCLK www.vishay.com S FaxBack 408-970-5600 5-3 DG485 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter V+ = 15 V, V– = –15 V VL = 5 V, VIN = 2.4 V, 0.8 Vf Symbol Tempb Typc Room 7 A Suffix D Suffix –55 to 125_C –40 to 85_C Mind Maxd Mind Maxd Unit Dynamic Characteristics (Cont’d) Source Off Capacitancee CS(off) Drain Off Capacitancee CD(off) On-State Capacitancee CD(on) Vgen = 0 V,, Rgen = 0 W , f = 1 MHz Room 43 Vgen = 0 V, Rgen = 0 W , f = 1 MHz One Channel On Room 53 Vgen = 0 V, Rgen = 0 W , f = 1 MHz All Channels On Room 122 Room Full 0.001 Room Full –0.001 Room Full 0.001 Room Full –0.001 F pF Power Supplies Positive Supply Current I+ Negative Supply Current I– Logic Supply Current IL Ground Current V+ = 16.5 V 16 5 V, V V– V = –16.5 16 5 V VIN = 0 or 5 V, VL = 5.25 V DOUT Open IGND 3 10 3 10 –3 –10 –3 –10 3 10 3 10 –3 –10 mA A –3 –10 Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. r DS(on) MAX – r DS(on) MIN g. For each V : Dr + D DS(on) r AVE ǒ Ǔ DS(on) TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Supply Currents vs. Temperature 1 mA V+ = 15 V V– = –15 V VL = 5 V r DS(on)– Drain-Source On-Resistance ( W ) 100 nA rDS(on) vs. VD and Power Supply Voltage 160 I+, I–, I GND 10 nA IL IPOS 1 nA INEG 100 pA IGND 10 pA 1 pA 0.1 pA –50 VL = 5 V IS = –5 mA 120 "5 V 100 80 "8 V "10 V 60 40 20 "12 V "20 V "15 V 0 –30 –10 10 30 50 70 Temperature (_C) www.vishay.com S FaxBack 408-970-5600 5-4 140 90 110 130 –20 –15 –10 –5 0 5 10 15 20 VD – Drain Voltage (V) Document Number: 70065 S-52433—Rev. E, 06-Sep-99 DG485 Vishay Siliconix _ rDS(on) vs. VD and Unipolar Power Supply Voltage r DS(on)– Drain-Source On-Resistance ( ) r DS(on)– Drain-Source On-Resistance ( ) V– = 0 V VL = 5 V IS = –5 mA 350 300 250 V+ = 5 V 200 150 8V 10 V 100 12 V 15 V 50 20 V 90 80 70 60 125_C 50 40 25_C 30 V+ = 15 V V– = –15 V VL = 5 V IS = –5 mA 20 10 –55_C 0 0 0 2 4 6 8 10 12 14 16 18 20 –15 0 5 10 Channel On/Off Leakage Currents vs. Analog Voltage Channel On/Off Leakage Currents vs. Temperature 1 mA 15 V+ = 15 V V– = –15 V VL = 5 V VS or VD = – 14 V 100 nA 10 nA 20 1 nA IS(off) I D, I S 0 ID(off) –20 –5 VD – Drain Voltage (V) V+ = 15 V V– = –15 V VL = 5 V 40 –10 VD – Drain Voltage (V) 60 I S, I D , I S + D (pA) rDS(on) vs. VD and Temperature 100 400 IS(off) ID(on) 100 pA 10 pA ID(on) –40 ID(off) 1 pA –60 0.1 pA 0.01 pA –80 –15 –10 –5 0 5 10 –50 15 –30 –10 10 VD or VS – Drain or Source Voltage (V) 50 70 90 110 130 Temperature (_C) Switching Threshold vs. Power Supply Voltage and VL RF Characteristics –140 3.0 –120 5V 2.5 30 VL = 7 V 6V –100 XTALK OIRR –80 (dB) V TH (V) 2.0 1.5 –60 4V V+ = 15 V V– = –15 V VL = 5 V See Figures 9, 10 1.0 –40 0.5 –20 0 0 5 6 7 8 9 10 11 V+ Supply (V) Document Number: 70065 S-52433—Rev. E, 06-Sep-99 12 13 14 15 1k 10 k 100 k 1M 10 M f – Frequency (Hz) www.vishay.com S FaxBack 408-970-5600 5-5 DG485 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Supply Currents vs. Switching Frequency Source/Drain On Capacitance vs. Analog Voltage 180 10 mA V+ = 15 V V– = –15 V VL = 5 V VIN = 3 V 1 mA In C S, D (pF) I+, I–, I GND 140 IL 100 mA 10 mA V+ = 15 V V– = –15 V VL = 5 V 160 Ip CD(on) 120 (All Channels On) 100 1 mA 80 100 nA 60 10 nA 40 CD(on) (Channel 1 On Only) 100 1k 10 k 100 k 1M –15 –10 f – Frequency (Hz) Source/Drain Off Capacitance vs. Analog Voltage 10 15 V+ = 15 V V– = –15 V VL = 5 V CL = 1 nF 45 CD(off) 35 40 Q (pC) C S, D (pF) 5 Charge Injection vs. Analog Voltage V+ = 15 V V– = –15 V VL = 5 V 50 30 25 15 20 10 5 CS(off) 0 –15 0 55 70 60 –5 VANALOG – Analog Voltage (V) –5 –10 –5 0 5 10 15 –15 –10 VANALOG – Analog Voltage (V) –5 0 5 10 15 VS – Source Voltage (V) TIMING DIAGRAMS 3V 3V 50% 50% LD 0V VS VD 0V LD 0V VS VD 0V 90% Repeat for All Channels tON 90% tOFF FIGURE 1. tON from LD Repeat for All Channels FIGURE 2. tOFF from LD 3V 50% RS 0V VS VD 90% 0V tOFF FIGURE 3. tOFF from RS www.vishay.com S FaxBack 408-970-5600 5-6 Document Number: 70065 S-52433—Rev. E, 06-Sep-99 DG485 Vishay Siliconix 50% CLOCK 50% DATA tDH tDS FIGURE 4. Data Setup and Hold Time CLOCK RS LOAD tLH tRH tDRC FIGURE 5. Timing Relationships RS DIN CLK LD S1 S2 S3 S4 S5 S6 S7 S8 DOUT S1 – S8 and DOUT are expected output with the drain connected high. The sources require pull-down of 1 k. FIGURE 6. Document Number: 70065 S-52433—Rev. E, 06-Sep-99 www.vishay.com FaxBack 408-970-5600 5-7 DG485 Vishay Siliconix V+ S1 VL V+ RS RS D1 S8 Octal Latch Dn DIN Shift Register CLK CLK Level Shift/ Drive V– D8 LD V+ D DOUT V+ LD GND V– FIGURE 7. www.vishay.com FaxBack 408-970-5600 5-8 Document Number: 70065 S-52433—Rev. E, 06-Sep-99 DG485 Vishay Siliconix +15 V +5 V 50 V+ VS S1 50 VL S1 S2 50 35 pF S7 S8 S2 VO D D 1 k DG485 DG485 50 S3 CLK 50 LD DIN RS V– S8 GND 50 –15 V FIGURE 8. Switching Time Test Circuit FIGURE 9. Adjacent Input Crosstalk 50 S1 50 VO DG485 S2 50 50 S8 50 FIGURE 10. Off Isolation Document Number: 70065 S-52433—Rev. E, 06-Sep-99 www.vishay.com FaxBack 408-970-5600 5-9 DG485 Vishay Siliconix f= for CLK and LD inputs of the same frequency. The recommended phase delay of LD from CLK is ½ tLOGIC to tLOGIC: CLK f tLOGIC(MIN): 80 ns at 25_C 150 ns at 125_C V+ = 15 V V– = –15 V GND = 0 V LD tLOGIC tLOGIC FIGURE 11. C1 DG485 VREF C2 R1 IN1 RIN DIN DG485 R2 CLK RF IN2 R0 RIN R1 R2 R7 – – VOUT + + FIGURE 12. Multi-Function Circuit Provides Input Selection, Gain Ranging and Filtering with One DG485 www.vishay.com S FaxBack 408-970-5600 5-10 FIGURE 13. Serial DAC Circuit Document Number: 70065 S-52433—Rev. E, 06-Sep-99 DG485 Vishay Siliconix RF V1 V2 V8 R VOUT – R + + CH R – DG485 DG485 FIGURE 14. Summing Node Mixer FIGURE 15. Multiplexing, Sampling Application S1 S2 S8 DG485 D Switch Array Octal Latch 8085 DIN SOD ALE LD Data Bus DOUT S/R CLK To Next Switch Array RS 8212 (8) (8) Address Bus Decoder 8205 WR R/S FIGURE 16. Direct Serial Interface (8085) Document Number: 70065 S-52433—Rev. E, 06-Sep-99 www.vishay.com FaxBack 408-970-5600 5-11