CA3098 CT T ODU CEMEN R P E A 3 T L 4 OLE REP -724-71 O BS E NDE D 1 2 or 3 M COM TERSIL E R N NO 8-I 1-88 Call TM Programmable Schmitt Trigger with Memory, Dual Input Precision Level Detector ) ma itt ith , ut ) () ds duc e, tor, January 1999 File Number 896.5 Features • Programmable Operating Current The CA3098 Programmable Schmitt Trigger is a monolithic silicon integrated circuit designed to control high operating current loads such as thyristors, lamps, relays, etc. The CA3098 can be operated with either a single power supply with maximum operating voltage of 16V, or a dual power supply with maximum operating voltage of ±8V. It can directly control currents up to 150mA and operates with microwatt standby power dissipation when the current to be controlled is less than 30mA. The CA3098 contains the following major circuit function features (see Block Diagram): • Micropower Standby Dissipation • Direct Control of Currents Up to . . . . . . . . . . . . . . . 150mA • Low Input On/Off Current of Less Than 1nA for Programmable Bias Current of 1µA • Built-in Hysteresis . . . . . . . . . . . . . . . . . . . . . 20mV (Max) Applications • Control of Relays, Heaters, LEDs, Lamps, Photosensitive Devices, Thyristors, Solenoids, etc. 1. Differential amplifiers and summer: the circuit uses two differential amplifiers, one to compare the input voltage with the “high” reference, and the other to compare the input with the “low” reference. The resultant output of the differential amplifiers actuates a summer circuit which delivers a trigger that initiates a change in state of a flipflop. • Signal Reconditioning 2. Flip-flop: the flip-flop functions as a bistable “memory” element that changes state in response to each trigger command. • Overvoltage, Overcurrent, Overtemperature Protection 3. Driver and output stages: these stages permit the circuit to “sink” maximum peak load currents up to 150mA at terminal 3. • Square and Triangular-Wave Generators 4. Programmable operating current: the circuit incorporates access at terminal 2 to permit programming the desired quiescent operating current and performance parameters. • Phase and Frequency Modulators • On/Off Motor Switching • Schmitt Triggers, Level Detectors • Time Delays • Battery-Operated Equipment Part Number Information PART NUMBER CA3098E t ent, Pinout TEMP RANGE ( oC) -55 to 125 PACKAGE 8 Ld PDIP PKG. NO. E8.3 CA3098 (PDIP) TOP VIEW le low l ut, LOW REF. 1 8 +IN I BIAS 2 7 HIGH REF. OUT 3 6 V+ V- 4 5 CURRENT CONTROL ure itt ilt is, put 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved CA3098 Block Diagram 2 PROGRAMMABLE BIAS CURRENT INPUT (IBIAS) 6 V+ OUTPUT CURRENT CONTROL “HIGH” REF. (HR) 5 7 DIFF. AMP SIGNAL INPUT “SINK OUTPUT” 8 SUMMER “LOW” REF. (LR) FLIP-FLOP (MEMORY) DIFF. AMP 1 DRIVER OUTPUT 3 SUBSTRATE 4 COMPARATOR V- Schematic Diagram 6 Q8 Q6 “HIGH” REF. (HR) 7 Q7 Q9 Q20 Q39 Q24 Q10 Q22 Q11 Q23 Q2 OUTPUT CURRENT CONTROL Q25 Q40 Q4 Q1 V+ 5 Q3 R14 500Ω Q41 Q26 Q27 Q28 Q29 SIGNAL INPUT 8 Q30 Q43 Q31 Q16 “LOW” REF. (LR) 1 Q33 Q32 Q44 “SINK” OUTPUT 3 Q46 Q45 R3 50K Q14 Q12 Q15 Q34 Q37 Q19 V4 Q42 Q5 Q17 Q18 2 Q35 Q36 Q38 2 PROGRAMMABLE BIAS CURRENT INPUT (IBIAS) CA3098 Absolute Maximum Ratings Thermal Information Supply Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . .16V Voltage Between High Reference or Sink Output and V-. . . . . . .16V Differential Input Voltage Between Terminals 8 and 1 . . . . . . . . .10V and Terminals 7 and 8 Load Current (Terminal 3) (Duty Cycle ≤25%) . . . . . . . . . . . . 150mA Input Current to Voltage Regulator (Terminal 5) . . . . . . . . . . . 25mA Programmable Bias Current (Terminal 2) . . . . . . . . . . . . . . . . . 1mA Output Current Control (Terminal 5). . . . . . . . . . . . . . . . . . . . . 15mA Thermal Resistance (Typical, Note 3) θJA PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125oC/W Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package). . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Voltage Range +IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+ HIGH REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V- +2.0V) to V+ LOW REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) to (V+ -2.0V) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = 25oC, Unless Otherwise Specified Electrical Specifications CA3098 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Offset Voltage “Low” Reference (Figures 2, 5) VIO(LR) VLR = GND, V HR = V+ to (V- +2V), IBIAS = 100µA -15 -3 6 mV “High Reference (Figures 2, 6) VIO(HR) VHR = GND, V LR = V- to (V+ -2V), IBIAS = 100µA -10 -1 10 mV Temperature Coefficient “Low” Reference (Figure 7) -55oC to 125oC - 4.5 - µV/oC “High” Reference (Figure 8) -55oC to 125oC - ±8.2 - µV/oC VREG = 0V (Note 1), V+ = 4V, V- = -4V, IBIAS = 1µA - 3 20 mV -55oC to 125oC - 6.7 - µV/oC - 0.72 1.2 V VI = 6V, VREG > 6V (Note 1), V+ = 16V, IBIAS = 100µA 500 710 800 µA VI = 10V, VREG < 10V (Note 1), V+ = 16V, IBIAS = 100µA 400 560 750 µA VI = 16V, VREG < 16V (Note 1), V+ = 16V, IBIAS = 100µA - 42 100 nA VI = 6V, VREG > 6V (Note 1), V+ = 16V, IBIAS = 100µA - 28 100 nA Current from Terminal 3 when Q46 is “OFF” - - 10 µA IBIAS = 100µA, V+ = 5V, V REG = 2.5V (Note 1) - 900 - ns ns Minimum Hysteresis Voltage (Figure 9) VIO(HRLR) Temperature Coefficient (Figure 10) VCE(SAT) VI = 5V, VREG = 6V (Note 1), V+ = 12V, IBIAS = 100µA Output Saturation Voltage (Figures 11, 12) Total Supply Current “ON” (Figures 3, 13, 14) ITOTAL “OFF” (Figures 3, 13, 14) Input Bias Current (Figures 3, 15) IB(PNP) IIB IB(NPN) Output Leakage Current ICE(OFF) Switching Times (Figures 4, 16-27) Delay Time tD tF Fall Time Rise Time Storage Time Output Current (Note 2) - 30 - tR tS - 2000 - ns - 6.5 - µs IO 100 - - mA NOTES: 1. For definition of VREG see Figure 3. 2. Continuous (DC) output current must be limited to ≤40mA. For 100mA output current, the duty cycle must be ≤40%. 3. θJA is measured with the component mounted on an evaluation PC board in free air. 3 CA3098 General Description of Circuit Operation When the signal input voltage of the CA3098 is equal to or less than the “low” reference voltage (LR), current flows from an external power supply through a load connected to Terminal 3 (“sink” output). This condition is maintained until the signal input voltage rises to or exceeds the “high” reference voltage (HR), thereby effecting a change in the state of the flip-flop (memory) such that the output stage interrupts current flow in the external load. This condition, in turn, is maintained until such time as the signal again becomes equal to or less than the “low” reference voltage. The CA3098 comparator is unique in that it contains circuit provisions to permit programmability. This feature provides flexibility to the designer to optimize quiescent power consumption, input circuit characteristics, hysteresis, and additionally permits independent control of the comparator, namely, pulsing, strobing, keying, squelching, etc. Programmability is accomplished by means of the bias current (IBIAS) supplied to Terminal 2. An auxiliary means of controlling the magnitude of load current flow at Terminal 3 is provided by “sinking” current into Terminal 5. Figure 1 highlights the operation of the CA3098 when connected as a simple hysteresis switch (Schmitt trigger). V+ = 12VDC IO 120kΩ RB 2 “HIGH” REF. = 8V 5 7 INPUT SIGNAL EIN 8 RL 6 3 EO CA3098 1 “LOW” REF. = 4V 4 SEQUENCE INPUT SIGNAL LEVEL OUTPUT VOLTAGE (V) (TERMINAL 3) 1 4 ≥ EIN > 0 0 2 8 ≥ EIN > 4 0 3 EIN > 8 12 2 8 ≥ EIN > 4 12 1 4 ≥ EIN > 0 0 FIGURE 1. BASIC HYSTERESIS SWITCH (SCHMITT TRIGGER) AND RESULTANT OUTPUT STATES Metallization Mask Layout 0 61 10 20 30 40 50 58 60 50 Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). 40 66 (1.676) 30 20 10 0 63 (1.600) 4 The layout represents a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90o with respect to the face of the chip. Therefore, the isolated chip is actually 7mils (0.17mm) larger in both dimensions. CA3098 Test Circuits V+ +6V IBIAS IBIAS ITOTAL mA 1.5kΩ 2 IIB 150Ω 5 8 mA 3 CA3098 VHR 5 8 7 VO 3 CA3098 1 1 VI 110Ω 6 6 7 1.1kΩ 2 4 4 VLR VI VREG -6V FIGURE 2. INPUT OFFSET VOLTAGE TEST CIRCUIT FIGURE 3. TOTAL SUPPLY CURRENT, AND INPUT BIAS CURRENT TEST CIRCUIT V+ IBIAS VI 450Ω 2 45Ω 6 VI 5 8 7 VO CA3098 3 VO tD tS 1 tF 4 VREG FIGURE 4. SWITCHING TIME TEST CIRCUIT 5 tR CA3098 -5 HIGH REF. INPUT OFFSET VOLTAGE (mV) LOW REF. INPUT OFFSET VOLTAGE (mV) Typical Performance Curves TA = 25 oC, V+ = +12V, VHR = 6V, VLR = 6V -4 VIO (LR) = VI - VLR -3 -2 -1 0 10 100 PROGRAMMING BIAS CURRENT (µA) 1 -3.5 -3.0 -2.5 -2.0 -50 -25 0 25 50 75 TEMPERATURE (oC) 100 125 FIGURE 7. INPUT OFFSET VOLTAGE (“LOW” REFERENCE) vs AMBIENT TEMPERATURE TA = 25oC, V+ = +12V, VHR = 6V, VLR = 6V 3 2 1 0 1 10 100 PROGRAMMING BIAS CURRENT (µA) FIGURE 9. MINIMUM HYSTERESIS VOLTAGE vs PROGRAMMING BIAS CURRENT 6 ±1 0 1000 10 100 PROGRAMMING BIAS CURRENT (µA) 1 1000 3 IBIAS = 100µA VIO (HR) = VI - VHR 2 1 0 -75 -50 -25 0 25 50 75 TEMPERATURE (oC) 100 125 FIGURE 8. INPUT OFFFSET VOLTAGE (“HIGH” REFERENCE) vs AMBIENT TEMPERATURE MIN. HYSTERESIS VOLTAGE (mV) MIN. HYSTERESIS VOLTAGE (mV) 4 ±2 FIGURE 6. INPUT OFFSET VOLTAGE (“HIGH” REFERENCE) vs PROGRAMMING BIAS CURRENT HIGH REF. INPUT OFFSET VOLTAGE (mV) LOW REF. INPUT OFFSET VOLTAGE (mV) VIO (LR) = VI - VLR TA = 25 oC, V+ = +12V, VHR = 6V, VLR = 0V VIO (HR) = VI - VHR ±3 1000 FIGURE 5. INPUT OFFSET VOLTAGE (“LOW” REFERENCE) vs PROGRAMMING BIAS CURRENT -1.5 -75 ±4 4 3 2 1 -100 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) FIGURE 10. MINIMUM HYSTERESIS VOLTAGE vs AMBIENT TEMPERATURE CA3098 Typical Performance Curves 1.2 TA = 25 oC, IBIAS = 100µA V+ = 12V OUTPUT SATURATION VOLTAGE (V) OUTPUT SATURATION VOLTAGE (V) 1.4 (Continued) 1.0 0.8 0.6 0.4 0.2 0 10 100 IBIAS = 100µA V+ = 10V 1.0 0.9 0.8 0.7 0.6 0.5 -100 1000 -50 -75 -25 FIGURE 11. OUTPUT SATURATION VOLTAGE vs OUTPUT SINK CURRENT 25 50 75 100 TA = 25 oC, V+ = 12V 800 IBIAS = 100µA VREG = 6V (NOTE) 1,000 100 10 1 700 600 500 400 300 200 0.1 1 10 100 PROGRAMMING BIAS CURRENT (µA) 1000 -75 -50 NOTE: See Figure 3 for definition of VREG 0 25 50 75 100 125 FIGURE 14. TOTAL SUPPLY CURRENT vs AMBIENT TEMPERATURE 1050 TA = 25 oC, V+ = 12V VREG = 6V (NOTE) 1000 10 DELAY TIME (ns) INPUT BIAS CURRENT (nA) -25 TEMPERATURE (oC) FIGURE 13. TOTAL SUPPLY CURRENT vs PROGRAMMING BIAS CURRENT 100 IIB (p-n-p) IIB (n-p-n) 1 TA = 25oC IBIAS = 100µA VLR = VHR = VREG = V+/2 950 900 850 0.1 1 10 100 PROGRAMMING BIAS CURRENT (µA) 1000 NOTE: See Figure 3 for definition of VREG FIGURE 15. INPUT BIAS CURRENT vs PROGRAMMING BIAS CURRENT 7 125 FIGURE 12. OUTPUT SATURATION VOLTAGE vs AMBIENT TEMPERATURE TOTAL SUPPLY CURRENT (µA) TOTAL SUPPLY CURRENT (µA) 10,000 0 TEMPERATURE (oC) OUTPUT SINK CURRENT (mA) 800 5 10 15 POSITIVE SUPPLY VOLTAGE (V) FIGURE 16. DELAY TIME vs SUPPLY VOLTAGE CA3098 Typical Performance Curves (Continued) TA = 25 oC OUTPUT FALL TIME (ns) IBIAS = 100µA STORAGE TIME (ns) VLR = VHR = VREG = V+/2 7000 40 TA = 25 oC IBIAS = 100µA VLR = VHR = VREG = V+/2 35 30 6500 5 10 5 15 FIGURE 17. STORAGE TIME vs SUPPLY VOLTAGE 2600 2500 VLR = VHR = VREG = V+/2 2400 OUTPUT RISE TIME (ns) OUTPUT RISE TIME (ns) 15 FIGURE 18. OUTPUT FALL TIME vs SUPPLY VOLTAGE TA = 25 oC IBIAS = 100µA 4000 10 POSITIVE SUPPLY VOLTAGE (V) POSITIVE SUPPLY VOLTAGE (V) 3000 2000 SUPPLY VOLTAGE = 5V IBIAS = 100µA VLR = VHR = VREG = 2.5V 2300 2200 2100 2000 1900 1800 5 10 1700 15 -40 -20 FIGURE 19. OUTPUT RISE TIME vs SUPPLY VOLTAGE 40 60 80 9000 SUPPLY VOLTAGE = 5V IBIAS = 100µA 8000 VLR = VHR = VREG = 2.5V STORAGE TIME (ns) OUTPUT FALL TIME (ns) 20 FIGURE 20. OUTPUT RISE TIME vs AMBIENT TEMPERATURE 45 40 0 TEMPERATURE (oC) POSITIVE SUPPLY VOLTAGE (V) 35 30 SUPPLY VOLTAGE = 5V IBIAS = 100µA VLR = VHR = VREG = 2.5V 7000 6000 5000 25 -40 -20 0 20 40 60 80 TEMPERATURE (oC) FIGURE 21. OUTPUT FALL TIME vs AMBIENT TEMPERATURE 8 4000 -40 -20 0 20 40 60 80 100 TEMPERATURE (oC) FIGURE 22. STORAGE TIME vs AMBIENT TEMPERATURE CA3098 Typical Performance Curves (Continued) 1100 SUPPLY VOLTAGE = 5V TA = 25oC, VLR = VHR = VREG = 2.5V 1000 DELAY TIME (ns) 1000 DELAY TIME (ns) 1100 SUPPLY VOLTAGE = 5V IBIAS = 100µA VLR = VHR = VREG = 2.5V 900 800 900 800 700 600 700 500 600 -40 -20 0 20 40 60 80 100 400 0 TEMPERATURE (oC) FIGURE 23. DELAY TIME vs AMBIENT TEMPERATURE 1000 FIGURE 24. DELAY TIME vs PROGRAMMING BIAS CURRENT 60 12000 SUPPLY VOLTAGE = 5V TA = 25 oC VLR = VHR = VREG = 2.5V 11000 SUPPLY VOLTAGE = 5V TA = 25 oC VLR = VHR = VREG = 2.5V 50 OUTPUT FALL TIME (ns) 10000 STORAGE TIME (ns) 500 PROGRAMMING BIAS CURRENT (µA) 9000 8000 7000 6000 5000 40 30 20 10 4000 3000 0 0 500 PROGRAMMING BIAS CURRENT (µA) 1000 0 FIGURE 25. STORAGE TIME vs PROGRAMMING BIAS CURRENT 500 PROGRAMMING BIAS CURRENT (µA) FIGURE 26. OUTPUT FALL TIME vs PROGRAMMING BIAS CURRENT 3000 OUTPTUT RISE TIME (ns) SUPPLY VOLTAGE = 5V TA = 25oC, VLR = VHR = VREG = 2.5V 2500 2000 1500 1000 0 500 1000 PROGRAMMING BIAS CURRENT (µA) FIGURE 27. OUTPUT RISE TIME vs PROGRAMMING BIAS CURRENT 9 1000 CA3098 Typical Applications +6V τ = RC x ln2 +6V 1N914 12kΩ RL 1.2kΩ 6 C 10kΩ R 12kΩ 5 RL 1.2kΩ 7 τ = RC x ln2 IL 6 10kΩ 3 CA3098 8 3 CA3098 2 8 60kΩ 4 R IL 5 7 2 10kΩ 60kΩ 4 C 1 1 1N914 10kΩ FIGURE 28. TIME DELAY CIRCUIT: TERMINAL 3 “SINKS” AFTER τ SECONDS FIGURE 29. TIME DELAY CIRCUIT: “SINK” CURRENT INTERRUPTED AFTER τ SECONDS +6V 10kΩ 1kΩ 6 V1 5 7 SINE WAVE INPUT 8 CA3098 1 V2 3 SQUARE WAVE OUTPUT 2 4 60kΩ -6V FIGURE 30. SINE WAVE TO SQUARE WAVE CONVERTER WITH DUTY CYCLE ADJUSTMENT (V 1 AND V2) 2kΩ TH1 120kΩ 10kΩ TANK 2 UPPER THRESHOLD ADJUST 10kΩ 6 LOWER THRESHOLD ADJUST 10kΩ 5kΩ CA3098 3 TH2 1kΩ 8 TH2 5 7 3 G 60Hz TH1 MT1 1 2 WATER LEVEL 1 120VAC 4 10kΩ T2301B MT2 PUMP MOTOR -6V (+) FIGURE 31A. WATER LEVEL CONTROL CIRCUIT NOTES: 1. Motor pump is “ON” when water level rises above thermistor TH2. 2. Motor pump remains “ON” until water level falls below thermistor TH1. 3. Thermistors, operate in self heating mode. FIGURE 31B. WATER LEVEL DIAGRAM FOR CIRCUIT FIGURE 31. WATER LEVEL CONTROL APPLICATION 10 CA3098 Typical Applications (Continued) +6V 1kΩ 1MΩ C1 LAMP 7 6 1.1MΩ 5 8 TRIGGER INPUT 2.5V R4 100kΩ R3 100kΩ 120VAC 60Hz SENSOR 1kΩ R2 100kΩ 1 CA3098 2 1kΩ 5 8 3 4 60kΩ MT1 6 7 0V G 2 R1 100kΩ CA3098 1 -6V 3 TRIAC MT2 DESIRED tON (ms) VALUE OF C 1 (µF) 15 0.01 150 0.1 300 0.2 LOAD (e.g., 100kΩ) 4 V- FIGURE 32. OFF/ON CONTROL OF TRIAC WITH PROGRAMMABLE HYSTERESIS 11 FIGURE 33. ONE SHOT MULTIVIBRATOR CA3098 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - -B-AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 8 10.92 3.81 8 7 4 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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