CET CEG9926

CEG9926
Nov. 2002
Dual N-Channel Enhancement Mode Field Effect Transistor
FEATURES
20V , 4.5A , RDS(ON)=30mΩ @VGS=4.5V.
RDS(ON)=40m Ω @VGS=2.5V.
Super high dense cell design for extremely low RDS(ON).
D1 1
8 D2
S1 2
High power and current handing capability.
S1 3
7 S2
6 S2
TSSOP-8 for Surface Mount Package.
G1 4
5 G2
G2
S2
S2
D2
ȀȀȀ
G1
S1
S1
D1
9
TSSOP-8
ABSOLUTE MAXIMUM RATINGS (TA=25 C unless otherwise noted)
Parameter
Symbol
Limit
Unit
Drain-Source Voltage
VDS
20
V
Gate-Source Voltage
VGS
Ć8
V
Drain Current-Continuous a
b
-Pulsed
ID
Ć4.5
A
IDM
Ć25
A
Drain-Source Diode Forward Current a
IS
1.7
A
Maximum Power Dissipation a
PD
ȑȎȐ
W
Operating Junction and Storage
Temperature Range
TJ, TSTG
-55 to 150
C
RįJA
125
C/W
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient a
9-17
CEG9926
ELECTRICAL CHARACTERISTICS (TA=25 C unless otherwise noted)
Parameter
Symbol
Condition
Drain-Source Breakdown Voltage
BVDSS
VGS= 0V, ID=250µA
Zero Gate Voltage Drain Current
IDSS
VDS=20V, VGS=0V
Gate-Body Leakage
IGSS
VGS=Ć8V, VDS=0V
VGS(th)
VDS=VGS, ID=250µA
RDS(ON)
VGS=4.5V, ID=4.5A
VGS=4.0V, ID=5A
VGS=2.5V, ID=3.5A
Min Typ C Max Unit
OFF CHARACTERISTICS
20
V
1
µA
ĆȑȐȐ nA
ON CHARACTERISTICS b
Gate Threshold Voltage
9
Drain-Source On-State Resistance
ID(ON)
gFS
On-State Drain Current
Forward Transconductance
VDS=5V, VGS=4.5V
VDS=10V, ID=4.5A
0.5
24
23
32
1.0
V
30
mΩȀȀȀ
mΩ
mΩ
40
A
10
10
S
500
PF
300
PF
140
PF
C
DYNAMIC CHARACTERISTICS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 8V, VGS = 0V
f =1.0MHZ
C
SWITCHING CHARACTERISTICS
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
tD(ON)
tr
tD(OFF)
VDD = 10V,
ID =1A,
VGEN = 4.5V,
RGEN = 6 Ω
20
40
ns
18
40
ns
60
108
ns
Fall time
tf
28
56
ns
Total Gate Charge
Qg
10
15
nC
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS =10V, ID =4.5A,
VGS =4.5V
9-18
2.3
nC
2.9
nC
CEG9926
ELECTRICAL CHARACTERISTICS (TA=25 C unless otherwise noted)
Parameter
C
Min Typ Max Unit
Condition
Symbol
DRAIN-SOURCE DIODE CHARACTERISTICS b
Diode Forward Voltage
VGS = 0V, Is =1.7A
VSD
0.8
1.2
V
Notes
a.Surface Mounted on FR4 Board, t ś10sec.
b.Pulse Test:Pulse Width ś300ijs, Duty Cycle ś 2%.
c.Guaranteed by design, not subject to production testing.
25
10
VGS=4.5,3.5,2.5V
VGS=2.0V
20
ID, Drain Current (A)
ID, Drain Current(A)
8
6
4
2
VGS=1.5V
0.5
1.0
1.5
2.0
2.5
10
5
Tj=125 C
0
0.0
0
0
3.0
VDS, Drain-to-Source Voltage (V)
0.5
25 C
-55 C
1
1.5
2
2.5
3
VGS, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
1.80
RDS(ON), Normalized
RDS(ON), On-Resistance(Ohms)
600
Ciss
500
C, Capacitance (pF)
9
15
400
Coss
300
200
Crss
100
0
0
2
4
6
8
10
12
1.60
ID=4.5A
VGS=4.5V
1.40
1.20
1.00
0.80
0.60
-50 -25
0
25
50
75
100 125 150
TJ, Junction Temperature( C)
VDS, Drain-to Source Voltage (V)
Figure 4. On-Resistance Variation with
Temperature
Figure 3. Capacitance
9-19
1.60
BVDSS, Normalized
Drain-Source Breakdown Voltage
Vth, Normalized
Gate-Source Threshold Voltage
CEG9926
VDS=VGS
ID=250ijA
1.40
1.20
1.00
0.80
0.60
0.40
-50 -25
0
25
50
75 100 125 150
1.15
ID=250ijA
1.10
1.05
1.00
0.95
0.90
0.85
-50 -25
50
75 100 125 150
Figure 6. Breakdown Voltage Variation
with Temperature
Figure 5. Gate Threshold Variation
with Temperature
30
20
10
25
Is, Source-drain current (A)
gFS, Transconductance (S)
25
Tj, Junction Temperature ( C)
Tj, Junction Temperature ( C)
20
15
10
VDS=10V
5
0
0
3
6
9
12
1
0.1
0.4
15
IDS, Drain-Source Current (A)
0.6
1.0
0.8
1.2
1.4
VSD, Body Diode Forward Voltage (V)
Figure 7. Transconductance Variation
with Drain Current
Figure 8. Body Diode Forward Voltage
Variation with Source Current
2
10
5
4
ID, Drain Current (A)
6
10 12 14 16
Qg, Total Gate Charge (nC)
s
2
1s
0m
0
)
s
10
8
s
-1
10
-2
0
ON
10
1
S(
t
C
2
10
RD
0
i
Lim
m
3
1m
10 1
10
VDS=10V
ID=4.5A
4
D
VGS, Gate to Source Voltage (V)
9
0
TA=25 C
Tj=150 C
Single Pulse
10 -2
10 -1
10 0
10
1
VDS, Drain-Source Voltage (V)
Figure 10. Maximum Safe
Operating Area
Figure 9. Gate Charge
9-20
10
2
CEG9926
4
VDD
t on
RL
V IN
D
td(off)
tf
90%
90%
VOUT
VOUT
VGS
RGEN
toff
tr
td(on)
10%
INVERTED
10%
G
90%
S
VIN
50%
50%
10%
PULSE WIDTH
Figure 12. Switching Waveforms
Figure 11. Switching Test Circuit
r(t),Normalized Effective
Transient Thermal Impedance
9
0
10
D=0.5
0.2
10
-1
0.1
0.05
PDM
0.02
10
t1
0.01
-2
t2
1. RįJA (t)=r (t) * RįJA
2. RįJA=See Datasheet
3. TJM-TA = P* RįJA (t)
4. Duty Cycle, D=t1/t2
Single Pulse
10
-3
10
-4
10
-3
10
-2
10
-1
10
0
10
1
Square Wave Pulse Duration (sec)
Figure 13. Normalized Thermal Transient Impedance Curve
9-21
10
2