TI CSD16323Q3

CSD16323Q3
SLPS224B – AUGUST 2009 – REVISED NOVEMBER 2011
www.ti.com
N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD16323Q3
FEATURES
1
•
•
•
•
•
•
•
•
2
Optimized for 5V Gate Drive
Ultra Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb Free Terminal Plating
RoHS Compliant
Halogen Free
SON 3.3mm x 3.3mm Plastic Package
PRODUCT SUMMARY
VDS
Drain to Source Voltage
25
V
Qg
Gate Charge Total (4.5V)
6.2
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
Vth
•
Point-of-Load Synchronous Buck Converter
for Applications in Networking, Telecom and
Computing Systems
Optimized for Control or Synchronous FET
Applications
DESCRIPTION
Top View
S
1
8
D
S
2
7
D
S
3
6
D
G
4
mΩ
VGS = 4.5V
4.4
mΩ
VGS = 8V
3.8
mΩ
Threshold Voltage
1.1
V
ORDERING INFORMATION
Package
Media
CSD16323Q3
SON 3.3 × 3.3
Plastic Package
13-inch
reel
Qty
Ship
2500
Tape and
Reel
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
VDS
Drain to Source Voltage
25
V
VGS
Gate to Source Voltage
+10 / –8
V
Continuous Drain Current, TC = 25°C
60
A
Continuous Drain Current(1)
21
A
Pulsed Drain Current, TA = 25°C(2)
112
A
ID
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion and optimized
for 5V gate drive applications.
Drain to Source On Resistance
nC
5.4
Device
APPLICATIONS
•
1.1
VGS = 3V
IDM
(1)
PD
Power Dissipation
3
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 50A, L = 0.1mH, RG = 25Ω
125
mJ
(1) RθJA = 43°C/W on 1in2 Cu (2 oz.) on 0.060" thick FR4 PCB.
(2) Pulse width ≤300μs, duty cycle ≤2%
D
5
D
P0095-01
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
CSD16323Q3
SLPS224B – AUGUST 2009 – REVISED NOVEMBER 2011
www.ti.com
RDS(ON) vs VGS
Gate Charge
10
ID = 24A
14
12
10
TC = 125°C
8
ID = 24A
VDS = 12.5V
9
VG − Gate Voltage − V
RDS(on) − On-State Resistance − mW
16
6
4
8
7
6
5
4
3
2
2
TC = 25°C
1
0
0
0
1
2
3
4
5
6
7
8
VGS − Gate to Source Voltage − V
9
0
10
2
4
6
8
10
12
14
Qg − Gate Charge − nC
G006
G003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, ID = 250μA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 20V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = +10/-8V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, ID = 250μA
RDS(on)
gfs
Drain to Source On Resistance
Transconductance
25
0.9
V
1
μA
100
nA
1.1
1.4
V
VGS = 3V, ID = 24A
5.4
7.2
mΩ
VGS = 4.5V, ID = 24A
4.4
5.5
mΩ
VGS = 8V, ID = 24A
3.8
4.5
mΩ
VDS = 12.5V, ID = 24A
108
S
Dynamic Characteristics
CISS
Input Capacitance
1020
1300
pF
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
740
960
pF
50
65
Rg
pF
Series Gate Resistance
1.4
2.8
Ω
Qg
Gate Charge Total (4.5V)
6.2
8.4
nC
Qgd
Gate Charge Gate to Drain
1.1
nC
Qgs
Gate Charge Gate to Source
1.8
nC
Qg(th)
Gate Charge at Vth
1
nC
QOSS
Output Charge
14
nC
td(on)
Turn On Delay Time
5.3
ns
tr
Rise Time
15
ns
td(off)
Turn Off Delay Time
13
ns
tf
Fall Time
6.3
ns
VGS = 0V, VDS = 12.5V, f = 1MHz
VDS = 12.5V, ID = 24A
VDS = 12.5V, VGS = 0V
VDS = 12.5V, VGS = 4.5V ID = 24A
RG = 2Ω
Diode Characteristics
VSD
Diode Forward Voltage
IS = 24A, VGS = 0V
Qrr
Reverse Recovery Charge
VDD = 12.5V, IF = 24A, di/dt = 300A/μs
21
nC
trr
Reverse Recovery Time
VDD = 12.5V, IF = 24A, di/dt = 300A/μs
16
ns
2
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0.85
1
V
Copyright © 2009–2011, Texas Instruments Incorporated
Product Folder Link(s): CSD16323Q3
CSD16323Q3
SLPS224B – AUGUST 2009 – REVISED NOVEMBER 2011
www.ti.com
THERMAL INFORMATION
THERMAL METRIC (1) (2)
CSD16323Q3
8 PINS
θJA
Junction-to-ambient thermal resistance
42.0
θJCtop
Junction-to-case (top) thermal resistance
20.6
θJB
Junction-to-board thermal resistance
8.8
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
8.7
θJCbot
Junction-to-case (bottom) thermal resistance
0.1
(1)
(2)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
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3
CSD16323Q3
SLPS224B – AUGUST 2009 – REVISED NOVEMBER 2011
GATE
www.ti.com
GATE
Source
Source
Max RθJA = 162°C/W
when mounted on
minimum pad area of 2
oz. Cu.
Max RθJA = 58°C/W
when mounted on 1
inch2 of 2 oz. Cu.
DRAIN
DRAIN
M0161-02
M0161-01
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
ZqJA – NormalizedThermal Impedance
10
1
0.5
0.3
0.1
Duty Cycle = t1/t2
0.1
0.05
0.01
P
0.02
0.01
t1
t2
Typical RqJA = 138°C/W (min Cu)
TJ = P ´ ZqJA ´ RqJA
Single Pulse
0.001
0.001
0.01
0.1
1
10
100
1k
tP – Pulse Duration–s
G012
Figure 1. Transient Thermal Impedance
4
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CSD16323Q3
SLPS224B – AUGUST 2009 – REVISED NOVEMBER 2011
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
60
60
50
VGS = 4.5V
40
ID − Drain Current − A
ID − Drain Current − A
VDS = 5V
VGS = 8V
50
VGS = 2V
VGS = 3.5V
30
20
VGS = 2.5V
10
40
TC = 125°C
30
TC = 25°C
20
TC = −55°C
10
0
0.0
0
0.5
1.0
1.5
1
2.0
VDS − Drain to Source Voltage − V
1.25
1.75
2
2.25
2.5
VGS − Gate to Source Voltage − V
G001
Figure 2. Saturation Characteristics
G002
Figure 3. Transfer Characteristics
10
2.5
f = 1MHz
VGS = 0V
ID = 24A
VDS = 12.5V
9
8
C − Capacitance − nF
VG − Gate Voltage − V
1.5
7
6
5
4
3
2.0
CISS = CGD + CGS
1.5
COSS = CGD + CGS
1.0
CRSS = CGD
0.5
2
1
0
0.0
0
2
4
6
8
10
12
14
Qg − Gate Charge − nC
0
5
20
25
G004
Figure 5. Capacitance
16
RDS(on) − On-State Resistance − mW
1.4
VGS(th) − Threshold Voltage − V
15
VDS − Drain to Source Voltage − V
G003
Figure 4. Gate Charge
ID = 250mA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−75
10
ID = 24A
14
12
10
TC = 125°C
8
6
4
2
TC = 25°C
0
−25
25
75
125
175
TC − Case Temperature − °C
0
1
3
4
5
6
7
8
9
10
VGS − Gate to Source Voltage − V
G005
Figure 6. Threshold Voltage vs. Temperature
2
G006
Figure 7. On Resistance vs. Gate Voltage
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CSD16323Q3
SLPS224B – AUGUST 2009 – REVISED NOVEMBER 2011
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
100
ID = 24A
VGS = 10V
1.4
ISD − Source to Drain Current − A
Normalized On-State Resistance
1.6
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−75
10
1
TC = 125°C
0.1
TC = 25°C
0.01
0.001
0.0001
−25
25
75
125
175
TC − Case Temperature − °C
0.0
0.2
0.6
0.8
VSD − Source to Drain Voltage − V
G007
Figure 8. Normalized On Resistance vs. Temperature
1.0
G008
Figure 9. Typical Diode Forward Voltage
1000
1k
1ms
10ms
100ms
1s
DC
I(AV) − Peak Avalanche Current − A
IDS - Drain-to-Source Current - A
0.4
100
10
Area Limited
by Rds(on)
1
0.1
Single Pulse
Typical RthetaJA = 138ºC/W(min Cu)
0.01
0.01
0.1
1
10
TC = 125°C
10
1
0.01
100
VDS - Drain-to-Source Voltage - V
TC = 25°C
100
0.1
1
10
100
G001
t(AV) − Time in Avalanche − ms
Figure 10. Maximum Safe Operating Area
G010
Figure 11. Single Pulse Unclamped Inductive Switching
80
ID − Drain Current − A
70
60
50
40
30
20
10
0
−50
−25
0
25
50
75
100
125
TC − Case Temperature − °C
150
175
G011
Figure 12. Maximum Drain Current vs. Temperature
6
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Product Folder Link(s): CSD16323Q3
CSD16323Q3
SLPS224B – AUGUST 2009 – REVISED NOVEMBER 2011
www.ti.com
MECHANICAL DATA
Q3 Package Dimensions
D2
D
H
L
1
2
7
3
6
4
5
5
4
3
b
E2
E
6
e
E
7
2
8
8
1
q
L1
Top View
A1
Bottom View
A
Side View
c
D
Front View
M0142-01
DIM
MILLIMETERS
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
A
0.950
1.000
1.100
0.037
0.039
0.043
A1
0.000
0.000
0.050
0.000
0.000
0.002
b
0.280
0.340
0.400
0.011
0.013
0.016
c
0.150
0.200
0.250
0.006
0.008
0.010
D
3.200
3.300
3.400
0.126
0.130
0.134
D1
–
–
–
–
–
–
D2
1.650
1.750
1.800
0.065
0.069
0.071
E
3.200
3.300
3.400
0.126
0.130
0.134
E1
–
–
–
–
–
–
E2
2.350
2.450
2.550
0.093
0.096
0.100
e
0.650 TYP
0.026
H
0.35
0.450
0.550
0.014
0.018
0.022
L
0.35
0.450
0.550
0.014
0.018
0.022
L1
–
–
–
–
–
–
θ
–
–
–
–
–
–
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CSD16323Q3
SLPS224B – AUGUST 2009 – REVISED NOVEMBER 2011
www.ti.com
2.31
1
8
8
1
0.65 Typ.
2.45
5
4
5
3.50
0.56
0.41
4
0.50 Typ.
Recommended PCB Pattern
0.63
M0143-01
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
1.75 ±0.10
Q3 Tape and Reel Information
4.00 ±0.10 (See Note 1)
Ø 1.50
+0.10
–0.00
3.60
1.30
3.60
5.50 ±0.05
12.00
+0.30
–0.10
8.00 ±0.10
2.00 ±0.05
M0144-01
Notes:
1. 10 sprocket hole pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm IN 100mm, noncumulative over 250mm
3. Material:black static dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and Convection) PbF Reflow Compatible
8
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CSD16323Q3
SLPS224B – AUGUST 2009 – REVISED NOVEMBER 2011
www.ti.com
REVISION HISTORY
Changes from Original (August 2009) to Revision A
Page
•
Changed RDS(on) - VGS = 3V, ID = 24A MAX value From: 6.5 To: 7.2 ................................................................................... 2
•
Deleted the Package Marking Information section ............................................................................................................... 8
Changes from Revision A (April 2010) to Revision B
Page
•
Replaced the THERMAL CHARACTERISTICS table with the new Thermal Information Table .......................................... 3
•
Replaced Figure 10 - Maximum Safe Operating Area .......................................................................................................... 6
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PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD16323Q3
Package Package Pins
Type Drawing
SON
DQG
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
3.6
B0
(mm)
K0
(mm)
P1
(mm)
3.6
1.2
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD16323Q3
SON
DQG
8
2500
335.0
335.0
32.0
Pack Materials-Page 2
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