CSD17301Q5A www.ti.com SLPS215A – JANUARY 2010 – REVISED FEBRUARY 2010 30V, N-Channel NexFET™ Power MOSFETs Check for Samples: CSD17301Q5A FEATURES 1 • • • • • • • • 2 PRODUCT SUMMARY Optimized for 5V Gate Drive Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package VDS Drain to Source Voltage 30 V Qg Gate Charge Total (4.5V) 19 nC Qgd Gate Charge Gate to Drain RDS(on) • Drain to Source On Resistance VGS(th) mΩ VGS = 4.5V 2.3 mΩ 2 mΩ Threshold Voltage 1.1 V Text and br Added for Spacing ORDERING INFORMATION Notebook Point of Load Point-of-Load Synchronous Buck in Networking, Telecom and Computing Systems Optimized for Synchronous FET Applications DESCRIPTION Device Package Media CSD17301Q5A SON 5-mm × 6-mm Plastic Package 13-inch reel Top View Qty Ship 2500 Tape and Reel Text and br Added for Spacing ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications, and optimized for 5V gate drive applications. VALUE UNIT VDS Drain to Source Voltage 30 V VGS Gate to Source Voltage +10 / –8 V Continuous Drain Current, TC = 25°C 100 A Continuous Drain Current (1) 28 A IDM Pulsed Drain Current, TA = 25°C (2) 118 A PD Power Dissipation (1) 3.2 W ID S 1 8 D TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C S 2 7 D EAS Avalanche Energy, single pulse ID = 91A, L = 0.1mH, RG = 25Ω 414 mJ S 3 6 D G 4 5 D D (1) (2) P0093-01 Typical RqJA = 39°C/W on 1in2 Cu (2 oz) on 0.060" thick FR4 PCB. Pulse width ≤300ms, duty cycle ≤2% RDS(on) vs VGS GATE CHARGE 10 8 ID = 25A 9 VGS - Gate-to-Source Voltage - V RDS(on) - On-State Resistance - mΩ nC 2.9 VGS = 8V APPLICATIONS • • 4.3 VGS = 3V 8 7 6 T C = 125°C 5 4 3 2 T C = 25°C 1 0 ID = 25A VDS = 15V 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 G006 0 5 10 15 20 Qg - Gate Charge - nC 25 30 G003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CSD17301Q5A SLPS215A – JANUARY 2010 – REVISED FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250mA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 24V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10/-8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250mA RDS(on) Drain to Source On Resistance 30 0.9 Transconductance mA 100 nA 1.1 1.55 V VGS = 3V, ID = 25A 2.9 3.7 mΩ VGS = 4.5V, ID = 25A 2.3 3 mΩ 2 2.6 mΩ VGS = 8V, ID = 25A gfs V 1 VDS = 15V, ID = 25A 149 S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance 2660 3480 pF 1420 1850 Crss pF Reverse Transfer Capacitance 80 105 pF RG Series Gate Resistance 1.3 2.6 Ω Qg Gate Charge Total (4.5V) 19 25 nC Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 15V, f = 1MHz VDS = 15V, ID = 25A VDS = 14V, VGS = 0V VDS = 15V, VGS = 4.5V, ID = 25A RG = 2Ω 4.3 nC 5.7 nC 2.9 nC 35 nC 10.7 ns 16.2 ns 28 ns 10.5 ns Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 25A, VGS = 0V 0.8 VDD= 14V, IF = 25A, di/dt = 300A/ms 50 1 nC V 33 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER (1) R qJC Thermal Resistance Junction to Case R qJA Thermal Resistance Junction to Ambient (1) (1) (2) 2 (2) MIN TYP MAX UNIT 2.2 °C/W 49 °C/W R qJC is determined with the device mounted on a 1 inch square 2 oz. Cu pad on a 1.5 × 1.5 in 0.060 inch thick FR4 board. R qJC is specified by design while R qJA is determined by the user’s board design. Device mounted on FR4 Material with 1 inch2 of 2 oz. Cu. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17301Q5A CSD17301Q5A www.ti.com SLPS215A – JANUARY 2010 – REVISED FEBRUARY 2010 GATE GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RqJA = 49°C/W when mounted on 1inch2 of 2 oz. Cu. Source Max RqJA = 120°C/W when mounted on minimum pad area of 2 oz. Cu. DRAIN DRAIN M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA - Normalized Thermal Impedance 10 1 0.5 0.3 0.1 Duty Cycle = t1/t2 0.1 0.05 P 0.02 0.01 t1 0.01 t2 Typical RqJA = 96°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA Single Pulse 0.001 0.001 0.01 0.1 1 tp - Pulse Duration - s 10 100 1k G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17301Q5A 3 CSD17301Q5A SLPS215A – JANUARY 2010 – REVISED FEBRUARY 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 80 70 IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A 80 VGS = 8V 60 VGS = 4.5V 50 VGS = 3V 40 VGS = 2.5V 30 20 VGS = 2V 10 0 VDS = 5V 70 60 50 T C = 125°C 40 T C = 25°C 30 20 T C = -55°C 10 0 0 0.2 0.4 0.6 0.8 VDS - Drain-to-Source Voltage - V 1 0 0.5 Figure 2. Saturation Characteristics TEXT ADDED FOR SPACING G002 TEXT ADDED FOR SPACING ID = 25A VDS = 15V 7 f = 1MHz VGS = 0V 6 C - Capacitance - nF 6 5 4 3 2 5 Coss = Cds + Cgd 4 Ciss = Cgd + Cgs 3 2 Crss = Cgd 1 1 0 0 5 10 15 20 Qg - Gate Charge - nC 25 30 0 5 10 15 20 VDS - Drain-to-Source Voltage - V G003 Figure 4. Gate Charge 25 30 G004 Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 10 1.4 RDS(on) - On-State Resistance - mΩ ID = 250µA VGS(th) - Threshold Voltage - V 3 7 0 1.2 1 0.8 0.6 0.4 0.2 0 -75 ID = 25A 9 8 7 6 T C = 125°C 5 4 3 2 T C = 25°C 1 0 -25 25 75 T C - Case Temperature - °C 125 175 0 1 G005 Figure 6. Threshold Voltage vs. Temperature 4 2.5 Figure 3. Transfer Characteristics 8 VGS - Gate-to-Source Voltage - V 1 1.5 2 VGS - Gate-to-Source Voltage - V G001 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 G006 Figure 7. On Resistance vs. Gate Voltage Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17301Q5A CSD17301Q5A www.ti.com SLPS215A – JANUARY 2010 – REVISED FEBRUARY 2010 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 ID = 25A VGS = 4.5V 1.6 ISD - Source-to-Drain Current - A Normalized On-State Resistance 1.8 1.4 1.2 1 0.8 0.6 0.4 0.2 -75 10 1 T C = 125°C 0.1 T C = 25°C 0.01 0.001 0.0001 -25 25 75 T C - Case Temperature - °C 125 175 0 0.2 G007 Figure 8. On Resistance vs. Temperature 1 G008 Figure 9. Typical Diode Forward Voltage TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1k I(AV) - Peak Avalanche Current - A 1k IDS - Drain-to-Source Current - A 0.4 0.6 0.8 VSD - Source-to-Drain Voltage - V 100 1ms 10 10ms 100ms 1001 1 Area Limited by RDS(on) 0.1 1s Single Pulse Typical R θJA = 96°C/W (min Cu) 0.01 0.01 DC 0.1 1 10 VDS - Drain-to-Source Voltage - V 100 100 T C = 25°C 10 T C = 125°C 1 0.01 G009 Figure 10. Maximum Safe Operating Area 0.1 1 10 t(AV) - Time in Avalanche - ms 100 G010 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING IDS - Drain-to-Source Current - A 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 T C - Case Temperature - °C 150 175 G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17301Q5A 5 CSD17301Q5A SLPS215A – JANUARY 2010 – REVISED FEBRUARY 2010 www.ti.com MECHANICAL DATA Q5A Package Dimensions L E2 H K 7 D2 3 4 b 4 5 5 6 3 6 e D1 7 2 2 8 8 1 1 q L1 Top View Bottom View Side View c A q E1 E Front View M0135-01 DIM MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.30 D1 4.80 4.90 5.00 D2 3.61 3.81 3.96 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 e 6 1.27 BSC H 0.41 K 1.10 0.51 0.61 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 q 0° Submit Documentation Feedback 12° Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17301Q5A CSD17301Q5A www.ti.com SLPS215A – JANUARY 2010 – REVISED FEBRUARY 2010 MILLIMETERS INCHES Recommended PCB Pattern DIM MIN MAX MIN MAX F1 F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 F8 F4 F10 M0139-01 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket 6. MSL1 260°C (IR and convection) PbF reflow compatible Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17301Q5A 7 CSD17301Q5A SLPS215A – JANUARY 2010 – REVISED FEBRUARY 2010 www.ti.com Package Marking Information Location 8 1st Line CSD = Fixed Characters NNNNN = Product Code 2nd Line (Date Code) YY = Last 2 digits of the Year WW = 2-digit Work Week C = Country of Origin 5 5 8 4 1 CSDNNNNN YYWWC LLLLL > Philippines = P > Taiwan = T > China = C 3rd Line LLLLL = Last 5 digits of the Wafer Lot # 1 4 Pin 1 Identifier M0136-01 REVISION HISTORY Changes from Original (January) to Revision A Page • Changed the Abs Max Ratings table, Avalanche Energy, single pulse From: ID = 85A, L = 0.1mH, RG = 25Ω Value = 361 To: ID = 91A, L = 0.1mH, RG = 25Ω Value = 414 .......................................................................................................... 1 • Changed Figure 11 ............................................................................................................................................................... 5 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17301Q5A IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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