Actual Size 3 mm x 3 mm DAC7553 www.ti.com SLAS477 – AUGUST 2005 12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER FEATURES 2.7-V to 5.5-V Single Supply 12-Bit Linearity and Monotonicity Rail-to-Rail Voltage Output Settling Time: 5 µs (Max) Ultralow Glitch Energy: 0.1 nVs Ultralow Crosstalk: –100 dB Low Power: 440 µA (Max) Per-Channel Power Down: 2 µA (Max) Power-On Reset to Midscale 2s Complement Input Data Format SPI-Compatible Serial Interface: Up to 50 MHz Daisy-Chain Capability Asynchronous Hardware Clear Simultaneous or Sequential Update Specified Temperature Range: –40°C to 105°C Small 3-mm × 3-mm, 16-Lead QFN Package The DAC7553 is a 12-bit, dual-channel, voltage-output DAC with exceptional linearity and monotonicity. Its proprietary architecture minimizes undesired transients such as code-to-code glitch and channel-to-channel crosstalk. The low-power DAC7553 operates from a single 2.7-V to 5.5-V supply. The DAC7553 output amplifiers can drive a 2-kΩ, 200-pF load rail-to-rail with 5-µs settling time; the output range is set using an external voltage reference. The 3-wire serial interface operates at clock rates up to 50 MHz and is compatible with SPI, QSPI, Microwire™, and DSP interface standards. The outputs of all DACs may be updated simultaneously or sequentially. The parts incorporate a power-on-reset circuit to ensure that the DAC outputs power up at midscale and remain there until a valid write cycle to the device takes place. The parts contain a power-down feature that reduces the current consumption of the device to under 2 µA. The small size and low-power operation makes the DAC7553 ideally suited for battery-operated portable applications. The power consumption is typically 1.5 mW at 5 V, 0.75 mW at 3 V, and reduces to 1 µW in power-down mode. APPLICATIONS • • • • • Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control The DAC7553 is available in a 16-lead QFN package and is specified over –40°C to 105°C. FUNCTIONAL BLOCK DIAGRAM VDD IOVDD VREFA VFBA _ Input Register SCLK DAC Register String DAC A Interface Logic SYNC Input Register CLR DAC Register String DAC B Power-On Reset DAC7553 DCEN + VFBB _ SDIN SDO VOUT A GND VOUT B + Power-Down Logic VREFB PD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Microwire is a trademark of National Semiconductor Corp.. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2005, Texas Instruments Incorporated PRODUCT PREVIEW • • • • • • • • • • • • • • • • DESCRIPTION DAC7553 www.ti.com SLAS477 – AUGUST 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING DAC7553 16 QFN RGT –40°C TO 105°C D753 (1) ORDERING NUMBER TRANSPORT MEDIA DAC7553IRGTT 250-piece Tape and Reel DAC7553IRGTR 2500-piece Tape and Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS PRODUCT PREVIEW over operating free-air temperature range (unless otherwise noted) (1) UNIT VDD to GND –0.3 V to 6 V Digital input voltage to GND –0.3 V to VDD + 0.3 V Vout to GND –0.3 V to VDD+ 0.3 V Operating temperature range –40°C to 105°C Storage temperature range –65°C to 150°C Junction temperature (TJ Max) (1) 2 150°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. DAC7553 www.ti.com SLAS477 – AUGUST 2005 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 12 Relative accuracy Differential nonlinearity Specified monotonic by design ±1 LSB ±0.08 ±0.5 LSB ±12 mV ±12 mV Offset error Zero-scale error All zeroes loaded to DAC register Gain error Full-scale error Zero-scale error drift Gain temperature coefficient PSRR VDD = 5 V Bits ±0.35 ±0.15 %FSR ±0.5 %FSR 7 µV/°C 3 ppm of FSR/°C 0.75 mV/V OUTPUT CHARACTERISTICS (2) Output voltage settling time 0 RL = 2 kΩ; 0 pF < CL < 200 pF 5 Slew rate Capacitive load stability VREF 1.8 RL = ∞ Digital-to-analog glitch impulse 1 LSB change around major carry Channel-to-channel crosstalk 1-kHz full-scale sine wave, outputs unloaded µs V/µs 470 RL = 2 kΩ V pF 1000 0.1 nV-s –100 dB Digital feedthrough 0.1 nV-s Output noise density (10-kHz offset frequency) 120 nV/rtHz –85 dB 1 Ω Total harmonic distortion FOUT = 1 kHz, FS = 1 MSPS, BW = 20 kHz DC output impedance Short-circuit current Power-up time VDD = 5 V 50 VDD = 3 V 20 Coming out of power-down mode, VDD = 5 V 15 Coming out of power-down mode, VDD = 3 V 15 PRODUCT PREVIEW Output voltage range mA µs REFERENCE INPUT VREF Input range Reference input impedance Reference current 0 VDD VREFA and VREFB shorted together 50 VREFA = VREFB = VDD = 5 V, VREFA and VREFB shorted together 100 250 VREFA = VREFB = VDD = 3 V, VREFA and VREFB shorted together 60 123 V kΩ µA LOGIC INPUTS (2) Input current VIN_L, Input low voltage IOVDD ≥ 2.7 V VIN_H, Input high voltage IOVDD ≥ 2.7 V Pin capacitance (1) (2) ±1 µA 0.3 IOVDD V 3 pF 0.7 IOVDD V Linearity tested using a reduced code range of 30 to 4065; output unloaded. Specified by design and characterization, not production tested. For 1.8 V < IOVDD < 2.7 V, It is recommended that VIH = IOVDD, VIL = GND. 3 DAC7553 www.ti.com SLAS477 – AUGUST 2005 ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS VDD,, IOVDD (3) IDD(normal operation) VDD = 3.6 V to 5.5 V VDD = 2.7 V to 3.6 V 2.7 5.5 V DAC active and excluding load current VIH = IOVDD and VIL = GND 300 440 250 400 0.2 2 0.05 2 µA IDD (all power-down modes) VDD = 3.6 V to 5.5 V VDD = 2.7 V to 3.6 V VIH = IOVDD and VIL = GND POWER EFFICIENCY IOUT/IDD (3) PRODUCT PREVIEW 4 ILOAD = 2 mA, VDD = 5 V 93% IOVDD operates down to 1.8 V with slightly degraded timing, as long as VIH = IOVDD and VIL = GND. µA DAC7553 www.ti.com SLAS477 – AUGUST 2005 TIMING CHARACTERISTICS (1) (2) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified TEST CONDITIONS t1 (3) SCLK cycle time t2 SCLK HIGH time t3 SCLK LOW time t4 SYNC falling edge to SCLK falling edge setup time t5 Data setup time t6 Data hold time t7 SCLK falling edge to SYNC rising edge t8 Minimum SYNC HIGH time t9 SCLK falling edge to SDO valid t10 CLR pulse width low (1) (2) (3) MIN VDD = 2.7 V to 3.6 V 20 VDD = 3.6 V to 5.5 V 20 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 4 VDD = 3.6 V to 5.5 V 4 VDD = 2.7 V to 3.6 V 5 VDD = 3.6 V to 5.5 V 5 VDD = 2.7 V to 3.6 V 4.5 VDD = 3.6 V to 5.5 V 4.5 VDD = 2.7 V to 3.6 V 0 VDD = 3.6 V to 5.5 V 0 VDD = 2.7 V to 3.6 V 20 VDD = 3.6 V to 5.5 V 20 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 TYP MAX UNITS ns ns ns ns ns ns ns PRODUCT PREVIEW PARAMETER ns ns ns All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Serial Write Operation timing diagram Figure 1. Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. t1 SCLK t8 t2 t3 t4 t7 SYNC t5 SDIN D15 t6 D14 D13 D12 D11 D1 D0 Input Word n SDO D0 t9 D15 Undefined CLR D15 Input Word n+1 D14 D0 Input Word n t10 Figure 1. Serial Write Operation 5 DAC7553 www.ti.com SLAS477 – AUGUST 2005 PIN DESCRIPTION VFBA VREFA CLR SDIN RGT PACKAGE (TOP VIEW) 1 16 15 14 13 12 2 11 3 10 4 9 6 7 8 SCLK SYNC IOVDD SDO DCEN 5 VFBB VREFB PD VOUTA VDD GND VOUTB Terminal Functions PRODUCT PREVIEW TERMINAL NO. 6 DESCRIPTION NAME 1 VOUTA Analog output voltage from DAC A 2 VDD Analog voltage supply input 3 GND Ground 4 VOUTB Analog output voltage from DAC B 5 VFBB DAC B amplifier sense input. 6 VREFB Positive reference voltage input for DAC B 7 PD Power down 8 DCEN Daisy-chain enable 9 SDO Serial data output 10 IOVDD I/O voltage supply input 11 SYNC Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out to the DAC7553 12 SCLK Serial clock input 13 SDIN Serial data input 14 CLR Asynchronous input to clear the DAC registers. When CLR is low, the DAC registers are set to 000H and the output to midscale voltage. 15 VREFA Positive reference voltage input for DAC A 16 VFBA DAC A amplifier sense input. DAC7553 www.ti.com SLAS477 – AUGUST 2005 TYPICAL CHARACTERISTICS LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 Channel A VREF = 4.096 V Linearity Error − LSB VDD = 5 V 0.5 0 −0.5 VREF = 4.096 V 0.25 0 −0.25 −0.5 0 0 −0.5 512 1024 1536 2048 2560 3072 3584 4096 0.5 0.25 0 −0.25 −0.5 0 512 1024 Digital Input Code 2560 3072 3584 Figure 3. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 4096 1 Channel A VREF = 2.5 V VDD = 2.7 V Linearity Error − LSB Linearity Error − LSB 2048 Figure 2. 0.5 0 −0.5 Channel B VREF = 2.5 V VDD = 2.7 V 0.5 0 −0.5 −1 0.5 0.25 0 −0.25 0 512 1024 1536 2048 2560 Digital Input Code Figure 4. 3072 3584 4096 Differential Linearity Error − LSB −1 Differential Linearity Error − LSB 1536 Digital Input Code 1 −0.5 VDD = 5 V −1 0.5 Differential Linearity Error − LSB Differential Linearity Error − LSB −1 Channel B 0.5 PRODUCT PREVIEW Linearity Error − LSB 1 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Input Code Figure 5. 7 DAC7553 www.ti.com SLAS477 – AUGUST 2005 TYPICAL CHARACTERISTICS (continued) ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE 3 3 VDD = 2.7 V, VREF = 2.5 V 2 2 Zero-Scale Error − mV Zero-Scale Error − mV VDD = 5 V, VREF = 4.096 V Channel A 1 Channel B 1 Channel A 0 0 Channel B PRODUCT PREVIEW −1 −40 −10 20 50 −1 −40 80 TA − Free-Air Temperature − °C 50 Figure 6. Figure 7. FULL-SCALE ERROR vs FREE-AIR TEMPERATURE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 80 1 VDD = 2.7 V, VREF = 2.5 V Full-Scale Error − mV VDD = 5 V, VREF = 4.096 V Full-Scale Error − mV 20 TA − Free-Air Temperature − °C 1 0 Channel B −1 Channel A −2 −40 −10 20 50 TA − Free-Air Temperature − °C Figure 8. 8 −10 80 0 Channel B Channel A −1 −2 −40 −10 20 50 TA − Free-Air Temperature − °C Figure 9. 80 DAC7553 www.ti.com SLAS477 – AUGUST 2005 TYPICAL CHARACTERISTICS (continued) SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 0.2 5.50 Typical for All Channels VDD = 2.7 V, VREF = 2.5 V 0.15 VO − Output Voltage − V VO − Output Voltage − V Typical for All Channels 0.1 VDD = 5.5 V, VREF = 4.096 V VDD = VREF = 5.5 V 5.40 5.30 0.05 0 0 5 10 ISINK − Sink Current − mA DAC Loaded with FFFh 5.20 15 0 5 10 ISOURCE − Source Current − mA Figure 10. Figure 11. SOURCE CURRENT AT POSITIVE RAIL SUPPLY CURRENT vs DIGITAL INPUT CODE 2.7 15 PRODUCT PREVIEW DAC Loaded with 000h 400 Typical for All Channels VDD = 5.5 V, VREF = 4.096 V I DD − Supply Current − µ A VO − Output Voltage − V 350 2.6 VDD = VREF = 2.7 V 2.5 300 VDD = 2.7 V, VREF = 2.5 V 250 200 150 100 50 DAC Loaded with FFFh All Channels Powered, No Load 2.4 0 5 10 ISOURCE − Source Current − mA Figure 12. 15 0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Input Code Figure 13. 9 DAC7553 www.ti.com SLAS477 – AUGUST 2005 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 400 400 I DD − Supply Current − µ A I DD − Supply Current − µ A All DACs Powered, No Load, VREF = 2.5 V 350 VDD = 5.5 V, VREF = 4.096 V 300 VDD = 2.7 V, VREF = 2.5 V 250 350 300 250 PRODUCT PREVIEW All Channels Powered, No Load 200 −40 3.1 3.4 3.8 4.1 4.5 4.8 5.2 5.5 VDD − Supply Volatge − V Figure 14. Figure 15. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION - 5.5 V 2000 TA = 25C, SCL Input (All Other Inputs = GND) VDD = 5.5 V, VREF = 4.096 V 1500 1200 VDD = 5.5 V, VREF = 4.096 V 800 400 1000 500 VDD = 2.7 V, VREF = 2.5 V 0 0 0 1 2 3 4 VLOGIC − Logic Input Voltage − V Figure 16. 10 200 2.7 110 f − Frequency − Hz I DD − Supply Current − µ A 1600 −10 20 50 80 TA − Free-Air Temperature − °C 5 253 264 275 286 297 308 319 330 341 IDD − Current Consumption − A Figure 17. DAC7553 www.ti.com SLAS477 – AUGUST 2005 TYPICAL CHARACTERISTICS (continued) HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V TOTAL ERROR - 5 V 4 1500 VDD = 5 V, VREF = 4.096 V, TA = 25C VDD = 2.7 V, VREF = 2.5 V Total Error − mV f − Frequency − Hz 2 1000 Channel A Output 0 Channel B Output 500 −2 −4 0 239 249 259 269 279 289 299 309 319 IDD − Current Consumption − A Figure 18. 512 1024 1536 2048 2560 3072 3584 4095 Digital Input Code PRODUCT PREVIEW 0 Figure 19. TOTAL ERROR - 2.7 V EXITING POWER-DOWN MODE 4 5 VDD = 5 V, VREF = 4.096 V, Power-Up Code 4000 VDD = 2.7 V, VREF = 2.5 V, TA = 25C Total Error − mV Channel A Output 0 Channel B Output −2 VO − Output Voltage − V 4 2 3 2 1 −4 0 0 512 1024 1536 2048 2560 3072 3584 4095 Digital Input Code Figure 20. t − Time − 4 s/div Figure 21. 11 DAC7553 www.ti.com SLAS477 – AUGUST 2005 TYPICAL CHARACTERISTICS (continued) LARGE-SIGNAL SETTLING TIME - 5 V LARGE-SIGNAL SETTLING TIME - 2.7 V 5 3 VDD = 2.7 V, VREF = 2.5 V Output Loaded With 200 pF to GND Code 41 to 4055 VDD = 5 V, VREF = 4.096 V Output Loaded With 200 pF to GND Code 41 to 4055 VO − Output Voltage − V VO − Output Voltage − V 4 3 2 2 1 1 0 0 PRODUCT PREVIEW t − Time − 5 s/div Figure 23. MIDSCALE GLITCH WORST-CASE GLITCH VO - VO - (5 mV/Div) (5 mV/Div) Figure 22. Trigger Pulse Trigger Pulse Time - (400 nS/Div) Figure 24. 12 t − Time − 5 s/div Time - (400 nS/Div) Figure 25. DAC7553 www.ti.com SLAS477 – AUGUST 2005 TYPICAL CHARACTERISTICS (continued) CHANNEL-TO-CHANNEL CROSSTALK FOR A FULL-SCALE SWING VO - VO - (5 mV/Div) (5 mV/Div) DIGITAL FEEDTHROUGH ERROR PRODUCT PREVIEW Trigger Pulse Trigger Pulse Time - (400 nS/Div) Time - (400 nS/Div) Figure 26. Figure 27. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY THD − Total Harmonic Distortion − dB −40 VDD = 5 V, VREF = 4.096 V −1 dB FSR Digital Input, Fs = 1 Msps Measurement Bandwidth = 20 kHz −50 −60 −70 THD −80 2nd Harmonic −90 −100 3rd Harmonic 0 1 2 3 4 5 6 7 8 Output Frequency (Tone) − kHz 9 10 Figure 28. 13 DAC7553 www.ti.com SLAS477 – AUGUST 2005 TYPICAL CHARACTERISTICS (continued) 3-Wire Serial Interface The DAC7553 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface. Table 1. Serial Interface Programming CONTROL DATA BITS DAC(s) FUNCTION PRODUCT PREVIEW DB15 DB14 DB13 DB12 DB11-DB10 0 0 0 0 data A Single Channel Store. The TMP register of channel A is updated. 0 0 1 0 data B Single Channel Store. The TMP register of channel B is updated. 0 1 0 0 data A Single Channel Update. The TMP and DAC registers of channel A are updated. 0 1 1 0 data B Single Channel Update. The TMP and DAC registers of channel A are updated and the DAC register of channel B is updated with input register data. 1 0 0 0 data A Single Channel Update. The TMP and DAC registers of channel B are updated. 1 0 1 0 data B Single Channel Update. The TMP and DAC registers of channel B are updated and the DAC register of channel A is updated with input register data. 1 1 0 0 data A–B All Channel Update. The TMP and DAC registers of channels A and B are updated. 1 1 1 0 data A–B All Channel DAC Update. The DAC register of channels A and B are updated with input register data. POWER-DOWN MODE In power-down mode, the DAC outputs are programmed to one of three output impedances, 1 kΩ, 100 kΩ, or floating. Table 2. Power-Down Mode Control EXTENDED CONTROL 14 DATA BITS FUNCTION DB15 DB14 DB13 DB12 DB11 DB10 DB9-DB0 0 0 X 1 0 0 X PWD Hi-Z (all channels) 0 0 X 1 0 1 X PWD 1 kΩ (all channels) 0 0 X 1 1 0 X PWD 100 kΩ (all channels) 0 0 X 1 1 1 X PWD Hi-Z (all channels) 0 1 X 1 0 0 X PWD Hi-Z (selected channel = A) 0 1 X 1 0 1 X PWD 1 kΩ (selected channel = A) 0 1 X 1 1 0 X PWD 100 kΩ (selected channel = A) 0 1 X 1 1 1 X PWD Hi-Z (selected channel = A) 1 0 X 1 0 0 X PWD Hi-Z (selected channel = B) 1 0 X 1 0 1 X PWD 1 kΩ (selected channel = B) 1 0 X 1 1 0 X PWD 100 kΩ (selected channel = B) 1 0 X 1 1 1 X PWD Hi-Z (selected channel = B) 1 1 X 1 0 0 X PWD Hi-Z (all channels) 1 1 X 1 0 1 X PWD 1 kΩ (all channels) 1 1 X 1 1 0 X PWD 100 kΩ (all channels) 1 1 X 1 1 1 X PWD Hi-Z (all channels) DAC7553 www.ti.com SLAS477 – AUGUST 2005 THEORY OF OPERATION D/A SECTION OUTPUT BUFFER AMPLIFIERS The architecture of the DAC7553 consists of a string DAC followed by an output buffer amplifier. Figure 29 shows a generalized block diagram of the DAC architecture. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with up to 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1.8 V/µs with a typical settling time of 3 µs with the output unloaded. VREF 100 k 100 k VFB 50 k _ DAC Register VOUT + GND Figure 29. Typical DAC Architecture DAC External Reference Input Two separate reference pins are provided for two DACs, providing maximum flexibility. VREFA serves DAC A and VREFB serves DAC B. VREFA and VREFB can be externally shorted together for simplicity. The 2s-complement input coding to the DAC7553 gives the ideal output voltage as: VOUT = VREF × D/4096 It is recommended to use a buffered reference in the external circuit (e.g., REF3140). The input impedance is typically 100 kΩ for each reference input pin.. Where D = decimal equivalent of the 2s-complement input that is loaded to the DAC register, which can range from 0 to 4095. Amplifier Sense Input To Output Amplifier VREF R R R R GND Figure 30. Typical Resistor String RESISTOR STRING The resistor string section is shown in Figure 30. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is specified monotonic. The DAC7553 architecture uses four separate resistor strings to minimize channel-to-channel crosstalk. The DAC7553 contains two amplifier feedback input pins, VFBA and VFBB. For voltage output operation, VFBA and VFBB must externally connect to VOUTA and VOUTB, respectively. For better DC accuracy, these connections should be made at load points. The VFBA and VFBB pins are also useful for a variety of applications, including digitally controlled current sources. Each feedback input pin is internally connected to the DAC amplifier's negative input terminal through a 100-kΩ resistor; and, the amplifier's negative input terminal internally connects to ground through another 100-kΩ resistor (See Figure 29). This forms a gain-of-two, noninverting amplifier configuration. Overall gain remains one because the resistor string has a divide-by-two configuration. The resistance seen at each VFBx pin is approximately 200 kΩ to ground. Power-On Reset On power up, all internal registers are cleared and all channels are updated with midscale voltages. Until valid data is written, all DAC outputs remain in this state. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. In order not to turn on ESD protection devices, VDD should be applied before any other pin is brought high. 15 PRODUCT PREVIEW Ref + Resistor String Ref − DAC7553 www.ti.com SLAS477 – AUGUST 2005 Power Down The DAC7553 has a flexible power-down capability as described in Table 2. Individual channels could be powered down separately or all channels could be powered down simultaneously. During a power-down condition, the user has flexibility to select the output impedance of each channel. During power-down operation, each channel can have either 1-kΩ, 100-kΩ, or Hi-Z output impedance to ground. Asynchronous Clear The DAC7553 output is asynchronously set to midscale voltage immediately after the CLR pin is brought low. The CLR signal resets all internal registers and therefore behaves like the Power-On Reset. The DAC7553 updates at the first rising edge of the SYNC signal that occurs after the CLR pin is brought back to high. IOVDD and Level Shifters PRODUCT PREVIEW The DAC7553 can be used with different logic families that require a wide range of supply voltages (from 1.8 V to 5.5 V). To enable this useful feature, the IOVDD pin must be connected to the logic supply voltage of the system. All DAC7553 digital input and output pins are equipped with level-shifter circuits. Level shifters at the input pins ensure that external logic high voltages are translated to the internal logic high voltage, with no additional power dissipation. Similarly, the level shifter for the SDO pin translates the internal logic high voltage (VDD) to the external logic high level (IOVDD). For single-supply operation, the IOVDD pin can be tied to the VDD pin. SERIAL INTERFACE The DAC7553 is controlled over a versatile 3-wire serial interface, which operates at clock rates up to 50 MHz and is compatible with SPI, QSPI, Microwire, and DSP interface standards. In daisy-chain mode (DCEN = 1) the DAC7553 requires a falling SCLK edge after the rising SYNC, in order to initialize the serial interface for the next update. 16-Bit Word and Input Shift Register The input shift register is 16 bits wide. DAC data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK, as shown in the Figure 1 timing diagram. The 16-bit word, illustrated in Table 1, consists of four control bits followed by 12 bits of DAC data. The 12-bit data is in 2s-complement format, with 800H corresponding to 0-V output and 7FFH corresponding to full-scale output (VREF – 1 LSB). Data is loaded MSB first (Bit 15) where the first two bits (DB15 and DB14) determine if the input register, DAC register, or both are updated with shift 16 register input data. Bit 13 (DB13) determines whether the data is for DAC A, DAC B, or both DACs. Bit 12 (DB12) determines either normal mode or power-down mode (see Table 2). All channels are updated when bits 15 and 14 (DB15 and DB14) are high. The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data is shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses. When DCEN is low, the SDO pin is brought to a Hi-Z state. The first 16 data bits that follow the falling edge of SYNC are stored in the shift register. The rising edge of SYNC that follows the 16th data bit updates the DAC(s). If SYNC is brought high before the 16th data bit, no action occurs. When DCEN is high, data can continuously be shifted into the shift register, enabling the daisy-chain operation. The SDO pin becomes active and outputs SDIN data with 16 clock cycle delay. A rising edge of SYNC loads the shift register data into the DAC(s). The loaded data consists of the last 16 data bits received into the shift register before the rising edge of SYNC. If daisy-chain operation is not needed, DCEN should permanently be tied to a logic low voltage. Daisy-Chain Operation When DCEN pin is brought high, daisy chaining is enabled. The Serial Data Output (SDO) pin is provided to daisy-chain multiple DAC7553 devices in a system. As long as SYNC is high or DCEN is low, the SDO pin is in a high-impedance state. When SYNC is brought low, the output of the internal shift register is tied to the SDO pin. As long as SYNC is low and DCEN is high, SDO duplicates the SDIN signal with a 16-cycle delay. To support multiple devices in a daisy chain, SCLK and SYNC signals are shared across all devices, and SDO of one DAC7553 should be tied to the SDIN of the next DAC7553. For n devices in such a daisy chain, 16n SCLK cycles are required to shift the entire input data stream. After 16n SCLK falling edges are received, following a falling SYNC, the data stream becomes complete and SYNC can be brought high to update n devices simultaneously. SDO operation is specified at a maximum SCLK speed of 10 MHz. DAC7553 www.ti.com SLAS477 – AUGUST 2005 The DAC7553 uses precision thin-film resistors providing exceptional linearity and monotonicity. Integral linearity error is typically within (+/-) 0.35 LSBs, and differential linearity error is typically within (+/-) 0.08 LSBs. GLITCH ENERGY The DAC7553 uses a proprietary architecture that minimizes glitch energy. The code-to-code glitches are so low, they are usually buried within the wide-band noise and cannot be easily detected. The DAC7553 glitch is typically well under 0.1 nV-s. Such low glitch energy provides more than 10X improvement over industry alternatives. change the loop can generate. A DNL error less than –1 LSB (non-monotonicity) can create loop instability. A DNL error greater than +1 LSB implies unnecessarily large voltage steps and missed voltage targets. With high DNL errors, the loop loses its stability, resolution, and accuracy. Offering 12-bit ensured monotonicity and ± 0.08 LSB typical DNL error, 755X DACs are great choices for precision control loops. Loop Speed: The DAC7553 architecture is designed to minimize channel-to-channel crosstalk. The voltage change in one channel does not affect the voltage output in another channel. The DC crosstalk is in the order of a few microvolts. AC crosstalk is also less than –100 dBs. This provides orders of magnitude improvement over certain competing architectures. Many factors determine control loop speed. Typically, the conversion time of the ADC and the computation time of the MCU are the two major factors that dominate the time constant of the loop. DAC settling time is rarely a dominant factor because ADC conversion times usually exceed DAC conversion times. DAC offset, gain, and linearity errors can slow the loop down only during the start-up. Once the loop reaches its steady-state operation, these errors do not affect loop speed any further. Depending on the ringing characteristics of the loop's transfer function, DAC glitches can also slow the loop down. With its 1 MSPS (small-signal) maximum data update rate, DAC7553 can support high-speed control loops. Ultralow glitch energy of the DAC7553 significantly improves loop stability and loop settling time. APPLICATION INFORMATION Generating Industrial Voltage Ranges: CHANNEL-TO-CHANNEL CROSSTALK Waveform Generation Due to its exceptional linearity, low glitch, and low crosstalk, the DAC7553 is well suited for waveform generation (from DC to 10 kHz). The DAC7553 large-signal settling time is 5 µs, supporting an update rate of 200 KSPS. However, the update rates can exceed 1 MSPS if the waveform to be generated consists of small voltage steps between consecutive DAC updates. To obtain a high dynamic range, REF3140 (4.096 V) or REF02 (5 V) are recommended for reference voltage generation. Generating ±5-V, ±10-V, and ± 12-V Outputs For Precision Industrial Control Industrial control applications can require multiple feedback loops consisting of sensors, ADCs, MCUs, DACs, and actuators. Loop accuracy and loop speed are the two important parameters of such control loops. For control loop applications, DAC gain and offset errors are not important parameters. This could be exploited to lower trim and calibration costs in a high-voltage control circuit design. Using an operational amplifier (OPA130), and a voltage reference (REF3140), the DAC7553 can generate the wide voltage swings required by the control loop. Vtail DAC7553 R1 REF3140 R2 VREF VREFH DAC7553 _ Vdac + VOUT OPA130 Figure 31. Low-cost, Wide-swing Voltage Generator for Control Loop Applications Loop Accuracy: The output voltage of the configuration is given by: In a control loop, the ADC has to be accurate. Offset, gain, and the integral linearity errors of the DAC are not factors in determining the accuracy of the loop. As long as a voltage exists in the transfer curve of a monotonic DAC, the loop can find it and settle to it. On the other hand, DAC resolution and differential linearity do determine the loop accuracy, because each DAC step determines the minimum incremental V out V REF R2 1 Din V tail R2 4096 R1 R1 (1) Fixed R1 and R2 resistors can be used to coarsely set the gain required in the first term of the equation. Once R2 and R1 set the gain to include some minimal over-range, a DAC7553 channel could be used to set the required offset voltage. Residual 17 PRODUCT PREVIEW INTEGRAL AND DIFFERENTIAL LINEARITY DAC7553 www.ti.com SLAS477 – AUGUST 2005 errors are not an issue for loop accuracy because offset and gain errors could be tolerated. One DAC7553 channel can provide the Vtail voltage, while the other DAC7553 channel can provide Vdac voltage to help generate the high-voltage outputs. For ±5-V operation: R1=10 kΩ, R2 = 15 kΩ, Vtail = 3.33 V, VREF= 4.096 V PRODUCT PREVIEW 18 For ±10-V operation: R1=10 kΩ, R2 = 39 kΩ, Vtail = 2.56 V, VREF = 4.096 V For ±12-V operation: R1=10 kΩ, R2 = 49 kΩ, Vtail = 2.45 V, VREF = 4.096 V IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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