EDI88128CS HI-RELIABILITY PRODUCT 128Kx8 Monolithic SRAM, SMD 5962-89598 FEATURES ■ Access Times of 15*, 17, 20, 25, 35, 45, 55ns The EDI88128CS is a high speed, high performance, 128Kx8 megabit density Monolithic CMOS Static RAM. ■ CS and OE Functions for Bus Control The device has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. ■ 2V Data Retention (EDI88128LPS) ■ TTL Compatible Inputs and Outputs ■ Fully Static, No Clocks ■ Organized as 128Kx8 A Low Power version with 2V Data Retention (EDI88128LPS) is also available for battery back-up opperation. Military product is available compliant to MIL-PRF-38535. ■ Commercial, Industrial and Military Temperature Ranges ■ Thru-hole and Surface Mount Packages JEDEC Pinout • 32 pin Ceramic DIP, 400 mil (Package 102) • 32 pin Ceramic DIP, 600 mil (Package 9) • 32 lead Ceramic ZIP (Package 100) • 32 lead Ceramic SOJ (Package 140) • 32 pad Ceramic LCC (Package 141) • 32 lead Ceramic Flatpack (Package 142) * 15ns access time is advanced information, contact factory for availability. ■ Single +5V (±10%) Supply Operation FIG. 1 PIN CONFIGURATION 32 32 32 32 PIN DESCRIPTION DIP SOJ LCC FLATPACK 32 ZIP TOP VIEW NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TOP VIEW 32 VCC 31 A15 30 NC 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 VCC 4 A15 6 NC 8 WE 10 A13 12 A8 14 A9 16 A11 18 OE 20 A10 22 CS 24 I/O7 26 I/O6 28 I/O5 30 I/O4 32 I/O3 I/O0-7 Data Inputs/Outputs A0-16 Address Inputs WE Write Enable CS Chip Select OE Output Enable VCC Power (+5V ±10%) VSS Ground NC Not Connected BLOCK DIAGRAM Memory Array AØ-16 Address Buffer Address Decoder I/O Circuits I/OØ-7 WE CS OE February 2000 Rev. 10 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88128CS TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Unit OE CS WE Mode Output Power V X H L X H L L L X H H L Standby Output Deselect Read Write High Z High Z Data Out Data In Icc 2 , Icc3 Icc 1 Icc 1 Icc 1 -0.5 to 7.0 Operating Temperature TA (Ambient) 0 to +70 °C -40 to +85 °C Military -55 to +125 °C Storage Temperature, Plastic -65 to +150 °C Power Dissipation 1.5 W Output Current 20 mA Junction Temperature, TJ 175 °C Commercial Industrial RECOMMENDED OPERATING CONDITIONS Parameter NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Min Typ Max Supply Voltage VCC 4.5 5.0 5.5 Unit V Supply Voltage VSS 0 0 0 V Input High Voltage VIH 2.2 — Vcc +0.5 V Input Low Voltage VIL -0.3 — +0.8 V CAPACITANCE (TA = +25°C) Max Parameter Symbol Condition Unit CSOJ, LCC ZIP, DIP, Flatpack Address Lines CI VIN = Vcc or Vss, f = 1.0MHz 6 12 pF Data Lines CO VOUT = Vcc or Vss, f = 1.0MHz 8 14 pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS (VCC = 5V, TA = -55°C to +125°C) Parameter Symbol Conditions Units Min Typ Max Input Leakage Current ILI VIN = 0V to VCC — — ±5 Output Leakage Current ILO VI/O = 0V to VCC — — ±10 µA Operating Power Supply Current I CC1 WE, CS = VIL, II/O = 0mA, Min Cycle µA (15-17ns) — 300 mA mA (20ns) — 225 (25-55ns) — 200 mA — 25 mA 60 mA I CC2 CS ≥ VIH, VIN ≤ VIL, VIN ≥ VIH (17-55ns) (15ns) — CS (17-55ns) — 3 10 mA Full Standby Power Supply Current I CC3 CS ≥ VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V CS (15ns) — — 15 mA LPS — — 5 mA Output Low Voltage VOL IOL = 8.0mA — — 0.4 V Output High Voltage VOH IOH = -4.0mA 2.4 — — V Standby (TTL) Power Supply Current NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V White Electronic Designs Corporation • (602) 437-1520 • ww.whiteedc.com 2 EDI88128CS AC CHARACTERISTICS – READ CYCLE (15 to 20ns) (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol JEDEC Alt. Min Read Cycle Time tAVAV tRC 15 Address Access Time tAVQV tAA 15 17 20 Chip Enable Access Time tELQV tACS 15 17 20 Chip Enable to Output in Low Z (1) tELQX tCLZ Chip Disable to Output in High Z (1) tEHQZ tCHZ Output Hold from Address Change tAVQX tOH Output Enable to Output Valid tGLQV tOE Output Enable to Output in Low Z (1) tGLQX tOLZ Output Disable to Output in High Z(1) tGHQZ tOHZ Chip Enable to Power Up (1) tELICCH tPU Chip Enable to Power Down (1) tEHICCL tPD 15ns* 17ns Max Min 20ns Max Min 17 3 Max 3 ns 10 ns 0 6 ns 6 8 0 ns 0 6 ns 6 0 ns ns 8 0 0 ns 3 8 0 Units 20 8 0 ns 0 15 ns 17 20 ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – READ CYCLE (25 to 55ns) (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol JEDEC Alt. Min Read Cycle Time tAVAV tRC 25 Address Access Time tAVQV tAA 25 35 45 55 ns Chip Enable Access Time tELQV tACS 25 35 45 55 ns Chip Enable to Output in Low Z (1) tELQX tCLZ Chip Disable to Output in High Z (1) tEHQZ tCHZ 20 ns Output Hold from Address Change tAVQX tOH Output Enable to Output Valid tGLQV tOE 25 ns 20 ns 55 ns Output Enable to Output in Low Z (1) tGLQX tOLZ Output Disable to Output in High Z(1) tGHQZ tOHZ Chip Enable to Power Up (1) tELICCH tPU Chip Enable to Power Down (1) tEHICCL tPD 25ns 35ns Max Min 45ns Max 35 3 0 0 0 0 ns 0 ns 20 0 35 ns 0 0 0 25 ns 20 15 Units 3 0 0 Max 20 15 10 Min 55 3 20 10 55ns Max 45 3 12 Min 0 ns 45 1. This parameter is guaranteed by design but not tested. AC TEST CONDITIONS Figure 1 Figure 2 Vcc 480Ω Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Vcc 480Ω VSS to 3.0V 5ns 1.5V Figure 1 NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2) Q Q 255Ω 30pF 255Ω 5pF 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88128CS AC CHARACTERISTICS – WRITE CYCLE (12 to 20ns) (VCC = 5.0V, VSS = 0V, T A = -55°C to +125°C) Parameter Symbol JEDEC Alt. Min 15ns* 17ns Write Cycle Time tAVAV tWC 15 17 20 ns Chip Enable to End of Write tELWH tELEH tCW tCW 12 12 13 13 15 15 ns ns Address Setup Time tAVWL tAVEL tAS tAS 0 0 0 0 0 0 ns ns Address Valid to End of Write tAVWH tAVEH tAW tAW 12 12 13 13 15 15 ns ns Write Pulse Width tWLWH tWLEH tWP tWP 12 12 13 13 15 15 ns ns Write Recovery Time tWHAX tEHAX tWR tWR 0 0 0 0 0 0 ns ns Data Hold Time tWHDX tEHDX tDH tDH 0 0 0 0 0 0 ns ns Max Min 8 20ns Max 0 Min 8 Max 0 Units Write to Output in High Z (1) tWLQZ tWHZ 0 Data to Write Time tDVWH tDVEH tDW tDW 7 7 7 7 10 10 10 ns ns ns Output Active from End of Write (1) tWHQX tWLZ 3 3 3 ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – WRITE CYCLE (25 to 55ns) (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol JEDEC Alt. Min 25ns 35ns Write Cycle Time tAVAV tWC 25 35 45 55 ns Chip Enable to End of Write tELWH tELEH tCW tCW 20 20 25 25 35 35 45 45 ns ns Address Setup Time tAVWL tAVEL tAS tAS 0 0 0 0 0 0 0 0 ns ns Address Valid to End of Write tAVWH tAVEH tAW tAW 20 20 25 25 35 35 45 45 ns ns Write Pulse Width tWLWH tWLEH tWP tWP 20 20 30 30 30 30 35 35 ns ns Write Recovery Time tWHAX tEHAX tWR tWR 0 0 0 0 5 5 5 5 ns ns Data Hold Time tWHDX tEHDX tDH tDH 0 0 0 0 0 0 0 0 ns ns Max 10 Min 15 Min 0 Max 20 Units tWLQZ tWHZ 0 tDVWH tDVEH tDW tDW 15 15 20 20 20 20 25 25 ns ns Output Active from End of Write (1) tWHQX tWLZ 3 3 3 3 ns 4 0 55ns Max Write to Output in High Z (1) White Electronic Designs Corporation • (602) 437-1520 • ww.whiteedc.com 13 Min Data to Write Time 1. This parameter is guaranteed by design but not tested. 0 45ns Max ns EDI88128CS FIG. 2 tAVAV ADDRESS TIMING WAVEFORM - READ CYCLE tAVQV CS tELQV tELQX tELICCH tAVAV ADDRESS DATA I/O ADDRESS 1 ADDRESS 2 Icc tAVQV tAVQX OE DATA 1 tGLQV tGLQX DATA 2 tEHQZ tEHICCL tGHQZ DATA I/O READ CYCLE 1 (WE HIGH; OE, CS LOW) READ CYCLE 2 (WE HIGH) FIG. 3 WRITE CYCLE - WE CONTROLLED tAVAV ADDRESS tAVWH tELWH tWHAX CS tAVWL tWLWH WE tDVWH DATA IN tWHDX DATA VALID tWLQZ tWHQX HIGH Z DATA OUT WRITE CYCLE 1, WE CONTROLLED FIG. 4 WRITE CYCLE - CS CONTROLLED tAVAV WS32K32-XHX ADDRESS tAVEH tELEH tEHAX CS tAVEL tWLEH WE tDVEH DATA IN tEHDX DATA VALID HIGH Z DATA OUT WRITE CYCLE 2, CS CONTROLLED 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88128CS DATA RETENTION CHARACTERISTICS (EDI88128LPA ONLY) (TA = -55°C to +125°C) Characteristic Low Power Version only Data Retention Voltage Sym VDD VDD = 2.0V 2 – – V Data Retention Quiescent Current ICCDR CS ≥ VDD -0.2V – 0.5 2 mA Chip Disable to Data Retention Time (1) TCDR VIN ≥ VDD -0.2V Operation Recovery Time (1) TR Conditions Min or VIN ≤ 0.2V Typ 0 – – ns – – ns * Read Cycle Time FIG. 5 DATA RETENTION - CS CONTROLLED Data Retention Mode 4.5V WS32K32-XHX VDD 4.5V tCDR CS tR CS = VDD -0.2V DATA RETENTION, CS CONTROLLED White Electronic Designs Corporation • (602) 437-1520 • ww.whiteedc.com 6 Units TAVAV* NOTE: 1. Parameter guaranteed by design, but not tested. Vcc Max EDI88128CS PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600mils wide) 1.616 1.584 0.620 0.600 0.060 0.040 Pin 1 Indicator 0.175 0.125 0.061 0.017 0.155 0.115 0.100 TYP 0.020 0.016 0.600 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES PACKAGE 100: 32 LEAD CERAMIC ZIP 1.65 MAX 0.125 MAX 0.500 MAX 0.040 0.020 0.155 0.125 0.100 NOM 0.040 MIN 0.050 31 x 0.050 = 1.550 ALL DIMENSIONS ARE IN INCHES PACKAGE 102: 32 PIN SIDEBRAZED CERAMIC DIP (400mils wide) 1.616 1.584 0.420 0.400 0.060 0.040 Pin 1 Indicator 0.175 0.125 0.061 0.017 0.100 TYP 0.020 0.016 0.155 0.115 0.400 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com EDI88128CS PACKAGE 140: 32 LEAD CERAMIC SOJ 0.108 0.088 0.840 0.820 0.040 0.030 0.440 0.430 0.379 REF 0.155 0.120 0.050 TYP ALL DIMENSIONS ARE IN INCHES PACKAGE 141: 32 PAD CERAMIC LCC 0.096 0.080 0.028 0.022 0.840 0.820 0.050 TYP 0.405 0.395 ALL DIMENSIONS ARE IN INCHES PACKAGE 142: 32 PIN CERAMIC FLATPACK 0.830 0.810 0.007 0.003 0.420 0.400 1.00 RE 0.290 0.270 0.040 0.030 Pin 1 0.045 0.020 0.370 0.250 0.019 0.015 0.050 TYP ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corporation • (602) 437-1520 • ww.whiteedc.com 8 0.116 0.100 EDI88128CS ORDERING INFORMATION EDI 8 8 128 CS X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 128Kx8 TECHNOLOGY: CS = CMOS Standard Power LPS = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) F = 32 lead Ceramic Flatpack (Package 142) L = 32 pad Ceramic LCC (Package 141) N = 32 lead Ceramic SOJ (Package 140) T = 32 lead Sidebrazed DIP, 400 mil (Package 102) Z = 32 lead Ceramic ZIP (Package 100) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com