STMICROELECTRONICS EMIF09

EMIF09-02726Sx

Application Specific Discretes
A.S.D.TM
EMI FILTER
INCLUDING ESD PROTECTION
MAIN APPLICATIONS
Where EMI filtering in ESD sensitive equipment is
required :
Computers and printers
Communication systems
Mobile phones
MCU Boards
SO-20
DESCRIPTION
The EMIF09-02726sx is a highly integrated array
designed to suppress EMI / RFI noise in all
systems
subjected
to
electromagnetic
interferences.
Additionally, this filter includes an ESD protection
circuitry which prevents the protected device from
destruction when subjected to ESD surges up to
15 kV.
SSOP20
PIN-OUT CONFIGURATION
BENEFITS
I1
O1
I2
O2
I3
Cost-effectiveness compared to discrete
solution
EMI bi-directional low-pass filter
High efficiency in ESD suppression.
High reliability offered by monolithic integration
O3
9
I4
I5
O4
O5
C
E
L
L
S
GND
I6
I7
GND
O6
O7
I8
O8
I9
O9
COMPLIESWITH THE FOLLOWING STANDARD:
I
IEC 1000-4-2
15kV
8 kV
(air discharge)
(contact discharge)
O
D
D
RI/O = 27 Ω, tolerance +/-20%
EMIF09-02726Sxfiltering response curves
CIN = 130pF
Typical response to IEC1000-4-2
(16 kV air discharge)
ASD is a trademark of STMicroelectronics
August 1999 - Ed: 2
1/12
EMIF09-02726Sx
ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C)
Symbol
Value
Unit
Maximum electrostatic discharge in following
measurement conditions:
MIL STD 883C - METHOD 3015-6
IEC1000-4-2 - air discharge
IEC1000-4-2 - contact discharge
25
16
9
kV
PPP
Peak pulse power (8/20µs)
200
W
Tstg
Tj
Storage temperature range
Junction temperature
- 55 to + 150
150
°C
°C
TOP
Operating temperature range
- 40 to + 85
°C
VPP
Symbol
Parameter
IF
VRM
Stand-offvoltage
VBR
Breakdown voltage
VCL
Clamping voltage
VF
Forward voltage drop
CIN
Input capacitance per line
Rd
Dynamic impedance
IRM
Leakage current
IPP
Peak pulse current
Symbol
I
Parameter
VBR
VF
VCL
V
IRM
Slope = 1 / Rd
IPP
Test conditions
Min.
Typ.
Max.
Unit
20
µA
7.2
V
1.25
V
IRM
VRM = 5.25 V, between any I/O pin and GND
VBR
IR = 1 mA, between any I/O pin and GND
VF
IF = 200 mA, between any I/O pin and GND
Rd
IPP = 15 A, t p = 2.5µs (note 2)
0.3
Ω
C
0V bias VRMS = 30mV
130
pF
F = 1MHz (note 3)
Note 1: VCL corresponds to the voltage level seen at the output pin
Note 2: Rd is given per diode
Note 3: C is given per diode
2/12
VRM
6.1
EMIF09-02726Sx
Fig. 1: Peak power dissipation versus initial junction temperature.
Fig. 2: Peak pulse power versus exponentialpulse
duration (Tj initial=25°C).
Ppp[Tj initial]/Ppp[Tj initial=25°C]
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Ppp(W)
2000
1000
100
tp(µs)
Tj initial(°C)
10
0
25
50
75
100
125
150
Fig. 3: Clamping voltage versus peak pulse current (Tj initial=25°C).
Rectangular waveform: tp = 2.5µs
10
100
Fig. 4: Input capacitance versus reverse applied
voltage (typical values).
Ipp(A)
30.0
1
C(pF)
tp=2.5µs
220
Output Vcl
F=1MHz
Vosc=30mV
Input Vcl
10.0
200
180
160
1.0
140
120
Vcl(V)
0.1
5
6
7
8
9
10
11
100
12
13
14
15
Fig. 5: Relative variation of leakagecurrent versus
junction temperature (typical values).
VR(V)
1
5
10
Fig. 6: Peak forward voltage drop versus peak forward current (typical values).
Rectangular waveform: tp = 2.5µs
IR[Tj] / IR[Tj=25°C]
5.00
3.0
2
IFM(A)
2.5
1.00
2.0
1.5
0.10
1.0
0.5
0.0
25
Tj(°C)
50
75
100
VFM(V)
125
150
0.01
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
3/12
EMIF09-02726Sx
ESD protection by the EMIF09-02726Sx
Electrostatic discharge (ESD) is a major cause of failure in electronic systems.
Transient Voltage Suppressors are an ideal choice for ESD protection. They are capable of clamping the
incoming transient to a low enough level such that damage to the protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line to ground. As the transient
rises above the operatingvoltage of the device, the TVS array becomes a low impedancepath diverting the
transient current to ground.
Fig. 7: Example of connectionfor one cell of the EMIF09-02726Sx
I1
O1
I2
O2
I3
O3
I4
O4
I5
O5
GND
GND
I6
O6
I7
Logic
Transceiver
I8
I9
O7
EMIF09-02726Sx
1284-A
Connector
O8
O9
The EMIF09-02726Sx array is the ideal board level protection of ESD sensitive semiconductor
components. It provides best efficiency when using separated inputs and outputs, in the so called 4-points
structure.
Circuit Board Layout
Circuit board layout is a critical design step in the suppression of ESD induced transients. The following
guidelines are recommended :
The EMIF09-02726Sx should be placed as near as possible to the input terminals or connectors.
The path length between the ESD suppressor and the protectedline should be minimized.
All conductive loops, including power and ground loops should be minimized.
The ESD transient return path to ground should be kept as short as possible.
Ground planes should be used whenever possible.
Fig. 8: Recommended PCB layout to benefit from 4-point structure
NOT TO DO
TO DO
I1
O 1
I2
O 2
I3
O 3
I4
O 4
I5
Logic
Transceiver,
ASIC,...
O1
I2
O2
I3
O3
I4
O4
I5
O5
GND
GND
I6
O6
I7
O7
I8
O8
I9
O9
O 5
GND
GND
I6
O 6
I7
O 7
I8
O 8
I9
O 9
EMIF09-02726Sx
footprint
4/12
I1
Logic
Transceiver,
ASIC,...
EMIF09-02726Sx
footprint
EMIF09-02726Sx
TECHNICAL INFORMATION
ESD PROTECTION
The EMIF09-02726Sx is particularly optimized to perform high level ESD protection. The clamping voltage
is given by the formula:
VCL = Vbr + Rd.IPP
The protection function is splitted in 2 stages. As shown in figure A1, the ESD strike is clamped by the first
stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a
configuration makes the output voltage very low at the Vout level.
Fig. A1: ESD clamping behavior
Rg
ESD
Surge
R
Rd
Rd
Vg
Vout
Vin
Rload
Vbr
Vbr
S1
S2
EMIF09-02726Sx
Device to be protected
To determine the remaining voltages at both Vin and Vout stages, we give the typical dynamic resistance
value Rd. Considering that : R>>Rd, Rg>>Rd and Rload>>Rd, the voltages are given by the following
formulas:
Rg.Vbr + Rd.Vg
Vin =
Rg
Vout =
R.Vbr + Rd.Vin
R
The result of the calculation made for VG= 8kV, Rg= 330 Ω (IEC1000-4-2 standard), Vbr=6.6V, Rd=0.3 Ω
and R=27 Ω is:
Vin = 13.87V
Vout = 6.75 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be few
tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side because the
current involved after the resistance R is low.
5/12
EMIF09-02726Sx
LATCH-UP PHENOMENA
The early aging and destruction of IC’s is often
due to latch-up phenome na which is principally
induced by dV/dt. Thanks to its RC structure, the
EMIF09-02726Sx provides a high immunity to
latch-up by integration of fast edges. (See the
response of EMIF09-02726Sx to a 1ns edge on
Fig. A3)
The measurements performed as described below
show very clearly the high efficiency of the ESD
protection:
- no influence of the parasitic inductances on Vout
stage
- Vout clamping voltage very close to Vbr
Fig. A2: Measurement conditions
EMIF09-02726Sx
ESD
SURGE
R
Vin
Vout
GND
GND
Fig. A3: Remaining voltage at both stages S1 (Vin) and S2 (Vout) during ESD surge
a) Positive surge
b) Negative surge
It should be noted that the EMIF09-02726Sxis not only active for positive ESD surges but also for negative
ones. For this kind of disturbance,it clamps close to ground voltage as shown in Fig. A3b.
NOTE: DYNAMIC RESISTANCE MEASUREMENT
Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the
dynamic resistance in addition to the classical parameters. Figure A4 illustrates the current waveform used
to measure the Rd.
Fig. A4: Rd measurement current wave
As the value of the dynamic resistance remains
I
stable for a surge duration lower than 20µs, the
2.5µs rectangular surge is well adapted. In
additionboth rise and fall times are optimized to
I
avoid any parasitic phenomenon during the
measurement of Rd.
PP
t
2 µs
2.5 µs
2.5µs durationmeasurement wave
6/12
EMIF09-02726Sx
FREQUENCY BEHAVIOR
In addition to the ESD protection, the EMIF09-02726Sx offers an EMI / RFI filtering function thanks to its
Pi-filter structure. This low-pass filter is characterized by the following parameters:
- Cut-off frequency
- Insertion loss
- High frequency rejection
20MHz
-3dBm
>-18dBm
Fig. A5: EMIF09-02726Sxfiltering response curves
Figure A5 gives these parameters, in particular the signal rejection at the 900MHz GSM frequency is
measured at about -21dBm (SO-20) and -26dBm (SSOP20), while the attenuation for FM broadcastrange
(around 100MHz) is better than -17dBm for both SO-20 and SSOP20.
Fig. A6: Measurement conditions
TRACKING
GENERATOR
TG OUTPUT
SPECTRUM
ANALYSER
50Ω
RF INPUT
EMIF09
-02726Sx
Vg
50Ω
Vin
Vout
TEST BOARD
1
20
EMIF0902726Sx
7/12
EMIF09-02726Sx
CROSSTALK BEHAVIOR
1- Crosstalk phenomena
Fig. A7: Crosstalk phenomena
RG1
line 1
VG1
RL1
RG2
α 1 VG1 + β12 VG2
line 2
VG2
α 2VG2 + β21 VG1
RL2
DRIVERS
RECEIVERS
The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor ( β12 or β21 )
increases when the gap across lines decreases, particularly in silicon dice. In the example above the
expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1.
This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2.
This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency
analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage
signal or high load impedance (few kΩ). The following chapters give the value of both digital and analog
crosstalk.
2- Digital Crosstalk
Fig. A8: Digital crosstalk measurements
+5V
EMIF09-02726Sx
+5V
74HC04
74HC04
Line 1
Square
Pulse
Generator
5KHz
+5V
VG1
Line 2
β 21 VG1
Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital
application.
Figure A9 shows that in the case of a signal from 0 to 5V with a rise time of a few tenths of ns, the impact
on the disturbed line is less than 100mV peak to peak. No data disturbance is noted on the concerned line.
The same results are obtained with falling edges.
Note: The measurements have been performed in the worst case i.e. on two adjacent cells (1/20 & 2/19).
8/12
EMIF09-02726Sx
Fig. A9: Digital crosstalk results
3- Analog Crosstalk
Fig. A10: Analog crosstalk measurements
TG OUTPUT
Fig. A11: Typical analog crosstalk results
RF INPUT
TEST BOARD
1
19
EMIF0902726Sx
Figure A10 gives the measurement circuit for the analog application. In figure A11, the curves show the
effect of cell 1/20 on cell 2/19,no differenceis found with other couples of adjacentcells. In usual frequency
range of analog signals (up to 100MHz) the effect on disturbedline is less than -32 dBm for SO-20 package
and -37dBm for SSOP20package.
9/12
EMIF09-02726Sx
4- PSpice model
Fig. A12: PSpicemodelof oneEMIF09-02726Sxcell
27Ω
5nH
5nH
IN
OUT
Dz
Df
Dr
Dz
Df
Dr
Lg
GND
Figure A12 shows the PSpice model of one cell of the EMIF09-02726Sx. In this model, the diodes are
defined by the following PSpice parameters :
Dz
5.6
130p
1m
1000
10E-21
1p
1
0.3333
0.3
0.6
1u
BV
Cjo
IBV
IKF
IS
ISR
N
M
RS
VJ
TT
Df
1000
130p
100u
0
2.0861E-21
1n
1
0.3333
0.3
0.6
1u
Dr
1000
1p
100u
1000
10E-15
100p
0.6
0.3333
1m
0.6
1n
Note: This simulation model is given for an ambient temperature of 27°C.
The value of Lg is depending on the package:
SSOP20
-->
Lg=0.7nH
SO-20
-->
Lg=1.4nH
The comparison between the PSpice simulation and the measured frequency response is given in fig A13a
& A13b. This shows that the PSpice model is very close to the product behavior.
Fig. A13: Comparison between PSpice simulation and measured frequency response
b) SO-20 Package
a) SSOP20Package
27 Ω
5nH
5nH
IN
OUT
Dz
Dr
Df
Dz
Dr
Lg
GND
10/12
Df
EMIF09-02726Sx
PART NUMBERING AND ORDERING INFORMATION
EMIF
09
-
027
26
R value (Ω)
EMI FILTERING
9 Bits Wide
S
3
Surface mount
C/10
2 x 130pF = 260pF
Package:
3: SO-20
6: SSOP20
PACKAGE MECHANICAL DATA
SO-20 (Plastic)
DIMENSIONS
REF.
D
B
e
K
A1
E
L
C
Inches
Min. Typ. Max. Min. Typ. Max.
hx45°
A
Millimeters
A
2.35
2.65 0.092
0.104
A1
0.10
0.20 0.004
0.008
B
0.33
0.51 0.013
0.020
C
0.23
0.32 0.009
0.013
D
12.6
13.0 0.484
0.512
E
7.40
7.60 0.291
0.299
H
e
1.27
0.050
H
10.0
10.65 0.394
0.419
h
0.25
0.75 0.010
0.029
L
0.50
1.27 0.020
0.050
K
8° (max)
11/12
EMIF09-02726Sx
PACKAGE MECHANICAL DATA
SSOP20 (Plastic)
DIMENSIONS
REF.
Min.
L
A2 A
e
b
k
A1
c
E
D
20
11
E1
1
Millimeters
10
Inches
Typ. Max. Min.
Typ. Max.
A
2.00
0.079
A1
0.25
0.010
2.00 0.059
0.079
A2
1.51
b
0.25
c
0.10
0.35 0.004
0.014
D
7.05
8.05 0.278
0.317
E
7.60
8.70 0.299
0.343
E1
5.02
e
0.30
6.10
0.35 0.010 0.012 0.014
6.22 0.198 0.240 0.245
0.65
k
0°
L
0.25
0.026
10°
0.50
0°
10°
0.80 0.010 0.020 0.031
ORDERING CODE
Order code
Marking
Package
Weight
Delivery
mode
Base qty
(pcs)
EMIF09-02726S3
ESDR6V1-27
SO-20
0.52 g.
Tube
50
EMIF09-02726S6
ESDR6V1-27
SSOP20
0.18 g.
Tube
50
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of
use of such information nor for any infringementof patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
 1999 STMicroelectronics - Printed in Italy - All rights reserved.
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