EMIF10-1K010F1 ® A.S.D. EMI FILTER INCLUDING ESD PROTECTION TM MAIN APPLICATIONS Where EMI filtering in ESD sensitive equipment is required: Computers and printers Communication systems Mobile phones MCU Boards ■ ■ ■ ■ DESCRIPTION The EMIF10-1K010F1 is a highly integrated device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 flip-chip packaging means the package size is equal to the die size. That's why EMIF10-1K010F1 is a very small device. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges up to 15 kV. Flip Chip package BENEFITS ■ ■ ■ ■ ■ ■ ■ EMI symetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consuming: 2.6 x 2.6 mm2 Very thin package: 0.65 mm High efficiency in ESD suppression on both input & output PINS (IEC61000-4-2 level 4). High reliability offered by monolithic integration High reducing of parasitic elements through integration & wafer level packaging. PIN CONFIGURATION (Ball Side) A 1 2 BASIC CELL CONFIGURATION Low-pass filter I3 B C D E I1 I2 O1 O2 I5 I4 O3 O4 3 GND GND I6 O5 O6 4 GND GND I8 O7 O8 I10 O9 O10 Output Input 5 I7 I9 Ri/o = 1kΩ Cinput = 100pF TM : ASD is a trademark of STMicroelectronics. July 2002 - Ed: 3C 1/13 EMIF10-1K010F1 COMPLIES WITH FOLLOWING STANDARD: IEC61000-4-2 level 4 15 KV (air discharge) 8 kV (contact discharge) on input & output pins MIL STD 883C - Method 3015-6 Class 3 ESD response to IEC61000-4-2 (16kV Air Discharge) Filtering Behavior S21 (dB) 0 -10 -20 V(in1) -30 V(out1) -40 -50 1 10 100 frequency (MHz) 1,000 Capacitance versus reverse applied voltage. C(pF) 100 90 80 70 60 50 40 30 20 10 0 2/13 F=1MHz Vosc=30mV VR(V) 1 2 5 10 EMIF10-1K010F1 ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C) Symbol VPP Tj Parameter and test conditions Value Unit ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge MIL STD 883C Method 3015-6 15 8 25 kV Junction temperature 125 °C Top Operating temperature range -40 to + 85 °C Tstg Storage temperature range -55 to +150 °C ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol Parameters VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Series resistance between Input & Output Cin VCL VBR VRM V IRM IR slope : 1 / R d IPP Input capacitance per line Symbol Test conditions VBR IR = 1mA IRM VRM = 3V per line Rd IPP = 10A, tp = 2.5µs (see note 1) RI/O Cline I At 0V bias Min Typ Max Unit 6 8 10 V 500 nA Ω 1 900 1000 1100 Ω 80 100 120 pF Note 1: To calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on page 5. 3/13 EMIF10-1K010F1 TECHNICAL INFORMATION Fig. A1: Frequency response curve FREQUENCY BEHAVIOR The EMIF10-1K010F1 is firstly designed as an EMI / RFI filter. This low-pass filter is characterized by the following parameters: - Cut-off frequency - Insertion loss - High frequency S21 (dB) 0 -10 -20 Figure A1 gives these parameters, in particular the signal rejection at the GSM frequency: - 25dB @ 900Mhz - 14dB @ 1800Mhz -30 -40 -50 1 10 100 frequency (MHz) 1,000 Fig. A2: Measurements conditions TEST BOARD 50 Ω 4/13 EMIF10 1K010F1 out1 50 Ω in1 Vg EMIF10-1K010F1 ESD PROTECTION In addition with the filtering the EMIF10-1K010F1 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at: Vcl = Vbr + Rd ⋅ Ipp This protection function is splitted in 2 stages. As shown in Figure A3, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level. Fig. A3: ESD clamping behavior Rg S1 R=1k Rd Rd Vinput Vg Rload Voutput Vbr Vbr EMIF10-1k010F1 ESD Surge S2 Device to be protected To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical dynamic resistance value Rd. By taking into account these following hypothesis : R>>Rd, Rg>>Rd and Rload>>Rd, it gives these formulas: Rg ⋅ Vbr + Rd ⋅ Vg Rg R ⋅ Vbr + Rd ⋅ Vin Voutput = R Vinpout = The results of the calculation done for an IEC 1000-4-2 Level 4 Contact Discharge surge (Vg=8kV, Rg=330Ω ) and Vbr=7V (typ.) give: Vinput = 31.24V Voutput = 7.03V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the series resistance R. 5/13 EMIF10-1K010F1 LATCH-UP PHENOMENA The early ageing and destruction of IC’s is often due to latch-up phenomena which mainly induced by dV/dt. Thanks to its RC structure, the EMIF10-1K010F1 provides a high immunity to latch-up by integration of fast edges. (Please refer to the response of the EMIF10-1K010F1 to a 3 ns edge on Fig. A9) The measurements done here after show very clearly (Fig. A5a & A5b) the high efficiency of the ESD protection : - almost no influence of the parasitic inductances on Vout stage - Vout clamping voltage very close to Vbr for positive surge and close to ground for negative one Fig. A4: Measurement conditions TEST BOARD V(out1) ESD SURGE V(in1) EMIF10 1K010F1 16kV Air Discharge Fig.A5: Remaining voltage at both stages S1 (Vin1) and S2 (Vout1) during ESD surge V(in1) V(in1) V(out1) V(out1) a: Positive Surge b:Negative Surge Please note that the EMIF10-1K010F1 is not only acting for positive ESD surges but also for negative ones. For negatives surges, it clamps close to ground voltage as shown in Fig. A5b. 6/13 EMIF10-1K010F1 Note: Dynamic resistance measurement Fig. A6: Rd measurement current wave I As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd IPP tt 2 µs 2.5 µs 2.5µs duration measurement wave CROSSTALK BEHAVIOR 1 - Crosstalk phenomena Fig. A7: Crosstalk phenomena RG1 Line 1 VG1 a 1 VG1 + b12 VG2 RL1 RG2 VG2 Line 2 RL2 DRIVERS a 2VG2 + b21VG1 RECEIVERS The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor ( 12 or 21 ) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is VG2, in fact the actual voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kW). The following chapters give the value of both digital and analog crosstalk. 7/13 EMIF10-1K010F1 2 - Digital Crosstalk EMIF10 1K010F1 Fig. A8: Digital crosstalk measurement +5V 74HC04 in1 +5V VG1 +5V 74HC04 out2 b21VG1 Square Pulse Generator in2 out1 Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A9 shows that in such a condition signal from 0 to 5V and rise time of few ns, the impact on the disturbed line is less than 40mV peak to peak. No data disturbance was noted on the concerned line. The measurements performed with falling edges gives an impact within the same range. Fig. A9: Digital crosstalk results VG1 β21VG1 8/13 EMIF10-1K010F1 3 - Analog Crosstalk Fig. A10: Analog crosstalk measurement TEST BOARD 50 Ω EMIF10 1K010F1 out2 50 Ω in1 Vg Fig. A11: Typical analog crosstalk results Analog crosstalk (dB) 0 -20 -40 -60 -80 -100 1 10 100 frequency (MHz) 1,000 Figure A10 gives the measurement circuit for the analog application. In Figure A11, the curve shows the effect of cell I1/O1 on cell I2/O2. In usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -47 dB. 9/13 EMIF10-1K010F1 4 - Spice model Fig. A13: Diodes Spice parameters Fig. A12: Spice model of one EMIF01 cell DZ Input 0.1nH 0.1nH 1kW Dz Output Dz 0.3nH GND Note: this model is available for an ambient temperature of 27°C. BV 7 Cjo 50p IBV 1m IKF 1000 IS 10E-15 ISR 100p N 1 M 0.3333 RS 1 VJ 0.6 TT 100n Fig. A14: Spice simulation: IEC 1000-4-2 Level 4 Contact Discharge response (V) (V) 60 0 Vinput Vinput 50 Voutput -10 Voutput 40 -20 30 -30 20 -40 10 0 0 20 40 60 80 time (ns) a: Positive surge 10/13 100 -50 0 20 40 60 time (ns) 80 100 b: Negative surge EMIF10-1K010F1 Fig. A15: Comparison between PSpice simulation and measured frequency response. S21 (dB) 0 measure -10 Spice -20 -30 -40 -50 1 10 100 frequency (MHz) 1,000 5 - Aplac model Fig. A16: Aplac model of one EMIF10 cell. Rs Ls 50pH 50m 50pH Ii 50m Ls Rs O1 cap_line Port15 50 Port16 50 cap_line Rgnd Lgnd Rgnd Lgnd Rgnd Rseries Ii Lgnd Rgnd Lgnd Oi MODEL = demif10 MODEL = demif10 sub Fig. A17: Aplac model of bump connections. Rsub Fig. A18: Aplac model of ground connections. GND1 sub GND Lbump Rbump I/O Csubump Rsubump + Lhole + cap_hole Rhole 11/13 EMIF01-1K010F1 Fig. A20: Comparison between Aplac simulation and measured frequency response. Fig. A19: Aplac model parameters. aplacvar Cz 57pF aplacvar Rseries 960 aplacvar cap_line 0.8pF aplacvar Ls 0.6nH aplacvar Rbump 50m aplacvar Lbump 50pH aplacvar Rs 0.15 aplacvar Csubump 1.5pF aplacvar Rsubump 0.15 aplacvar Rsub 0.1 aplacvar lhole 1.2nH opt aplacvar Rhole 0.15 aplacvar cap_hole 0.15pF aplacvar Rgnd 0.25 aplacvar lgnd 0.4nH Demif10 diodes model BV=7 IBV=1m CJO=Cz M=0.3333 RS=1 VJ=0.6 TT=100n EMIF10-1K010F1: Aplac model Aplac 7.60 User: STMicroelectronics Jan 25 2001 0.00 dB - 5.00 - 10.00 - 15.00 Aplac - 20.00 Measure - 25.00 - 30.00 - 35.00 - 40.00 - 45.00 - 50.00 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G f/Hz ORDERING CODE EMIF 10 - 1K0 10 F 1 Pitch and bump version 1: pitch = 0.5 mm bump = 300 µm EMI Filter Nb of lines Flip-Chip Resistance value (Ohms) Capacitance value / 10 (pF) 12/13 EMIF10-1K010F1 All dimensions in µm PACKAGE MECHANICAL DATA DIE SIZE 2570 650 500 ■ ■ ■ ■ ■ Die size: (2570 ± 50) x (2570 ± 50) Die height (including bumps): 650 ± 65 Bump diameter: 315 ± 50 Pitch: 500 ± 50 Weight: 9.2mg 2570 MARKING 500 300 ■ 500 ■ Bottom side (balls view): Pin A1 missing for die orientation Top side (balls underneath): see the marking on the left. 2570 diam 400 FDT YWW 330 100 ■ YWW: Date code 2570 PACKING: EMIF10-1K010F1 is delivered in Tape & Reel (7 inches reel); one Tape & Reel contains 5000 dice. Note: More packing information are available in the application note AN1235: ''Filp-Chip package description and recommandations for use'' Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All rights reserved. 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