EUTECH EUA6412

EUA6412
2.6-W Stereo Audio Power Amplifier
with Four Selectable Gain Settings
DESCRIPTOIN
FEATURES
The EUA6412 is a stereo audio power amplifier. When
driving 1 W into 8–Ω speakers, the EUA6412 has less than
0.8% THD+N across its specified frequency range. Included
within this device is integrated depop circuitry that virtually
eliminates transients that cause noise in the speakers.
Amplifier gain is internally configured and controlled by way
of two terminals (GAIN0 and GAIN1). BTL gain settings of 6
dB, 10 dB, 15.6 dB, and 21.6 dB are provided, while SE
gain is always configured as 4.1 dB for headphone drive. An
internal input MUX allows two sets of stereo inputs to the
amplifier .The HP/LINE terminal allows the user to select
which MUX input is active, regardless of whether the
amplifier is in SE or BTL mode. In notebook applications,
where internal speakers are driven as BTL and the line outputs
(often headphone drive) are required to be SE, the EUA6412
automatically switches into SE mode when the SE/ BTL input
is activated, and this reduces the gain to 4.1 dB.
The EUA6412 consumes only 5.2mA of supply current during
normal operation.
z
z
Block Diagram
DS6412 Ver 1.0 Dec. 2006
1
z
z
z
z
z
z
z
z
2.6W per Channel Output Power Into 3-Ω Load
Internal Gain Control, Which Eliminates
External Gain-Setting Components
Input MUX Select Terminal
PC-Beep Input
Depop Circuitry Integrated
Two Input Modes Allowable with Single-Ended or
Fully Differential Input
Low Supply Current and Shutdown Current
Thermal Shutdown Protection
TSSOP-24 with Thermal Pad
RoHS Compliant and 100% Lead (Pb)-Free
APPLICATIONS
z
z
z
Notebook Computers
Multimedia Monitors
Digital Radios and Portable TVs
EUA6412
Typical Application Circuit
Figure 1. Application circuit using single-ended inputs and input MUX
Figure 2. Application circuit using differential input
DS6412 Ver 1.0 Dec. 2006
2
EUA6412
Pin Configurations
Package Type
Pin Configurations(Top View)
TSSOP-24 with a Thermal
Pad exposure on the bottom
of the package
Pin Description
PIN
PIN
BYPASS
GAIN0
GAIN1
LHPIN
11
2
3
1,12
13,24
6
LIN
10
I
LLINEIN
LOUT+
LOUT-
5
4
9
I
O
O
PC-BEEP
14
I
17
I
PVDD
RHPIN
7,18
20
I
I
RIN
8
I
RLINEIN
ROUT+
ROUT-
23
21
16
I
O
O
SHUTDOWN
22
I
SE/ BTL
15
I
VDD
19
I
GND
HP/ LINE
DS6412 Ver 1.0 Dec. 2006
I/O
I
I
DESCRIPTION
Tap to voltage divider for internal mid-supply bias generator
Bit 0 of gain control
Bit 1 of gain control
Ground connection for circuitry. Connected to thermal pad.
I
Left channel headphone input, selected when SE/ BTL is held high.
Common left input for fully differential input. AC ground for single-ended
inputs.
Left channel line input, selected when SE/ BTL is held low.
Left channel positive output in BTL mode and positive output in SE mode.
Left channel negative output in BTL mode and high-impedance in SE mode.
The input for PC Beep mode. PC-BEEP is enabled when a > 1-V (peak-to-peak)
square wave is input to PC-BEEP or PCB ENABLE is high.
HP/LINE is the input MUX control input. When the HP/LINE terminal is held
high, the headphone inputs (LHPIN or RHPIN [6, 20]) are active. When the
HP/LINE terminal is held low, the line BTL inputs (LLINEIN or RLINEIN [5,
23]) are active.
Power supply for output stage.
Right channel headphone input, selected when SE/ BTL is held high
Common right input for fully differential input. AC ground for single-ended
inputs.
Right channel line input, selected when SE/ BTL is held low.
Right channel positive output in BTL mode and positive output in SE mode.
Right channel negative output in BTL mode and high-impedance in SE mode.
When held low, this terminal place the entire device, except PC-BEEP detect
circuitry, in shutdown mode.
Input and output MUX control. When this terminal is held high, the LHPIN or
RHPIN and SE output is selected. When this terminal is held low, the LLINEIN
or RLINEIN and BTL output are selected.
Analog VDD input supply. This terminal needs to be isolated from PVDD to
achieve highest performance.
3
EUA6412
Ordering Information
Order Number
Package Type
Marking
Operating Temperature range
EUA6412QIR1
TSSOP 24
xxxx
A6412A
-40 °C to 85°C
EUA6412QIT1
TSSOP 24
xxxx
A6412A
-40 °C to 85°C
EUA6412
□ □ □ □
Lead Free Code
1: Lead Free 0: Lead
Packing
R: Tape& Reel
T: Tube
Operating temperature range
I: Industry Standard
Package Type
Q: TSSOP
DS6412 Ver 1.0 Dec. 2006
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EUA6412
Absolute Maximum Ratings
„
„
„
„
„
„
„
Supply voltage, VDD------------------------------------------------------------------------------------------------ 6V
Input voltage, VI------------------------------------------------------------------------------ –0.3 V to VDD +0.3 V
Operating free-air temperature range, TA--------------------------------------------------------- –40°C to 85° C
Operating junction temperature range, TJ ------------------------------------------------------ - –40°C to 150°C
Storage temperature range, Tstg------------------------------------------------------------------ -- –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds----------------------------------------- 260°C
Thermal Resistance
θJA (TSSOP) ----------------------------------------------------------------------------------------------- 87.9°C/W
Recommended Operating Conditions
Supply voltage, VDD
High-level input voltage, VIH
Low-level input voltage, VIL
Min
Max
Unit
4.5
5.5
V
SE/ BTL
4
SHUTDOWN
2
V
SE/ BTL
3
SHUTDOWN
0.8
Operating free-air temperature, TA
-40
85
V
°C
Electrical Characteristics at Specified Free-air Temperature, VDD = 5V, TA = 25°C
EUA6412
Symbol
Parameter
Conditions
VOO
Output offset voltage
(measured differentially)
VI =0V, AV =2 V/V
PSRR
Power supply rejection ratio
VDD= 4 V to 5 V
IIH
High-level input current
VDD=5.5 V, VI = VDD
1
µA
IIL
Low-level input current
VDD=5.5 V, VI = 0V
1
µA
IDD
Supply current
IDD(SD)
Supply current, shutdown mode
DS6412 Ver 1.0 Dec. 2006
Min.
Typ.
Max.
30
70
mV
dB
BTL mode
5.2
10
SE mode
3
5
150
300
5
Unit
mA
µA
EUA6412
Operating Characteristics, VDD = 5V, TA = 25°C, RL = 8Ω, Gain =-2V/V, BTL mode
Symbol
Parameter
PO
Output power
THD+N
BOM
RL=3Ω
Total harmonic distortion plus
noise
Maximum output power
bandwidth
Supply ripple rejection ratio
SNR
Signal-to-noise ratio
Vn
Noise output voltage
EUA6412
Conditions
Min.
Typ.
THD+N=10%
2.6
THD+N=1%
2.05
Max.
0.75%
THD=5%
＞15
kHz
72
dB
94
dB
f =1kHz,
C(BYP)=0.47µF
BTL mode
BTL mode
C(BYP)=0.47µF,
f= 20 kHz to 20 kHz
SE mode
Item
50
55
Figure
1
THD+N vs. Output Power
3,6,7,8,10,11,12,15, 16,17,19
2
THD+N vs. Output Frequency
4,5,9,13,14,18,20
3
THD+N vs. Output Voltage
21
4
Output Noise Voltage vs Bandwidth
22
5
Supply Ripple Rejection Ratio vs. Frequency
23,24
6
Crosstalk vs. Frequency
25,26
7
Shutdown Attenuation
27
8
Signal to noise ratio vs. Frequency
28
9
Closed Loop Response
29,30,31
10
Output Power vs. Load Resistance
32,33
11
Power Dissipation vs. Output Power
34,35
DS6412 Ver 1.0 Dec. 2006
W
PO=1W, f=20 Hz to 15 kHz
Typical Characteristics (Table of Graphs)
No
Unit
6
µVRMS
EUA6412
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
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EUA6412
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
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EUA6412
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
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EUA6412
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
DS6412 Ver 1.0 Dec. 2006
Figure 26
10
EUA6412
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
DS6412 Ver 1.0 Dec. 2006
Figure 32
11
EUA6412
Figure 33
Figure 34
Figure 35
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EUA6412
Application Information
Input Capacitor, Ci
In the typical application an input capacitor, Ci, is
required to allow the amplifier to bias the input signal to
the proper dc level for optimum operation. In this case, Ci
and the input impedance of the amplifier, Zi, from a
high-pass filter with the corner frequency determined in
equation 2.
Gain Setting
The gain of the EUA6412 is set by two input terminals,
Gain0 and Gain1.The gains listed in Table 1 are realized
by changing the taps on the input resistors inside the
amplifier.
Table 1.Gain Setting
fc(highpass)=
GAIN0
GAIN1
SE/ BTL
AV(inv)
ZI
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
6dB
10dB
15.6dB
21.6dB
4.1dB
90kΩ
70kΩ
45kΩ
25kΩ
i i
The value of Ci is important to consider as it directly
affects the bass (low frequency) performance of the
circuit. Consider the example where Zi is 710kΩ and the
specification calls for a flat bass response down to 40Hz.
Equation 2 is reconfigured as equation 3.
1
Ci =
----------------------------- (3 )
2 π Z fC
Input Resistance
Each gain setting is achieved by varying the input
resistance of the amplifier, which can range from its
smallest value to over 6 times that value. As a results, if a
single capacitor is used in the input high pass filter,
the –3 dB or cut off frequency will also change by over 6
times. If an additional resistor is connected from the input
pin of the amplifier to ground, as shown in the figure
below, the variation of the cut-off frequency will be much
reduced.
i
In this example, Ci is 5.6nF so one would likely choose a
value in the range of 5.6nF to 1µF. A further
consideration for this capacitor is the leakage path from
the input source through the input network (Ci) and the
feedback network to the load. This leakage current
creates a dc offset voltage at the input to the amplifier
that reduces useful headroom, especially in high gain
applications. For this reason a low- leakage tantalum or
ceramic capacitor is the best choice. When polarized
capacitors are used, the positive side of the capacitor
should face the amplifier input in most applications as
the dc level there is held at VDD/2, which is likely higher
than the source dc level. Note that it is important to
confirm the capacitor polarity in the application.
The-3dB frequency can be calculated using
equation 1:
f-3dB =
1
2 π C (R || R )
i
---------------------- (1)
If the filter must be more accurate, the value of the
capacitor should be increased while the value of the
resistor to ground should be decreased. In addition, the
order of the filter could be increased.
DS6412 Ver 1.0 Dec. 2006
1
-----------------(2)
2π Z C
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EUA6412
Decoupling Capacitor, (CS)
The main disadvantage, from a performance standpoint,
is the load impedances are typically small, which drives
the low-frequency corner higher, degrading the bass
response. Large values of CC are required to pass low
frequencies into the load. Consider the example where a
CC of 330µF is chosen and loads vary from 3Ω, 4Ω,
8Ω, 32Ω, 10kΩ, to 47kΩ. Table 2 summarizes the
frequency response characteristics of each configuration.
The EUA6412 is a high-performance CMOS audio
amplifier that requires adequate power supply
decoupling to ensure the output total harmonic distortion
(THD) is as low as possible. Power supply decoupling
also prevents oscillations for long lead lengths between
the amplifier and the speaker. The optimum decoupling
is achieved by using two capacitors of different types
that target different types of noise on the power supply
leads. (ESR) ceramic capacitor, typically 0.1µF placed
as close as possible to the device VDD lead, works best.
For filtering lower-frequency noise signals, a larger
aluminum electrolytic capacitor of 10µF or greater
placed near the audio power amplifier is recommended.
Table2. Common Load Impedances vs Low
Frequency Output characteristics in SE Mode
Lowest
CC
RL
Frequency
3Ω
330µF
161Hz
4Ω
330µF
120Hz
8Ω
330µF
60Hz
32Ω
330µF
15Hz
10000Ω
330µF
0.05Hz
47000Ω
330µF
0.01Hz
Bypass Capacitor, (CB)
The bypass capacitor, CB, is the most critical capacitor
and serves several important functions. During start-up or
recovery from shutdown mode, CB determines the rate at
which the amplifier starts up. The second function is to
reduce noise produced by the power supply caused by
coupling into the output drive signal. This noise is from
the midrail generation circuit internal to the amplifier,
which appears as degraded PSRR and THD+N. Bypass
capacitor, CB, values of 0.47µF to 1µF ceramic or
tantalum low-ESR capacitors are recommended for the
best THD and noise performance.
Output Coupling Capacitor, (CC)
As Table 2 indicates, most of the bass response is
attenuated into a 4-Ω load and 8-Ω load is adequate,
headphone response is good, and drive into line level
inputs (a home stereo for example) is exceptional.
Using Low- ESR Capacitors
Low- ESR capacitors are recommended throughout this
applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series
with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor
in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an
ideal capacitor.
For general signal-supply SE configuration, the output
coupling capacitor (CC) is required to block the dc bias
at the output of the amplifier thus preventing dc currents
in the load. As with the input coupling capacitor, the
output coupling capacitor and impedance of the load
form a high-pass filter governed by equation 4.
fc(high)=
1
2π R C
L C
DS6412 Ver 1.0 Dec. 2006
------------------------ (4)
14
EUA6412
Bridged-Tied Load Versus Single-Ended Mode
Figure 37 show a Class-AB audio power amplifier (APA)
in a BTL configuration. The EUA6412 BTL amplifier
consists of two Class-AB amplifiers driving both ends of
the load. There are several potential benefits to this
differential drive configuration, but initially consider
power to the load. The differential drive to the speaker
means that as one side is slewing up, the other side is
slewing down, and vice versa. This in effect doubles the
voltage swing on the load as compared to a ground
referenced load. Plugging 2×VO(PP) into the power
equation, where voltage is squared, yields 4× the output
power from the same supply rail and load impedance(see
equation 5)
V(rms) =
V
O(PP)
2 2
Power =
V
(rms)
R
For example, a 68µF capacitor with an 8-Ω speaker
would attenuate low frequencies below 293 Hz. The
BTL configuration cancels the dc offsets, which
eliminates the need for the blocking capacitors.
Low-frequency performance is then limited only by the
input network and speaker response. Cost and PCB
space are also minimized by eliminating the bulky
coupling capacitor.
2
------(5)
L
Increasing power to the load does carry a penalty of
increased internal power dissipation. The increased
dissipation is understandable considering that the BTL
configuration produces 4 × the output power of the SE
configuration. Internal dissipation versus output power is
discussed further in the crest factor and thermal
considerations section.
Single-Ended Operation
In SE mode the load is driven from the primary
amplifier output for each channel (OUT+, terminals 21
and 4 ). The amplifier switches single-ended operation
when the SE/ BTL terminal is held high. This puts the
negative outputs in a high-impedance state, and reduces
the amplifier’s gain to 1V/V.
In a typical computer sound channel operating at 5V,
bridging raises the power into an 8-Ω speaker from a
singled-ended (SE, ground reference) limit of 250 mW
to 1W. In sound power that is a 6-dB improvement—
which is loudness that can be heard. In addition to
increased power there are frequency response concerns.
Consider the single-supply SE configuration shown in
Figure 38.
A coupling capacitor is required to block the dc offset
voltage from reaching the load. These capacitors can be
quite large (approximately 33µF to 1000µF) so they tend
to be expensive, heavy, occupy valuable PCB area, and
have the additional drawback of limiting low-frequency
performance of the system. This frequency limiting
effect is due to the high pass filter network created with
the speaker impedance and the coupling capacitance and
is calculated with equation 6.
fC =
1
2π R C
L C
Input MUX Operation
The input MUX allows two separate inputs to be applied
to the amplifier. This allow the designer to choose which
input is active independent of the state of the
SE/ BTL terminal. When the HP/LINE terminal is held
high, the headphone inputs are active. When the
HP/LINE terminal is held low, the line BTL inputs are
active.
----------------------------------(6)
DS6412 Ver 1.0 Dec. 2006
15
EUA6412
SE/BTL Operation
The ability of the EUA6412 to easily switch between
BTL and SE modes is one of its most important cost
saving features. This feature eliminates the requirement
for an additional headphone amplifier in applications
where internal stereo speakers are driven in BTL mode
but external headphone or speakers must be
accommodated. Internal to the EUA6412 , two separate
amplifiers drive OUT+ and OUT- .The SE/ BTL input
(terminal 15) control the operation of the follower
amplifier that drives LOUT- and ROUT- (terminals 9
and 16).When SE/ BTL is held low, the amplifier is on
and the EUA6412 is in the BTL mode. When
SE/ BTL is held high, the OUT- amplifiers are in a high
output impedance state, which configures the EUA6412
as an SE driver from LOUT+ and ROUT+ (terminals 4
and 21). IDD is reduced by approximately one-half in SE
mode. Control of the SE/ BTL input can be from a
logic-level CMOS source or, more typically, from a
resistor divider network as shown in Figure 39.
PC BEEP Operation
The PC BEEP input allows a system beep to be sent
directly from a computer through the amplifier to the
speakers with few external components. The input is
activated automatically. When the PC BEEP input is
active, both of the LINEIN and HPIN inputs are
deselected and both the left and right channels are driven
in BTL mode with the signal from PC BEEP. The gain
from the PC BEEP input to the speakers is fixed at
0.3V/V and is independent of the volume setting. When
the PC BEEP input is deselected, the amplifier will
return to the previous operating mode and volume
setting. Furthermore, if the amplifier is in shutdown
mode, activating PC BEEP will take the device out of
shutdown and output the PC BEEP signal, then return
the amplifier to shutdown mode.
The preferred input signal is a square wave or pulse train
with an amplitude of 1 VPP or greater. When the signal is
no longer detected, the amplifier will return to its
previous operating mode and volume setting.
If it is desired to ac-couple the PC BEEP input, the value
of the coupling capacitor should be chosen to satisfy
equation 7:
1
C
≥
− − − − − − − − (7 )
PCB
2πf PCB (100k Ω )
The PC BEEP input can also be dc- coupled to avoid
using this coupling capacitor. The pin normally sits at
midrail when no signal is present.
Shutdown Modes
The EUA 6412 employs a shutdown mode of operation
designed to reduce supply current, IDD, to the absolute
minimum level during periods of nonuse for
battery-power conservation. The SHUTDOWN input
terminal should be held high during normal operation
when the amplifier is in use. Pulling SHUTDOWN low
causes the outputs to mute and the amplifier to enter a
low-current state, IDD=150µA. SHUTDOWN should
never be left unconnected because amplifier operation
would be unpredictable.
Using a readily available 1/8-in. (3.5mm) stereo
headphone jack, the control switch is closed when no
plug is inserted. When closed the 100-kΩ /1-kΩ divider
pulls the SE/BTL input low. When a plug is inserted, the
1-kΩ resistor is disconnected and the SE/ BTL input is
pulled high. When the input goes high, the OUTamplifier is shut down causing the speaker to
mute(virtually open-circuits the speaker).The OUT+
amplifier then drives through the output capacitor (CO)
into the headphone jack.
Table 6 . HP/LINE , SE/ BTL , and Shutdown Function
Inputs
HP/ LINE
SE/ BTL
SHUTDOWN
X
Low
Low
High
High
X
Low
High
Low
High
Low
High
High
High
High
X= Do not care
DS6412 Ver 1.0 Dec. 2006
16
Amplifier State
INPUT
OUTPUT
X
Line
Line
HP
HP
Mute
BTL
SE
BTL
SE
EUA6412
Thermal Pad Considerations
The thermal pad must be connected to ground. The
package with thermal pad of the EUA6412 requires
special attention on thermal design. If the thermal
design issues are not properly addressed, the
EUA6412 will go into thermal shutdown when
driving a heavy load.
The thermal pad on the bottom of the EUA6412
should be soldered down to a copper pad on the
circuit board. Heat can be conducted away from the
thermal pad through the copper plane to ambient. If
the copper plane is not on the top surface of the
circuit board, 8 to 10 vias of 13 mil or smaller in
diameter should be used to thermally couple the
thermal pad to the bottom plane.
For good thermal conduction, the vias must be plated
through and solder filled. The copper plane used to
conduct heat away from the thermal pad should be as
large as practical.
If the ambient temperature is higher than 25℃,a
larger copper plane or forced-air cooling will be
required to keep the EUA6412 junction temperature
below the thermal shutdown temperature (150℃). In
higher ambient temperature, higher airflow rate
and/or larger copper area will be required to keep the
IC out of thermal shutdown.
DS6412 Ver 1.0 Dec. 2006
17
EUA6412
Package Information
TSSOP-24 (FD)
SYMBOLS
A
A1
b
D
E
E1
e
L
DS6412 Ver 1.0 Dec. 2006
MILLIMETERS
MIN.
MAX.
1.20
0.00
0.15
0.19
0.30
7.80
6.20
6.60
4.40
0.65
0.45
0.75
18
INCHES
MIN.
0.000
0.007
MAX.
0.047
0.006
0.012
0.307
0.244
0.260
0.173
0.026
0.018
0.030