FDD8424H tm Dual N & P-Channel PowerTrench® MOSFET N-Channel: 40V, 20A, 24mΩ P-Channel: -40V, -20A, 54mΩ Features General Description Q1: N-Channel These dual N and P-Channel enhancement Max rDS(on) = 24mΩ at VGS = 10V, ID = 9.0A MOSFETs are produced using Fairchild Semiconductor’s mode Power advanced PowerTrench- process that has been especially Max rDS(on) = 30mΩ at VGS = 4.5V, ID = 7.0A tailored to minimize on-state resistance and yet maintain superior switching performance. Q2: P-Channel Max rDS(on) = 54mΩ at VGS = -10V, ID = -6.5A Application Max rDS(on) = 70mΩ at VGS = -4.5V, ID = -5.6A Inverter Fast switching speed H-Bridge RoHS Compliant D1 D2 D1/D2 G1 G2 G2 S2 G1 S1 S1 Dual DPAK 4L N-Channel S2 P-Channel MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter Q1 40 Q2 -40 Units V VGS Gate to Source Voltage ±20 ±20 V Drain Current 20 -20 - Continuous (Package Limited) ID - Continuous (Silicon Limited) TC = 25°C 26 -20 - Continuous TA = 25°C 9.0 -6.5 55 -40 - Pulsed Power Dissipation for Single Operation TC = 25°C PD EAS Single Pulse Avalanche Energy TJ, TSTG Operating and Storage Junction Temperature Range (Note 1) 30 35 TA = 25°C (Note 1a) 3.1 TA = 25°C (Note 1b) 1.3 (Note 3) A 29 W 33 -55 to +150 mJ °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case, Single Operation for Q1 (Note 1) 4.1 RθJC Thermal Resistance, Junction to Case, Single Operation for Q2 (Note 1) 3.5 °C/W Package Marking and Ordering Information Device Marking FDD8424H Device FDD8424H ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C Package TO-252-4L 1 Reel Size 13” Tape Width 12mm Quantity 2500 units www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench® MOSFET March 2007 Symbol Parameter Test Conditions Type Min 40 -40 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V ID = -250µA, VGS = 0V Q1 Q2 ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient ID = 250µA, referenced to 25°C ID = -250µA, referenced to 25°C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 32V, VGS = 0V VDS = -32V, VGS = 0V Q1 Q2 1 -1 µA IGSS Gate to Source Leakage Current VGS = ±20V, VDS = 0V Q1 Q2 ±100 ±100 nA nA 3 -3 V V 34 -32 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA VGS = VDS, ID = -250µA Q1 Q2 ∆VGS(th) ∆TJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250µA, referenced to 25°C ID = -250µA, referenced to 25°C Q1 Q2 -5.3 4.8 VGS = 10V, ID = 9.0A VGS = 4.5V, ID = 7.0A VGS = 10V, ID = 9.0A, TJ = 125°C Q1 19 23 29 24 30 37 VGS = -10V, ID = -6.5A VGS = -4.5V, ID = -5.6A VGS = -10V, ID = -6.5A, TJ = 125°C Q2 42 58 62 54 70 80 VDS = 5V, ID = 9.0A VDS = -5V, ID = -6.5A Q1 Q2 29 13 Q1 VDS = 20V, VGS = 0V, f = 1MHZ Q1 Q2 750 1000 1000 1330 pF Q1 Q2 115 140 155 185 pF Q1 Q2 75 75 115 115 pF Q1 Q2 1.1 3.3 Q1 Q2 7 7 14 14 ns Q1 Q2 13 3 24 10 ns Q1 Q2 17 20 31 36 ns Q1 Q2 6 3 12 10 ns Q1 Q2 14 17 20 24 nC Q1 Q2 2.3 3.0 nC Q1 Q2 3.2 3.6 nC rDS(on) gFS Static Drain to Source On Resistance Forward Transconductance 1 -1 1.7 -1.6 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance Q2 VDS = -20V, VGS = 0V, f = 1MHZ f = 1MHz Ω Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) Total Gate Charge Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C Q1 VDD = 20V, ID = 9.0A, VGS = 10V, RGEN = 6Ω Q2 VDD = -20V, ID = -6.5A, VGS = -10V, RGEN = 6Ω Q1 VGS = 10V, VDD = 20V, ID = 9.0A Q2 VGS = -10V, VDD = -20V, ID = -6.5A 2 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25°C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0V, IS = 9.0A VGS = 0V, IS = -6.5A Q1 IF = 9.0A, di/dt = 100A/s Q2 IF = -6.5A, di/dt = 100A/s (Note 2) (Note 2) Q1 Q2 0.87 0.88 1.2 -1.2 V Q1 Q2 25 29 38 44 ns Q1 Q2 19 29 29 44 nC Notes: 1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. Q1 b. 96°C/W when mounted on a minimum pad of 2 oz copper a. 40°C/W when mounted on a 1 in2 pad of 2 oz copper Scale 1 : 1 on letter size paper Q2 b. 96°C/W when mounted on a minimum pad of 2 oz copper a. 40°C/W when mounted on a 1 in2 pad of 2 oz copper Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%. 3. Starting TJ = 25°C, N-ch: L = 0.3mH, IAS = 14A, VDD = 40V, VGS = 10V; P-ch: L = 0.3mH, IAS = -15A, VDD = -40V, VGS = -10V. ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 3 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25°C unless otherwise noted 60 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 3.0 VGS = 4.0V ID, DRAIN CURRENT (A) 50 VGS = 10V PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX 40 VGS = 4.5V 30 VGS = 3.5V 20 10 VGS = 3.0V 0 0 1 2 3 VGS = 3.0V 2.5 2.0 VGS = 4.5V 1.5 1.0 VGS = 10V 0.5 4 0 10 rDS(on), DRAIN TO 1.0 0.8 -50 -25 0 25 50 75 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.2 ID = 9A 60 PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX TJ = 125oC 30 TJ = 25oC 20 10 100 125 150 2 TJ, JUNCTION TEMPERATURE ( C) 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On -Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 60 60 PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 50 40 o VDS = 5V 30 20 TJ = 150oC TJ = 25oC 10 TJ = -55oC 0 1.5 40 50 ID = 9A VGS = 10V 1.4 40 30 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.8 50 20 ID, DRAIN CURRENT(A) Figure 1. On- Region Characteristics 0.6 -75 VGS = 4.0V VGS = 3.5V VDS, DRAIN TO SOURCE VOLTAGE (V) 1.6 PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX 2.0 2.5 3.0 3.5 4.0 TJ = 150oC 1 TJ = 25oC 0.1 0.01 TJ = -55oC 0.001 0.0 4.5 0.3 0.6 0.9 1.2 1.5 VSD, BODY DIODE FORWARD VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C VGS = 0V 10 Figure 6. Source to Drain Diode Forward Voltage vs Source Current 4 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted 2000 ID = 9A Ciss 1000 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE(V) 10 6 VDD = 20V VDD = 15V 4 VDD = 25V Coss 100 2 f = 1MHz VGS = 0V 30 0.1 0 0 4 8 12 16 1 Figure 7. Gate Charge Characteristics 40 Figure 8. Capacitance vs Drain to Source Voltage 30 ID, DRAIN CURRENT (A) 30 IAS, AVALANCHE CURRENT(A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC) TJ = 25oC 10 TJ = 125oC 25 Limited by Package 20 VGS = 10V 15 10 VGS = 4.5V 5 o RθJC = 4.1 C/W 1 0.001 0.01 0.1 1 10 0 25 100 50 75 100 125 150 o TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE(ms) Figure 9. Unclamped Inductive Switching Capability Figure 10. Maximum Continuous Drain Current vs Case Temperature 100 10000 P(PK), PEAK TRANSIENT POWER (W) 10us ID, DRAIN CURRENT (A) Crss 100us 10 THIS AREA IS LIMITED BY rDS(on) 1 SINGLE PULSE TJ = MAX RATED o 1ms 10ms DC RθJC = 4.1 C/W TC = 25oC 0.1 1 10 80 VDS, DRAIN to SOURCE VOLTAGE (V) ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 1000 150 – T C -----------------------125 I = I25 TC = 25oC 100 SINGLE PULSE o RθJC = 4.1 C/W 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 t, PULSE WIDTH (s) Figure 11. Forward Bias Safe Operating Area ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C FOR TEMPERATURES VGS = 10V Figure 12. Single Pulse Maximum Power Dissipation 5 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJC 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 0.005 -5 10 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE RθJC = 4.1oC/W -4 10 -3 -2 10 10 -1 10 0 10 1 10 t, RECTANGULAR PULSE DURATION (s) Figure 13. Transient Thermal Response Curve ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 6 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted FDD8424H Dual N & P-Channel PowerTrench® MOSFET ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 7 www.fairchildsemi.com 3.0 VGS = -10V PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX 30 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) 40 VGS = -4.5V VGS = -4V 20 VGS = -3.5V 10 VGS = -3V 0 0 1 2 3 VGS = -3V PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX 2.5 VGS = -3.5V VGS = -4V 2.0 VGS = -4.5V 1.5 VGS = -10V 1.0 0.5 0 4 10 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 14. On- Region Characteristics 40 160 ID = -6.5A VGS = -10V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 30 Figure 15. Normalized on-Resistance vs Drain Current and Gate Voltage 1.6 PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX 120 40 TJ = 25oC 2 6 8 10 Figure 17. On-Resistance vs Gate to Source Voltage 40 -IS, REVERSE DRAIN CURRENT (A) 30 VDS = -5V 20 TJ = 25oC 10 TJ = 150oC TJ = -55oC VGS = 0V 10 1 TJ = 25oC TJ 0.1 5 = 150oC TJ = -55oC 0.01 0.001 0.0 0 2 3 4 -VGS, GATE TO SOURCE VOLTAGE (V) 4 -VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX 0.3 0.6 0.9 1.2 1.5 -VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 18. Transfer Characteristics ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C TJ = 125oC 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 40 1 ID = -6.5A 80 Figure 16. Normalized On-Resistance vs Junction Temperature -ID, DRAIN CURRENT (A) 20 -ID, DRAIN CURRENT(A) Figure 19. Source to Drain Diode Forward Voltage vs Source Current 8 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q2 P-Channel)TJ = 25°C unless otherwise noted 2000 Ciss ID = -6.5A 8 1000 VDD = -15V CAPACITANCE (pF) -VGS, GATE TO SOURCE VOLTAGE(V) 10 VDD = -20V 6 VDD = -25V 4 Coss Crss 100 2 f = 1MHz VGS = 0V 30 0.1 0 0 4 8 12 16 20 1 Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 25 10 -ID, DRAIN CURRENT (A) -IAS, AVALANCHE CURRENT(A) 30 TJ = 25oC TJ = 125oC 20 VGS = -10V 15 10 VGS = -4.5V 5 o RθJC = 3.5 C/W 1 0.001 0.01 0.1 1 10 0 100 25 50 tAV, TIME IN AVALANCHE(ms) 75 100 125 150 o TC, CASE TEMPERATURE ( C) Figure 23. Maximum Continuous Drain Current vs Case Temperature Figure 22. Unclamped Inductive Switching Capability 100 P(PK), PEAK TRANSIENT POWER (W) 10000 10us -ID, DRAIN CURRENT (A) 40 10 -VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC) 100us 10 THIS AREA IS LIMITED BY rds(on) 1ms 1 SINGLE PULSE TJ = MAX RATED RθJC = 3.5oC/W TC = 25oC 0.1 1 10 10ms DC 80 -VDS, DRAIN to SOURCE VOLTAGE (V) FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 1000 150 – T C -----------------------125 I = I25 TC = 25oC 100 SINGLE PULSE o 10 -5 10 RθJC = 3.5 C/W -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 t, PULSE WIDTH (s) Figure 24. Forward Bias Safe Operating Area ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C VGS = -10V Figure 25. Single Pulse Maximum Power Dissipation 9 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q2 P-Channel)TJ = 25°C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJC 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 0.005 -5 10 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE o RθJC = 3.5 C/W -4 10 -3 -2 10 10 -1 10 0 10 1 10 t, RECTANGULAR PULSE DURATION (s) Figure 26. Transient Thermal Response Curve ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 10 www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q2 P-Channel)TJ = 25°C unless otherwise noted FDD8424H Dual N & P-Channel PowerTrench® MOSFET ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C 11 www.fairchildsemi.com TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx® Across the board. Around the world.™ ActiveArray™ Bottomless™ Build it Now™ CoolFET™ CROSSVOLT™ CTL™ Current Transfer Logic™ DOME™ E2CMOS™ EcoSPARK® EnSigna™ FACT Quiet Series™ FACT® FAST® FASTr™ FPS™ FRFET® GlobalOptoisolator™ GTO™ HiSeC™ i-Lo™ ImpliedDisconnect™ IntelliMAX™ ISOPLANAR™ MICROCOUPLER™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR® PACMAN™ POP™ Power220® Power247® PowerEdge™ PowerSaver™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ ScalarPump™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TCM™ The Power Franchise® ™ TinyBoost™ TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyWire™ TruTranslation™ µSerDes™ UHC® UniFET™ VCX™ Wire™ tm DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor.The datasheet is printed for reference information only. Definition Rev. I24 ©2007 Fairchild Semiconductor Corporation FDD8424H Rev.C www.fairchildsemi.com FDD8424H Dual N & P-Channel PowerTrench® MOSFET tm