HD74LS273 Octal D-type Positive-edge-triggered Flip-Flops (with Clear) REJ03D0473–0300 Rev.3.00 Jul.15.2005 The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS273P DILP-20 pin PRDP0020AC-B (DP-20NEV) P — HD74LS273FPEL SOP-20 pin (JEITA) PRSP0020DD-B (FP-20DAV) FP EL (2,000 pcs/reel) PRSP0020DC-A RP (FP-20DBV) Note: Please consult the sales office for the above package availability. HD74LS273RPEL SOP-20 pin (JEDEC) EL (1,000 pcs/reel) Pin Arrangement Clear 1 1Q 2 1D 3 Clear D CK 2D 4 D 2Q 5 Q 3Q 6 Q 3D 7 Clear D CK 4D 8 D 4Q 9 Q GND 10 Q CK Clear CK Clear 20 VCC Q Clear CK D 19 8Q 18 8D CK D Clear Q 17 7D 16 7Q Q Clear CK D 15 6Q 14 6D CK D Clear Q 13 5D 12 5Q 11 Clock (Top view) Rev.3.00, Jul.15.2005, page 1 of 6 HD74LS273 Function Table Inputs Clock X ↑ ↑ L Clear L H H H Output Q L H L Q0 D X H L X Notes: H; high level, L; low level, X; irrelevant ↑; transition from low to high level Q0; level of Q before the indicated steady-state input conditions were established. Block Diagram 1D 2D 3D 4D 5D 6D 7D 8D Clock (1) D Q CK Clear D Q CK Clear D Q CK Clear D Q CK Clear D Q CK Clear D Q CK Clear D Q CK Clear D Q CK Clear Clear (2) 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC 7 V Input voltage VIN 7 V PT 400 mW Tstg –65 to +150 °C Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA mA IOL — — 8 Operating temperature Topr –20 25 75 °C Clock frequency ƒclock 0 — 30 MHz tw (clock) 20 — — ns Clock pulse width Clear pulse width tw (clear) 20 — — ns Data setup time tsu (data) 20↑ — — ns Clear (inactive-state) setup time tsu (clear) 25↑ — — ns Data hold time th (data) 5↑ — — ns Rev.3.00, Jul.15.2005, page 2 of 6 HD74LS273 Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V — — — — — –20 — — — — 0.5 0.4 20 –0.4 0.1 –100 27 –1.5 Output voltage VOL IIH IIL Input current V µA mA mA mA mA V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 8 mA VCC = 4.75 V, VIH = 2 V, IOL = 4 mA VIL = 0.8 V VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA II Short-circuit output current IOS — Supply current ICC** 17 Input clamp voltage VIK — Notes: * VCC = 5 V, Ta = 25°C ** With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V is applied to clock. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol ƒmax tPHL tPLH tPHL Inputs Clock Clear min. 30 — — — Clock typ. 40 18 17 18 max. — 27 27 27 Testing Method Test Circuit VCC Input 4.5V P.G. Zout = 50Ω Output Input P.G. Zout = 50Ω D 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Rev.3.00, Jul.15.2005, page 3 of 6 Q Clock Clear Notes: RL CL Unit MHz ns Condition CL = 15 pF, RL = 2 kΩ HD74LS273 Waveforms 1 tTLH Data tTHL 90% 1.3 V 3V 90% 1.3 V 1.3 V 10% 10% tsu 0V tsu th tTLH th tTHL 3V 90% 90% 1.3 V 1.3 V 10% Clock 1.3 V 10% tw 0V tw tPHL tPLH VOH Q 1.3 V 1.3 V VOL Notes: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, Clock input; PRR = 1 MHz, duty cycle 50% Data input; PRR = 500 kHz, duty cycle 50% Waveforms 2 tTLH tTHL Clear 90% 1.3V 3V 90% 1.3V 10% 10% tw 0V tw Clock tTHL tTLH 90% 1.3V 90% 1.3V 10% 10% 3V 0V tPHL tw Q 1.3V tPLH VOH 1.3V VOL Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz. Rev.3.00, Jul.15.2005, page 4 of 6 HD74LS273 Package Dimensions JEITA Package Code P-DIP20-6.3x24.5-2.54 RENESAS Code PRDP0020AC-B Previous Code DP-20NEV MASS[Typ.] 1.26g D 11 E 20 1 10 b3 0.89 Z Dimension in Millimeters Min Nom Max A Reference Symbol A1 e D 24.50 E 6.30 L θ c e1 A1 0.51 b p 0.40 b 3 JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B *1 Previous Code FP-20DAV 0.48 0.56 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.27 L 2.54 MASS[Typ.] 0.31g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 20 7.00 1.30 Z ( Ni/Pd/Au plating ) 25.40 5.08 A bp e 7.62 1 11 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Z e *3 bp Nom Max D 12.60 13.0 E 5.50 A2 10 1 A1 x Dimension in Millimeters Min M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 2.20 A L1 bp b1 c A c 1 θ 0° HE A1 θ y L Detail F e 8° 1.27 x 0.12 y 0.15 0.80 Z 0.50 L L Rev.3.00, Jul.15.2005, page 5 of 6 7.50 1 0.70 1.15 0.90 HD74LS273 JEITA Package Code P-SOP20-7.5x12.8-1.27 RENESAS Code PRSP0020DC-A *1 Previous Code FP-20DBV MASS[Typ.] 0.52g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET. 11 HE c *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 12.80 13.2 E 7.50 A2 10 1 Z e *3 bp x A1 M 0.10 0.20 0.30 0.34 0.40 0.46 0.20 0.25 0.30 10.40 10.65 A L1 2.65 bp b1 c A c A1 θ L y 1 θ 0° HE 10.00 8° 1.27 e x 0.12 y 0.15 0.935 Z Detail F L L Rev.3.00, Jul.15.2005, page 6 of 6 0.40 1 0.70 1.45 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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