HD74SSTV16857B
1:1 14-bit SSTL_2 Registered Buffer
REJ03D0023–0100Z
(Previous ADE-205-712 (Z))
Rev.1.00
Jun.03.2003
Description
The HD74SSTV16857B is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and
LVCMOS reset (RESET)) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK, CLK
CLK) and the RESET.
RESET Data is
triggered on the positive edge of the positive
itive clock (CLK), and the negative clock (CLK)
CLK) must be used to
CLK
maintain noise margins. When RESET is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
Features
• Supports LVCMOS reset (RESET)
RESET) input / SSTL_2 data (D) inputs and CLK input
RESET
• Differential SSTL_2 (Stub series terminated logic) CLK signal
• Flow through architecture optimizes PCB layout
• Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping
Abbreviation (Quantity)
HD74SSTV16857BTEL
TSSOP-48 pin
TTP-48DBV
T
EL (1,000 pcs / Reel)
HD74SSTV16857BNEL
TVSOP-48 pin
TTP-48DEV
N
EL (1,000 pcs / Reel)
Note: Please consult the sales office for the above package availability.
Rev.1.00, Jun.03.2003, page 1 of 16
HD74SSTV16857B
Function Table
Inputs
Output Q
RESET
CLK
CLK
D
L
X
X
X
L
H
↓
↑
H
H
H
↓
↑
L
L
H
L or H
H or L
X
Q0 *1
H:
L:
X:
↑:
↓:
Note:
High level
Low level
Immaterial
Low to high transition
High to low transition
eady state input conditions were established.
1. Output level before the indicated steady
Rev.1.00, Jun.03.2003, page 2 of 16
HD74SSTV16857B
Pin Arrangement
Q1 1
48 D1
Q2 2
47 D2
GND 3
46 GND
V DDQ 4
45 V CC
Q3 5
44 D3
Q4 6
43 D4
Q5 7
42 D5
GND 8
41 D6
V DDQ 9
40 D7
Q6 10
39 CLK
Q7 11
38 CLK
V DDQ 12
37 V CC
GND 13
36 GND
Q8 14
35 V REF
Q9 15
RESE
34 RESET
V DDQ 16
33 D8
GND 17
32 D9
Q10 18
31 D10
Q11 19
30 D11
Q12 20
29 D12
V DDQ 21
28 V CC
GND 22
27 GND
Q13 23
26 D13
Q14 24
25 D14
(Top view)
Rev.1.00, Jun.03.2003, page 3 of 16
HD74SSTV16857B
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
VCC or VDDQ
–0.5 to 3.6
V
VI
–0.5 to VDDQ+0.5
V
VO
–0.5 to VDDQ+0.5
V
Input clamp current
IIK
±50
mA
VI < 0 or VI > VCC
Output clamp current
IOK
±50
mA
VO < 0 or VO > VDDQ
Continuous output current
IO
±50
mA
VO = 0 to VDDQ
VCC, VDDQ or GND current / pin
ICC, IDDQ or IGND ±100
mA
Package thermal impedance
θJA
115
°C / W
Storage temperature
Tstg
–65 to +150
°C
Supply voltage
Input voltage
*1
Output voltage
Notes:
*1, 2
Conditions
TSSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and
d functional operation of the device at these or
any other conditions beyond those indicated under
der “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This current will flow only when the output is in the high state and VO > VDDQ.
Rev.1.00, Jun.03.2003, page 4 of 16
HD74SSTV16857B
Recommended Operating Conditions
Item
Symbol Min
Typ
Max
Unit Conditions
Supply voltage
VCC
VDDQ
2.5
2.7
V
Output supply voltage
VDDQ
2.3
2.5
2.7
V
Reference voltage
VREF
1.15
1.25
1.35
V
Termination voltage
VTT
VREF–40 mV
VREF
VREF+40 mV
V
Input voltage
VI
0
—
VCC
V
AC high level input voltage
VIH
VREF+310 mV —
—
V
D
AC low level input voltage
VIL
—
VREF–310 mV V
D
DC high level input voltage
VIH
VREF+150 mV —
—
V
D
DC low level input voltage
VIL
—
—
VREF–150 mV V
D
High level input voltage
VIH
1.7
—
VDDQ+0.3
V
RESET
Low level input voltage
VIL
–0.3
—
0.7
V
RESET
0.97
—
1.53
V
CLK, CLK
360
—
—
mV
CLK, CLK
Differential (Common mode range) VCMR
input voltage (Minimum peak to
VPP
—
VREF = 0.5
× VDDQ
peak input)
High level output current
IOH
—
—
–20
mA
Low level output current
IOL
—
—
20
mA
m
Operating temperature
Ta
0
—
70
°C
Note: The RESET input of the device must be held at VDDQ or GND to ensure proper device operation.
The differential inputs must not be floating, unless RESET is low.
Rev.1.00, Jun.03.2003, page 5 of 16
HD74SSTV16857B
Logic Diagram
*1
RESET
34
CLK
CLK
38
39
D1
VREF
48
35
1D
C1
R
To thirteen other channels
Note:
1.
RESET input gate is connected to VDDQ.
Rev.1.00, Jun.03.2003, page 6 of 16
1
Q1
HD74SSTV16857B
Electrical Characteristics
Item
Symbol VCC (V)
Min
Typ
Max
Unit Test Conditions
Input diode voltage
VIK
2.3
—
—
–1.2
V
IIN = –18 mA
Output voltage
VOH
2.3 to 2.7 VCC–0.2 —
—
V
IOH = –100 µA
2.3
—
VDDQ
IOH = –16 mA
2.3 to 2.7 —
—
0.2
IOL = 100 µA
2.3
—
0.35
IOL = 16 mA
VOL
Input current
(All inputs)
IIN
1.95
0
2.7
—
—
±5
µA
VIN = 2.7 V or 0
2.7
—
25
45
mA
VIN = VIH(AC) or VIL(AC), IO =
0
ICC (stdy) 2.7
—
—
10
µA
RESET = GND
Quiescent supply current
ICC
Standby current
*2
*2
2.7
—
38
45
µA/ RESET = VCC,
clock VI = VIH(AC) or VIL(AC),
MHz CLK and CLK switching 50%
duty cycle
Dynamic operating per each ICCD *2
data input
2.7
—
11
15
µA/
clock
MHz
/
data
input
RESET = VCC,
VI = VIH(AC) or VIL(AC),
Dynamic operating clock only ICCD
Output high *3
Output low
rOH
*3
rOH – rOL each
*3
separate bit
Input
capacitance
Notes: 1.
2.
3.
4.
2.3 to 2.7 7
—
20 *4
Ω
IOH = –20 mA
*4
Ω
IOL = 20 mA
IO = 20 mA, Ta = 25°C
rOL
2.3 to 2.7 7
—
20
rO(∆)
2.5
—
4
Ω
pF
Data inputs CIN
2.5 *1
—
CLK and CLK switching 50%
duty cycle. One data input
switching at half clock
frequency, 50% duty cycle.
2.5
—
3.5
CLK and CLK
2.5
—
3.5
VCMR = 1.25 V, VPP = 360 mV
VI = VREF±310 mV
RESET
—
3.0
—
VI = VCC or GND
All typical values are at VCC = 2.5 V, Ta = 25°C.
Total ICC (max) = ICC + {ICCD (clock)
(clock)×f(clock)} + {ICCD (Data)×1/2f(clock)×14}
This is effective in the case that it did terminate by resistance.
See figure. 1, 2.
Rev.1.00, Jun.03.2003, page 7 of 16
HD74SSTV16857B
Switching Characteristics
Item
Symbol
Clock frequency
*1
Setup time
Fast slew rate
Slow slew rate
Hold time
Fast slew rate
Slow slew rate
*4, 6
Unit
Test Condition
Min
Max
fclock
—
200
MHz
tsu
0.75
—
ns
Data before CLK↑, CLK↓
0.9
—
0.75
—
ns
Data after CLK↑, CLK↓
0.9
—
*5, 6
*4, 6
VCC = 2.5 ± 0.2 V
th
*5, 6
Differential inputs
active time
tact
22
—
ns
Data inputs must be low
after RESET high.
Differential inputs
inactive time
tinact
22
—
ns
Data and clock inputs
must be held at valid
levels (not floating) after
RESET low.
Pulse width
tw
2.5
—
ns
CLK, CLK “H” or “L”
tSL
1
4
volt/ns
Output slew
*3
(CL = 30 pF, RL = 50 Ω, VREF = VTT = VDDQ × 0.5)
Item
Symbol
Maximum clock frequency
Propagation delay time
*2
VCC = 2.5±0.2 V
Unit
Min
Typ
Max
fmax
200
—
—
MHz
tPLH, tPHL
1.1
—
2.8
ns
tPHL
—
—
5.0
FROM
(Input)
TO
(Output)
CLK, CLK Q
RESET
Q
Notes: 1. Although the clock is differential, all timing is relative to CLK going high and CLK going low.
2. This timing relationship is specified into test lo
load (see waveforms – 3, 4) with all of the outputs
switching.
3. Assumes into an equivalent, distributed lo
load to the address net structure defined in the
application information provided in this specification.
4. For data signal input slew rate ≥ 1 V/ns.
5. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns.
6. CLK, CLK signals input slew rates are ≥ 1 V/ns.
Rev.1.00, Jun.03.2003, page 8 of 16
HD74SSTV16857B
Test Circuit
VTT
*2
50 Ω
Test point
*1
C L = 30 pF
Notes:
1.
2.
CL includes probe and jig capacitance.
VTT = VREF = VDDQ × 0.5
Waveforms – 1
LVCMOS
RESET
Input
VCC
VCC /2
VCC /2
0V
tinact
tact
*1
I CC
90 %
10 %
Rev.1.00, Jun.03.2003, page 9 of 16
I CCH
I CCL
HD74SSTV16857B
Waveforms – 2
tw
VIH
Input
VREF
VREF
VIL
Timing input
VCMR
tsu
VPP
th
VIH
Input
VREF
VREF
VIL
Waveforms – 3
Timing input
VCMR
VCMR
tPLH
VPP
tPHL
V OH
Output
VTT
VTT
VOL
Rev.1.00, Jun.03.2003, page 10 of 16
HD74SSTV16857B
Waveforms – 4
VIH
LVCMOS
RESET
Input
VCC /2
VIL
tPHL
VOH
Output
VTT
VOL
Notes:
1.
2.
3.
4.
5.
6.
7.
ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
All input pulses are supplied by generators
s having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω,, input slew rate = 1 V/ns ±20% (unless otherwise specified).
The outputs are measured one at a time with one transition per measurement.
VTT = VREF = VDDQ/2
VIH = VREF+310 mV (AC voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
VIL = VREF–310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
tPLH and tPHL are the same as tpd
Rev.1.00, Jun.03.2003, page 11 of 16
HD74SSTV16857B
Application Data
• Pull-down
150
Current (Amps)
120
90
60
Min
Max
30
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.0
2.5
3.0
Voltage (V)
Figure. 1
• Pull-up
Voltage (V)
0.0
0
0.5
1.0
1.5
Min
Max
Current (Amps)
-30
-60
-90
-120
-150
Figure. 2
Rev.1.00, Jun.03.2003, page 12 of 16
HD74SSTV16857B
Curve Data
Voltage (V)
Pull-down
Pull-up
I (mA)
I (mA)
I (mA)
I (mA)
Min
Max
Min
Max
0
0
0
0
0
0.1
8
12.5
–8
–10
0.2
15.5
24
–16
–21
0.3
23
36
–23.5
–31
0.4
29.5
47
–30.5
–41
0.5
35.5
57.5
–37
–50.5
0.6
41
67.5
–43.5
–59.5
0.7
46
77
–49
–68
0.8
51
86
–54.5
–77
0.9
55
95
–59.5
–85
1
58
103
–64
–92
1.1
61
110
–67.5
–99.5
1.2
63
116
–71
–106
1.3
64.5
122
–73.5
–112
1.4
65.5
126
–75.5
–118
1.5
66
130
–77
–123
1.6
66.5
132
–78
–127
1.7
67
133
–79
–131
1.8
67
134
–80
–134
1.9
67
134
–81
–137
2
67.5
134
–82
–139
2.1
67.5
135
–83
–141
2.2
68
135
–83.5
–142
2.3
68
135
–84.5
–144
2.4
68
135
–85
–145
2.5
68
135
–86
–147
2.6
68
135
–86.5
–148
2.7
68
135
–87
–149
Rev.1.00, Jun.03.2003, page 13 of 16
HD74SSTV16857B
Package Dimensions
As of January, 2003
12.5
12.7 Max
25
6.10
48
Unit: mm
*0.19 ± 0.05
0.50
24
0.08 M
1.0
8.10 ± 0.20
0.10
*Ni/Pd/Au plating
Rev.1.00, Jun.03.2003, page 14 of 16
0˚ – 8˚
*0.15 ± 0.05
1.20 Max
0.65 Max
0.10 ± 0.05
1
0.50 ± 0.1
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-48DBV
—
—
0.20 g
HD74SSTV16857B
As of January, 2003
9.70
9.90 Max
25
4.40
48
Unit: mm
*0.18 ± 0.05
0.40
24
0.07 M
6.40 ± 0.20
1.00
0.08
*Ni/Pd/Au plating
Rev.1.00, Jun.03.2003, page 15 of 16
*0.15 ± 0.05
1.20 Max
0.40 Max
0.10 ± 0.05
1
0˚ – 8˚
0.50 ± 0.10
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-48DEV
—
—
0.12 g
HD74SSTV16857B
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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