HI20201 10-Bit, 160 MSPS, Ultra High Speed D/A Converter August 1997 Features Description • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 160MHz The HI20201 is a 160MHz ultra high speed D/A converter. The converter is based on an R/2R switched current source architecture that includes an input data register with a complement feature and is Emitter Coupled Logic (ECL) compatible. • Resolution (HI20201) . . . . . . . . . . . . . . . . . . . . . . . 10-Bit • Differential Linearity Error . . . . . . . . . . . . . . . . 0.5 LSB • Low Glitch Noise The HI20201 is available in a commercial temperature range and offered in a 28 lead plastic SOIC (300 mil) and a 28 lead plastic DIP package. • Analog Multiplying Function • Low Power Consumption . . . . . . . . . . . . . . . . . .420mW Ordering Information • Evaluation Board Available • Direct Replacement for Sony CX20201-1, CX20202-1 PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. Applications HI20201JCB -20 to 75 28 Ld SOIC M28.3A-S • Wireless Communications HI20201JCP -20 to 75 28 Ld PDIP E28.6A-S HI20201-EV 25 • Signal Reconstruction Evaluation Kit • Direct Digital Synthesis • High Definition Video Systems • Digital Measurement Systems • Radar Pinout HI20201 (PDIP, SOIC) TOP VIEW (MSB) D9 1 28 AVSS D8 2 27 VREF D7 3 26 AVEE D6 4 25 NC D5 5 24 NC D4 6 23 NC D3 7 22 NC D2 8 21 NC D1 9 20 IOUT 19 NC (LSB) D0 10 NC 11 18 AVSS NC 12 17 DVSS CLK 13 16 COMPL CLK 14 15 DVEE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 10-1197 File Number 3581.5 HI20201 Typical Application Circuit HI20201 DIGITAL DATA (ECL) D9 D9 (MSB) (1) D8 D8 (2) D7 D7 (3) D6 D6 (4) D5 D5 (5) D4 D4 (6) D3 D3 (7) D2 D2 (8) D1 D1 (9) D0 D0 (LSB) (10) . (28) AVSS 1.5kΩ 1kΩ (27) VREF ~2.7V 2kΩ (26) AVEE TL431CP -5.2V 0.047µF 1.0µF 75Ω COAX CABLE (11) (20) IOUT (12) D/A OUT (18, 19, 21-25) NC 82Ω 82Ω CLK CLK (13) (17) DVSS -1.3V CLK (14) (16) COMPL 131Ω (15) DVEE 131Ω 1.0µF 0.047µF -5.2V 3.6kΩ -5.2V Functional Block Diagram (LSB) D0 D1 6 LSBs CURRENT CELLS D2 D3 D4 D5 R/2R NET/WORK INPUT 8-BIT REGISTER BUFFER 15 15 15 15 15 15 15 15 D6 D7 UPPER 4-BIT ENCODER D8 (MSB) D9 15 SWITCHED CURRENT CELLS IOUT COMPL CLK CLK BIAS CURRENT GENERATOR CLOCK BUFFER 10-1198 VREF HI20201 Absolute Maximum Ratings Thermal Information Digital Supply Voltage DVEE to DVSS . . . . . . . . . . . . . . . . . . . -7.0V Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . -7.0V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 to DVEE V Reference Input Voltage . . . . . . . . . . . . . . . . . . . . . . +0.3 to AVEE V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Recommended Operating Conditions Supply Voltage AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to -5.45V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to +0.05V Digital Input Voltage VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to -0.7V VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.9V to -1.6V Reference Input Voltage, VREF . . . . . . . . VEE + 0.5V to VEE + 1.4V Load Resistance, RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≥75Ω Output Voltage, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 1.2V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, AVEE = DVEE = -5.2V, AGND = DGND = 0V, RL = ∞, VOUT = -1V HI20201JCB/JCP PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 10 - - Bits SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL fS = 160MHz (End Point) - - ±1.0 LSB Differential Linearity Error, DNL fS = 160MHz - - ±0.50 LSB Offset Error, VOS (Adjustable to Zero) (Note 3) - 7 - LSB Full Scale Error, FSE (Adjustable to Zero) (Note 3) - - ±102 LSB - - 20 mA 160 - - MHz - 15 - pV/s Full Scale Output Current, IFS DYNAMIC CHARACTERISTICS Throughput Rate See Figure 11 Glitch Energy, GE ROUT = 75Ω REFERENCE INPUT Voltage Reference Input Range With Respect to AVEE +0.5 - +1.4 V Reference Input Current VREF = -4.58V -0.1 -0.4 -3.0 µA Voltage Reference to Output Small Signal Bandwidth -3dB point 1VP-P Input - 14.0 - MHz Output Rise Time, tr RLOAD = 75Ω - 1.5 - ns Output Fall Time, tf RLOAD = 75Ω - 1.5 - ns -1.0 -0.89 DIGITAL INPUTS Input Logic High Voltage, VIH (Note 2) Input Logic Low Voltage, VIL (Note 2) Input Logic Current, IIL , IIH (For D9 thru D6, COMPL) VIH = -0.89V, VIL = -1.75V (Note 2) Input Logic Current, IIL , IIH (For D5 thru D0) VIH = -0.89V, VIL = -1.75V (Note 2) V -1.75 -1.6 V 0.1 1.5 6.0 µA 0.1 0.75 3.0 µA - - ns TIMING CHARACTERISTICS Data Setup Time, tSU See Figure 11 5 Data Hold Time, tHLD See Figure 11 1 - - ns Propagation Delay Time, tPD See Figure 11 - 3.8 - ns Settling Time, tSET (to 1/2 LSB) See Figure 11 - 5.2 - ns 10-1199 HI20201 TA = 25oC, AVEE = DVEE = -5.2V, AGND = DGND = 0V, RL = ∞, VOUT = -1V (Continued) Electrical Specifications HI20201JCB/JCP PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER SUPPLY CHARACTERISITICS IEE Power Dissipation 75Ω load -60 -75 -90 mA - 420 470 mW NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. Excludes error due to reference drift. 4. Electrical specifications guaranteed only under the stated operating conditions. Timing Diagram CLK CLK DATA tSU tHD N N+1 tD tD 0V 90% D/A OUT N+1 N 50% 10% -1V tf tr FIGURE 1. LADDER SETTLING TIME FULL POWER BANDWIDTH (LS) Pin Descriptions 28 PIN SOIC PIN NAME PIN DESCRIPTION 1-10 D0 (LSB)-D9 (MSB) 11, 12, 19, 21- 25 NC No Connect, not used. 13 CLK Negative Differential Clock Input. 14 CLK Positive Differential Clock Input 15 DVEE 16 COMPL 17 DVSS Digital Ground. 18 AVSS Analog Ground. 20 IOUT Current Output Pin. 26 AVEE Analog Supply -4.75V to -7V. 27 VREF Input Reference Voltage used to set the output full scale range. 28 AVSS Analog Ground. Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 9, the Most Significant Bit. Digital (ECL) Power Supply -4.75V to -7V. Data Complement Pin. When set to a (ECL) logic High the input data is complemented in the input buffer. When cleared to a (ECL) logic Low the input data is not complemented. 10-1200 HI20201 FULL SCALE OUTPUT VOLTAGE (V) -2.0 FULL SCALE OUTPUT VOLTAGE (RELATIVE VALUE) VO(FS)/(VO(FS) AT TA = 25oC) Typical Performance Curves TA = 25oC, VEE = -5.2V LINEAR AREA RL = 10kΩ -1.0 0 0.5 RL = 75Ω 1.0 VREF - VEE (V) 1.5 FIGURE 2. VO(FS) RATIO vs (VREF - VEE) 1.05 RL = 10kΩ 1.00 RL = 75Ω 0.95 -20 0 20 40 60 AMBIENT TEMPERATURE (oC) 80 FIGURE 3. FULL SCALE OUTPUT VOLTAGE vs AMBIENT TEMPERATURE 0 10.0 fCLK = 100MHz PHASE -90 -10 PHASE (DEGREE) GAIN (dB) 0 -180 -20 10K 100K 1M 10M MULTIPLYING INPUT SIGNAL FREQUENCY (Hz) GLITCH ENERGY (pV/s) GAIN 6.0 4.0 2.0 100M FIGURE 4. OUTPUT CHARACTERISTICS vs MULTIPLYING INPUT SIGNAL FREQUENCY 8.0 -50 0 50 CASE TEMPERATURE (oC) 100 FIGURE 5. GLITCH ENERGY vs CASE TEMPERATURE (FULL SCALE - 1023mV) 10-1201 HI20201 Detailed Description The HI20201 is a 10-bit, current output D/A converter. The DAC can run at 160MHz and is ECL compatible. The architecture is segmented/R2R combination to reduce glitch and improve linearity. Architecture The HI20201 is a combined R2R/segmented current source design. The 6 least significant bits of the converter are derived by a traditional R2R network to binary weight the 1mA current sources. The upper 4 most significant bits are implemented as segmented or thermometer encoded current sources. The encoder converts the incoming 4 bits to 15 control lines to enable the most significant current sources. The thermometer encoder will convert binary to individual control lines. See Table 1. 01 1111 1111 to 10 0000 0000. But in the HI20201 the glitch is moved to the 00 0001 1111 to 11 1110 0000 transition. This is achieved by the split R2R/segmented current source architecture. This decreases the amount of current switching at any one time and makes the glitch practically constant over the entire output range. By making the glitch a constant size over the entire output range this effectively integrates this error out of the end application. In measuring the output glitch of the HI20201 the output is terminated into a 75Ω load. The glitch is measured at the major carry’s throughout the DAC’s output range. HI20201 TABLE 1. THERMOMETER ENCODER 34MHz LOW PASS FILTER (20) IOUT MSB BIT 8 BIT 7 BIT 6 THERMOMETER CODE 1 = ON, 0 = OFF, I15 - I0 0 0 0 0 000 0000 0000 0000 0 0 0 1 000 0000 0000 0001 0 0 1 0 000 0000 0000 0011 0 0 1 1 000 0000 0000 0111 0 1 0 0 000 0000 0000 1111 0 1 0 1 000 0000 0001 1111 0 1 1 0 000 0000 0011 1111 0 1 1 1 000 0000 0111 1111 1 0 0 0 000 0000 1111 1111 1 0 0 1 000 0001 1111 1111 1 0 1 0 000 0011 1111 1111 1 0 1 1 000 0111 1111 1111 1 1 0 0 000 1111 1111 1111 1 1 0 1 001 1111 1111 1111 1 1 1 0 011 1111 1111 1111 1 1 1 1 111 1111 1111 1111 SCOPE 50Ω 75Ω FIGURE 6. HI20201 GLITCH TEST CIRCUIT The glitch energy is calculated by measuring the area under the voltage-time curve. Figure 7 shows the area considered as glitch when changing the DAC output. Units are typically specified in picoVolt/seconds (pV/s). A (mV) The architecture of the HI20201 is designed to minimize glitch while providing a manufacturable 10-bit design that does not require laser trimming to achieve good linearity. GLITCH ENERGY = (a x t)/2 t (ns) FIGURE 7. GLITCH ENERGY Glitch Glitch is caused by the time skew between bits of the incoming digital data. Typically the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time (TTL designs). In an ECL system where the logic levels switch from one non-saturated level to another, the switching times can be considered close to symmetrical. This helps to reduce glitch in the D/A. Unequal delay paths through the device can also cause one current source to change before another. To minimize this the Intersil HI20201 employs an internal register, just prior to the current sources, that is updated on the clock edge. Lastly the worst case glitch usually happens at the major transition i.e., Setting Full Scale The full scale output voltage is set by the Voltage Reference pin (27). The output voltage performance will vary as shown in Figure 2. The output structure of the HI20201 can handle down to a 75Ω load effectively. To drive a 50Ω load Figure 8 is suggested. Note the equivalent output load is ~75Ω. 10-1202 HI20201 Clock Phase Relationship The HI20201 is designed to be operated at very high speed (i.e., 160MHz). The clock lines should be driven with ECL100K logic for full performance. Any external data drivers and clock drivers should be terminated with 50Ω to minimize reflections and ringing. HI20201 39Ω (20) IOUT 50Ω COAX CABLE D/A OUT 100Ω Internal Data Register (18, 19, 21-25) NC The HI20201 incorporates a data register as shown in the Functional Block Diagram. This register is updated on the rising edge of the CLK line. The state of the Complement bit (COMPL) will determine the data coding. See Table 2. FIGURE 8. HI20201 DRIVING A 50Ω LOAD Variable Attenuator Capability TABLE 2. INPUT CODING TABLE The HI20201 can be used in a multiplying mode with a variable frequency input on the VREF pin. In order for the part to operate correctly a DC bias must be applied and the incoming AC signal should be coupled to the VREF pin. See Figure 13 for the application circuit. The user must first adjust the DC reference voltage. The incoming signal must be attenuated so as not to exceed the maximum (+1.4V) and minimum (+0.5V) reference input. The typical output Small Signal Bandwidth is 14MHz. OUTPUT CODE INPUT CODE COMPL = 1 COMPL = 0 00 0000 0000 0 -1 10 0000 0000 -0.5 -0.5 11 1111 1111 -1 0 Integral Linearity Thermal Considerations The Integral Linearity is measured using the End Point method. In the End Point method the gain is adjusted. A line is then established from the zero point to the end point or Full Scale of the converter. All codes along the transfer curve must fall within an error band of 1 LSB of the line. Figure 10 shows the linearity test circuit. The temperature coefficient of the full scale output voltage and zero offset voltage depend on the load resistance connected to IOUT . The larger the load resistor, the better (i.e., smaller) the temperature coefficient of the D/A. See Figure 3 in the performance curves section. Differential Linearity Digital switching noise must be minimized to guarantee system specifications. Since 1 LSB corresponds to 1mV for 10-bit resolution, care must be taken in the layout of a circuit board. The Differential Linearity is the difference from the ideal step. To guarantee monotonicity a maximum of 1 LSB differential error is allowed. When more than 1 LSB is specified the converter is considered to be missing codes. Figure 10 shows the linearity test circuit. Noise Reduction Separate ground planes should be used for DVSS and AVSS . They should be connected back at the power supply. Separate power planes should be used for DVEE and AVEE . They should be decoupled with a 1µF tantalum capacitor and a ceramic 0.047µF capacitor positioned as close to the body of the IC as possible. 10-1203 HI20201 Test Circuits a b a b a b a b a b a b a b a b a b a b I2 S11 a b -0.89V -1.75V S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 -0.89V OR -1.75V a S14 I3 b a S15 I4 b -0.89V 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 a S20 b S16 a b a b I1 I6 5.2V 4.56V 1mA S19 a b V1 S17 a S12 13 b a S13 14 b a b 16 I5 S18 a b 15 5.2V -1.75V FIGURE 9. CURRENT CONSUMPTION, INPUT CURRENT AND OUTPUT RESISTANCE LINEARITY ERRORS ARE MEASURED AS FOLLOWS “1” S1 S2 “0” 0.89V S3 1.75V S4 S5 S6 10-BIT DATA S7 S8 S9 S10 1.3V 1 SHOT CLK 1 28 2 27 3 26 † 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 S2 0 0 0 S3 0 0 0 1 1 1 10K 5.2V 4 S1 0 0 0 D/A OUT V0 5.2V •••• •••• •••• •••• • • • •••• S9 0 0 1 S10 0 1 0 1 1 D/A OUT V0 V1 V2 • • • V1023 INTEGRAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR V0 V1 V2 V4 V8 V16 V32 V64 V128 V192 • • • V960 V1023 V1 - V0 V2 - V1 V4 - V3 V8 - V7 V16 - V15 V32 - V31 V64 - V63 V128 - V127 V192 - V191 • • • V960 - V959 Error at individual measurement points are calculated according to the following definition. † Adjust so that the full scale of DC voltage at pin 20 becomes (V1023 - V0)/1023 = V0(FS)/1023 ≡ 1 LSB. 1.023V, that is, to satisfy VO - V1023 = 1.023V. FIGURE 10. DIFFERENTIAL LINEARITY ERROR AND LINEARITY ERROR 10-1204 HI20201 Test Circuits (Continued) 1/ HD100151 6 B 10kΩ D Q Q 131 1 82 82 -5.2V CLKF 131 -5.2V TO PG -1.3V 50Ω 1 28 MSB 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 OUT 20 -5.2V C 50Ω 39 HD100116 1 82 CLKF 470 131 82 82 DL 10 LSB 19 11 18 12 17 13 CLK 16 14 CLK 15 TO SCOPE 100 A 1 131 -1.3V 131 -5.2V -5.2V 131 DL: Delay line Capacitors are 0.047µF ceramic chip capacitors unless otherwise specified. FIGURE 11. MAXIMUM CONVERSION RATE, RISE TIME, FALL TIME, PROPAGATION DELAY, SETUP TIME, HOLD TIME AND SETTLING TIME CIRCUIT Measuring Settling Time Settling time is measured as follows. The relationship between V and V0(FS) as shown in the D/A output waveform in Figure 12 is expressed as V = V0(FS) (1 - e-tτ). The settling time for respective accuracy of 10, 9 and 8-bit is specified as τ V = 0.9995 V0(FS) V = 0.999 V0(FS) V = 0.999 V0(FS) which results in the following: tS = 7.60τ tS = 6.93τ tS = 6.24τ for 10-bit, for 9-bit, and for 8-bit, V Rise time (tr) and fall time (tf) are defined as the time interval to slew from 10% to 90% of full scale voltage (V0(FS)): V = 0.1 V0(FS) V = 0.9 V0(FS) τ FIGURE 12. D/A OUTPUT WAVEFORM and calculated as tr = tf = 2.20τ. The settling time is obtained by combining these expressions: tS = 3.45tr tS = 3.15tr tS = 6.24tr V0(FS) = 1V for 10-bit, for 9-bit, and for 8-bit 10-1205 HI20201 Test Circuits (Continued) Adjust so that the voltage at point B becomes -1V with no AC input. “1” 10kΩ 1 28 2 27 0.1µF OSC 0.047µ 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 CLK 13 16 CLK 14 15 51 A -5.2V B TO SCOPE A GND -5.2V FIGURE 13A. VEE -0.62V WAVEFORM AT POINT A VEE -0.31V FIGURE 13B. 1VP-P AT 1MHz -1V WAVEFORM AT POINT B FIGURE 13C. FIGURE 13. MULTIPLYING BANDWIDTH 10-1206 D GND HI20201 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 10-1207 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029