HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS HMS81C4x60 User’s Manual (Ver. 1.1) Version 1.1 Published by MCU Application Team Heung-il Bae(hibae@hynix.com), Byoung-jin Lim( bjinlim@hynix.com) 2001 Hynix Semiconductor Inc. All rights reserved. Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed at address directory. Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. HMS81C4x60 HMS81C4x60 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION 1. OVERVIEW 1.1 Description The HMS81C4x60 is an advanced CMOS 8-bit microcontroller with 60K bytes of ROM. This is one of the HMS800 family. This is a powerful microcontroller which provides a high flexibility and cost effective solution to many TV applications. The HMS81C4x60 provides following standard features: 60K bytes of ROM, 1024 bytes of RAM, 8/16-bit timer/counter, onchip PLL oscillator and clock circuitry. In addition, there are other package types, HMS81C4360(32PDIP), HMS81C4360SK(32SKDIP), HMS81C4460(42SDIP). This document is explained for the base of HMS81C4x60, the eliminated functions are same as below. Device name ROM Size EPROM Size RAM Size I/O Package HMS81C4260 60K bytes - 1024bytes 31 52SDIP 60K bytes 1024bytes 31 52SDIP HMS87C4260 1.2 Features • 60K Bytes of On-chip Program Memory • 1024 Bytes of On-chip Data RAM • Minimum Instruction Cycle Time - 256ns (NOP operation) • PLL Oscillator for OSD and System Clock - External 4MHz Crystal Input • 31 Programmable I/O pins - 26 Input/Output and 5 Input pins • I2C Bus Interface - Multimaster (2 Pairs interface pins) • A/D Converter - 8-bit × 5 ch • Pulse Width Modulation - 14-bit × 1 ch - 8-bit × 5 ch • Timer - Timer/Counter : 8-bit × 4 ch(16-bit × 2 ch) - Basic interval timer November 2001 Ver 1.1 - Watch Dog Timer • Number of Interrupt Source - 16 Interrupts - 3 External Interrupts • On Screen Display - 512 character fonts pattern - Character Size : 1.0, 1.5, 2.0 times - Character Pixel size : 12 × 10, 12 × 12, 12 × 14, 12 × 16, 16 × 18 - Display Capability : 48 Characters × 16 Lines - Character, Background color : 512 colors, 8 pallet - Special functions : Rounding, Outline, Shadow, Underline, Double scanned line OSD • Buzzer Driving Port - 500Hz ~ 250KHz @4MHz (Duty 50%) • Vertical Blanking Interveral Information capture for EIA-608(Closed Caption) or VPS, etc 1 HMS81C4x60 1.3 Development Tools Note: There are several setting switches in the Emulator. User should read carefully and do setting properly before developing the program. Otherwise, the Emulator may not work properly. The HMS87C4x60 is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM and EPROM programmers. There are two different type programmers such as single type and gang type. For more detail, refer to EPROM Programming chapter. Macro assembler operates under the MSWindows 95/98TM. Please contact sales part of Hynix Semiconductor. 1.4 Ordering Information Device name ROM Size (bytes) RAM size Package Mask ROM version HMS81C4260 60K bytes 1024 bytes 52SDIP OTP ROM version HMS87C4260 60K bytes EPROM (OTP) 1024 bytes 52SDIP Mask ROM version HMS81C4360SK 60K bytes 1024 bytes 32SKDIP OTP ROM version HMS87C4360SK 60K bytes EPROM (OTP) 1024 bytes 32SKDIP Mask ROM version HMS81C4360 60K bytes 1024 bytes 32PDIP OTP ROM version HMS87C4360 60K bytes EPROM (OTP) 1024 bytes 32PDIP Mask ROM version HMS81C4460 60K bytes 1024 bytes 42SDIP OTP ROM version HMS87C4460 60K bytes EPROM (OTP) 1024 bytes 42SDIP 2 November 2001 Ver 1.1 HMS81C4x60 YM YS R Vss Xin Xout Vdd RESET TEST VS HS 2. BLOCK DIAGRAM PLL OSD G B CVBS SCAP D ATA SLICER PRESCALER /BIT R10/AN0 R11/AN1 R12/AN2 ADC R13/AN3 WATCH DOG TIMER R14/AN4 R30/PWM0 R31/PWM1 R32/PWM2 R33/PWM3 R34/PW M 4 R35/PW M 5 CLOCK GENERATION / SYSTEM CONTROLLER PWM R36/BUZ G8MC CORE RAM ( 1024) MASK ROM ( User ROM : 60KB Font ROM : 32KB ) BUZZER REMOCON R4 PORT R40 ~ R43 R3 PORT R30 ~ R37 R2 PORT R20 ~ R25 R1 PORT R10 ~ R14 R0 PORT R00 ~ R07 R40/SCL0 R41/SDA0 R42/S CL1 I2C R43/SDA1 INTERRUPT CONTROLLER R24/EC2 R25/EC3 TIMER R23/INT3 R22/INT2 R21/INT1 R37/TM R1 Figure 2-1 Block Diagram November 2001 Ver 1.1 3 HMS81C4x60 3. PIN ASSIGNMENT R40/SCL0 1 52 R30/PWM0 R41/SDA0 2 51 R31/PWM1 R42/SCL1 3 50 R32/PWM2 R43/SDA1 4 49 R33/PWM3 R04 5 48 R34/PWM4 R05 6 47 R35/PWM5 R06 7 46 R36/BUZ R07 8 45 R37/TMR1 VDD 9 44 TEST R14/AD4 10 HMS81C4260 SCAP 11 52SDIP CVBS 43 VSS 42 YM 12 41 YS VDD 13 40 B VSS 14 39 G R10/AD0 15 38 R R11/AD1 16 37 VDD R12/AD2 17 36 VSS R13/AD3 18 35 XIN HS 19 34 XOUT VS 20 33 RESET R20 21 32 R03 R21/INT1 22 31 R02 R22/INT2 23 30 VDD R23/INT3 24 29 VSS R24/EC2 25 28 R01 26 27 R00 R25/EC3 Figure 3-1 52SDIP 4 November 2001 Ver 1.1 HMS81C4x60 1 42 R31/PWM1 R41/SDA0 2 41 R32/PWM2 R42/SCL1 R40/SCL0 3 40 R33/PWM3 R43/SDA1 4 39 R34PWM4 R04 5 38 R35/PWM5 VDD 6 37 R36/BUZ R14/AD4 7 36 R37/TMR1 SCAP 8 35 TEST 9 34 YM CVBS VDD 10 VSS 11 R10/AD0 HMS81C4460 33 YS 42SDIP 32 B 12 31 G R11/AD1 13 30 R R12/AD2 14 29 XIN R13/AD3 15 28 XOUT HS 16 27 RESET VS 17 26 R03 R21/INT1 18 25 R02 R22/INT2 19 24 R01 R23/INT3 20 23 R00 R24/EC2 21 22 R25/EC3 Figure 3-2 42SDIP November 2001 Ver 1.1 5 HMS81C4x60 1 32 R33/PWM3 R41/SDA0 2 31 R34/PWM4 R42/SCL1 R40/SCL0 3 30 R35/PWM5 R43/SDA1 4 29 R37/TMR1 VDD 5 28 TEST R14/AD4 6 27 YM SCAP 7 26 YS CVBS 8 25 B 24 G VDD 9 VSS HMS81C4360SK 32SKDIP 10 23 R R10/AD0 11 22 XIN R13/AD3 12 21 XOUT HS 13 20 RESET VS 14 19 R02 R21/INT1 15 18 R24/EC2 R22/INT2 16 17 R23/INT3 Figure 3-3 32SKDIP 1 32 R34PWM4 R41/SDA0 2 31 R35PWM5 R42/SCL1 3 30 R37/TMR1 R43/SDA1 R40/SCL0 4 29 TEST VDD 5 28 YM R14/AD4 6 27 YS SCAP 7 26 B CVBS 8 HMS81C4360 25 G VDD 9 32PDIP 24 R VSS 10 23 XIN R10/AD0 11 22 XOUT R11/AD1 12 21 RESET R12/AD2 13 20 R02 R13/AD3 14 19 R24/EC2 HS 15 18 R23/INT3 VS 16 17 R21/INT1 Figure 3-4 32PDIP 6 November 2001 Ver 1.1 HMS81C4x60 4. PACKAGE DIAGRAM 52 27 13.97 15.24 0.25 0.25 HYNIX HMS81C4260 0 ~ 15 26 1 0.25 4.38 Max. 0.13 0.13 0.76 0.13 3.81 45.97 0.05 UNIT: mm 1.02 0.25 1.778 0.20 32 0.25 3.24 0.13 0.50 Min. 0.47 17 HYNIX HMS81C4360 UNIT: inch TYP 0.600 BSC 16 1 1.665 1.645 0.2 max 0.550 0.530 MIN 0.015 0.140 0.120 0.022 0.015 November 2001 Ver 1.1 0.065 0.045 0.1 BSC 2 0.01 8 0.00 0 ~ 15° 7 HMS81C4x60 42 22 13.97 15.24 0.25 0.25 HYNIX HMS81C4460 0 ~ 15 21 1 0.25 4.38 Max. 0.13 0.13 0.76 0.13 3.81 36.83 0.05 UNIT: mm 1.02 0.25 1.778 0.25 0.20 32 3.24 0.13 0.50 Min. 0.47 0 ~ 15 17 10.16 8.89 0.25 0.25 HYNIX HMS81C4360SK 16 1 0.25 4.38 Max. 0.13 0.13 0.76 0.13 3.81 27.68 0.05 UNIT: mm 1.02 0.25 1.778 0.25 3.24 0.13 0.20 0.50 Min. 0.47 Figure 4-1 Package Diagram 8 November 2001 Ver 1.1 HMS81C4x60 5. PIN FUNCTION R30~R37: R3 is 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. VDD: Supply voltage. VSS: Circuit ground. TEST: Used for shipping inspection of the IC. For normal operation, it should not be connected . In addition, R3 serves the functions of the various following special features. RESET: Reset the MCU. Port pin XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. R00~R07: R0 is an 8-bit bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R30 R31 R32 R33 R34 R35 R10~R14: R1 is a 5-bit read only port. R1 pins 1 or 0 written to the Port Direction Register can be used as inputs. R36 R37 XOUT: Output from the inverting oscillator amplifier. In addition, R1 serves the functions of the various following special features. Port pin R10 R11 R12 R13 R14 Alternate function R40~R43: R4 is a 4-bit open drain I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs. Port pin R40 R41 R42 R43 R20~R25: R2 is a 6-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs. In addition, R2 serves the functions of the various following special features. R21 R22 R23 R24 R25 Alternate function INT1 (External interrupt input 1) INT2 (External interrupt input 2) INT3 (External interrupt input 3) EC2 (Event counter input 2) EC3 (Event counter input 3) PIN NAME PWM0 (Pulse Width Modulation output 0) PWM1 (Pulse Width Modulation output 1) PWM2 (Pulse Width Modulation output 2) PWM3 (Pulse Width Modulation output 3) PWM4 (Pulse Width Modulation output 4) PWM5 (Pulse Width Modulation output 5) with 14bit resolution BUZ (Buzzer output) TMR1 (Timer Interrupt 1) In addition, R4 serves the functions of the various following special features. AD0 (A/D converter input 0) AD1 (A/D converter input 1) AD2 (A/D converter input 2) AD3 (A/D converter input 3) AD4 (A/D converter input 4) Port pin Alternate function Alternate function SCL0 (I2C Clock 0) SDA0 (I2C Data0) SCL1 (I2C Clock 1) SDA1 (I2C Data 1) R,G,B: R,G,B are output port. Each pins controls Red, Green, Blue color control. YM,YS: YM,YS are CMOS output port. Each pins controls Background, Edge control. HS,VS: HS,VS are CMOS input port. Each pins Vertical Sync. input and Horizaltal Sync. inputs. CVBS: CVBS is a CVBS(Composit Video in) signal input pin. Pin No. In/Out Function VDD 9,13,30, 37 - Supply voltage VSS 14,29, 36,43 - Circuit ground Table 5-1 Port Function Description November 2001 Ver 1.1 9 HMS81C4x60 PIN NAME Pin No. In/Out Function TEST 44 I TEST signal input (internal pull up resister) RESET 33 I Reset signal input XIN 35 I Main oscillation input XOUT 34 O Main oscillation output HS 19 I Horisontal Sync. input VS 20 I Vertical Sync. input R 38 O Red signal output G 39 O Green signal output B 40 O Blue signal output YS 41 O Edge signal output YM 42 O Background signal output R30/PWM0 52 I/O 8bit PWM (pull up) R31/PWM1 51 I/O 8bit PWM (pull up) R32/PWM2 50 I/O 8bit PWM (pull up) R33/PWM3 49 I/O R34/PWM4 48 I/O R35/PWM5 47 I/O 14bit PWM R36/BUZ 46 I/O Buzzer (pull up) R37/TMR1 45 I/O Timer Interrupt 1 R40/SCL0 1 I/O I2C Serial clock 0 R41/SDA0 2 I/O R42/SCL1 3 I/O R43/SDA1 4 I/O I2C Serial data 1 R20 21 I/O (pull up) R21/INT1 22 I/O External interrupt input 1 R22/INT2 23 I/O R23/INT3 24 I/O R24/EC2 25 I/O Event counter input 2 R25/EC3 26 I/O Event counter input 3 (pull up) SCAP 11 I Data slicer comparation reference voltage R10/AD0 15 I Analog input 0 R11/AD1 16 I Analog input 1 R12/AD2 17 I R13/AD3 18 I Analog input 3 R14/AD4 10 I Analog input 4 CVBS 12 I Composit video input PWM functions I2C functions (open drain) External interrupt functions A/D conversion functions 8bit PWM (pull up) 8bit PWM I2C Serial data 0 I2C Serial clock 1 External interrupt input 2 (pull up) External interrupt input 3 Analog input 2 Table 5-1 Port Function Description 10 November 2001 Ver 1.1 HMS81C4x60 PIN NAME Pin No. In/Out Function R00 27 I/O (normal I/O, pull up) R01 28 I/O (normal I/O, pull up) R02 31 I/O (normal I/O) R03 32 I/O R04 5 I/O R05 6 I/O (open drain, pull up) R06 7 I/O (open drain, pull up) R07 8 I/O (open drain, pull up) Digital I/O functions (normal I/O, pull up) (open drain, pull up) Table 5-1 Port Function Description November 2001 Ver 1.1 11 HMS81C4x60 6. PORT STRUCTURES XIN, XOUT R14~10, CVBS VDD VDD VDD VDD I Data out Pin Out Enable XIN VDD VSS VSS VSS VSS VSS Data in Data in XOUT Schmitt STOP Û{ Analog in VSS Main frequency clock Analog in R03~R00,R37~R30,HS,VS,YS,YM R07~R04, R43~R40, TEST VDD VDD VDD I/O I/O Data out Pin Out Enable VSS Data in Data out Out Enable VSS Pin VSS Data in Data in Schmitt Û{ Data in Schmitt 12 VSS Û{ November 2001 Ver 1.1 HMS81C4x60 R,G,B SCAP VDD VDD I/O Data In Pin VSS VDD I/O Pin VSS VSS R25~R20, RESET VDD VDD I/O Data out Pin Out Enable VSS VSS Data in Data in Schmitt Û{ November 2001 Ver 1.1 Noise Filter 13 HMS81C4x60 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage ........................................... -0.3 to +6.0 V Maximum current (ΣIOL) .................................... 100 mA Storage Temperature ................................-40 to +125 °C Maximum current (ΣIOH)...................................... 80 mA Voltage on any pin with respect to Ground (VSS) ............................................................... -0.3 to VDD+0.3 Maximum current out of Vss pin.........................160 mA Maximum current into VDD pin ..........................160 mA Maximum current sunk by(IOL per I/O Pin) .........20 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum output current sourced by (IOH per I/O Pin) .................................................................................8 mA 7.2 Recommended Operating Conditions Specifications Parameter Symbol Condition Unit Min. Max. Supply Voltage VDD VDD=4.5~5.5V 4.5 5.5 V Operating Frequency fXIN fXIN=4MHz - 4.0(typical) MHz -10 70 °C Operating Temperature TOPR 7.3 DC Electrical Characteristics (TA=-10~70°C, VDD=4.5~5.5V), Specifications Parameter Symbol Condition Unit Min. Typ. Max. 0.8 VDD - VDD V 0 - 0.12 VDD V VDD - 1 - - V High level input voltage VIH TEST, RESET, Xin, R0, R1, R2, R3, HS, VS Low level input voltage VIL TEST, RESET, Xin, R0, R1, R2, R3,R4 HS, VS High level output voltage VOH IOH = -5mA R0, R1, R2, R3, YS, YM Low level output voltage VOL IOL = 5mA R0, R1, R2, R4 - - 1.0 v Supply current in ACTIVE mode IDD VDD - 40 80 mA pull-up lekage current IRUP VDD = 5.5v, VPIN = 0.4V TEST, R00, R01, R03, R04, R05, R06, R07, R20, R22, R25, R30, R31, R32, R33 R36 -400 µA High input leakage current IIZH VDD = 5.5V, VPIN = VDD All input, I/O pins except XIN 5 µA 14 -1.5 -5 - November 2001 Ver 1.1 HMS81C4x60 Specifications Parameter Symbol Condition Unit Min. Typ. Max. VDD = 5.5V, VPIN = 0V All input, I/O pins except XIN, OSC1 -5 - 5 µA Low input leakage current IIZL RAM data retention voltage VRAM VDD 1.2 - - V Hysterisis Vt+ ~ Vt- TEST, RESET, Xin, HS, VS, R07 ~ R00, R21, R23, R24, R25, R37 ~ R30 1.0 - - V Comparator operating range VrCVBS VDD = 5V CVBS pin 1.2 - 3.5 V Comparator resolution VaCVBS VDD = 5V CVBS pin - - 0.08 V RGB DAC Resolution 1 RGBR1 VDD = 5V No in/out current in R,G,B pin - - 5 % RGB DAC On No in/out current in R,G,B pin RGB DAC Output voltage RGB Voh RGB Vol VRGB Level 0 3/40Vdd Level 1 5/40Vdd Level 2 8/40Vdd Level 3 12/40Vdd Level 4 17/40Vdd Level 5 23/40Vdd Level 6 30/40Vdd Level 7 38/40Vdd V Vohrgb VDD = 5V RGB DAC On Level 7 IOH = -3mA 3.1 3.5 3.9 V Volrgb VDD = 5V RGB DAC On Level 0 IOL = 3mA 0.4 0.6 0.8 V 7.4 AC Characteristics (TA=-10~70°C, VDD=5V±10%, VSS=0V) Specifications Parameter Crystal oscillator Frequency External Clock Pulse Width External Clock Transition Time November 2001 Ver 1.1 Symbol Pins Unit Min. Typ. Max. fXIN XIN 3 4 5 MHz tMCPW XIN 180 - 350 nS tSCPW SCLK 0.5 - tMRCP,tMFCP XIN - - 20 nS tSRCP,tSFCP SCLK - - 20 nS µS 15 HMS81C4x60 Specifications Parameter Symbol Pins Unit Min. Typ. Max. Oscillation Stabilizing Time tST XIN, XOUT - - 20 mS Interrupt Pulse Width tIW INT1~3 2 - - tSYS1 RESET Input Width tRST RESET 8 - - tSYS1 Event Counter Input Pulse Width tECW EC2, EC3 2 - - tSYS1 tREC,tFEC EC2, EC3 - - 20 nS Event Counter Transition Time 1. tSYS is one of 1/fXIN main clock operation mode, tMCPW 1/fXIN tMCPW VDD-0.5V XIN 0.5V tMRCP tIW INT1 ~ 3 tMFCP tIW 0.8VDD 0.2VDD tRST RESET 0.2VDD tECW tECW 0.8VDD EC2, EC3 0.2VDD tREC tFEC Figure 7-1 Timing Chart 16 November 2001 Ver 1.1 HMS81C4x60 7.5 A/D Converter Characteristics (TA=25°C, VDD=5V, VSS=0V) Specifications Parameter Symbol Condition Unit Min. Typ. Max. VAN - VSS-0.3 - VDD+0.3 Overall Accuracy CAIN - - ±1.5 ±2.5 Non Linearity Error NNLE - - ±1.5 ±2.5 NDNLE - - ±1.5 ±2.5 Zero Offset Error NZOE - - ±0.5 ±2.0 Full Scale Error NFSE - - ±0.75 ±1.0 Gain Error NGE - - ±1.5 ±2.0 TCONV fMAIN=4MHz - - 15 Analog Input Voltage Range Differential Non Linearity Error Conversion Time November 2001 Ver 1.1 V LSB µS 17 HMS81C4x60 7.6 Typical Characteristics These graphs and tables are for design guidance only and are not tested or guaranteed. The data is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation In some graphs or tables, the datas presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. IOH−VOH, VDD=5.2V IOH (mA) -16 -14 IOL (mA) 40 -20°C 25°C 70°C IOL−VOL, VDD=5.2V -20°C 25°C 70°C -12 30 -10 -8 20 -6 -4 10 -2 0 2.0 3.0 4.0 5.0 VOH (V) 1.0 VIH2 (V) fMAIN=4MHz Ta=25°C 4 4 3 3 2 2 1 1 0 4 18 4.5 3.0 4.0 VOL (V) VDD−VIH VDD−VIH VIH1 (V) 2.0 5 5.5 VDD 6 (V) Hysterisis fMAIN=4MHz Ta=25°C 0 4 4.5 5 5.5 VDD 6 (V) November 2001 Ver 1.1 HMS81C4x60 VDD−VIL VDD−VIL VIL1 (V) VIL1 (V) fMAIN=4MHz Ta=25°C 3 3 2 2 1 4 4.5 5 VDD 6 (V) 5.5 1 4 Operating Area fMAIN (MHz) Ta= -20~70°C (Main-clock) 6 Hysterisis fMAIN=4MHz Ta=25°C IDD (mA) 60 4.5 5 5.5 VDD 6 (V) Normal Mode (Main opr.) IDD1−VDD Ta=25°C fMAIN=4MHz 5 4 50 3 40 2 30 1 0 4 November 2001 Ver 1.1 4.5 5 5.5 6 VDD 6.5 (V) 20 4 4.5 5 5.5 VDD 6 (V) 19 HMS81C4x60 8. MEMORY ORGANIZATION The GMS81C4x60 has separate address spaces for Program memory, Data Memory and Display memory. Program memory can only be read, not written to. It can be up to 60K bytes of Program memory. Data memory can be read and written to up to 1024 bytes including the stack area. Font memory has prepared 32K bytes for OSD. 8.1 Registers This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. A ACCUMULATOR X X REGISTER Y Y REGISTER SP PCH STACK POINTER PCL PROGRAM COUNTER PSW PROGRAM STATUS WORD Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 00H to FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “FFH” is used. Stack Address (00H ~ FFH) 15 8 7 1 Figure 8-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. 0 SP Hardware fixed Caution: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP Y LDX TXSP Y #0FFH ; SP ← FFH A A Two 8-bit Registers can be used as a “YA” 16-bit Register Figure 8-2 Configuration of YA 16-bit Register Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore). This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. 20 [Carry flag C] November 2001 Ver 1.1 HMS81C4x60 [Zero flag Z] or data transfer is “0” and is cleared by any other result. This flag is set when the result of an arithmetic operation MSB PSW N LSB V G B H I Z C RESET VALUE : 00H CARRY FLAG RECEIVES CARRY OUT NEGATIVE FLAG OVERFLOW FLAG ZERO FLAG SELECT DIRECT PAGE when g=1, page is addressed by RPR INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS BRK FLAG Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] November 2001 Ver 1.1 This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned by RPR register (address 0F3H). It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to “1” when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127 (7FH) or −128 (80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag. 21 HMS81C4x60 At execution of a CALL/TCALL/PCALL 01BC 01BC 01BD 01BD PSW 01BE PCL 01BF PCH 01BE PCL 01BF PCH At execution of RET instruction At acceptance of interrupt Push down 01BC 01BC 01BD Push down At execution of RETI instruction 01BE PCL 01BF PCH Pop up 01BD PSW 01BE PCL 01BF PCH SP before execution 01BF 01BF 01BD 01BC SP after execution 01BD 01BC 01BF 01BF At execution of PUSH instruction PUSH A (X,Y,PSW) At execution of POP instruction POP A (X,Y,PSW) 01BC 01BC 01BD 01BD 01BE 01BF Pop up 0100H Stack depth 01BE A Push down 01BF A SP before execution 01BF 01BE SP after execution 01BE 01BF Pop up 01BFH Figure 8-4 Stack Operation 22 November 2001 Ver 1.1 HMS81C4x60 8.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 60K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Example: Usage of TCALL Figure 8-5 shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6. ; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. 1000H PROGRAM MEMORY FEFFH FF00H FFC0H FFDFH FFE0H FFFFH TCALL AREA PCALL AREA INTERRUPT VECTOR AREA Figure 8-5 Program Memory Map LDA #5 TCALL 15 : : Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7. 1 ;TCALL ADDRESS AREA The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 1, for example, is assigned to location 0FFF8H. The interrupt service locations spaces 2-byte interval: 0FFF6H and 0FFF7H for External Interrupt 2, 0FFE8H and 0FFE9H for External Interrupt 3, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory. Address 0FFE0H Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. ;1BYTE INSTRUCTION ;INSTEAD OF 2 BYTES ;NORMAL CALL Vector Area Memory I2C Bus Interface Interrupt Vector E2 - E4 Basic Interval Timer Interrupt Vector E6 Watchdog Timer Interrupt Vector E8 External Interrupt 3/4 Vector EA Timer/Counter 3 Interrupt Vector EC Timer/Counter 1 Interrupt Vector EE V-Sync Interrupt Vector F0 Slicer Interrupt Vector F2 Timer/Counter 2 Interrupt Vector F4 Timer/Counter 0 Interrupt Vector F6 External Interrupt 2 Vector F8 External Interrupt 1 Vector FA On Screen Display Interrupt Vector FC - FE RESET Vector NOTE: "-" means reserved area. Figure 8-6 Interrupt Vector Area November 2001 Ver 1.1 23 HMS81C4x60 Address Address Program Memory 0FFC0H C1 TCALL 15 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF PCALL Area Memory 0FF00H PCALL Area (256 Bytes) TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF 0FFFFH TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * NOTE: * means that the BRK software interrupt is using same address with TCALL0. Figure 8-7 PCALL and TCALL Memory Area PCALL→ rel TCALL→ n 4F35 4A PCALL 35H TCALL 4 4A 4F Reverse 35 ~ ~ 01001010 ~ ~ ~ ~ 0D125H ~ ~ NEXT PC: 11111111 11010110 FH FH DH 6H 0FF00H 0FF35H 0FFFFH NEXT 0FF00H 25 0FFD7H D1 0FFFFH 24 à 0FFD6H À à : index address November 2001 Ver 1.1 HMS81C4x60 Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW I2C_INT NOT_USED BIT_INT WDT_INT IR_INT TIMER3 TIMER1 VSYNC_INT SLICE_INT T2_INT T0_INT EXT2_INT EXT1_INT OSD_INT NOT_USED RESET ORG 0F000H ;******************************************** ; MAIN PROGRAM * ;******************************************** ; RESET: DI ;Disable All Interrupts CLRG LDX #0 RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; LDX #0FFH ;Stack Pointer Initialize TXSP ; LDM PLLC,#0000_0101b ;16MHz system clock ; LDM R0, #0FFh ;Normal Port 0 LDM R0DIR,#0FFh ;Normal Port Direction : : LDM TM0,#0000_0000B ;timer stop : : CALL VRAM_CLR ;Clear VRAM : : November 2001 Ver 1.1 25 HMS81C4x60 8.3 Data Memory Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM, control registers, Stack, and OSD memory. 0000H in each peripheral section. Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. RAM (192 bytes) 00C0H 0100H Page0 Peripheral Reg. (64 bytes) RAM (256 bytes) Stack area Page1 RAM (256 bytes) Page2 Example; To write at CKCTLR LDM 0200H 0300H RAM (256 bytes) 0400H 0440H Page3 RAM (64 bytes) Page4 NOT USED 0500H 0600H NOT USED Page5 RAM (Slicer RAM) ( 256 Byte) Page6 0700H Not Used 0A00H OSD RAM (192 bytes) 0AC0H 0B00H PageA Peripheral Reg. (32 bytes) OSD RAM (192 bytes) PageB 0BC0H Peripheral Reg. (32 bytes) 0C00H CKCTLR,#05H ;Divide ratio ÷ 8 Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 22. NOT USED 0FFFH Figure 8-8 Data Memory Map User Memory The GMS81C4x60 has 1,024 × 8 bits for the user memory (RAM) except Peripheral Reg. (64 bytes) . Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. Address Symbol R/W Reset Value Addressin g mode 00C0H 00C1H 00C2H 00C3H 00C4H 00C5H 00C6H 00C7H 00C8H 00C9H 00CAH 00CBH 00CCH 00CDH 00CEH 00CFH R0 R0DD R1 R1DD R2 R2DD R3 R3DD R4 R4DD reserved reserved reserved reserved FUNC PLLC R/W W R W R/W W R/W W R/W W W W ???????? 00000000 ???????? ---00000 ???????? --000000 ???????? 00000000 ???????? ----0000 0000000-0000000 byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte byte Table 8-1Control registers More detailed informations of each register are explained 26 November 2001 Ver 1.1 HMS81C4x60 0D0H 0D1H 0D2H 0D3H 0D4H 0D5H 0D6H 0D6H 0D7H 0D8H 0D9H 0DAH 0DBH 0DCH 0DEH 0DFH TM0 TM2 TDR0 TDR1 TDR2 TDR3 BITR CKCTLR WDTR ICAR ICDR ICSR ICCR reserved reserved reserved R/W R/W R/W R/W R/W R/W R W W R/W R/W R/W R/W - -0000000 -0000000 ???????? ???????? ???????? ???????? ???????? --010111 -0111111 00000000 11111111 000100000000000 - byte byte byte, bit byte, bit byte, bit byte, bit byte byte byte byte, bit byte, bit byte, bit byte, bit - 0AD0 0AD1 0AD2 0AD3 0AD4 0AD5 0AD6 0AD7 0AD8 0AD9 0ADA 0ADB 0ADC 0ADD 0ADE 0ADF RED0 RED1 RED2 GREEN0 GREEN1 GREEN2 BLUE0 BLUE1 BLUE2 reserved reserved reserved reserved reserved reserved reserved W W W W W W W W W - ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? - byte, bitbyte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit - 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H 0E8H 0E9H 0EAH 0EBH 0ECH 0EDH 0EEH 0EFH PWMR0 PWMR1 PWMR2 PWMR3 PWMR4 PWMR5H PWMR5L reserved reserved reserved PWMCR1 PWMCR2 reserved reserved reserved AIPS W W W W W R/W R/W R/W R/W W ???????? ???????? ???????? ???????? ???????? ???????? --?????? 00000000 -----000 --000000 byte byte byte byte byte byte byte, bit byte, bit byte, bit byte 0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH ADCM ADR IEDS IMOD IENL IRQL IENH IRQH reversed IDCR IDFS IDR DPGR TMR reserved reserved R/W R W R/W R/W R/W R/W R/W R/W R R R/W W - ???????? ???????? --000000 --000000 00000000 00000000 00000000 00000000 0000-000 1----001 ???????? ----0000 ???????? - byte, bit byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte, bit byte - 0AE0H 0AE1H 0AE2H 0AE3H 0AE4H 0AE5H 0AE6H 0AE7H 0AE8H 0AE9H 0AEAH 0AEBH 0AECH 0AEDH 0AEEH 0AEFH 0AF0H 0AF1H 0AF2H 0AF3H 0AF4H 0AF5H 0AF9H OSDCON1 OSDCON2 OSDCON3 FDWSET EDGECOL CHEDCL OSDLN LHPOS DLLMOD DLLTST L1ATTR L1EATR L1VPOS L2ATTR L2EATR L2VPOS WINSH WINSY WINEH WINEY VCNT HCNT CULTAD R/W R/W W W W W R W W R W W W W W W W W W W R R W 00000000 00000000 00000000 01111010 10000111 ???????? ---00000 ???????? 00000000 --000000 ??????-? ---????? ???????? ???????? ---????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? byte, bit byte, bit byte, bit byte byte byte byte byte byte byte byte, bit byte, bit byte byte, bit byte, bit byte, bit byte byte byte byte byte byte byte 0BE0H 0BE1H 0BE2H 0BE3H 0BE4H 0BE7H 0BE8H SLCON SLINF0 SLINF1 RIKST RIKED SNCST SNCED R/W W W W W W W 00000000 00000000 00000000 ???????? ???????? ???????? ???????? byte, bit byte, bit byte, bit byte byte byte byte Table 8-1Control registers November 2001 Ver 1.1 Table 8-1Control registers 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. 27 HMS81C4x60 8.4 Addressing Mode The GMS81C4x60 uses six addressing modes; (3) Direct Page Addressing → dp • Register addressing In this mode, a address is specified within direct page. • Immediate addressing Example; G=0 • Direct page addressing E551: C535 LDA ;A ←RAM[35H] 35H • Absolute addressing • Indexed addressing 35H • Register-indirect addressing data À ~ ~ (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. ~ ~ 0E550H C5 0E551H 35 þ data → A þ : direct page (2) Immediate Addressing → #imm In this mode, second byte (operand) is accessed as a data immediately. (4) Absolute Addressing → !abs Example: FE0435 ADC #35H MEMORY 04 A+35H+C → A 35 Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; F100: 0735F0 ADC !0F035H ;A ←ROM[0F035H] When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1, RPR=01H E45535 LDM data 0F035H ~ ~ 0F100H ~ ~ 28 ~ ~ þ A+data+C → A 07 0F101H 35 0F102H F0 address: 0F035 ~ ~ þ 0F100H data ← 55H data 0135H À 35H,#55H À E4 0F101H 55 0F102H 35 November 2001 Ver 1.1 HMS81C4x60 The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag and RPR. F100: 981501 INC !0115H ;A ←ROM[115H] X indexed direct page, auto increment→ {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H F100: DB data 115H ~ ~ LDA {X}+ à À ~ ~ data+1 → data 35H À data ~ ~ 0F100H 98 þ 0F101H 15 address: 0115 0F102H 01 data → A ~ ~ þ 36H → X DB (5) Indexed Addressing X indexed direct page (no offset) → {X} X indexed direct page (8 bit offset) → dp+X In this mode, a address is specified by the X register. This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1, RPR=01H E550: D4 LDA {X} ;ACC←RAM[X]. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H E550: C645 115H data ~ ~ 45H+X À data → A ~ ~ þ 0E550H LDA 3AH data à D4 ~ ~ November 2001 Ver 1.1 À ~ ~ 0E550H C6 0E551H 45 data → A þ 45H+0F5H=13AH 29 HMS81C4x60 Y indexed direct page (8 bit offset) → dp+Y FA00: 3F35 JMP [35H] This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. 35H 0A 36H E3 Y indexed absolute → !abs+Y ~ ~ Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H F100: D500FA 0F100H D5 00 0F102H FA ~ ~ ~ ~ þ 3F 35 !0FA00H+Y ~ ~ À jump to address 0E30AH NEXT 0FA00H LDA 0F101H 0FA55H 0E30AH ~ ~ þ X indexed indirect → [dp+X] 0FA00H+55H=0FA55H ~ ~ À data → A data à Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H FA00: 1625 ADC [25H+X] (6) Indirect Addressing Direct page indirect → [dp] Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL 35H 05 36H E0 ~ ~ À ~ ~ 0E005H 0FA00H 25 + X(10) = 35H ~ ~ 16 25 30 þ data ~ ~ Example; G=0 0E005H à A + data + C → A November 2001 Ver 1.1 HMS81C4x60 Y indexed indirect → [dp]+Y Absolute indirect → [!abs] Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y-register data. The program jumps to address specified by 16-bit absolute address. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H FA00: 1725 ADC JMP Example; G=0 FA00: 1F25E0 JMP [!0E025H] [25H]+Y PROGRAM MEMORY 25H 26H 05 0E025H 25 E0 0E026H E7 ~ ~ 0E015H ~ ~ 0FA00H 0E005H + Y(10) = 0E015H þ data ~ ~ À ~ ~ þ 0E725H 0FA00H 17 November 2001 Ver 1.1 À jump to address 0E725H NEXT ~ ~ ~ ~ 25 ~ ~ ~ ~ 1F 25 à A + data + C → A E0 31 HMS81C4x60 9. I/O PORTS The HMS81C4x60 has 5 ports (R0, R1, R2, R3 and R4) and OSD ports (R,G,B,YS,YM). These ports pins may be multiplexed with an alternatefunction for the peripheral features on the device. In general, in an initial reset state, R ports are used as a general purpose digital port. 9.1 Registers for Port Port Data Registers The Port Data Registers (R0, R1, R2, R3, R4) are represented as a D-Type flip-flop, which will clock in a value from the internal bus in response to a “write to data register” signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a “read data register” signal from the CPU. The level of the port pin itself is placed on the internal bus in response to “read data register” signal from the CPU. Some instructions that read a port activating the “read register” signal, and others activating the “read pin” signal. Port Direction Registers All pins have data direction registers which can define these ports as output or input. A “1” in the port direction register configure the corresponding port pin as output. Conversely, write “0” to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write “55H” to address 0C1H (R0 port direction reg- 32 ister) during initial setting as shown in Figure 9-1. All the port direction registers in the HMS81C4x60 have been written to zero by reset function. On the other hand, its initial status is input. WRITE “55H” TO PORT R0 DIRECTION REGISTER 0C0H R0 DATA 0C1H R0 DIRECTION ~ ~ 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 BIT 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 BIT ~ ~ 0C8H R4 DATA 0C9H R4 DIRECTION I O I O I O I O PORT 7 6 5 4 3 2 1 0 I : INPUT PORT O : OUTPUT PORT Figure 9-1 Example of port I/O assignment November 2001 Ver 1.1 HMS81C4x60 9.2 I/O Ports Configuration R0 Ports functions as following table. R07 ~ R04 is an open drain bidirectional I/O port and R03 ~ R00 is a CMOS bidirectional I/O port(address 0C0H). Each I/O pin can independently used as an input or an output through the R0DD register (address 0C1H). Port Pin R10 R11 R12 R13 R14 The control registers for R0 are shown below. ADDRESS : 00C0H RESET VALUE : Undefined R0 Data Register R0 R/W R/W R/W R/W R/W R/W R/W R/W R07 R06 R05 R04 R03 R02 R01 R00 ADDRESS : 00C1H RESET VALUE : 0000 0000b R0 Direction Register W W W W W W W Alternate Function AN0 (A/D input 0) AN1 (A/D input 1) AN2 (A/D input 2) AN3 (A/D input 3) AN4 (A/D input 4) Port R1 is multiplexed with various special features.The control registers controls the selection of alternate function. After reset, this value is “0”, port may be used as normal input port. The way to select alternate function such as comparator input will be shown in each peripheral section. In addition, R1 port is used as key scan function which operate with normal input port. W R0DD Port Direction 0: Input 1: Output Input or output is configured automatically by each function register (KSMR) regardless of R1DD. R2 Port R1 Ports R1 is a 5-bit CMOS input port only(address 0C2H). Each pin can independently used as an input through the R1DD register (address 0C3H). User can use R0DD register when its bit is 0 only. The control registers for R1 are shown below. ADDRESS : 00C2H RESET VALUE : Undefined R1 Data Register R R R R1 R R R R R R14 R13 R12 R11 R10 R2 is a 6-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R2DD register (address 00C5H).The control registers for R2 are shown below. ADDRESS : 00C4H RESET VALUE : Undefined R2 Data Register R/W R/W R2 R/W R/W R/W R/W R/W R/W R25 R24 R23 R22 R21 R20 ADDRESS : 00C5H RESET VALUE : 0000 0000b R2 Direction Register ADDRESS : 00C3H RESET VALUE : ---0 0000b R1 Direction Register R1DD W W W - - - W W W W W W - - R2DD W W W W W W W Port Direction 0: Input 1: Output Port Direction 0 : use Input only ADDRESS: 00CEH INITIAL VALUE: 0000 0000b AIPS W W - - W W ADDRESS: 00EFH INITIAL VALUE: --00 0000H W W W W AIPS5 AIPS4 AIPS3 AIPS2 AIPS1 AIPS0 MSB LSB AIPS.5 ~ AIPS.0 0 : R0 Port 1 : ADC Input R1 port also can use the value bit5 ~ bit0 of AIPS register to secondary function register. R1 port have secondary November 2001 Ver 1.1 W W W W - - EC 3S EC 2S FUNC W W W IN T3S IN T2S IN T 1S MSB W 1 LSB FUNC.5 ~ FUNC.1 0 : R2 Port 1 : INT mode, EC mode user m ust set 1 R2 port also use the value bit5 ~ bit1 of FUNC register to secondary function register. R2 port have secondary func- 33 HMS81C4x60 R4 Port tions as following table. Port Pin R4 is a 4-bit open drain and bidirectional I/O port (address 0C8H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0C9H). Alternate Function R21 R22 R23 R24 R25 INT1 (External Interrupt 1) INT2 (External Interrupt 2) INT3 (External Interrupt 3) EC2 (Event Counter 2) EC3 (Event Counter 3) The control registers for R4 are shown below. R/W R3 Port The control registers for R3 are shown below. R/W R/W R4DD R/W R/W R/W R/W R/W R/W R/W R/W R37 R36 R35 R34 R33 R32 R31 R30 W W W W - - - - R3 Direction Register W W W W W W W ICCR Port Direction 0: Input 1: Output R/W R/W R/W R/W R/W R/W R/W R/W BU Z EN 5 EN 4 EN 3 EN 2 EN 1 E N0 MSB LSB PWMCR.7 ~ PWMCR.0 0 : R3 Port 1 : PWM, BUZ, TMR1 R/W R41 R40 W W W W R/W R/W R/W R/W R/W R/W R/W BSEL1 BSEL0 AC Kb ESO CCR3 C C R 2 C CR 1 C C R0 MSB R3DD TM R 1 R/W R42 ADDRESS: 00DBH INITIAL VALUE: 0000 0000b W ADDRESS: 00EAH INITIAL VALUE: 0000 0000b R/W R43 Port Direction 0: Input 1: Output R/W ADDRESS : 00C7H RESET VALUE : 0000 0000b R/W ADDRESS : 00C9H RESET VALUE : 0000 0000b R4 Direction Register ADDRESS : 00C6H RESET VALUE : Undefined R3 Data Register PWMCR1 R/W R4 R3 is a 8-bit CMOS bidirectional output port (address 0C6H). Each I/O pin can independently used as an input or an output through the R3DD register (address 0C7H). R3 ADDRESS : 00C8H RESET VALUE : Undefined R4 Data Register ICCR.7 ~ ICCR.6 00 : R4 Port 01 : SCL0, SDA0, R42, R43 10 : SCL1, SDA1, R40, R41 11 : SCL0, SDA0, SCL1, SDA1 LSB R4 port also use the value bit7 ~ bit6 of ICCR register to secondary function register. R4 port have secondary functions as following table. R40 R41 R42 R43 SCL0 (Serial Clock 0) SDA0 (Serial Data 0) SCL1 (Serial Clock 1) SDA1 (Serial Data 1) R3 port also use the value bit7 ~ bit0 of PWMCR1 register to secondary function register. R3 port have secondary functions as following table. R30 R31 R32 R33 R34 R35 R36 R37 34 PWM0 (Pulse Width Modulation 0) PWM1 (Pulse Width Modulation 1) PWM2 (Pulse Width Modulation 2) PWM3 (Pulse Width Modulation 3) PWM4 (Pulse Width Modulation 4) PWM5 (Pulse Width Modulation 5 - 14bit) BUZ (Buzzer Output) TMR1 (Timer Interrup 1) November 2001 Ver 1.1 HMS81C4x60 10. CLOCK GENERATOR generate standard time, Watch Dog Timer which is protect Software Overflow. As shown in Figure 10-1, the clock generation Circuit consist PLL that generate multiplicated frequency of Crystal clock, Generation Circuit which create CPU clock, Prescaler which generate input clock of Basic Interval Timer and variable hardware clock, Basic Interval timer which is See “12.1 BASIC INTERVAL TIMER” on page for details. Data Slicer Clock OSD Clock OSC Circuit Internal System Clock (16MHz typical) Clock Pulse Generator PLL PRESCALER (11) ENPCK Peripheral Circuit 11 8 0 MUX 7 Basic Interval Timer(8) 0 IFBIT 5 Watch Dog Timer(6) BTCL WDTCL 6 COMPARATOR IFWDT 6 WDTON 0 CKCTRL 0 1 2 3 4 5 6 5 WDTR to RESET CIRCUIT 6 WDTCL 7 8 Internal DATA BUS 10.1 Clock Generation Circuit The clock signal come from crystal oscillator or ceramic via Xin and Xout or from external clock via Xin is supplied to Clock Pulse Generator and Prescaler. Internal System Clock for CPU is made by Clock Pulse November 2001 Ver 1.1 Generator, and several peripherial clock is divided by prescaler. Clock Generation circuit of Crystal Oscillator or Ceramic Resonator is shown as below. 35 HMS81C4x60 Cout Xout Xout GND Xin Open External Clock Xin Cin Figure 10-2 External Clock Figure 10-1 Cristal Oscillator or Ceramic Resonator 10.2 Phase Locked Loop PLL(Phase Locked Loop) from OSC 4MHz clock circuit generate Internal System clock, Timer clock(PS0), Data Slicer Clock, OSD clock, etc. Figure 10-3 PLL Control Register W W W W W W - - - - PC F2 PC F1 PLLC W W ADDRESS: 00CFH INITIAL VALUE: -000 0000b PCF 0 PLLO N MSB LSB PLL clock frequency 0 : Off PLL 1 : On PLL, in the case system clock supply OSD circuit PLL clock frequency 000 : 8MHz 001 : 12MHz 010 : 16MHz(typical) 011 : 24MHz 100 : 32Mhz Test mode 10.3 PRESCALER Prescaler consistor of 11-bit binary counter, and input clock which is supplied by oscillation circuit. Frequency fex PS1 PS2 PS3 PS4 PS5 PS6 divided by prescaler is used as a source clock for peripherial hardwares. PS7 PS8 PS9 PS10 PS11 ENPCK B.I.T 8 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 12 PERIPHERAL Figure 10-4 Prescaler 36 November 2001 Ver 1.1 HMS81C4x60 Peripheral Clock supplied from prescaler can be stopped by ENPCK. Peripheral clock is determined by CKCTLR CKCTLR W W - - MSB W W W W D TO N EN PC K BT CL Register.(However, PS11 cannot be stopped by ENPCK) W W W BTS2 BTS1 BTS 0 ADDRESS: 00F6H INITIAL VALUE: --00 0000b LSB B.I.T input clock select 000 : PS4 (4µS) 001 : PS5 (8µS) 010 : PS6 (16µS) 011 : PS7 (32µS) 100 : PS8 (64µS) 101 : PS9 (128µS) 110 : PS10 (256µS) 111 : PS11 (512µS) B.I.T clear (when write) 0 : B.I.T Free-run 1 : B.I.T clear (Auto reset when after 1 cycle) Peripherial clock enable (when write) 0 : Peripherial clock stop 1 : Peripherial clock supply WDT function control(when write) 0 : 6 bit TIMER 1 : WATCH-DOG TIMER B.I.T value (when read) data : 00h ~ FFh Figure 10-5 Clock Control Register November 2001 Ver 1.1 37 HMS81C4x60 11. INTERRUPTS The HMS81C4x60 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH and IRQL, Priority circuit and Master enable flag ("I" flag of PSW). 16 interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 11-2. Below table shows the Interrupt priority Reset/Interrupt Symbol Priority Hardware Reset reserved OSD Interrupt External Interrupt 1 External Interrupt 2 Timer/Counter 0 Timer/Counter 2 Slicer Interrupt VSync Interrupt Timer/Counter 1 Timer/Counter 3 Interrupt interval measure Watchdog Timer Basic Interval Timer reserved I2C Interrupt RESET OSD INT1 INT2 Timer 0 Timer 2 Slicer VSync Timer 1 Timer 3 INTV(INT3/4) WDT BIT I2C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Interrupt Mode Register It controls interrupt priority. It takes only one specified interrupt. Of course, interrupt’s priority is fixed by H/W, but sometimes user want to get specified interrupt even if higher priority interrupt was occured. Higher priority interrupt is occured the next time. It contains 2bit data to enable priority selection and 4bit data to select specified interrupt. Bit No. 5,4 3~0 Name IM1~0 IP3~0 Mode 0: H/W priority Mode 1: S/W priority Interrupt is disabled, even if IE is set. OSD INT1 INT2 Timer 0 Timer 2 Slicer VSync Timer 1 Timer 3 INTV(INT3/4) WDT BIT I2C Not used ADDRESS : 00F3H RESET VALUE : Undefined Interrupt Mode Register R/W 38 00 01 1X Table 11-1 Bit function T he Timer/Co un ter In ter ru p ts a r e gen e rated by TnIF(n=0~3), which is set by a match in their respective timer/counter register. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), that is the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH,IRQL) except Power-on reset and software BRK interrupt. Function 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 The External Interrupts can be transition-activated (1-to-0 or 0-to-1 transition). When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transitionactivated. The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflow in the timer register. Value IMOD R/W R/W R/W R/W R/W R/W R/W M1 M0 IP3 IP2 IP1 IP0 Figure 11-1 Interrupt Mode Register November 2001 Ver 1.1 HMS81C4x60 Internal bus line IENH [00F6H] Interrupt Enable Register (Higher byte) IMOD [00F3H] IRQH [0F7H] Bit5 - IFOSD OSD INT1 INT1 INT2 INT2 RESET BRK T0 Timer 2 T2 Slicer SLICE IFVSync VSync Timer 1 T1 Timer 3 T3 Intr. interval INTV IFWDT WDT IFBIT BIT To CPU Priority Control Timer 0 I Flag Interrupt Master Enable Flag I-flag is in P SW , it is cleared by "D I", set by "EI" instruction. W hen it goes interrupt service, I-flag is cleared by hardw are, thus any other interrupt are inhibited. W hen interrupt service is com pleted by "R ETI" instruction, I-flag is set to "1" by hardw are. I2C IFI2C Interrupt Vector Address Generator IRQL [00F5H] IENL [00F4H] Interrupt Enable Register (Lower byte) Internal bus line Figure 11-2 Block Diagram of Interrupt November 2001 Ver 1.1 39 HMS81C4x60 request is occured, but no accepted request flag is set to hold when the interrupt is accepted. Also, interrupt request flag register(IRQH, IRQL) is the register of read or write. So, request flag can be changed by program. Interrupt request flag registers are shown in Figure 11-3. Interrupt request is generated when suitable bit is set, and suitable request flag of accepted interrup is clear when interrupt processing cycle. Suitable bit is set when interrupt R/W IRQH - R/W R/W R/W R/W OSD INT1 R/W INT2 T0 T2 R/W R/W SLICE VSync MSB ADDRESS: 00F7H INITIAL VALUE: 0000 0000b LSB VSync interrupt request flag Slicer interrupt request flag Timer / Counter 2 interrupt request flag Timer / Counter 0 interrupt request flag External interrupt 2 interrupt request flag External interrupt 1 interrupt request flag On screen display interrupt request flag IRQL R/W R/W R/W R/W R/W R/W R/W T1 T3 INTV WDT BIT - I2C MSB ADDRESS: 00F5H INITIAL VALUE: 0000 000-b LSB I2C interrupt request flag Basic interval timer interrupt request flag Watch-dog timer interrupt request flag Interrupt interval measurement interrupt request flag (INT3/4) Timer / Counter 3 interrupt request flag Timer / Counter 1 interrupt request flag Figure 11-3 Interrupt Request Flag Registers 40 November 2001 Ver 1.1 HMS81C4x60 a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. Interrupt enable flag registers are shown in Figure 11-4. These registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is "0", R/W IENH - R/W R/W R/W R/W OSD INT1 R/W INT2 T0 T2 R/W R/W SLICE VSync MSB ADDRESS: 00F6H INITIAL VALUE: 0000 0000b LSB VSync interrupt enable flag Slicer interrupt enable flag Timer / Counter 2 interrupt enable flag Timer / Counter 0 interrupt enable flag External interrupt 2 interrupt enable flag External interrupt 1 interrupt enable flag On screen display interrupt enable flag IENL R/W R/W R/W R/W R/W R/W R/W T1 T3 INTV WDT BIT - I2C MSB ADDRESS: 00F4H INITIAL VALUE: 0000 000-b LSB I2C interrupt enable flag Basic interval timer interrupt enable flag Watch-dog timer interrupt enable flag Interrupt interval measurement interrupt enable flag (INT3/4) Timer / Counter 3 interrupt enable flag Timer / Counter 1 interrupt enable flag Figure 11-4 Interrupt Enable Flag Regesters November 2001 Ver 1.1 41 HMS81C4x60 11.1 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 f ex (2 µs at fMAIN=4MHz) after the completion of the current instruction execution. The interrupt service task terminates upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decrements 3 times. 4. The entry address of the interrupt service program is read from the vector table address, and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed. 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. System clock Instruction Fetch Address Bus PC Data Bus Not used SP SP-1 PCH PCL SP-2 PSW V.L. V.L. ADL V.H. ADH New PC OP code Internal Read Internal Write Interrupt Processing Step Interrupt Service Task V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents. Figure 11-5 Interrupt Service routine Entering Timing 42 November 2001 Ver 1.1 HMS81C4x60 Basic Interval Timer Vector Table Address 0FFE6H 0FFE7H 012H 0E3H Entry Address 0E312H 0E313H General-purpose register save/restore using push and pop instructions; 0EH 2EH main task acceptance of interrupt interrupt service task saving registers Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. restoring registers A maskable interrupt is not accepted until the I-flag is set to "1" even if a maskable interrupt of higher priority than that of the current interrupt being serviced. When nested interrupt service is necessary, the I-flag is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. Saving/Restoring General-purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but not the accumulator and other registers. These registers are saved by the program if necessary. Also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. interrupt return 11.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which is the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 11-6. The following method is used to save/restore the generalpurpose registers. Example: Register save using push and pop instructions INTxx: PUSH PUSH LDA A X DPGR PUSH A ;SAVE ACC. ;SAVE X REG. ;SAVE DPGR ; Direct page ; accessable reg. ; : interrupt processing : POP STA POP POP RETI A DPGR X A November 2001 Ver 1.1 B-FLAG BRK or TCALL0 =0 =1 BRK INTERRUPT ROUTINE TCALL0 ROUTINE RETI RET Figure 11-6 Execution of BRK/TCALL0 ;RESTORE DPGR ;RESTORE X REG. ;RESTORE ACC. ;RETURN 43 HMS81C4x60 11.3 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines by hardware which request is serviced. Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. Main Program service TIMER 1 service enable INT0 disable other INT0 service EI Occur TIMER1 interrupt However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user set I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. Occur INT0 enable INT0 enable other TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI A X Y IENH,#20H IENL,#0 IENH,#FFH IENL,#FEH Y X A ;Enable INT1 only ;Disable other ;Enable Interrupt ;Enable all interrupts In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine. Figure 11-7 Execution of Multi Interrupt 44 November 2001 Ver 1.1 HMS81C4x60 11.4 External Interrupt The external interrupt on INT1, INT2... pins are edge triggered depending the edge selection register. Refer to “6. PORT STRUCTURES” on page 12. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, both edge. INT1 pin INT2IF edge selection INT2 pin INT1IF INT3 pin INT3IF INT1 INTERRUPT INT2 INTERRUPT INT1, INT2 and INT3 are multiplexed with general I/O ports. To use external interrupt pin, the bit of port function register FUNC1 should be set to "1" correspondingly. Response Time The INT1, INT2 and INT3 edge are latched into INT1IF, INT2IF and INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. For example, the DIV instruction takes twelve machine cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine INT3 INTERRUPT IEDS [00F2H] Figure 11-8 External Interrupt Block Diagram System clock Instruction Fetch Last instruction execution (0~12cycle) Enter interrupt service routine (8cycle) Interrupt request sampling 1cycle Interrupt overhaed (9~21cycle) Figure 11-9 Interrupt Response Timing Diagram ( Interrupt overhead ) November 2001 Ver 1.1 45 HMS81C4x60 12. TIMER 12.1 Basic Interval Timer The HMS81C4x60 has one 8-bit Basic Interval Timer that is free-run and can not be stopped. Block diagram is shown in Figure 12-1. generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 12-2. Source clock can be selected by lower 3 bits of CKCTLR. The Basic Interval Timer generates the time base for watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (BITIF). As the count overflow from FFH to 00H, this overflow causes the interrupt to be fex÷24 fex÷25 fex÷26 fex÷27 fex÷28 fex÷29 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 8-bit up-counter source clock MUX BITR and CKCTLR are located at same address, and address 00D6H is read as a BITR and written to CKCTLR.. overflow BITR [0D6H] fex÷210 fex÷211 BITIF Basic Interval Timer Interrupt Watchdog timer clock (WDTCK) clear 3 BITCK Select Input clock Clock control register [0D6H] CKCTLR BTCL WDT ENPCK BTCL BTS2 BTS1 BTS0 ON Internal bus line Figure 12-1 Block Diagram of Basic Interval Timer CKCTLR W W - - W W W W D TO N ENP CK BTC L W W W BTS2 BT S1 BT S0 MSB ADDRESS: 00D6H INITIAL VALUE: --00 0000b LSB B.I.T Clock B.I.T clear (when write) 0 : B.I.T Free-run 1 : B.I.T clear (Auto reset when after 1 cycle) Peripherial clock enable (write time) 0 : Peripherial clock stop 1 : Peripherial clock supply Caution: WDT function control 0 : 6 bit TIMER 1 : WATCH-DOG TIMER Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR. R R R R B.I.T value (when read) R R R R ADDRESS: 00D6H INITIAL VALUE: Undefined BITR MSB 8-BIT BINARY COUNTER LSB Figure 12-2 BITR Basic Interval Timer Mode Register 46 November 2001 Ver 1.1 HMS81C4x60 12.2 Timer 0, 1 Timer 0, 1 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, Control register, and Comparator as shown in Figure 12-3 and Figure 12-4. Note: You can read Timer 0, Timer 1 value from TDR0 or TDR1. But if you write data to TDR0 or TDR1, it changes Timer 0 or Timer 1 modulo data, not Timer value. These Timers can run separated 8bit timer or combined 16bit timer. These timers are operated by internal clock. The content of TDR0, TDR1 must be initialized (by software) with the value between 01H and FFH,not to 00H. Or not, Timer 0 or Timer 1 can not count up forever. The contents of TDR1 are compared with the contents of up-counter T1. If a match is found, a timer/counter 1 interrupt (T1IF) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. The control registers for Timer 0,1 are shown below. R/W R/W R/W R/W R/W R/W R/W R/W - T 1ST T1SL1 T1SL0 T 0ST T 0C N T 0SL1 T 0SL0 TM0 MSB ADDRESS: 00D0H INITIAL VALUE: -000 0000b LSB T0 input clock select(fex=4MHz) 00 : PS2(1µS) 01 : PS4(4µS) 10 : PS6(16µS) 11 : PS8(64µS) Timer 0 Continue/Hold control 0 : Count Hold 1 : Count Countinue Timer 0 Start control 0 : Count Hold 1 : Count Clear and Start Timer 1 input clock(fex=4MHz) 00 : Timer 0 overflow (16bit mode) 01 : PS2(1µS) 10 : PS4(4µS) 11 : PS6(16µS) Timer 1Start/Hold control 0 : Count Hold 0 : Count Clear and Start ADDRESS: 00D2H R/W R/W R/W R/W INITIAL VALUE: Undefined R/W R/W R/W R/W TDR0 MSB R/W LSB R/W R/W R/W ADDRESS: 00D3H INITIAL VALUE: Undefined R/W R/W R/W R/W TDR1 MSB LSB Figure 12-3 Timer / Event Count 0,1 (Example) TIMER0 1mS TIME INTERVAL INTERRUPT : : TDR_CNT: LDM TDR0,#249 LDM TDR1,#0 LDM TM0,#0011_1101b ; 4uSEC PRESCALER FOR T0 : : November 2001 Ver 1.1 47 HMS81C4x60 . Internal bus line TM0 TDR0 TDR1 T0CN PS2 PS4 PS6 PS8 8bit Comparator 8bit Comparator T0IF T1IF Timer 0 Timer 1 MUX Clock Clear Clock Clear T0ST NC PS2 PS4 PS6 MUX T1ST Figure 12-4 Simplified Block Diagram of 8bit Timer0, 1 TDR0 disable t ~~ clear & start enable up -c ou n stop ~~ TIME Timer 0 (T0IF) Interrupt Occur interrupt Occur interrupt T0ST Start & Stop T0ST = 1 T0ST = 0 T0CN Control count T0CN = 1 T0CN = 0 Figure 12-5 Count Example of Timer 48 November 2001 Ver 1.1 HMS81C4x60 Internal bus line TM0 TDR0 0 TDR1 0 T0CN 16bit Comparator T1IF PS2 PS4 PS6 PS8 Timer 0 Timer 1 MUX Clock Clear Clock Clear T0ST Figure 12-6 Simplified Block Diagram of 16bit Timer0, 1 November 2001 Ver 1.1 49 HMS81C4x60 12.3 Timer / Event Counter 2, 3 Timer 2, 3 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, Control register, and Comparator as shown in Figure 12-7 and Figure 12-8. Note: You can read Timer 2, Timer 3 value from TDR2 or TDR3. But if you write data to TDR2 or TDR3, it changes Timer 2 or Timer 3 modulo data, not Timer value. These Timers have two operating modes. One is the timer mode which is operated by internal clock, other is event counter mode which is operated by external clock from pin R24/EC2, R25/EC3. The content of TDR2, TDR3 must be initialized (by software) with the value between 01H and FFH,not to 00H. Or not, Timer 2 or Timer 3 can not count up forever. These Timers can run separated 8bit timer or combined 16bit timer. The control registers for Timer 2,3 are shown below R/W R/W R/W R/W R/W R/W R/W R/W - T3ST T 3SL1 T 3SL0 T3ST T3C N T3SL1 T3SL0 TM2 MSB ADDRESS: 00D1H INITIAL VALUE: -000 0000b LSB T2 input clock select 00 : External EVENT input(EC2) 01 : PS2(1µS) 10 : PS4(4µS) 11 : PS6(16µS) Timer 2 Continue/Hold control 0 : Count Hold 1 : Count Countinue Timer 2 Start/Hold control 0 : Count Hold 1 : Count Clear and Start Timer 3 input clock 00 : Connected to T2(16bit mode) 01 : External EVENT input(EC3) 10 : PS2 (1µS) 11 : PS6 (16µS) Timer 3 Start/Hold control 0 : Count Hold 0 : Count Clear and Start ADDRESS: 00D4H TDR2 R/W R/W R/W R/W INITIAL VALUE: Undefined R/W R/W R/W R/W T DR 7 T DR 6 TD R 5 TD R 4 TD R 3 TD R 2 T D R1 TD R 0 MSB TDR3 LSB R/W R/W R/W R/W ADDRESS: 00D5H INITIAL VALUE: Undefined R/W R/W R/W R/W TD R 7 TD R 6 TD R 5 TD R 4 TD R 3 TD R2 TD R 1 TD R 0 LSB MSB W W W W - - EC 1S EC 0S FUNC MSB W W W IN T 3S IN T 2S IN T1S W ADDRESS: 00CEH INITIAL VALUE: 0000 000-b LSB R24/EC2 Select 0 : R24 1 : EC2 R25/EC3 Select 0 : R25 1 : EC3 Figure 12-7 Timer / Event Count 2,3 50 November 2001 Ver 1.1 HMS81C4x60 . Internal bus line TM2 TDR2 TDR3 T2CN EC2 PS2 PS4 PS6 8bit Comparator 8bit Comparator T2IF T3IF Timer 2 Timer 3 MUX Clock Clear Clock Clear T2ST NC EC3 PS2 PS4 MUX T3ST Figure 12-8 Simplified Block Diagram of 8bit Timer/Event Counter 2,3 TDR2 disable t ~~ clear & start enable up -c o un stop ~~ TIME Timer 2 (T2IF) Interrupt Occur interrupt Occur interrupt T2ST Start & Stop T2ST = 1 T2ST = 0 T2CN Control count T2CN = 1 T2CN = 0 Figure 12-9 Count Example of Timer / Event counter November 2001 Ver 1.1 51 HMS81C4x60 Internal bus line TM2 TDR2 0 TDR3 0 T0CN 16bit Comparator T3IF Timer 2 EC2 PS4 PS6 PS8 Timer 3 MUX Clock Clear Clock Clear T0ST Figure 12-10 Simplified Block Diagram of 16bit Timer/Event Counter 2,3 Timer Mode n interrupt (TnIF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn (n=0~3) are compared with the contents of up-counter, Timer n. If match is found, a timer As the value of TDRn is changeable by software, time interval is set as you wantU Start count 0 TDRn (n=0~3) 1 2 3 N ~ ~ ~ ~ ~ ~ ~ ~ Up-counter ~ ~ Source clock N-2 N-1 N Match Detect 1 2 3 4 Counter Clear ~ ~ TnIF (n=0~3) interrupt 0 Figure 12-11 Timer Mode Timing Chart Event Counter Mode put. In event timer mode, counting up is started by an external trigger. This trigger means falling edge of the ECn (n=0~1 ) pin input. Source clock is used as an internal clock selected with TM2. The contents of TDRn are compared with the contents of the up-counter. If a match is found, an TnIF interrupt is generated, and the counter is cleared to 00H. The counter is restarted by the falling edge of the ECn pin in- The maximum frequency applied to the ECn pin is fex/2 [Hz] in main clock mode. 52 In order to use event counter function, the bit EC0S, EC1S of the Port Function Select Register FUNC(address 0CEH) is required to be set to "1". After reset, the value of TDRn is undefined, it should be November 2001 Ver 1.1 HMS81C4x60 initialized to between 01H~FFHS not to 00HU Start count ~ ~ ECn (n=2~3) pin 1 0 TDRn (n=2~3) ~ ~ ~ ~ ~ ~ ~ ~ Up-counter 2 N N 0 1 2 ~ ~ TnIF (n=2~3) interrupt N-1 Figure 12-12 Event Counter Mode Timing Chart The interval period of Timer is calculated as below equation. 1 Period = ------ × Prescaler ratio × TDR n fex TDR2 TDR2=n -c o 8 ~~ un t PCP ~~ n n-1 n-2 ~~ up 7 6 5 4 3 2 1 0 TIME Interrupt period = PCP x n Timer 2 (T2IF) Interrupt Occur interrupt Occur interrupt Occur interrupt Figure 12-13 Count Example of Timer / Event counter November 2001 Ver 1.1 53 HMS81C4x60 TDR2 disable t ~~ clear & start enable up -c o un stop ~~ TIME Timer 2 (T2IF) Interrupt Occur interrupt Occur interrupt T2ST Start & Stop T2ST = 1 T2ST = 0 T2CN Control count T2CN = 1 T2CN = 0 Figure 12-14 Count Operation of Timer / Event counter 54 November 2001 Ver 1.1 HMS81C4x60 13. A/D Converter The A/D converter circuit is shown in Figure 13-1. The A/D converter circuit consists of the comparator and c o n t r o l r e g i st e r A I P S ( 0 0 E F H ) , AD C M( 0 0F 0 H ) , ADR(00F1H). The AIPS register select normal port or an- alog input. The ADCM register control A/D converter’s activity. The ADR register stores A/D converted 8bit result. The more details are shown Figure 13-2. Data Bus 5 8 0 ADEN ADS2 ADS1 ADS0 ADST ADSF ADCM [F0H] ADR [F1H] 0 1 2 3 4 5 6 7 8 IFA Control circuit port select Comparator AN0 AN1 AN2 S/H MUX Vref AN3 + − Succesive Approximation Circuit AN4 Register ladder 8 Figure 13-1 Block Diagram of A/D convertor circuit Control The HMS81C4x60 contains a A/D converter module which has six analog inputs. 1. First of all, you have to select analog input pin by set the ADCM and AIPS. 2. Set ADEN (A/D enable bit : ADCM bit5). 3. Set ADST (A/D start bit : ADCM bit1). We recommend you do not set ADEN and ADST at once, it makes worse A/D converted result. 4. ADST bit will be cleared 1 cycle automatically after you set this. BBC ADCM.ADSF,$ LDA ADR ; or “SET1 ADST” : : 5. After A/D conversion is completed, ADSF bit and interrupt flag IFA will be set. (A/D conversion takes 36 machine cycle : 18uS when fex=4MHz). Note: Make sure AIPS bits, if you using a port which is set digital input by AIPS, analog voltage will be flow into MCU internal logic not A/D converter. Sometimes device or port is damaged permanently. [Example] ;Set AIPS, change ? to what you want ; 0 : digital port ; 1 : analog port LDM AIPS,#0000_1000b ; Set ADEN, xxx is analog port number LDM ADCM,#0010_1100b ; or “SET1 ADEN” ; Set ADST, xxx is analog port number LDM ADCM,#0010_11110b November 2001 Ver 1.1 55 HMS81C4x60 R/W R/W R/W R/W R/W R/W R/W R - - AD EN AD S2 AD S1 AD S0 AD ST AD SF ADCM MSB ADDRESS: 00F0H INITIAL VALUE: --01 1101b LSB A/D Converter Status bit 0 : Busy 1 : A/D conversion completed A/D Converter Start bit 0 : Ignore 1 : A/D start (‘0’ after 1 cycle) Analog Port Select 000 : AN0 select 001 : AN1 select 010 : AN2 select 011 : AN3 select 100 : AN4 select 101 : Default 110 : Default 111 : Default A/D Converter Enable bit 0 : Disable 1 : Enable ADDRESS: 00F1H ADR INITIAL VALUE: Undefined R R R R R R R R T DR 7 T DR 6 T DR 5 T DR 4 T DR 3 MSB T DR 2 TD R1 TD R 0 LSB AIPS W W W - - - W ADDRESS: 00EFH INITIAL VALUE: ---0 0000H W W W W A IPS4 A IPS3 AIPS2 AIPS1 AIPS0 MSB LSB Analog Input Select 0 : P1 input 1 : ADC Input Figure 13-2 A/D convertor Registers PORT select ADS2 ADS1 ADS0 Function R14/AN4 R13/AN3 R12/AN2 R11/AN1 R10/AN0 W 0 W AN0 R14 R13 R12 R11 AN0 W 0 X AN1 R14 R13 R12 AN1 R10 0 1 W AN2 R14 R13 AN2 R11 R10 0 1 X AN3 R14 AN3 R12 R11 R10 1 0 W AN4 AN4 R13 R12 R11 R10 Figure 13-3 A/D Conversion Data Register 56 November 2001 Ver 1.1 HMS81C4x60 14. Pulse Width Modulation (PWM) The PWM circuit is shown in Figure 14-1, . The PWM circuit consists of the counter, comparator, Data register. Example (fex=4MHz) 14bit PWM 8bit PWM Resolution 14 bits 8 bits Input Clock 2MHz 250KHz Frame cycle 8,192uS 1,024uS The PWM control registers are PWMR4~0, PWMCR2~1, PWM5H, PWM5L. The more details about registers are shown Figure 14-2 . PWMCR2 [EBH] PWMCR1 [EAH] EN4 EN3 EN2 EN1 EN0 EN5 3 21 0 CNTB PWMR5 [E5H] PWM5 EN5 PWM4 PWMR4 [E4H] EN4 PWM3 PWMR3 [E3H] EN3 PWM2 EN2 PWMR2 [E2H] PWM1 EN1 PWMR1 [E1H] PWMR0 [E0H] EN0 PWM0 8bit comparator CNTB PS5 IF1Frame 8bit counter PWMR5H 8bit [E8 H] PWMCR2 [EBH] PWMCR1 [EAH] CNT EN8 Internal Control Figure 14-1 8bit register (PWM7~0) circuit CNTB PWMR5L 6bit [E9H] PWM8 MSB 14bit comparator LSB PS2 14bit counter Figure 14-2 14bit register (PWM8) circuit November 2001 Ver 1.1 57 HMS81C4x60 8bit PWM Control Sub PWM Frame Cycle = Main Frame Cycle / 64. The HMS81C4x60 contains a one 14bit PWM and five 8bit PWM module. 1. 8bit PWM0~5 is wholy same internal circuit, but PWM0~5 output port is CMOS bidirectional I/O pin. 2. Al l PWM polarity has the same by POL2’s value. 3. Calulate Frame cycle and Pulse width is as following. PWM Frame Cycle = 213/ fex (Sec) PWM Width = (PWMRn+1) × 25 / fex (n=0~5) Pulse Duty (%) = (PWMRn +1) / 256 × 100(%) (n=0~5) Positive Polarity (POL2=0) 4. Table 14-1, “PWM5L and Sub frame matching table,” on page 58 show PWM5L function. Bit value 1 2 2 Pulse count if Bit0=1 32 1 if Bit1=1 16, 48 2 if Bit2=1 8, 24, 40, 56 4 if Bit3=1 4, 12, 20, 28, 36, 44, 52, 60 8 if Bit4=1 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54 16 if Bit5=1 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63 32 Negative Polarity (POL2=1) 1 Sub frame number which is added 1 clock Table 14-1 PWM5L and Sub frame matching table 1. Frame cycle 2. Pulse Width Main PWM Frame Figure 14-3 Wave form example for 8bit PWM 0 1 2 61 62 63 ..... 4. PWM output is enabled during ENn(n=0~5) bit (See PWMCR1~2) contains 1. Sub PWM Frame ADDRESS: 00E0H~E4H PWMR4~0 R/W R/W R/W R/W INITIAL VALUE: Undefined R/W R/W R/W R/W Sub PWM Frame which is added 1 clock 1 clock width : PS2 PW M0D7 PW M0D6 PW M0D5 PW M0D4 PW M0D3 PW M0D2 PW M0D1 PW M0D0 MSB Each PWM Data Store LSB Figure 14-5 Wave form example for 14bit PWM Figure 14-4 8bit PWM Registers 5. CNTB controls all PWM counter enable. If CNTB=0, than Counter is disabled. 14bit PWM Control 1. 14bit PWM’s operation concept is not the same as 8bit PWM. 1 PWM frame contains 64 sub PWMs. PWM5H : Set sub PWM’s basic Pulse Width. PWM5L : Number of sub PWM which is added 1 clock. 2. PWM polarity is selected by POL1’s value. If POL1=0, Positive Polarity. ADDRESS: 00E8H PWM5H R/W R/W R/W R/W INITIAL VALUE: Undefined R/W R/W R/W R/W PWM 5H7 PW M5H6 PW M5H5 PW M5H4 PW M5H3 PW M5H2 PW M5H1 PW M5H0 MSB LSB PWM5L R/W R/W - - R/W R/W ADDRESS: 00E9H INITIAL VALUE: Undefined R/W R/W R/W R/W PW M5L5 PW M5L4 PW M5L3 PW M5L2 PW M5L1 PW M5L0 MSB LSB Figure 14-6 PWM5H, PWM5L Register 3. Calulate Frame cycle and Pulse width is as following. Main PWM Frame Cycle = 216/ fex (Sec). 58 November 2001 Ver 1.1 HMS81C4x60 PWMCR1 R/W R/W R/W R/W R/W R/W R/W R/W TM R 1 BU Z EN 5 EN 4 EN 3 EN 2 EN 1 E N0 MSB ADDRESS: 00EAH INITIAL VALUE: 0000 0000b LSB R30/PWM0 Select 0 : R30 1 : PWM0 R31/PWM1 Select 0 : R31 1 : PWM1 R32/PWM2 Select 0 : R32 1 : PWM2 R33/PWM3 Select 0 : R33 1 : PWM3 R34/PWM4 Select 0 : R34 1 : PWM4 R35/PWM5 Select 0 : R35 1 : PWM5 R3]/Buzzer Select 0 : R36 1 : Buzzer output R37/TMR1 Select 0 : R37 1 : TMR1 Figure 14-7 PWM Control Register 1 R/W R/W R/W R/W R/W - - - - - PWMCR2 MSB R/W R/W R/W PO L8 PO L14 C N TB ADDRESS: 00EBH INITIAL VALUE: 0000 0000 b LSB 14Bit/8Bit PWM Count stop/start 0 : Count start 1 : Count stop 14Bit PWM Output Polarity 0 : Positive Polarity 1 : Negitive Polarity 8Bit PWM Output Polarity 0 : Positive Polarity 1 : Negative Polarity Figure 14-8 PWM Control Register 2 November 2001 Ver 1.1 59 HMS81C4x60 15. Interrupt Interval Measurement Circuit The Interrupt interval measurement circuit is shown in Figure 15-1. tor, 8bit counter, measured result storing register, FIFO (9 bit, 6 level) interrupt, Control register, etc. The Interrupt interval measurement circuit consists of the input multiplexer, sampling clock multiplexer, Edge detec- The more details about registers are shown Figure 15-2 . Data Bus 7 IDCR [F9H] PS8 FCLR IMS I34H I34L ISEL 4 IDCK IDST IDFS [FAH] FOE FFUL FEMP 1 MUX PS9 DPOL 8bit counter Clear 0 Overflow 8 4 INT34 1 MUX INT3 Edge detector 0 MUX 0 FCLR FIFO (9bit, 6level) 1 IDR [FBH] D7 D6 D5 D4 D3 D2 D1 D0 Figure 15-1 Block Diagram of Interrupt interval measurement circuit Control The HMS81C4x60 contains a Interrupt interval measurement module. 1. Select interrupt input pin what you want to measure by set the FUNC [00CEH]. 2. Set IDCR [00F9H] : FIFO clear, interrupt mode select, interrupt edge select, external interrupt INT3 select, sampling clock select, COUNT start/stop select. 3. Set IDCR [00F9H] : set IDST to start measuring. 4. Counter value is stored to IDR [00FBH] when selected edge is detected. After data was written, timer is cleard automatically and it counts continue. 60 5. You can select interrupt occuring point by set Interrupt Mode Select bit (IMS), every edge what you selected or FIFO 4 level is filled. 6. If input signal’s interval is larger than maximum counter value (0FFH), counter occurring an interrupt and count again from 00H. 7. See Figure 15-7 FIFO operating mechanism. [Example] ;Set INT3 for remote control pulse reception LDM LDM : : FUNC,#0000_1001b;INT3 SET IDCR,#1001_0001b ;64uSec PCS November 2001 Ver 1.1 HMS81C4x60 IDCR R/W R/W R/W R/W R/W R/W R/W R/W FC LR IM S I34H I34L - ISEL ID C K ID ST MSB ADDRESS: 00F9H INITIAL VALUE: 0001 -000b LSB Counter control 0 : Stop 1 : Clear & Count Sample Clock Select 0 : PS9(128uSec) 1 : PS8(64uSec) External Interrupt Select 0 : INT3 fixed External Interrupt Edge Select 00 : No Select 01 : Falling Edge 10 : Rising Edge 11 : Both Edge Interrupt Mode 0 : Every Selected Edge by I34H/L 1 : Every FIFO 4Level is Filled FIFO Clear 0 : Ignored 1 : Clear & Return to 0 Figure 15-2 Int. interval determination control register R/W IDFS R/W R/W R/W R/W D PO L R/W R/W R/W FO E FF UL F EM P MSB ADDRESS: 00FAH INITIAL VALUE: 0--- -001b LSB FIFO Empty Flag 0 : Data Filled 1 : Empty FIFO Full flag 0 : Not Full 1 : Full FIFO Overrun Error Flag 0 : No Error 1 : Error Detected Data Polarity 0 : Data is stored every falling edge 1 : Data is stored every rising edge Figure 15-3 Port function select register W W W W - - EC 3S EC 2S FUNC MSB W W W IN T3S IN T2S IN T1S W ADDRESS: 00CEH INITIAL VALUE: --00 000-b LSB R24/INT3 Select 0 : R23 1 : INT3 Figure 15-4 Port function select register November 2001 Ver 1.1 61 HMS81C4x60 Interrupt input c e R R R R ADDRESS: 00FBH INITIAL VALUE: Undefined R R R R D7 D6 D5 D4 D3 IDR d f D2 D0 D1 MSB LSB Figure 15-6 INT. interval determination FIFO data register Item Symbol c d e f Frame Cycle Pulse width I34H I34L Detecting edge 1 0 Rising edge 0 1 Falling edge 1 1 Both edge 1 1 Both edge Figure 15-5 Setting for measurement 1) FIFO storing mechanism FEMP=1, FFUL=0 FEMP=0, FFUL=0 FEMP=0, FFUL=0 FEMP=0, FFUL=1 FEMP=0, FFUL=1 Data 1 Data 1 Data 1 Data 1 Data 2 Data 2 Data 2 Data 3 Data 3 Data 4 Data 4 Data 5 Data 5 Data 6 Data 7 Data in 2) FIFO reading mechanism Read out FEMP=0 Data 1 Read out Data in Data in Data in Data 6 will be erased. FOE=1 (Over run error) FEMP=0 FEMP=1 Data 2 Data 2 Figure 15-7 Example for FIFO operating mechanism 62 November 2001 Ver 1.1 HMS81C4x60 16. Buzzer driver The Buzzer driver circuit is shown in Figure 16-1. register controls source clock and output frequency. The Buzzer driver circuit consists of the 6bit counter, 6bit comparator, Buzzer data register BUR(00EEH). The BUR The more details about registers are shown Figure 16-2 . Data Bus 8 BUR [EEH] BUCK BUCK 1 0 BU5 BU4 BU3 BU2 BU1 BUR write BU0 6 6bit Comparator clear PS7 PS8 PS9 PS10 BUZZ Output Generator 6 00 6bit counter 01 clear 10 11 MUX PWMCR1 TM R1 BUZ EN5 EN4 EN3 EN2 EN1 EN0 Figure 16-1 Block Diagram of Buzzer driver circuit Control 3. Set BUZ bit for output enable. The HMS81C4x60 contains a Buzzer driver module. 4. Output waveform is rectagle clock which has 50% duty. 1. Select an input clock among PS7~PS10 by set the BUCK1~0 of BUR. 5. You can use this clock for the other purposes. BUCK1 BUCK0 Clock source 0 0 PS7 0 1 PS8 1 0 PS9 1 1 PS10 W BUR Note: Do not select 00H to BU5~0. It means counter stop. November 2001 Ver 1.1 W W W W W W W BUCK1 BUCK0 BU5 BU4 BU3 BU2 BU1 BU0 Input select Buzzer count data ADDRESS : 0EAH RESET VALUE : 0000 0000b PWM control Register 1 RW 2. Select output frequency by change the BU5~0. Output frequency = 1 / (PSx × BUy × 2) Hz. x=7~10, y=5~0 See example Table 16-1. ADDRESS : 0EEH RESET VALUE : ???? ????b Buzzer data Register RW RW PWMCR1 TM R1 BUZ EN5 RW EN4 RW RW RW RW EN3 EN2 EN1 EN0 R36/Buzz select 0: R36 1: Buzz output Figure 16-2 Buzzer driver Registers 63 HMS81C4x60 BUR5~0 Dec Hex 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Output frequency (KHz) PS7 (32µS) 31.25 15.625 10.436 7.813 6.25 5.208 4.464 3.907 3.472 3.125 2.841 2.604 2.404 2.242 2.083 1.953 1.838 1.736 1.644 1.562 1.438 1.420 1.359 1.302 1.25 1.202 1.158 1.116 1.078 1.042 1.008 0.976 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496 PS8 (64µS) 62.50 31.25 20.872 15.626 12.50 10.416 8.928 8.814 6.942 6.25 5.682 5.208 4.808 4.484 4.166 3.906 3.676 3.472 3.288 3.124 2.876 2.840 2.718 2.604 2.50 2.404 2.316 2.232 2.156 2.084 2.016 1.952 1.894 1.838 1.786 1.736 1.690 1.644 1.602 1.562 1.524 1.488 1.454 1.420 1.388 1.358 1.33 1.302 1.276 1.25 1.226 1.202 1.18 1.158 1.136 1.116 1.096 1.078 1.06 1.042 1.024 1.008 0.992 PS9 (128µS) 125.0 62.5 41.744 31.252 25.0 20.832 17.858 17.628 13.884 12.5 12.364 10.416 9.616 8.968 8.332 7.812 7.342 6.944 6.576 6.248 5.752 5.680 5.436 5.208 5.0 4.808 4.632 4.464 4.302 4.168 4.032 3.904 3.788 3.676 3.552 3.472 3.380 3.288 3.204 3.124 3.048 2.978 2.908 2.840 2.776 2.706 2.66 2.604 2.542 2.5 2.452 2.404 2.36 2.316 2.272 2.232 2.192 2.156 2.12 2.084 2.048 2.016 1.984 PS10 (256µS) 250.0 125.0 83.488 62.504 50.0 41.664 35.716 35.256 27.768 25.0 24.728 20.832 19.232 17.936 16.664 15.624 14.684 13.888 13.152 12.496 11.504 11.360 10.872 10.416 10.0 9.616 9.262 8.928 8.604 8.336 8.064 7.808 7.576 7.352 7.104 6.944 6.760 6.576 6.408 6.248 6.096 5.956 5.816 5.680 5.552 5.412 5.320 5.208 5.184 5.0 4.904 4.808 4.720 4.632 4.544 4.464 4.384 4.312 4.24 4.168 4.096 4.032 3.968 Table 16-1 . Example for fex=4MHz 64 November 2001 Ver 1.1 HMS81C4x60 17. On Screen Display (OSD) OSD circuit consists of the Position attribute register, Line register, Full screen screen control register, I/O polarity register, font ROM, VRAM, etc. On Screen Display block diagram is shown in Figure 17-1 and the more details about display characters are shown in Figure 17-2. The HMS81C4x60 can support 512 OSD chacters and font size is used 12×10, 12×12, 12×14, 12×16, 16×18. It can support 48 character columns and 2 line buffers respectively and also support full screen OSD when use interrupt. Each characters have bit plane of 24bit and support attribute with OSD line and full screen OSD respectively. Line 1,2 Attribute, Position register Line register OSDLN [AE5H] L1ATTR [AF0H] L1VPOS [AF1H] Full screen control register Display On/Off Control register I/O Porarity Rigister OSDCON2 [AE1H] OSDCON3 [AE2H] OSDCON1 [AE0H] Horizontal position register L2ATTR [AF3H] Field detection register LHPOS [AE6H] FDWSET [AE3H] L2VPOS [AF4H] Edge color register EDGECOL [AE4H] OSD Control Circuit Color Pallet DAC R G B VRAM Font ROM Output Control Circuit OSD Generation Circuit YM dot clock HSYNC VSYNC Synchronization Circuit Xin YS PLL Figure 17-1 Block Diagram of On Screen Display circuit November 2001 Ver 1.1 65 HMS81C4x60 [12 × 10 Character Font] [12 × 12 Character Font] - italic (only 12 × 12 mode can be supported) [12 × 14 Character Font] Foreground Character - 512 color (8 pallet) - color selecting : VRAM n-character bit 19~16 Background - 512 color (8 pallet) - color selecting : VRAM n-character bit 23~20 Foreground Character outline - setting by LnATTR register - color selecting : EDGECOL register [12 × 16 Character Font] Character shadow - setting by LnATTR register and VRAM n-character bit 9 - color selecting : EDGECOL register Background shadow color - setting by VRAM n-character bit 15~12 - color selecting : EDGECOL register - 512 color (8 pallet) [16 × 18 Character Font] OSD background shadow - Character flash - background underline Figure 17-2 OSD Character Font Example 66 November 2001 Ver 1.1 HMS81C4x60 17.1 Feature of OSD - Character size The Feature of OSD shown in below. : 3 fonts(2 times, 1.5 times, 1 times) - Font pixel matrix : 12×10, 12×12, 12×14, 12×16, 16×18 dots - Progressive scan line switch - The number of font pattern - Attribute : 512 fonts : Outline, Shadow, Rounding - Display ability - RGB DAC : 48Character × n lines (multilined by OSD interrupt) : 8 level each color - 8 foreground pallet of 512 colors for each character - Display clock frequency - 8 background pallet of 512 colors for each character : 12MHz ~ 64MHz - Full screen 8 background color 17.2 OSD Registers R/W OSDCON1 R/W R/W R/W R/W R/W R/W R/W FSBC 3 FSBC 2 FSBC 1 FSBC 0 PR SC N DLIN E D D CLK STO CK MSB ADDRESS: 0AE0H INITIAL VALUE: 0000 0000b LSB Stop OSD clock 0 :Release OSD clock 1 : Stop OSD clock Double dot clock mode 0 : Normal 1 : Double Double scan line mode 0 : Normal 1 : Double Progressive scan line mode 0 : Interace mode 1 : Progressive mode Full screen background color register 0000 : Transparency 0001 : Half blank 0010 : white 0011 : Black 0111 ~ 0100 : Reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 Figure 17-3 OSD Control Registers - 1 OSDCON1 bit 0: STOCK It stop or start OSD clock. If oscillation is stoped, IC’s power consumption is decreased. bit 1: DDCLK November 2001 Ver 1.1 If you set this bit to 1, OSD input clock is divided by two , than it makes OSD horisontal image size as doubled. bit 2: DLINE If you set this bit to 1, OSD vertical scan counter input clock is doubled from normal state. It makes OSD vertical 67 HMS81C4x60 image size as doubled. bit 7~4: FSBC3 ~ FSBC0 bit 3: PRSCN It controls full screen background color as figure shows. It control progressive scan line mode. NOTE: Data slicer operate when OSDCON1.PRSCN(0AE0.3) bit of OSD register is cleared. Namely, it operate interace scan display mode. bit clear than interace mode and bit set than processive mode. R/W R/W R/W R/W R/W R/W FLAR T O BG W FS 3 FS 2 FS 1 FS 0 O LN O SD O N R/W OSDCON2 MSB R/W ADDRESS: 0AE1H INITIAL VALUE: 0000 0000b LSB On/off of all OSD 0 :Off 1 : On On OSD line1 and line2 0 : Off OSD line 1 : On OSD line Font size 0000 : 12 × 16 0001 : 12 × 14 0010 : 12 × 12 0011 : 12 × 10 0111 ~ 0100 : Reseved 1000 : 16 × 18 1111 ~ 1001 : Reserved 12/14 dot background width of 1 OSD character 0 : 12 dot 1 : 14 dot Flash rate when closed caption decoder is used 0 : 32 Vsync is one period 1 : 64 Vsync is one period Figure 17-4 OSD Control Register - 2 OSDCON2 It controls OSD font size. bit 0: OSDON bit 6: OBGW It controls OSD, Full screen background at once. It does not affect anything to Vsync interrupt and OSD interrupt, etc. It controls dot background width. Default width is 12dots. If its value is set, 2 dots (background color) are added both left and right side of character. bit 1: ONL bit 7: FLRAT It controls OSD line1 and line2 on/off. If its value is 1, OSD line is on. It controls OSD flash rate when closed caption decoder is used. Bit clear than 32 Vsync is one period and bit set than 64 Vsync is one period. bit 2 ~ 5: FS0 ~ FS3 68 November 2001 Ver 1.1 HMS81C4x60 W OSDCON3 W W W W W SELCK1 SELCK2 ONDAC POLRG POLYM POLYS W W POLHS POLVS MSB ADDRESS: 0AE2H INITIAL VALUE: 0000 0000b LSB Vsync polarity 0 : Active low 1 : Active high Hsync polarity 0 : Active low 1 : Active high YS polarity 0 : Active low 1 : Active high YM polarity 0 : Active low 1 : Active high RGB pin polarity 0 : Active low 1 : Active high On/Off of RGB DAC 0 : Off 1 : On Select dot clock 00 : Clock from DLL 01 : Clock from LC OSC for EVA only 10 : Clock 1 for test 11 : Reserved Figure 17-5 I/O Polarity(Initial) Register OSDCON3 It controls Hsync/Vsync polarity, YS/YM polarity, RGB polarity, RGB DAC on/off and select dot clock. bit7~0 : SELCK1, SELCK0, ONDAC, POLRG, POLYM, POLYS, POLHS, POLVS W FDWSET W W W W W W W FM AX3 FM AX2 FM AX1 FM AX0 D BFLG F M IN2 FM IN 1 FM IN 0 MSB ADDRESS: 0AE3H INITIAL VALUE: 0111 1010b LSB Field Detection Min. Pointer Field Detection Polarity 0 : Masking between Min. and Max. 1 : Detect between Min. and Max. Field Detection Max. Pointer Field Detection Window: ( {1’b0, (FMIN2 ~ FMIN0)} < hptr[10:7] < (FMAX3 ~ FMAX0)) FDWSET window. FDWSET (Field Detection Window Setting) register detects the begin of Vsync(Vertical Sync.) signal and distinguishs its current field is Even field or Odd field. FMAX[3:0] can divide the region between Hsync(Horizontal Sync.) by 16 windows. You can assume there is 4 bit horizontal counter, for example HCOUNT[3:0](hptr[10 :7]) which count 0~15. The region of FMIN[2:0] ~ FMAX[3:0] is field detection November 2001 Ver 1.1 69 HMS81C4x60 If the start of Vsync is detected at the window, next field is even. Else if Vsync is detected another region of the window, next field is odd. Ex1: VSync(Odd) It means start of Vsync is detected during FMIN[2:0] < HCOUNT[3:0] < FMAX[3:0] and DBFLG value is 0, it distinguish odd field. Ex2: VSync(Even) And, start of Vsync is detected during FMIN[2:0] < HCOUNT[3:0] < FMAX[3:0] and DBFLG value is 1, it distinguish even field. FMIN HSync FMIN[2:0], FMAX[3:0] are compared with the horizontal counter in OSD block. FMAX Figure 17-6 FDWSET detection region R/W EDGECOL R/W R/W R/W R/W R/W R/W R/W EDG2C3 EDG2C2 EDG2C1 EDG2C0 EDG1C3 EDG1C2 EDG1C1 EDG1C0 MSB ADDRESS: 0AE4H INITIAL VALUE: 1000 0111b LSB Edge 1 color of shadow, outline, edge 0000 : Transparency 0001 : Reserved 0010 : white 0011 : Black 0100 : Same as foreground character color 0111 ~ 0101 : Reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 Edge 2 color of shadow, outline, edge 0000 : Transparency 0001 : Reserved 0010 : white 0011 : Black 0100 : Same as foreground character color 0111 ~ 0101 : Reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 Figure 17-7 Character, Window color Register EDGECOL It control shadow color, outline color and edge color. bit 7 ~ bit 0 : EDG1C0,EDG1C1,EDG1C2,EDG1C3 Low 4 bits controls edge 1 shadow, outline color and high 4 bits controls edge 2 shadow, outline color. EDG2C0,EDG2C1,EDG2C2,EDG2C3 70 November 2001 Ver 1.1 HMS81C4x60 W CHEDCL W W W W W W W ADDRESS: 0AE5H INITIAL VALUE: Undefined W IN C 3 W IN C 2 W IN C 1 W IN C 0 SHEC 3 S HEC 2 SH EC 1 SH EC 0 MSB LSB Foreground shadow, outline edge color 0000 : Transparency 0001 : Reserved 0010 : white 0011 : Black 0100 : Same as foreground character color 0111 ~ 0101 : Reserved 1000 : color 0 1001 : color 1 1010 : color 2 1011 : color 3 1100 : color 4 1101 : color 5 1110 : color 6 1111 : color 7 Scroll window background color 0000 : Transparency 0001 : Reserved 0010 : White 0011 : Black 0111 ~ 0100 : Reserved 1000 : Color 0 1001 : Color 1 1010 : Color 2 1011 : Color 3 1100 : Color 4 1101 : Color 5 1110 : Color 6 1111 : Color 7 Figure 17-8 Scroll window color Register CHEDCL scroll window background color. bit 7 ~ bit 0 : SHEC0,SHEC1,SHEC2,SHEC3 Low 4 bits controls scroll window background color and high 4 bits controls foreground shadow outline edge color. WINC0,WINC1,WINC2,WINC3 It controls foreground shadow and outline edge color and R R R R R R R R - - - VLR 4 VLR 3 VLR 2 V LR 1 VLR 0 OSDLN MSB ADDRESS: 0AE6H INITIAL VALUE: ---0 0000H LSB OSD line being displayed 00000 : Not displayed any OSD line yet after Vsync 00001 : 1st line OSD being displayed ....... ....... 11111 : 31st line OSD being displayed Figure 17-9 OSD Line Register OSDLN bit 4 ~ bit 0 : VLR4 ~ VLR0 LHPOS It shows current display OSD line from 1 to 31. W W W W LH7 LH6 LH5 LH4 ADDRESS: 0AE7H INITIAL VALUE: Undefined W W W W LH3 LH2 LH 1 MSB LH 0 LSB OSD Line Horizontal Position 00H~ FFH November 2001 Ver 1.1 71 HMS81C4x60 Figure 17-10 OSD Line Horizontal Position Register It control OSD line horizontal position. Position value from 00h to FFh. LHPOS bit 7 ~ bit 0 : LH7 ~ LH0 W DLLMOD W W W W D C KF4 D C KF3 D C KF2 D C KF1 D C KF0 W W W - - - MSB ADDRESS: 0AE8H INITIAL VALUE: 0000 0000H LSB 1 : OSD test mode 1 : Dll test mode 1 : Reset clock count test mode Dot clock frequency DLLTST R R R R R R R R - - - - - - - - MSB ADDRESS: 0AE9H INITIAL VALUE: --00 0000H LSB Figure 17-11 DLL mode Register DLLMOD Value bit 2 ~ 0 : If you set this bit to 1, the status is changed test mode. bit 7 ~ bit 3 : DCKF4 ~ DCKF0 It control dot clock frequency. Dot clock frequency is as below. Value Frequency DCKF4 DCKF4 DCKF4 DCKF4 DCKF4 0 1 0 1 1 21.33MHz 0 1 1 0 0 19.69MHz 0 1 1 0 1 18.29MHz 0 1 1 1 0 17.07MHz 0 1 1 1 1 16.00MHz Frequency 1 0 0 0 0 15.05MHz DCKF4 DCKF4 DCKF4 DCKF4 DCKF4 0 0 0 0 0 stop dll clock 1 0 0 0 1 14.22MHz 0 0 0 0 1 reserved 1 0 0 1 0 13.47MHz 0 0 0 1 0 reserved 1 0 0 1 1 12.80MHz 0 0 0 1 1 64.00MHz 1 0 1 0 0 12.19MHz 0 0 1 0 0 51.20MHz 1 0 1 0 1 11.63MHz 0 0 1 0 1 42.67MHz 1 0 1 1 0 11.13MHz 0 0 1 1 0 36.57MHz 1 0 1 1 1 10.67MHz 0 0 1 1 1 32.00MHz 1 1 0 0 0 reserved 0 1 0 0 0 28.44MHz 1 1 0 0 1 reserved 0 1 0 0 1 25.60MHz 0 1 0 1 0 23.27MHz 72 Table 17-1 Dot Clock Frequency (fex=4Mhz) November 2001 Ver 1.1 HMS81C4x60 W L1ATTR W W W W W W O BG H1 W DS L1 EN O L1 ENSH 1 C SZ11 C SZ10 FSC 1 MSB W L1V8 ADDRESS: 0AEAH INITIAL VALUE: 0000 0000H LSB OSD line 1 vertical position (bit 8) Foreground shadow or outline color select 0 : Edge 1 color 1 : Edge 2 color Size of character 00 : Normal 01 : 1.5 times 10 : 2 times 11 : Reserved Enable/disable of shadow 0 : Disable 1 : Enable Enable/disable of outline 0 : Disable 1 : Enable Width of shadow, outline 0 : 1 dot 1 : Proportional to character size OSD chraracter background height 0 : font height 1 : font height + 2 Figure 17-12 OSD line 1 attribute register L1ATTR bit 4: ENSH1 bit 0 : L1V8 It enables line 1’s character(foreground) shadow. It is equivalent to L1VPOS’s most significant bit(bit 8). See more details in L1VPOS. bit 5: ENOL1 bit 1: FSC1 It selects character outline and shadow color. If it is 1, it select EDGE2 color of EDGECOL register. Or not, it select EDGE1 color. According to EDGECOL register and this bit character and shadow colors are selected simulteneously bit 3~2: CSZ11~CSZ10 It controls OSD character’s size ( normal, 1.5 times, 2 times). You can use this register and DDCLK, DLINE bit, horizontal / vertical size can be controlled (x1, x1.5, x2). November 2001 Ver 1.1 It enables line 1’s character(foreground) outline. bit 6: WDSL1 It shows thickness of line 1’s shadow and outline.This bit is set than one dot and bit clear is proportional to character size. If only character size is 2 times, 2 times per vertically and horizontally. In case 1 dot width would be enable. bit 7: OBGH1 It controls character’s background height. Default height is 16dots. If its value is set, 2 dots (background color) are added both top and bottom side of character. 73 HMS81C4x60 L1EATR W W W - - - W W W W W ADDRESS: 0AEBH INITIAL VALUE: Undefined SEL1U LSEL1O W SEL1FL SEL1IT S EL1SH MSB LSB Select shadow/round of line 1 each character when VRAM.ENRND is set. 0 : round character 1 : shadow character Select italic/upper edge of line 1 each character. Italic character can be displayed only when character size is 1, 1.5 times, and VRAM.BSU is set. 0 : Upper edge character 1 : Italic character Select flash/left edge of line 1 character when VRAM.BSL is set. 0 : Left edge character 1 : Flash Select OSD/window when display. If this bit is 0, background window would be displayed. 0 : Background window selected 1 : OSD line selected Select underline /lower edge of line 1 each character 0 : Underline 1 : Lower edge line L1EATR L1ATTR. It shows OSD line 1 extend attribute register. ADDRESS: 0AEEH INITIAL VALUE: Undefined W W W W L2EATR L1VPOS W W W W LIV7 LIV6 LIV5 LIV4 ADDRESS: 0AECH INITIAL VALUE: Undefined W W W W LIV3 LIV2 LIV1 MSB LIV0 W W W - - - W SEL2ULSEL2O W SEL2F L SEL2IT SEL2SH MSB LSB LSB OSD line 1 vertical position 000H~ 1FFH L2EATR It shows OSD line 2’s extened attribute register. L1VPOS It shows OSD line 1’s vertical position in 9bit format (LIV8 + L1VPOS, 000 ~ 1FFH). L2ATTR W W W W ADDRESS: 0AEDH INITIAL VALUE: Undefined W W W W O BG H 2 W D SL2 EN O L2 EN SH 2 C SZ 22 C SZ 21 F SC 2 MSB ADDRESS: 0AEFH INITIAL VALUE: Undefined W W W W L2VPOS W W W W L2V7 L2V6 L2V5 L2V4 MSB L2V3 L2V2 L2V1 L2V0 LSB L2V2 LSB L2VPOS It shows OSD line 2’s vertical position. Its function is the same as L1VPOS. L2ATTR It shows OSD line 2’s attributes. Its function is the same as 74 November 2001 Ver 1.1 HMS81C4x60 WINSH W W W W ADDRESS: 0AF0H INITIAL VALUE: Undefined W W W W VCNT R W INSH7 W INSH6 W INSH5 W INSH4 W INSH3 W INSH2 W INSH1 W INSH0 MSB LSB R R R ADDRESS: 0AF4H INITIAL VALUE: Undefined R R R R VC N T6 VC N T6 VC N T6 VC N T6 VC N T6 VC N T6 VCN T 6 F LD ID MSB LSB Current scan line line vertical position [6:0] OSD scroll window start horizontal position Current display field 0 : Odd field 1 : Even field WINSH It shows OSD scroll window start horizontal position. VCNT It shows Vsync count register and counted by pixel clock. WINSY W W W W ADDRESS: 0AF1H INITIAL VALUE: Undefined W W W W VCNT counter clock start at Vsync start edge. W INSY7 W INSY6 W INSY5 W INSY4 W INSY3 W INSY2 W INSY1 W INSY0 MSB LSB OSD scroll window start vertical position HCNT R R R R ADDRESS: 0AF5H INITIAL VALUE: Undefined R R R R H C NT 7 H C NT 6 H C NT 5 H C NT 4 H CN T 3 H CN T 2 H C N T1 H C N T0 WINSY MSB LSB Horizontal counter hptr[10:3] It shows OSD scroll window start vertical position. HCNT WINEH W W W W ADDRESS: 0AF2H INITIAL VALUE: Undefined W W W W W INEH7 W INEH6 W INEH5 W INEH4 W INEH3 W INEH2 W INEH1 W INEH0 MSB It shows Hsync count register and counted by pixel clock. HCNT counter clock start at Hsync start edge. LSB OSD scroll window end horizontal position CULTAD WINEH It shows OSD scroll window end horizontal position. W W W W - - - - ADDRESS: 0AF9H INITIAL VALUE: Undefined W W W W - - MSB F IL15 LSB Normal/Test mode select 00 : Normal mode 01 ~ 11 : Test mode WINEY W W W W ADDRESS: 0AF3H INITIAL VALUE: Undefined W W W W 1.5 times character mode 0 : line double mode 1.5 times 1 : field interleaving mode 1.5 times W INEY7 W INEY6 W INEY5 W INEY4 W INEY3 W INEY2 W INEY1 W INEY0 MSB LSB OSD scroll window end vertical position CULTAD It shows normal and test mode and 1.5 times mode. WINEY It shows OSD scroll window end vertical position. November 2001 Ver 1.1 75 HMS81C4x60 17.3 VRAM VRAM contains a OSD line buffer, 48 character’s attributes. Bit No. Name Function Each character’s attribute is constructed with 3 bytes, it contains color data for background, shadow, outline, character and character number ( 000H ~ 1FFH, 512 characters ), etc. 0B BSCDR Edge color of lower and right background shadow edge 0 : edge 1 color 1 : edge 2 color BSU Background shadow upper eddge control/italic depend on LxEATR.SELxIT 0 : disable 1 : enable if(LxEATR.SELxIT == 0) background shadow upper edge enable else(LxEATR.SELxIT == 1) italic enable BSD Background shadow lower edge control/underline depend on LxEATR.SELxUL 0 : disable 1 : enable if(LxEATR.SELxUL == 0) background shadow lower edge enable else(LxEATR.SELxUL == 1)underline enable 0E BSL Background shadoww left edge control/flash(blInking) depend on LxEATR.SELxFL 0 : disable 1 : enable if(LxEATR.SELxFL == 0) background shadow left edge enable else(LxEATR.SELxFL == 1) flash(flicking) enable 0F BSR Background shadow right edge control 0 : disable 1 : enable 10~13 FC3 ~FC0 Foreground color for character (11 colors) 14~17 BC3 ~BC0 Background color for character (12 colors) Line No. 1 2 Character add. No. Address (bit 47~0) Hexa decimal 1 A80 A40 A00 2 A81 A41 A01 3 A82 A42 A02 : : : : 46 AAD A6D A2D 47 AAE A6E A2E 48 AAF A6F A2F 1 B80 B40 B00 2 B81 B41 B01 3 B82 B42 B02 : : : : 46 BAD B6D B2D 47 BAE B6E B2E 48 BAF B6F B2F 0C 0D Table 17-2 VRAM memory map Bit No. Name 00~08 CG8 ~CG0 Character font code 1FFh ~ 000h 09 ENRND Round enable/disable 0 : disable 1 : enable 0A BSCUL Edge color of upper and left background shadow edge 0 : edge 1 color 1 : edge 2 color 76 Function Table 17-3 VRAM attribute November 2001 Ver 1.1 HMS81C4x60 RESET VALUE: Undefined Composition of VRAM LINE 1 (page A) LINE 2 (page B) CG 8 CG7 0A80 0A81 0A82 : 0AAF 0A40 0A41 0A42 : 0A6F 0A00 Character 1 Attr. 0A01 Character 2 Attr. 0A02 Character 3 Attr. : 0A2F Character 48 Attr. 0B80 0B81 0B82 : 0BAF 0B40 0B41 0B42 : 0B6F 0B00 0B01 0B02 : 0B2F CG6 CG5 CG4 CG3 CG2 Character 1 Attr. Character 2 Attr. Character 3 Attr. Character 48 Attr. CG1 CG 0 Character font address (512 fonts) BSR BSL BSD BSU BSC D R B SCU L EN R N D CG 8 see table 17-3 VRAM attribute BC 3 BC 2 BC 1 BC 0 FC 3 FC 2 FC1 FC 0 Character color select (11 characters) 0000 : Transparency 0001 : Reserved 0010 : White 0011 : Black 0111 ~ 0100 : Reserved 1000 : Color 0 1001 : Color 1 1010 : Color 2 1011 : Color 3 1100 : Color 4 1101 : Color 5 1110 : Color 6 1111 : Color 7 Background color select (12 characters) 0000 : Transparency 0001 : Reserved 0010 : White 0011 : Black 0111 ~ 0100 : Reserved 1000 : Color 0 1001 : Color 1 1010 : Color 2 1011 : Color 3 1100 : Color 4 1101 : Color 5 1110 : Color 6 1111 : Color 7 November 2001 Ver 1.1 77 HMS81C4x60 17.4 Character ROM The HMS81C4x60 Character ROM are used 512 types of Font Dot Pattern data. As displayed one character, need 12 × 10 ~ 16 × 18bits Dot Pattern data. 5. A character’s address and dot position in font ROM is described in Figure 17-13. 1. Each horizontal data (12dots) needs 2bytes ROM. 2. One character is constructed with 16 horizontal data to vertically. As a result, one character needs 32bytes (2 × 16 bytes). 3. HMS81C4x60 contains 512 characters. Total Font ROM memory size is calculated as 16,384bytes ( 32bytes / character × 512 characters ) 4. Font ROM memory is located from 10000H ~ 17FFFH, this memory can not be accessed by user program. Address range Charact er code Upper 8bit Lower 8bit 000H 14000H ~ 14011H 10000H ~ 10011H 001H 14020H ~ 14031H 10020H ~ 10031H 002H 14040H ~ 14051H 10040H ~ 10051H : : : xyzH (14000H + xyz0H) ~ (14000H + 2*xyzFH) (10000H + xyz0H) ~ (10000H + 2*xyzFH) : : : 1FDH 17FA0H ~ 17FB1H 13FA0H ~ 13FD1H 1FEH 17FC0H ~ 17FD1H 13FC0H ~ 13FD1H 1FFH 17FE0H ~ 17FF1H 13FE0H ~ 13FF1H 16 × 18 Left address 14060 14061 14062 14063 14064 14065 14066 14067 14068 14069 1406A 1406B 1406C 1406D 1406E 1406F 14070 14071 14072 14073 14074 14075 14076 14077 14078 14079 1407A 1407B 1407C 1407D 1407E 1407F 12 × 14 Right address 10060 10061 10062 10063 10064 10065 10066 10067 10068 10069 1006A 1006B 1006C 1006D 1006E 1006F 10070 10071 10072 10073 10074 10075 10076 10077 10078 10079 1007A 1007B 1007C 1007D 1007E 1007F Figure 17-13 Character Dot Pattern Table 17-4 Font ROM memory map 78 November 2001 Ver 1.1 HMS81C4x60 17.5 Color Look Up Table [Example] Color data table RESET VALUE : Undefined W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 RED0 <0AD0H> R07 R60 R50 R40 R30 R20 R10 R00 RED1 <0AD1H> R71 R62 R51 R41 R31 R21 R11 R01 RED2 <0AD2H> R72 R62 R52 R42 R32 R22 R12 R02 GREEN0 <0AD3H> G70 G60 G50 G40 G30 G20 G10 G00 GREEN1 <0AD4H> G71 G61 G51 G41 G31 G21 G11 G01 GREEN2 <0AD5H> G72 G62 G52 G42 G32 G22 G12 G02 BLUE0 <0AD6H> B70 B60 B50 B40 B30 B20 B10 B00 BLUE1 <0AD7H> B71 B61 B51 B41 B31 B21 B11 B01 BLUE2 <0AD8H> B72 B62 B52 B42 B32 B22 B12 B02 Composition of color 7 Composition of color 6 Composition of color 5 Composition of color 4 Color_example_table: db 0000_0000b ;color db 0000_0011b ;color db 0010_1011b ;color ; db 0000_0000b ;color db 0000_0101b ;color db 0100_1101b ;color ; db 0000_0000b ;color db 1001_0001b ;color db 1111_0001b 0 = Gray 1 = Red 2 = Green 3 = Yellow 4 = Blue 5 = Magenta 6 = Cyan 7 = half blue Composition of color 0 Composition of color 1 Composition of color 2 Composition of color 3 Red : {R02,R01,R00} Green : {G02,G01,G00} Blue : {B02,B01,B00} Figure 17-14 Color look up table November 2001 Ver 1.1 79 HMS81C4x60 18. DATA SLICER HMS81C4x60 supports Closed Caption decoding standard with 0.5MHz data rate. Also it can capture 4 horizontal lines information per frame, because it has 4 horozontal lines capture memory. It is able to select even or odd field at one field interval. Data Slicer captures caption information from line 21 in vertical blanking interval of CVBS, and stores these data to buffer memory. 18.1 Data Slicer Circuit Figure 18-1 shown the data slicer circuit. CVBS signal is entered to CVBS pin via 0.47uF capacitor. The black level of signal is about 2V. SCAP pin is connected to external 560pF capacitor which adjust the referance voltage of comparator. Its slicer level is adapted to input signal. SCAP 560pF CVBS 0.47uF HMS81C4x60 Figure 18-1 Data Slicer Circuit 18.2 Configuration of Data Slicer Figure 18-2 shows the block diagram of the Data Slicer. Run-in key timing Sync-tip timing Timing Controller CPU control Data capture timing CVBS Data Filter Memory Interface Controller Slicer Memory Reference Voltage Figure 18-2 Data Slicer Block Diagram This data slicer block separates caption information from CVBS signal. Data slicer composes high speed comparator and on-chip low pass filter. The output data of comparator 80 is stored in memory through the filter and memory interface controller, which should be decoded to caption data by software. Slicer memory addressed 600h ~ 6FFh. November 2001 Ver 1.1 HMS81C4x60 18.3 Slicer Registers Slicer Control Register which select operating frequency of the slicer, slicer decoding method and switch slicer on/off. Slicer Control Register is the specific control register, R/W SLCON - R/W R/W R IKTST SELC K R/W R/W - - R/W R/W R/W D EM E1 D EM E0 S LO N MSB ADDRESS: 0BE0H INITIAL VALUE: 0000 0000b LSB Slicer On/Off 0 : Slicer Off 1 : Slicer On Decoding Method 00 : Normal 01 : Reserved 10 : Reserved 11 : Reversed Slicer Clock 0 : Normal clock 1 : Test clock RIK slicer test mode 00 : Normal clock 01 : Reserved 10 : Reserved 11 : Reserved Figure 18-3 Slicer Control Register Slicer Information Register 0 buffer of line 0 and slicer line 0 position. Also it is used to select line number in Vertical blanking interval. Slicer Information Register 0 selects even or odd field W W SLINF0 W W W W SLP O S 0 W W LFC 0 LF C0 MSB ADDRESS: 0BE1H INITIAL VALUE: 0000 0000b LSB Line0 enable 00 : disable all line 0 01 : reserved 10 : reserved 11 : enable all line 0 (even and odd field) Slicer line 0 position Figure 18-4 Slicer Information Register 0 Slicer Information Register 1 buffer of line 1 and slicer line 1 position. Also it is used to select line number in Vertical blanking interval. Slicer Information Register 1 selects even or odd field W SLINF1 W W W SLP O S 1 MSB W W W W LFC 1 LF C1 ADDRESS: 0BE2H INITIAL VALUE: 0000 0000b LSB Line 1 Field 00 : disable all line 1 01 : reserved 10 : reserved 11 : enable all line 1 (even and odd field) Slicer line 1 position Figure 18-5 Slicer Information Register 1 November 2001 Ver 1.1 81 HMS81C4x60 Run-in key Start/End position Register Both timmings are counted up by 8MHz clock. The referance voltage of comparator is charged by external signal during this time interval. Figure 18-6 and Figure 18-7 shows the RIK register’s configure. RIKST points the start postion of run-in key, it is delayed from start edge of Hsync. RIKED points the end position of run-in key, it is also delayed from start edge of Hsync. W RIKST W W W W W W W R IKST7 R IKST6 R IKST5 R IKST4 R IKST3 R IKST2 R IKST1 RIKST 0 MSB ADDRESS: 0BE3H INITIAL VALUE: XXXX XXXXb LSB Run-in key window start position Figure 18-6 Run-in key Start Position Register W RIKED W W W W W W W R IKED 7 R IKED 6 R IKED 5 R IKED 4 R IKED 3 R IKED 2 RIKED 1 R IKE D0 MSB ADDRESS: 0BE4H INITIAL VALUE: XXXX XXXXb LSB Run-in key window end position Figure 18-7 Run-in key End Position Register Sync Start/End Position Register 16MHz clock. Figure 18-8 and Figure 18-9 shows the Sync-tip register’s configure. Sync Start and End position Register are used to make Sync tip window. Both timmings are counted up by W SNCST W W W W W W W SNCST7 SNCST6 SNCST5 SNCST4 SNCST3 SNCST2 SNCST1 SNCST0 MSB ADDRESS: 0BE7H INITIAL VALUE: XXXX XXXXb LSB Sync-tip window start position Figure 18-8 Sync-tip start position register W SNCED W W W W W W W SNCED7 SNCED6 SNCED5 SNCED4 SNCED3 SNCED2 SNCED1 SNCED0 MSB ADDRESS: 0BE8H INITIAL VALUE: XXXX XXXXb LSB Sync-tip window end position Figure 18-9 Sync-tip end position register 82 November 2001 Ver 1.1 HMS81C4x60 18.4 Data Sampling Line 21 Closed Caption signal Interrupt occurrence Figure 18-10 shows the closed caption signal. The signal composes color burst, clock run-in, start bit(001), 16bit ASCII data with 2 parity bit. Sliced raw datas are sampled by 4MHz frequency. The slicer interrupt is occured after writing the sliced two lines data to memory buffer. [ CAPTION DATA ] CLOCK RU N IN TW O (7 BIT + PARITY ) CHARACTERS ( DATA ) program color burst 12.91us START BIT(001) 33.76us 3.972us 51.26us 61.342us Signal timing Figure 18-11 shows an example of variable signals, which includes Vsync(vertical Sync.), Hsync(horizontal Sync.), CVBS(composit video in), SCAP(slicer capacitor), Run-in key and Sync tip. Line 21 closed caption signal run after Vsync interrupt. The signal’s black(base) level voltage is charged on Sync-tip switch-on period, and the referance voltage of comparator is charged on RIK switch-on perid. Because RIK time is related to SCAP voltage(comparator referance voltage or slicer level) which is charged by clock run-in signal, user can adjust the slicer level by RIK time. The sliced data is stored to RAM buffer. (0600h~ 06FFh) Figure 18-10 Closed caption signal Address assign Table 18-1 shows the map of assigned buffer memory. Setting Address Even Field 0600h ~ 063Fh Odd Field 0640h ~ 067Fh Even Field 0680h ~ 06BFh Odd Field 06C0h ~ 06FFh First Line Secont Line Table 18-1 Address assign November 2001 Ver 1.1 83 HMS81C4x60 5V 1 Vsync 5V 2 1 Hsync cycle 5V Hsync 5V 2.5V 2V CVBS line 21 signal 2.2V 0.5V SCAP Slicer capacitor charging level 5V Run-in key start/stop timming 3 RIK 0V 5V Sync-tip start/stop timming 4 Sync_tip 0V Figure 18-11 Signal timing [Example] Initializing slicer register. CCD_INIT: LDM LDM LDM LDM LDM LDM LDM 84 SLINF0,#0011_0011b SLINF1,#0000_0000b RIKST,#01 RIKED,#8Ch SNCST,#01 SNCED,#58h SLCON,#01h ; ; ; ; ; ; ; slicer line 21 no field run-in key start : 1 -> 0.125uS(8MHz) run-in key end : 8ch -> 17.5uS(8MHz) sync tip start : 1 -> 0.0625uS(16MHz) sync tip end : 58h -> 5.5uS(16MHz) normal clock, 16MHz, slicer start November 2001 Ver 1.1 HMS81C4x60 19. I2C Bus Interface The I2C Bus interface circuit is shown in Figure 19-1. This multi-master I2C Bus interface circuit consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. The multi-master I2C Bus interface is a serial communications circuit, conforming to the Phlips I2C Bus data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. ICAR [D8H] ICDR [D9H] The more details about registers are shown Figure 19-2~ Figure 19-5. SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 RWb D7 D6 D5 D4 D3 D2 D1 Address comparator Interrupt Generation Circuit IFI2CR D0 SDA Data Control Circuit Noise Elimination Circuit BB Circuit ICSR [00DAH] MST TRX BB PIN AL AD0 ADRb LRB AL Circuit ICCR [00DBH] B SEL1 B SEL1 ACKb ESO CCR3 CCR2 CCR1 CCR0 SCL Clock Control Circuit Noise Elimination Circuit Clock Source Clock division Figure 19-1 Block Diagram of multi-master I2C circuit Control I2C address register The HMS81C4x60 contains two I2C Bus interface modules. It supports multi-master function, so it contains arbitration lost detection, synchronization function,etc. It contains slave address (7bit) which is used during slave mode and Read/Write bit. ITEM Format Communication mode Function Philips I2C standard 7bit addressing format Bit 7 ~ 1 : Slave address 6~0 Note: Bit 7~1 (SAD6~0) store slave address. The address data transmitted from the master is compared with the contents of these bits. Master transmitter Master receiver Slave transmitter Slave receiver November 2001 Ver 1.1 85 HMS81C4x60 The more details about its bits are shown Table 19-1. ADDRESS : 00D8H RESET VALUE : 0000 0000b RW ICAR RW RW RW RW RW RW R Bit No. Name Function MST TRX 00: Slave / Receiver mode 01: Slave / Transmitter mode 10: Master / Receiver mode 11: Master / Transmitter mode MST is cleared when - After reset. - After the arbitration lost is occured and 1 byte data transmission is finished. - After stop condition is detected. - When start condition is disabled by start condition duplication preventation function. TRX is cleared when - After reset. - When arbitration lost or stop condition is occured . - When MST is ‘0’, and start condition or ACK non-return mode is detected. BB BB(Bus busy)bit is 1 during bus is busy. This bit can be written by S/W. its value is ‘1’ by start condition, and cleared by stop condition. 4 PIN PIN(Pending Interrupt Not)bit is interrupt request bit. If I2C interrupt request is issued, its value is 0. PIN is cleared when - After 1 byte trasmission / receive is finished. PIN is set when - After reset. - After write instruction is excuted into I2C data shift register ICDR. - When PIN bit low, the output of SCL is pulled down, So if you want to release SCL, you must perform write instruction CDR. 3 AL Arbitration lost detection flag. If arbitration lost is detected, AL=1, or 0. 2 AD0 General call detection flag. If general call is detected, AD0=1, or not 0. * General call : If received address is all ‘0’ . it is called general call. 1 ADRb SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 RWb Slave address Read/Write Bit Figure 19-2 I2C address Register 7 6 I2C data shift register [ICDR] The I2C data shift register is an 8bit shift register to store received data and write transmit data. When transmit data is written into this register, it is transfered to the outside from bit7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I 2 C control register (address 00DCH) is “1”. The bit counter is reset by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value. 5 ADDRESS : 00D9H RESET VALUE : 0000 0000b ICDR RW RW RW RW RW RW RW RW D7 D6 D5 D4 D3 D2 D1 D0 S hift left 1-bit ea ch S C L Figure 19-3 Data shift register I2C status register The I2C status register controls the I2C Bus interface status. The low-order 4bits are read only bits and the high-order 4bits can be read out and written to. 86 Address represent flag 0 : current contents is address 1 : current contents is data November 2001 Ver 1.1 HMS81C4x60 Bit No. Name 0 LRB Function Last received bit. it is used for receive confirmation. If ACK is returned, LRB=0, or not 1. 7 6 Table 19-1 Bit function ADDRESS : 00DAH RESET VALUE : 0001 0000b ICSR Bit No. RW RW RW RW R R R R MST TRX BB PIN AL AD0 ADRb LRB Name Function I2C connection control. 00: No connection BSEL1 BSEL0 01: SCL0, SDA0 10: SCL1, SDA1 11: SCL0, SDA0, SCL1, SDA1 5 ACK If acknowlege clock is returned, this bit is 0, or not 1. 4 ESO I2C Bus interface use enable flag 0: Disabled 1: Enabled Figure 19-4 I2C status Register SCL Frequency selection SCL frequency = fex / (12 * CCR) I2C control register Value It controls communication data format. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 It controls SCL mode, SCL frequency, etc. It contains 8bit data to transmit to external device when trasmitter mode, or received 8bit data from external device when receive mode. ADDRESS : 00DBH RESET VALUE : 0000 0000b RW ICCR RW RW BSEL1 BSEL0 ACKb RW ESO RW RW RW RW CCR3 CCR2 CCR1 CCR0 Figure 19-5 I2C control Register 3 2 1 0 CCR3 CCR2 CCR1 CCR0 fex = 4MHz Not allowed Not allowed 333.3KHz 222.2KHz 166.6KHz 133.3KHz 111.1KHz 95.2KHz 83.3KHz 74.1KHz 66.6KHz 60.6KHz 55.5KHz 51.3KHz 47.6KHz 44.4KHz Table 19-2 Bit function SCL PIN I2C Request Figure 19-6 Interrupt request signal generation timing November 2001 Ver 1.1 87 HMS81C4x60 START condition generation STOP condition generation When the ESO bit of the I2C control register (00DBH) is “1”, writing to the I2C status register will generate START condition. Refer to Figure 19-7 for the START condition generation timing diagram. Writing ‘C0h’ to ICSR will generate a stop condition, when ESO (ICCR bit3) is ‘1’ ICSR write signal (I2C status reg.) SCL tSETUP tHOLD ICSR write signal (I2C status reg.) SDA SCL tSETUP tBB tHOLD BB (Bus busy) flag SDA tBB tSETUP : Setup time tHOLD : Hold time tBB : Set time for BB BB (Bus busy) flag tSETUP : Setup time tHOLD : Hold time tBB : Set time for BB Figure 19-7 START condition generation timing RESTART condition generation RESTART condition’s setting sequence is as followings. 1. Write 020H to I2C status register (ICSR, 00DAH) 2. Write slave address to I2C data shift register (ICDR, 00D9H) 3. Write 0F0H to I2C status register (ICSR, 00DAH) 88 Figure 19-8 STOP condition generating timing diagram START / STOP condition generation time is shown Table 19-3. ITEM Timing SPEC. Setup time ( tSETUP ) 3.3uS (n=20cycles) Hold time ( tHOLD ) 3.3uS (n=20cycles) Set/Reset time for BB flag ( tBB ) 3.0uS (n=18cycles) Table 19-3 Example time ( fex=4MHz ) November 2001 Ver 1.1 HMS81C4x60 START / STOP condition detect Figure 19-9 START / STOP condition detection timing START / STOP condition is detected when Table 19-3 is satisfied. START / STOP detection time is showed Table 19-4. ITEM Timing SPEC. SCL release time > 2.0uS (n=12cycles) Setup time > 1.0uS (n=6cycles) Hold time > 1.0uS (n=6cycles) SCL release time SCL tSETUP tHOLD Table 19-4 Example time ( fex=4MHz ) SDA (START) Address data communication SDA (STOP) The first transmitted data from master is compared with I2C address register (ICAR, 00D8H). At this time R/W is not compared but it determines next data operation. i.e, transmitting or receiving data tSETUP : Setup time tHOLD : Hold time Master -> Slave (with 7bit address) START Slave addr. ACK 7bit R/W (“0”) Data ACK Data ACK STOP /ACK Slave -> Master (with 7bit address) Data block from master to slave Data block from slave to master START Slave addr. ACK 7bit R/W (“1”) Data ACK Data ACK STOP Figure 19-10 Address data communication format November 2001 Ver 1.1 89 HMS81C4x60 20. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. 6-bit up-counter Clock source (BIT overflow : IFBIT) WDT clear comparator IFWDT Watchdog Timer interrupt 6-bit compare data 6 WDTCL[bit6] to reset CPU enable WDTR[bit5~0] WDTON[bit5] WDTR [00D7H] Watchdog Timer Register CKCTLR [00D6H] Clock control Register Figure 20-1 Block Diagram of Watchdog Timer Watchdog Timer Control Figure 20-2 shows the watchdog timer control register. The watchdog timer is automatically disabled after reset. The CPU malfunction is detected as setting the detection time, selecting output, and clearing the binary counter. Repeatedly clearing the binary counter within the setting detection time. If the malfunction occurs for any cause, the watchdog timer output will become active at the rising overflow from the binary counters unless the binary counter are cleared. At this time, when WDTON=1 a reset is generated, which drives the RESET pin low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (IFWDT) is generated. ADDRESS : 00D6H RESET VALUE : 0000 0000b W WDT ON CKCTLR W W W W R ENP BTCL BTS2 BTS1 BTS0 CK Watchdog timer On/Off control 0: Normal 6bit timer, Watchdog off 1: Watchdog timer ADDRESS : 00D7H RESET VALUE : -011 1111b W WDTR WDT CL W W W W W D TR 5 W ~ W 0 Slave address Watchdog timer Clear 0: Watchdog timer free run 1: Watchdog timer clear and free run Automatically cleared this bit after 1cycle Figure 20-2 Watchdog timer register 90 November 2001 Ver 1.1 HMS81C4x60 Example: Sets the watchdog timer detection time Within WDT detection time Within WDT detection time LDM WDTR,#01??????b LDM CKCTLR,#00111???b ;Clear Counter and set value(??????b) ;You have to set WDTR first, for prevent unpredictable interrupt ;when you set WDTON bit. ;Select clock source(???b) and WDTON=1 LDM : : : : LDM : : : : LDM WDTR,#01??????b ;Clear counter WDTR,#01??????b ;Clear counter WDTR,#01??????b ;Clear counter Enable and Disable Watchdog Watchdog timer is enabled by setting WDTON (bit 5 in CKTCLR) to "1". WDTON is initialized to "0" during reset, WDTON should be set to "1" to operate after reset is released. Example: 6-bit timer interrupt setting up. LDX TXSP LDM LDM : : Example: Enables watchdog timer reset : LDM : : CKTCLR,#001?????b ;WDTON←1 The watchdog timer is disabled by clearing bit 5 (WDTON) of CKTCLR. Watchdog Timer Interrupt The watchdog timer can also be used as a simple 6-bit timer by clearing bit 5 (WDTON) of CKTCLR. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below. T = WDTR × Interval of BIT The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source. November 2001 Ver 1.1 #03FH ;SP ← 3F CKTCLR,#000?????b ;WDTON←0 WDTR,#01??????b ;WDTCL←0 Refer table and see BIT timer (). CKCTLR BTS2~0 BIT input clock Watchdog timer input clock IFWDT cycle 000b PS4 (4uS) 1,024uS 32,256uS 001b PS5 (8uS) 2,028uS 64,512uS 010b PS6 (16uS) 4,096uS 129,024uS 011b PS7 (32uS) 8,192uS 258,048uS 100b PS8 (64uS) 16,384uS 516,096uS 101b PS9 (128uS) 32,768uS 1,032,192uS 110b PS10 (256uS) 65,536uS 2,064,384uS 111b PS11 (512uS) 131,072uS 4,128,768uS Table 20-1 Watchdog timer MAX. cycle (Ex:fex=4MHz) 91 HMS81C4x60 Source clock BIT overflow Binary-counter 2 1 3 0 1 2 3 0 Counter Clear WDTR 3 n Match Detect IFWDT interrupt WDTR ← "0100_0011b" WDT reset reset Figure 20-3 Watchdog timer Timing Minimizing Current Consumption It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn’t flow. But input voltage level should be VSS or VDD. Be careful 92 that if unspecified voltage, i.e. if unfirmed voltage level is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. See Figure 20-4. November 2001 Ver 1.1 HMS81C4x60 INPUT PIN VDD OUTPUT PIN VDD ON internal pull-up VDD OPEN OFF ON O O OFF i i VDD GND GND VDD X OPEN Weak pull-up current flows ON X OFF O O In the left case, much current flows from port to GND. VDD INPUT PIN OUTPUT PIN VDD O OPEN VDD L i=0 ON i OFF L OFF ON i GND GND Very weak current flows X i=0 GND O X i=0 O In the left case, Tr. base current flows from port to GND. To avoid power consumption, low output to the port . When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption. Figure 20-4 Application example of Port under Power Consumption November 2001 Ver 1.1 93 HMS81C4x60 21. OSCILLATOR CIRCUIT The HMS81C4x60 has two oscillation circuits internally. XIN and XOUT are input and output for main frequency and OSC1 and OSC2 are input and output for OSD(On Screen display) frequency, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 21-1 . Recommend C1 fc (MHz) XOUT 4 C2 fc (MHz) C1 & C2 (pF) 15 XIN VSS Crystal Oscillator Open External Clock XOUT XIN External Oscillator Figure 21-1 Oscillation Circuit Oscillation components have their own characteristics, so user should consult the component manufacturers for appropriate values of external components. In addition, see Figure 21-2 for the layout of the crystal. Note: Minimize the wiring length. Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground to any ground pattern where high current is present. Do not fetch signals from the oscillator. XOUT XIN Figure 21-2 Layout example of Oscillator PCB circuit 94 November 2001 Ver 1.1 HMS81C4x60 22. RESET The HMS81C4x60 have two types of reset generation procedures; one is an external reset input, other is a watch-dog On-chip Hardware Program counter RAM page register G-flag of PSW Initial Value PC timer reset. Table 22-1 shows on-chip hardware initialization by reset action. On-chip Hardware Initial Value (FFFFH) - (FFFEH) Peripheral clock Off 00H Watchdog timer Disable 0 Control registers Refer to Table 8-1 on page 22 DPGR G Table 22-1 Initializing Internal Status by Reset Action 22.1 External Reset Input The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 22-2 . A connecting for simple power-on-reset is shown in Figure 22-1 . VDD RESET Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. + − GND When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. Figure 22-1 Simple Power-on-Reset Circuit 1 3 ? ? 4 5 6 7 ~ ~ RESET ~ ~ Fetch ~ ~ ? ? FFFE FFFF Start ~ ~ ~ ~ ? ? ? ? FE ADL ADH OP ~ ~ DATA BUS 2 ~ ~ Oscillator (XIN pin) ADDRESS BUS MCU Stabilization Time tST = 62.5mS at 4.19MHz RESET Process Step tST = 1 fMAIN ÷1024 MAIN PROGRAM x 256 Figure 22-2 Timing Diagram after RESET November 2001 Ver 1.1 95 HMS81C4x60 22.2 Watchdog Timer Reset Refer to “20. WATCHDOG TIMER” on page 90. 96 November 2001 Ver 1.1 HMS81C4x60 23. OTP Programming 23.1 HMS87C4x60 OTP Programming User can burn out HMS87C4x60 OTP through the general Gang programmer using special ROM writer. In Devleopment tool package auxiliary, HMS87C4x60 has ROM writer socket. HMS87C4x60 have two ROM memory areas. One is Program ROM memory and the other is Font ROM memory. Program ROM area is from 1000h to FFFFh Font ROM area is from 10000h to 17FFFh. Blank Check Program Writing There are two kind of OTP file. One is program OTP file(***.OTP) and the other is font OTP file(***.FNT). You can make each file through ASMLINKER.exe and OSDFONT.exe respectively. All OTP file is Motolora Sformat. You can burn the program file and font file respectively or together. To burn program file and font file respectively, refer following procedure 1. Make program OTP file and font OTP file repectively. 1000H 2. Burn program OTP file(Set chip target address 1000h ~ FFFFh) Program Memory 3. Burn font OTP file(Set chip target address 10000h ~17FFFh) To burn program file and font file together, refer following procedure FFFFH OSD Font Memory 17FFFH 1. Add program OTP file and font OTP file 2. Burn OTP file(Set chip target address 1000h ~ 17FFFh) About other details, refer ROM wirter manual. Figure 23-1 HMS87C4x60 OTP Memory Map November 2001 Ver 1.1 97 HMS81C4x60 23.2 .Device Configuration Data OM1 OM3 PGMB DIO<4> DIO<0> DIO<1> DIO<2> DIO<3> OEB CEB AHB ALB 32SDIP HYNIX HMS87C4260 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 OM2 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 DIO<6> DIO<5> VPP A16 DIO<7> Figure 23-2 Figure Pin Configuration in OTP Programming Mode HMS87C4x60 Mode VPP CEB OEB PGMB Program 11.25 Low High Low Verify 11.25 Low Low High Optional Verify 5 Low Low X Gang Write 11.25 Low High Low Gang Verify 11.25, 5 Low Low X Figure 23-3 Figure Mode Table 98 November 2001 Ver 1.1 HMS81C4x60 24. Assemble mnemonics 24.1 Instruction Map 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 00 01 02 03 04 05 06 07 08 09 SET1 BBS BBS ADC ADC ADC ADC ASL ASL dp.bit A.bit,rel dp.bit,rel #imm dp dp+X !abs A dp // // SBC SBC SBC SBC ROL ROL #imm dp dp+X !abs A dp CMP CMP CMP CMP LSR LSR #imm dp dp+X !abs A dp 000 NOP 001 CLRC // 010 CLRG // 011 DI // 100 CLRV // 101 SETC // 110 SETG // 111 EI // // // // // // // // // // // // // 0A 0B TCALL SETA1 0 .bit 2 .bit TCALL NOT1 0E PUSH dp A A PUSH BRA X X rel TST POP dp Y Y CMPX POP PUSH dp PSW PSW OR OR OR ROR ROR TCALL dp dp+X !abs A dp 6 OR1B AND AND AND AND INC INC #imm dp dp+X !abs A dp EOR EOR EOR EOR DEC DEC #imm dp dp+X !abs A dp LDA LDA LDA LDA #imm dp dp+X !abs LDM STA STA STA dp,#imm dp dp+X !abs BRK POP M.bit OR 0F dp 4 #imm TAX 0D POP TCALL CLRA1 COM OR1 TXA 0C BIT PUSH PCALL TCALL AND1 CMPY CBNE 8 dp dp+X AND1B TXSP TCALL EOR1 DBNE 10 dp EOR1B XMA TSPX dp+X LDY TCALL LDC LDX LDX dp 12 LDCB dp dp+Y STY TCALL STC STX STX dp 14 M.bit dp dp+Y XCN Upage RET INC X DEC X DAS XAS 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 000 001 010 011 100 101 110 111 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F BPL CLR1 BBC BBC ADC ADC ADC ADC ASL ASL TCALL JMP BIT ADDW LDX JMP rel dp.bit A.bit,rel dp.bit,rel {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 1 !abs !abs dp SBC SBC SBC SBC ROL ROL {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 3 CMP CMP CMP CMP LSR LSR TCALL {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 5 BVC // // // rel BCC // // // // // // rel BNE rel BMI // // // rel BVS // // // rel BCS // // // rel BEQ // // // rel November 2001 Ver 1.1 TCALL CALL OR OR OR OR ROR ROR {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 7 AND AND AND AND INC INC TCALL {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 9 EOR EOR EOR EOR DEC DEC TCALL {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 11 !abs MUL TEST SUBW !abs dp #imm [!abs] LDY JMP #imm [dp] TCLR1 CMPW CMPX !abs dp #imm TCALL DBNE CMPX LDYA CMPY Y DIV !abs dp CMPY INCW #imm INC !abs dp Y XMA XMA DECW DEC {X} dp dp Y LDA LDA LDA LDA LDY LDY TCALL LDA LDX STYA {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 13 {X}+ !abs dp STA STA STA STA STY STY TCALL STA STX CBNE {X} !abs+Y [dp+X] [dp]+Y !abs dp+X 15 {X}+ !abs dp CALL [dp] RETI TAY TYA XAY DAA XYX NOP 99 HMS81C4x60 24.2 Alphabetic order table of instruction NO. MNENONIC OP CODE BYTE NO. CYCLE NO FLAG NVGBHIZC OPERATION 1 ADC #imm 04 2 2 Add with carry. 2 ADC dp 05 2 3 A ← A + (M) + C 3 ADC dp + X 06 2 4 4 ADC !abs 07 3 4 5 ADC !abs+Y 15 3 5 6 ADC [dp+X] 16 2 6 7 ADC [dp]+Y 17 2 6 8 ADC {X} 14 1 3 NV - - H - ZC 9 ADDW dp 1D 2 5 16-bits add without carry : YA ← YA + (dp+1)(dp) 10 AND #imm 84 2 2 Logical AND 11 AND dp 85 2 3 A ← A ^ (M) 12 AND dp + X 86 2 4 13 AND !abs 87 3 4 14 AND !abs+Y 95 3 5 15 AND [dp+X] 96 2 6 16 AND [dp] + Y 97 2 6 17 AND {X} 94 1 3 18 AND1 M.bit 8B 3 4 Bit AND C-flag : C ← C ^ (M.bit) -------C 19 AND1B M.bit 8B 3 4 Bit AND C-flag and NOT : C ← C ^ ~(M.bit) -------C 20 ASL A 08 1 2 Arithmetic shift left 21 ASL dp 09 2 4 22 ASL dp + X 19 2 5 23 ASL !abs 18 3 5 24 BBC A.bit,rel y2 2 4/6 Branch if bit clear : 25 BBC dp.bit,rel y3 3 5/7 if(bit) = 0, then PC ← PC + rel 26 BBS A.bit,rel x2 2 4/6 Branch if bit clear : 27 BBS dp.bit,rel x3 3 5/7 if(bit) = 1, then PC ← PC + rel 28 BCC rel 50 2 2/4 Branch if carry bit clear : if(C) = 0, then PC ← PC + rel NV - - H - ZC N-----Z- C 7 6 5 4 3 2 1 0 ← ← ← ← ← ← ← ← ← ← "0" N - - - - - ZC --------------MM - - - - Z - 29 BCS rel D0 2 2/4 Branch if carry bit set : If (C) =1, then PC ← PC + rel -------- 30 BEQ rel F0 2 2/4 Branch if equal : if (Z) = 1, then PC ← PC + rel -------- 31 BIT dp 0C 2 4 Bit test A with memory : 32 BIT !abs 1C 3 5 Z ← A ^ M, N ← (M7), V ← (M6) MM - - - - Z - 33 BMI rel 90 2 2/4 Branch if munus : if (N) = 1, then PC ← PC + rel -------- 34 BNE rel 70 2 2/4 Branch if not equal : if (Z) = 0, then PC ← PC + rel -------- 35 BPL rel 10 2 2/4 Branch if not minus : if (N) = 0, then PC ← PC + rel -------- 36 BRA rel 2F 2 4 Branch always : PC ← PC + rel -------- 37 BRK 0F 1 8 Software interrupt: B ← “1”, M(SP) ← (PCH), SP ← SP - 1, ---1-0-- M(s) ← (PCL), SP ← S - 1, M(SP) ← PSW, SP ← SP - 1, PCL ← (0FFDEH), PCH ← (0FFDFH) 38 BVC rel 30 2 2/4 Branch if overflow bit clear : -------- If (V) = 0, then PC ← PC + rel 39 BVS rel B0 2 2/4 Branch if overflow bit set : -------- If (V) = 1, then PC ← PC + rel 40 CALL !abs 3B 3 8 Subroutine call 41 CALL [dp] 5F 2 8 M(SP) ← (PCH), SP ← SP-1, M(SP) ← (PCL), SP←SP-1 -------- if !abs, PC ← abs ; if [dp], PCL ← (dp), PCH ← (dp+1) 42 CBNE dp,rel FD 3 5/7 Compare and branch if not equal ; 43 CBNE dp + X, rel 8D 3 6/8 If A ≠ (M), then PC ← PC + rel. -------- 44 CLR1 dp.bit y1 2 4 Clear bit : (M.bit) ← “0” -------- 45 CLR1A A.bit 2B 2 2 Clear A.bit : (A.bit) ← “0” -------- 46 CLRC 20 1 2 Clear C-flag : C ← “0” -------0 47 CLRG 40 1 2 Clear G-flag : G ← “0” --0----- 100 November 2001 Ver 1.1 HMS81C4x60 NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION 48 CLRV 80 1 2 Clear V-flag : V ← “0” 49 CMP #imm 44 2 2 Compare accumulator contents with memory contents 50 CMP dp 45 2 3 A - (M) 51 CMP dp + X 46 2 4 52 CMP !abs 47 3 4 53 CMP !abs + Y 55 3 5 54 CMP [dp + X] 56 2 6 55 CMP [dp] + Y 57 2 6 56 CMP {X} 54 1 3 57 CMPW dp 5D 2 4 FLAG NVGBHIZC -0--0--- N - - - - - ZC Compare YA contents with memory pair contents : N - - - - - ZC YA - (dp+1)(dp) 58 CMPX #imm 5E 2 2 Compare X contents with memory contents 59 CMPX dp 6C 2 3 X - (M) 60 CMPX !abs 7C 3 4 61 CMPY #imm 7E 2 2 Compare Y contents with memory contents 62 CMPY dp 8C 2 3 Y - (M) 63 CMPY !abs 9C 3 4 N - - - - - ZC N - - - - - ZC 64 COM dp 2C 2 4 1’s complement : (dp) ← ~(dp) N-----Z- 65 DAA DF 1 3 Decimal adjust for addition N - - - - - ZC 66 DAS CF 1 3 Decimal adjust for substraction N - - - - - ZC 67 DBNE dp,rel AC 3 5/7 Decrement and branch if not equal : 68 DBNE Y,rel 7B 2 4/6 if (M) ≠ 0, then PC ← PC + rel. 69 DEC A A8 1 2 Decrement 70 DEC dp A9 2 4 M←M-1 71 DEC dp + X B9 2 5 72 DEC !abs B8 3 5 73 DEC X AF 1 2 74 DEC Y BE 1 2 75 DECW dp BD 2 6 Decrement memory pair : (dp+1)(dp) ← {(dp+1)(dp)} - 1 76 DI 60 1 3 Disable interrupts : I ← “0” 77 DIV 9B 1 12 Divide : YA / X ← Q:A, R:Y NV - - H - Z -----1-- -------- N-----Z- N-----Z-----0-- 78 EI E0 1 3 Enable interrupts : I ← “1” 79 EOR #imm A4 2 2 Exclusive OR 80 EOR dp A5 2 3 A ← A ⊕ (M) 81 EOR dp + X A6 2 4 82 EOR !abs A7 3 4 83 EOR !abs + Y B5 3 5 84 EOR [ dp + X] 96 2 6 85 EOR [dp] + Y 97 2 6 86 EOR {X} 94 1 3 87 EOR1 M.bit AB 3 5 Bit exclusive-OR C-flag : C ← C ⊕ (M.bit) 88 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ← C ⊕ ∼(M.bit) -------C 89 INC A 88 1 2 Increment N - - - - - ZC 90 INC dp 89 2 4 (M) ← (M) + 1 91 INC dp + X 99 2 5 92 INC !abs 98 3 5 93 INC X 8F 1 2 N-----Z- N-----Z- 94 INC Y 9E 1 2 95 INCW dp 9D 2 6 Increment memory pair : (dp+1)(dp) ← {(dp+1)(dp)} + 1 96 JMP !abs 1B 3 3 Unconditional jump PC ← jump address 97 JMP [!abs] 1F 3 5 98 JMP [dp] 3F 2 4 November 2001 Ver 1.1 -------C N-----Z-------- 101 HMS81C4x60 NO. MNENONIC OP CODE BYTE NO. CYCLE NO FLAG NVGBHIZC OPERATION 99 LDA #imm C4 2 2 Load accumulator 100 LDA dp C5 2 3 A ← (M) 101 LDA dp + X C6 2 4 102 LDA !abs C7 3 4 103 LDA !abs + Y D5 3 5 104 LDA [dp + X] D6 2 6 105 LDA [dp]+Y D7 2 6 106 LDA {X} D4 1 3 107 LDA {X}+ DB 1 4 108 LDC M.bit CB 3 4 Load C-flag : C ← (M.bit) -------C 109 LDCB M.bit CB 3 4 Load C-flag with NOT : C ← ~(M.bit) -------C 110 LDM dp,#imm E4 3 5 Load memory with immediate data : (M) ← imm -------- 111 LDX #imm 1E 2 2 Load X-register 112 LDX dp CC 2 3 X ← (M) 113 LDX dp + Y CD 2 4 114 LDX !abs DC 3 4 115 LDY #imm 3E 2 2 Load X-register 116 LDY dp C9 2 3 Y ← (M) 117 LDY dp + Y D9 2 4 118 LDY !abs D8 3 4 119 LDYA dp 7D 2 5 Load YA : YA ← (dp+1)(dp) 120 LSR A 48 1 2 Logical shift right 121 LSR dp 49 2 4 122 LSR dp + X 59 2 5 123 LSR !abs 58 3 5 124 MUL 5B 1 9 Multiply : YA ← Y x A 125 NOP 00,FF 1 2 No operation -------- 126 NOT1 M.bit 4B 3 5 Bit complement : (M.bit) ← ~(M.bit) -------- 127 OR #imm 64 2 2 Logical OR 128 OR dp 65 2 3 A ← A V (M) 129 OR dp + X 66 2 4 130 OR !abs 67 3 4 131 OR !abs + Y 75 3 5 132 OR [dp +X} 76 2 6 133 OR [dp] + Y 77 2 6 134 OR {X} 74 1 3 135 OR1 M.bit 6B 3 5 Bit OR C-flag : C ← C V (M.bit) -------C 136 OR1B M.bit 6B 3 5 Bit OR C-flag and NOT : C ← C V ~(M.bit) -------C 137 PCALL 4F 2 6 N-----Z- X-register auto-increment : A ← (M), X ← X + 1 N-----Z- N-----Z- N-----Z- 7 6 5 4 3 2 1 0 C "0"→ → → → → → → → → → N - - - - - ZC N-----Z- N-----Z- U-page call : M(SP) ← (PCH), SP ← SP -1, M(SP) ← (PCL), SP ← SP -1, -------- PCL ← (upage), PCH ←"OFFH" 138 POP A 0D 1 4 Pop from stack 139 POP X 2D 1 4 SP ← SP + 1, Reg. ← M(SP) 140 POP Y 4D 1 4 141 POP PSW 6D 1 4 142 PUSH A 0E 1 4 Push to stack 143 PUSH X 2E 1 4 M(SP) ← Reg. 144 PUSH Y 4E 1 4 145 PUSH PSW 6E 1 4 146 RET 6F 1 5 -------(restored) SP ← SP - 1 -------- Return from subroutine : SP ← SP+1, PCL ← M(SP), SP ← SP+1, PCH ← M(SP) 147 RETI 7F 1 6 -------- Return from interrupt : SP ← SP+1, PSW ← M(SP), SP ← SP+1,PCL ← M(SP), (restored) SP ← SP+1, PCH ← M(SP) 102 November 2001 Ver 1.1 HMS81C4x60 NO. MNENONIC OP CODE BYTE NO. CYCLE NO 148 ROL A 28 1 2 149 ROL dp 29 2 4 150 ROL dp + X 39 2 5 151 ROL !abs 38 3 5 152 ROR A 68 1 2 153 ROR dp 69 2 4 154 ROR dp + X 79 2 5 155 ROR !abs 78 3 5 OPERATION FLAG NVGBHIZC Rotate left through carry C 7 6 5 4 3 2 1 0 ←←←←←←←←← N - - - - - ZC Rotate right through carry 7 6 5 4 3 2 1 0 C →→→→→→→→→ N - - - - - ZC 156 SBC #imm 24 2 2 Substract with carry 157 SBC dp 25 2 3 A ← A - (M) - ~(C) 158 SBC dp + X 26 2 4 159 SBC !abs 27 3 4 160 SBC !abs + Y 35 3 5 161 SBC [dp + X] 36 2 6 162 SBC [dp] + Y 37 2 6 163 SBC {X} 34 1 3 164 SET1 dp.bit x1 2 4 Set bit : (M.bit) ← “1” -------- 165 SETA1 A.bit 0B 2 2 Set A.bit : (A.bit) ← “1” -------- 166 SETC A0 1 2 Set C-flag : C ← “1” -------1 167 SETG C0 1 2 Set G-flag : G ← “1” --1----- 168 STA dp E5 2 3 Store accumulator contents in memory 169 STA dp + X E6 2 4 (M) ← A 170 STA !abs E7 3 4 171 STA !abs + Y F5 3 5 172 STA [dp + X] F6 2 6 173 STA [dp] + Y F7 2 6 174 STA {X} F4 1 3 175 STA {X}+ FB 1 4 X-register auto-increment : (M) ← A, X ← X + 1 176 STC M.bit EB 3 6 Store C-flag : (M.bit) ← C 177 STX dp EC 2 4 Store X-register contents in memory 178 STX dp + Y ED 2 5 (M) ← X 179 STX !abs FC 3 5 180 STY dp E9 2 4 Store Y-register contents in memory 181 STY dp + X F9 2 5 (M) ← Y 182 STY !abs F8 3 5 183 STYA dp DD 2 5 Store YA : (dp+1)(dp) ← YA 184 SUBW dp 3D 2 5 16-bits substract without carry : YA ← YA - (dp+1)(dp) NV - - HZC -------- --------------- --------------NV - - H - ZC 185 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z- 186 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z- 187 TCALL n nA 1 8 Table call : M(SP) ← (PCH), SP ← SP -1, M(SP) ← (PCL), SP ← SP -1 -------- PCL ← (Table vector L), PCH ← (Table vector H) 188 TCLR1 !abs 5C 3 6 Test and clear bits with A : A - (M), (M) ← (M) ^ ~(A) 189 TSET1 !abs 3C 3 6 Test and set bits with A : A - (M), (M) ← (M) V (A) N-----ZN-----Z- 190 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← SP N-----Z- 191 TST dp 4C 2 3 Test memory contents for negative or zero : (dp) - 00H N-----Z- 192 TXA C8 1 2 Transfer X-register contents to accumulator : A ← X N-----Z- 193 TXSP 8E 1 2 Transfer X-register contents to stack-pointer : SP ← X N-----Z- 194 TYA BF 1 2 Transfer Y-register contents to accumulator : A ← Y N-----Z- 195 XAX EE 1 4 Exchange X-register contents with accumulator : X fA -------- 196 XAY DE 1 4 Exchange Y-register contents with accumulator : Y fA -------- November 2001 Ver 1.1 103 HMS81C4x60 NO. 197 MNENONIC XCN OP CODE BYTE NO. CYCLE NO CE 1 5 FLAG NVGBHIZC OPERATION Exchange nibbles within the accumulator: N-----Z- A7 ~ A4 f A3 ~ A0 198 XMA dp BC 2 5 Exchange memory contents with accumulator 199 XMA dp + X AD 2 6 (M) f A 200 XMA {X} BB 1 5 201 XYX FE 1 4 N-----Z- Exchange X-register contents with Y-register : X f Y -------- 24.3 Instruction Table by Function 1. Arithmetic/Logic Operation NO. MNENONIC OP CODE BYTE NO. CYCLE NO FLAG NVGBHIZC OPERATION 1 ADC #imm 04 2 2 Add with carry. 2 ADC dp 05 2 3 A ← A + (M) + C 3 ADC dp + X 06 2 4 4 ADC !abs 07 3 4 5 ADC !abs+Y 15 3 5 6 ADC [dp+X] 16 2 6 7 ADC [dp]+Y 17 2 6 8 ADC {X} 14 1 3 NV - - H - ZC 9 AND #imm 84 2 2 Logical AND 10 AND dp 85 2 3 A ← A ^ (M) 11 AND dp + X 86 2 4 12 AND !abs 87 3 4 13 AND !abs+Y 95 3 5 14 AND [dp+X] 96 2 6 15 AND [dp] + Y 97 2 6 16 AND {X} 94 1 3 17 ASL A 08 1 2 18 ASL dp 09 2 4 19 ASL dp + X 19 2 5 20 ASL !abs 18 3 5 21 CMP #imm 44 2 2 Compare accumulator contents with memory contents 22 CMP dp 45 2 3 A - (M) 23 CMP dp + X 46 2 4 N-----Z- Arithmetic shift left C 7 6 5 4 3 2 1 0 ← ← ← ← ← ← ← ← ← ← "0" 24 CMP !abs 47 3 4 25 CMP !abs + Y 55 3 5 26 CMP [dp + X] 56 2 6 27 CMP [dp] + Y 57 2 6 28 CMP {X} 54 1 3 29 CMPX #imm 5E 2 2 Compare X contents with memory contents 30 CMPX dp 6C 2 3 X - (M) 31 CMPX !abs 7C 3 4 N - - - - - ZC N - - - - - ZC 32 CMPY #imm 7E 2 2 Compare Y contents with memory contents 33 CMPY dp 8C 2 3 Y - (M) 34 CMPY !abs 9C 3 4 N - - - - - ZC N - - - - - ZC 35 COM dp 2C 2 4 1’s complement : (dp) ← ~(dp) N-----Z- 36 DAA DF 1 3 Decimal adjust for addition N - - - - - ZC 37 DAS CF 1 3 Decimal adjust for substraction N - - - - - ZC 38 DEC A A8 1 2 Decrement 39 DEC dp A9 2 4 M←M-1 40 DEC dp + X B9 2 5 41 DEC !abs B8 3 5 42 DEC X AF 1 2 43 DEC Y BE 1 2 104 N-----Z- November 2001 Ver 1.1 HMS81C4x60 NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION 44 DIV 9B 1 12 Divide : YA / X ← Q:A, R:Y 45 EOR #imm A4 2 2 Exclusive OR 46 EOR dp A5 2 3 A ← A ⊕ (M) 47 EOR dp + X A6 2 4 48 EOR !abs A7 3 4 49 EOR !abs + Y B5 3 5 50 EOR [ dp + X] 96 2 6 51 EOR [dp] + Y 97 2 6 52 EOR {X} 94 1 3 53 INC A 88 1 2 Increment 54 INC dp 89 2 4 (M) ← (M) + 1 55 INC dp + X 99 2 5 56 INC !abs 98 3 5 57 INC X 8F 1 2 58 INC Y 9E 1 2 59 LSR A 48 1 2 60 LSR dp 49 2 4 61 LSR dp + X 59 2 5 62 LSR !abs 58 3 5 63 MUL 5B 1 9 Multiply : YA ← Y x A 64 OR #imm 64 2 2 Logical OR 65 OR dp 65 2 3 A ← A V (M) 66 OR dp + X 66 2 4 67 OR !abs 67 3 4 68 OR !abs + Y 75 3 5 69 OR [dp +X} 76 2 6 70 OR [dp] + Y 77 2 6 71 OR {X} 74 1 3 72 ROL A 28 1 2 73 ROL dp 29 2 4 74 ROL dp + X 39 2 5 NV - - H - Z - N-----Z- N - - - - - ZC N-----Z- Logical shift right 7 6 5 4 3 2 1 0 C "0"→ → → → → → → → → → N - - - - - ZC N-----Z- N-----Z- Rotate left through carry C 7 6 5 4 3 2 1 0 ←←←←←←←←← 75 ROL !abs 38 3 5 76 ROR A 68 1 2 77 ROR dp 69 2 4 78 ROR dp + X 79 2 5 79 ROR !abs 78 3 5 80 SBC #imm 24 2 2 Substract with carry 81 SBC dp 25 2 3 A ← A - (M) - ~(C) 82 SBC dp + X 26 2 4 83 SBC !abs 27 3 4 84 SBC !abs + Y 35 3 5 85 SBC [dp + X] 36 2 6 86 SBC [dp] + Y 37 2 6 87 SBC {X} 34 1 3 88 TST dp 4C 2 3 Test memory contents for negative or zero : (dp) - 00H 89 XCN CE 1 5 Exchange nibbles within the accumulator: N - - - - - ZC Rotate right through carry 7 6 5 4 3 2 1 0 C →→→→→→→→→ N - - - - - ZC NV - - HZC A7 ~ A4 f A3 ~ A0 November 2001 Ver 1.1 FLAG NVGBHIZC N-----ZN-----Z- 105 HMS81C4x60 2. Register / Memory Operation NO. MNENONIC OP CODE BYTE NO. CYCLE NO FLAG NVGBHIZC OPERATION 1 LDA #imm C4 2 2 Load accumulator 2 LDA dp C5 2 3 A ← (M) 3 LDA dp + X C6 2 4 4 LDA !abs C7 3 4 5 LDA !abs + Y D5 3 5 6 LDA [dp + X] D6 2 6 7 LDA [dp]+Y D7 2 6 8 LDA {X} D4 1 3 9 LDA {X}+ DB 1 4 X-register auto-increment : A ← (M), X ← X + 1 10 LDM dp,#imm E4 3 5 Load memory with immediate data : (M) ← imm 11 LDX #imm 1E 2 2 Load X-register 12 LDX dp CC 2 3 X ← (M) 13 LDX dp + Y CD 2 4 14 LDX !abs DC 3 4 15 LDY #imm 3E 2 2 Load X-register 16 LDY dp C9 2 3 Y ← (M) 17 LDY dp + Y D9 2 4 18 LDY !abs D8 3 4 19 STA dp E5 2 3 Store accumulator contents in memory 20 STA dp + X E6 2 4 (M) ← A 21 STA !abs E7 3 4 22 STA !abs + Y F5 3 5 23 STA [dp + X] F6 2 6 24 STA [dp] + Y F7 2 6 25 STA {X} F4 1 3 26 STA {X}+ FB 1 4 X-register auto-increment : (M) ← A, X ← X + 1 27 STX dp EC 2 4 Store X-register contents in memory 28 STX dp + Y ED 2 5 (M) ← X 29 STX !abs FC 3 5 N-----Z- -------- N-----Z- N-----Z- -------- -------- 30 STY dp E9 2 4 Store Y-register contents in memory 31 STY dp + X F9 2 5 (M) ← Y 32 STY !abs F8 3 5 -------- 33 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z- 34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z- 35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← SP N-----Z- 36 TXA C8 1 2 Transfer X-register contents to accumulator : A ← X N-----Z- 37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer : SP ← X N-----ZN-----Z- 38 TYA BF 1 2 Transfer Y-register contents to accumulator : A ← Y 39 XAX EE 1 4 Exchange X-register contents with accumulator : X fA -------- 40 XAY DE 1 4 Exchange Y-register contents with accumulator : Y fA -------- 41 XMA dp BC 2 5 Exchange memory contents with accumulator 42 XMA dp + X AD 2 6 (M) f A 43 XMA {X} BB 1 5 44 XYX FE 1 4 OP CODE BYTE NO. CYCLE NO N-----Z- Exchange X-register contents with Y-register : X f Y -------- 3. 16-Bit Operation NO. MNENONIC FLAG NVGBHIZC OPERATION 1 ADDW dp 1D 2 5 16-bits add without carry : YA ← YA + (dp+1)(dp) NV - - H - ZC 2 CMPW dp 5D 2 4 Compare YA contents with memory pair contents : N - - - - - ZC YA - (dp+1)(dp) 3 DECW dp BD 2 6 Decrement memory pair : (dp+1)(dp) ← {(dp+1)(dp)} - 1 N-----Z- 4 INCW dp 9D 2 6 Increment memory pair : (dp+1)(dp) ← {(dp+1)(dp)} + 1 N-----Z- 106 November 2001 Ver 1.1 HMS81C4x60 NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION 5 LDYA dp 7D 2 5 Load YA : YA ← (dp+1)(dp) 6 STYA dp DD 2 5 Store YA : (dp+1)(dp) ← YA 7 SUBW dp 3D 2 5 16-bits substract without carry : YA ← YA - (dp+1)(dp) OP CODE BYTE NO. CYCLE NO FLAG NVGBHIZC N-----Z-------NV - - H - ZC 4. Bit Manipulation NO. MNENONIC OPERATION FLAG NVGBHIZC 1 AND1 M.bit 8B 3 4 Bit AND C-flag : C ← C ^ (M.bit) -------C 2 AND1B M.bit 8B 3 4 Bit AND C-flag and NOT : C ← C ^ ~(M.bit) -------C 3 BIT dp 0C 2 4 Bit test A with memory : 4 BIT !abs 1C 3 5 Z ← A ^ M, N ← (M7), V ← (M6) 5 CLR1 dp.bit y1 2 4 Clear bit : (M.bit) ← “0” -------- 6 CLR1A A.bit 2B 2 2 Clear A.bit : (A.bit) ← “0” -------- 7 CLRC 20 1 2 Clear C-flag : C ← “0” -------0 8 CLRG 40 1 2 Clear G-flag : G ← “0” --0----- MM - - - - Z - 9 CLRV 80 1 2 Clear V-flag : V ← “0” -0--0--- 10 EOR1 M.bit AB 3 5 Bit exclusive-OR C-flag : C ← C ⊕ (M.bit) -------C 11 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ← C ⊕ ∼(M.bit) -------C 12 LDC M.bit CB 3 4 Load C-flag : C ← (M.bit) -------C 13 LDCB M.bit CB 3 4 Load C-flag with NOT : C ← ~(M.bit) -------C 14 NOT1 M.bit 4B 3 5 Bit complement : (M.bit) ← ~(M.bit) -------- 15 OR1 M.bit 6B 3 5 Bit OR C-flag : C ← C V (M.bit) -------C -------C 16 OR1B M.bit 6B 3 5 Bit OR C-flag and NOT : C ← C V ~(M.bit) 17 SET1 dp.bit x1 2 4 Set bit : (M.bit) ← “1” -------- 18 SETA1 A.bit 0B 2 2 Set A.bit : (A.bit) ← “1” -------- 19 SETC A0 1 2 Set C-flag : C ← “1” -------1 20 SETG C0 1 2 Set G-flag : G ← “1” --1----- 21 STC M.bit EB 3 6 Store C-flag : (M.bit) ← C -------- 22 TCLR1 !abs 5C 3 6 Test and clear bits with A : A - (M), (M) ← (M) ^ ~(A) 23 TSET1 !abs 3C 3 6 Test and set bits with A : A - (M), (M) ← (M) V (A) N-----ZN-----Z- 5. Branch / Jump Operation NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION 1 BBC A.bit,rel y2 2 4/6 Branch if bit clear : 2 BBC dp.bit,rel y3 3 5/7 if(bit) = 0, then PC ← PC + rel 3 BBS A.bit,rel x2 2 4/6 Branch if bit clear : 4 BBS dp.bit,rel x3 3 5/7 if(bit) = 1, then PC ← PC + rel 5 BCC rel 50 2 2/4 Branch if carry bit clear : if(C) = 0, then PC ← PC + rel FLAG NVGBHIZC --------------MM - - - - Z - 6 BCS rel D0 2 2/4 Branch if carry bit set : If (C) =1, then PC ← PC + rel 7 BEQ rel F0 2 2/4 Branch if equal : if (Z) = 1, then PC ← PC + rel -------- 8 BMI rel 90 2 2/4 Branch if munus : if (N) = 1, then PC ← PC + rel --------------- -------- 9 BNE rel 70 2 2/4 Branch if not equal : if (Z) = 0, then PC ← PC + rel 10 BPL rel 10 2 2/4 Branch if not minus : if (N) = 0, then PC ← PC + rel -------- 11 BRA rel 2F 2 4 Branch always : PC ← PC + rel -------- 12 BVC rel 30 2 2/4 Branch if overflow bit clear : If (V) = 0, then PC ← PC + rel 13 BVS rel B0 2 2/4 Branch if overflow bit set : If (V) = 1, then PC ← PC + rel November 2001 Ver 1.1 --------------- 107 HMS81C4x60 NO. MNENONIC OP CODE BYTE NO. CYCLE NO OPERATION FLAG NVGBHIZC -------- 14 CALL !abs 3B 3 8 Subroutine call 15 CALL [dp] 5F 2 8 M(SP) ← (PCH), SP ← SP-1, M(SP) ← (PCL), SP←SP-1 if !abs, PC ← abs ; if [dp], PCL ← (dp), PCH ← (dp+1) 16 CBNE dp,rel FD 3 5/7 Compare and branch if not equal ; 17 CBNE dp + X, rel 8D 3 6/8 If A ≠ (M), then PC ← PC + rel. 18 DBNE dp,rel AC 3 5/7 Decrement and branch if not equal : 19 DBNE Y,rel 7B 2 4/6 if (M) ≠ 0, then PC ← PC + rel. 20 JMP !abs 1B 3 3 Unconditional jump 21 JMP [!abs] 1F 3 5 PC ← jump address 22 JMP [dp] 3F 2 4 23 PCALL 4F 2 6 --------------- -------- U-page call : M(SP) ← (PCH), SP ← SP -1, M(SP) ← (PCL), SP ← SP -1, -------- PCL ← (upage), PCH ←"OFFH" 24 TCALL n nA 1 8 Table call : M(SP) ← (PCH), SP ← SP -1, -------- M(SP) ← (PCL), SP ← SP -1 PCL ← (Table vector L), PCH ← (Table vector H) 6. Control Operation & etc. NO. 1 MNENONIC BRK OP CODE BYTE NO. CYCLE NO 0F 1 8 FLAG NVGBHIZC OPERATION Software interrupt: B ← “1”, M(SP) ← (PCH), SP ← SP - 1, ---1-0-- M(s) ← (PCL), SP ← S - 1, M(SP) ← PSW, SP ← SP - 1, PCL ← (0FFDEH), PCH ← (0FFDFH) 2 DI 60 1 3 Disable interrupts : I ← “0” -----0-- 3 EI E0 1 3 Enable interrupts : I ← “1” -----1-- 4 NOP FF 1 2 No operation -------- 5 POP A 0D 1 4 Pop from stack 6 POP X 2D 1 4 SP ← SP + 1, Reg. ← M(SP) 7 POP Y 4D 1 4 8 POP PSW 6D 1 4 9 PUSH A 0E 1 4 Push to stack 10 PUSH X 2E 1 4 M(SP) ← Reg. 11 PUSH Y 4E 1 4 12 PUSH PSW 6E 1 4 13 RET 6F 1 5 -------(restored) SP ← SP - 1 -------- Return from subroutine : SP ← SP+1, PCL ← M(SP), SP ← SP+1, PCH ← M(SP) 14 RETI 7F 1 6 -------- Return from interrupt : SP ← SP+1, PSW ← M(SP), SP ← SP+1,PCL ← M(SP), (restored) SP ← SP+1, PCH ← M(SP) 108 November 2001 Ver 1.1