HT9015 Preliminary RF Single Chip for Cordless Phone Features · · · · Operating voltage: 2.7V~6V Extremely low power consumption current - I CC= 0mA (typ.) in battery-saving mode - I CC= 8.5mA (typ.) in standby mode - I CC= 13.5mA (typ.) for communication Built-in IF decoder, compander and PLL IF decoder - 1st/2nd Mixers, RX VCO - RSSI quadrature detector, IF AMP - Noise detector · · · Compander - Expander, Compressor, Limiter - Receive AMP, MIC AMP, PRE AMP PLL - RX PLL, TX PLL - Local oscillator - Data latch control - Unlock detector Four threshold variable battery alarms General Description nal strength and built-in noise detector for S/N quality. The HT9015 is an RF single chip for cordless phone systems. Internally these are three major parts, a PLL, an IF decoder and a compander. The compander provides better S/N ratio for audio signal processing. The PLL provides radio channel selection for either the transmitter or receiver. Frequency locking status of the selected channel can be monitored by a control register. The HT9015 has a wide-range applications in FM/FSK, Transmitting/Receiving of VHF bandwidth including cordless phone, narrow band voice and data transceiver systems. The IF decoder provides two frequency down converters that let high frequency signals pass through a mixer and local oscillator to be lowered for frequency even base band signals. It also provides an RSSI (receiver signal strength indicator) function to detect the IF output sig- The most significant advantage of the HT9015 is in the reduction of many external components making it well suited for cordless phone baseset, handset radio section. 1 April 10, 2000 Preliminary HT9015 Block Diagram G N D 2 T X _ O U T R X _ O U T 4 5 C _ R E C T 3 V C O _ C O N T V C O 2 V C O 1 2 1 4 7 4 8 V C C 2 1 S T M IX _ IN 4 6 4 5 4 4 V C C 3 L O 1 L O 2 S IG _ O U T C L K D A T A S T B T X P L L 6 T X _ IN R X P L L R X V C O 1 s t M ix e r R e g u la to r 7 8 L O O S C 9 2 n d M ix e r 4 3 E _ R E C T 4 1 2 N D M IX _ IN 4 0 N _ R E C 1 0 3 9 1 1 D a ta L a tc h C o n tro l 1 2 1 3 3 8 L o w B A T A la r m 1 4 IF A M P L P F F IL _ IN C O M P _ O U T C _ N F M IC _ O U T R S S I L im ite r C o m p re s s o r Q u a d D e te c to r C _ M U T E 1 6 2 N D M IX _ O U T V C C 1 IF _ IN 3 6 D E C 3 5 G N D 1 3 4 1 5 3 3 IF _ O U T Q U A D E x p a n d e r 1 7 L P F E _ M U T E 3 2 A F _ O U T 1 8 3 1 C o m p a ra to r P R E A M P M IC A M P N o is e F ilte r R e c e iv e r A M P 3 0 M IC _ IN 1 S T M IX _ O U T 4 2 3 7 F IL _ O U T V R E F N _ F IL _ O U T N _ F IL _ IN 1 9 D a ta C o m p 2 0 P R E _ IN 2 1 2 2 2 3 P R E _ O U T E X P _ O U T R E C E _ IN 2 4 R O 1 2 5 R O 2 2 2 6 B A T _ A L M 2 7 2 8 R S S I D _ C O M P _ O U T 2 9 D _ C O M P _ IN April 10, 2000 Preliminary HT9015 Pin Assignment V C O 2 1 4 8 V C O 1 C _ R E C T 2 4 7 V C O _ C O N T R X _ O U T 3 4 6 V C C 2 T X _ O U T 4 4 5 1 S T M IX IN G N D 2 5 4 4 V R E F T X _ IN 6 4 3 1 S T M IX O U T V C C 3 7 4 2 E _ R E C T L O 1 8 4 1 2 N D M IX IN L O 2 9 4 0 N _ R E C S IG _ O U T 1 0 3 9 2 N D M IX O U T C L K 1 1 3 8 V C C 1 D A T A 1 2 3 7 IF _ IN S T B 1 3 3 6 D E C F IL _ O U T 1 4 3 5 G N D 1 F IL _ IN 1 5 3 4 IF _ O U T C O M P _ O U T 1 6 3 3 Q U A D C _ N F 1 7 3 2 A F _ O U T M IC _ O U T 1 8 3 1 N _ F IL _ O U T M IC _ IN 1 9 3 0 N _ F IL _ IN P R E _ IN 2 0 2 9 D _ C O M P _ IN P R E _ O U T 2 1 2 8 D _ C O M P _ O U T E X P _ O U T 2 2 2 7 R S S I R E C E _ IN 2 3 2 6 B A T _ A L M R O 1 2 4 2 5 R O 2 H T 9 0 1 5 4 8 S S O P Pin Description Pin No. Pin Name I/O Description 1 VCO2 I Connects LC network with VCO1 pin to provide the tank circuit for the received voltage control oscillator 2 C_RECT ¾ Normally connected to ground through a capacitor. 3 RX_OUT O Receiver phase detector output. The PDT of RX-PLL detects phase errors from the received PLL. The output is connected to external low pass filter. 4 TX_OUT O Transmitter phase detector output. The PDT of TX-PLL detects phase errors from the transmitted PLL. The output is connected to an external low pass filter. 5 GND2 ¾ Digital ground 6 TX_IN I 14-bit programmable transmit counter input. The output signal from the external VCO circuit can be AC coupled to this pin. 3 April 10, 2000 Preliminary Pin No. Pin Name I/O HT9015 Description 7 VCC3 ¾ Positive power supply for digital block circuits. 8 LO1 I This pin connects to LO2 pin with external crystal and capacitor. 9 LO2 O This output pin generates a reference frequency used for the PLL and the second mixer local oscillator when connected to LO1 pin with an external crystal and capacitor. 10 SIG_OUT O This pin outputs four-type states and is selected by an internal control register. There are RSSI state and noise state and RX/TX PLL lock states. Open drain output. 11 CLK I Clock input pin 12 DATA I Serial data input pin 13 STB I Data strobe control pin 14 FIL_OUT O Splatter filter output pin 15 FIL_IN I Splatter filter input pin 16 COMP_OUT O Compressor output pin 17 C_NF ¾ Normally connected to ground through a capacitor. 18 MIC_OUT O Microphone amplifier output pin 19 MIC_IN I Microphone amplifier input pin 20 PRE_IN I Pre-amplifier input pin 21 PRE_OUT O Pre-amplifier output pin 22 EXP_OUT O Expander output pin 23 RECE_IN I Receiver amplifier input pin 24 RO1 O Receiver amplifier output pin 25 RO2 O Receiver amplifier output pin 26 BAT_ALM O Battery alarm output pin. When the battery voltage is lower than the internal setting threshold this pin is active. Open drain output. 27 RSSI O Receiver signal strength indicator output pin, the output signal depends on the IF amplifier output signal. 28 D_COMP_OUT O Data comparator output pin 29 D_COMP_IN I Data comparator input pin. Input to comparator to distinguish digital data from audio. 30 N_FIL_IN I Input to noise filter 31 N_FIL_OUT O Output from noise filter 4 April 10, 2000 Preliminary Pin No. Pin Name I/O Description HT9015 32 AF_OUT O FM demodulator output pin. Output signal frequency is within the audio band. 33 QUAD I Normally provides a 455kHz carry frequency for the FM quadrature detector. 34 IF_OUT O IF amplifier output pin. Signal will later pass through external 90°C phase shifter for quadrature detector. 35 GND1 ¾ Analog ground 36 DEC ¾ Normally connected to VCC1 through a capacitor. 37 IF_IN I IF amplifier input pin it is necessary to use the IF filter network to get high quality IF signal. 38 VCC1 ¾ Analog power supply 39 2NDMIX_OUT O Second mixer IF signal output pin and down converter. IF frequency is 455kHz. 40 N_REC ¾ Connect to ground through capacitor. 41 2NDMIX_IN I Second mixer RF signal input pin and down converter. Frequency is 455kHz. 42 E_RECT ¾ Expander rectifier filter capacitor pin. 43 1STMIX_OUT O First mixer IF signal output pin and down converter. IF frequency is 10.7MHz. 44 VREF O Reference voltage input for compander. 45 1STMIX_IN I The first mixer RF signal input. Carrier frequency from 20~60MHz. 46 VCC2 ¾ Directly connects to the two voltage regulators inside. 47 VCO_CONT I Normally connected to ground through a capacitor. 48 VCO1 I Connects LC network with VCO2 pin to provide the tank circuit for the received voltage control oscillator. Absolute Maximum Ratings Supply Voltage...........................VSS-0.3V to 6V Storage Temperature.................-55°C to 150°C Input Voltage .................VSS-0.3V to VCC+0.3V Operating Temperature ..............-20°C to 70°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. 5 April 10, 2000 Preliminary HT9015 Electrical Characteristics Symbol Parameter Ta=25°C Test Conditions Conditions VCC VCC1=VCC3 Min. Typ. Max. Unit ¾ 3.6 ¾ V VCC Operating Voltage ICC1 Current 1 Consumption 3.6V All on ¾ 13.5 ¾ mA ICC2 Current 2 Consumption 3.6V RX-RF ON ¾ 8.5 ¾ mA ICC3 Current 3 Consumption 3.6V RX-AF ON ¾ 3.5 ¾ mA ICC4 Current 4 Consumption 3.6V TX-RF ON ¾ 2.1 ¾ mA ICC5 Current 5 Consumption 3.6V TX-AF ON ¾ 1.7 ¾ mA ICC(A) Current Alarm Supply 3.6V RL= 100kW ¾ 100 ¾ mA ICC(BS) Supply Current in Battery Saving Mode 3.6V All off ¾ 0 ¾ mA IREF VREF Voltage 3.6V ¾ ¾ 1.5 ¾ V VIH Data Input Threshold 3.6V ¾ ¾ VCC3 ¾ V VIL Data Input Threshold 3.6V ¾ ¾ 0 ¾ V IIH Data Input Current 3.6V VIH= VCC ¾ 0 ¾ mA IIL Data Input Current 3.6V VIL= GND ¾ 0 ¾ mA fCK CK Input Frequency 3.6V ¾ 38 1000 kHz ¾ ¾ Regulator Symbol Ta=25°C Parameter Test Conditions VCC Conditions VREG Output Voltage 3.6V IOUT= 1mA IOUT (MIN) Minimum Load Current 3.6V VOUT= VREG (Open)-0.05V Min. Typ. Max. Unit 1.7 2 2.3 V ¾ 3 ¾ mA Detector Symbol Ta=25°C Parameter Test Conditions VCC Conditions Min. Typ. Max. Unit VBAT-L Detection Voltage 1 3.6V ¾ ¾ 3.3 ¾ V VBAT-H Detection Voltage 1 3.6V ¾ ¾ 3.37 ¾ V VBAT-L Detection Voltage 2 3.6V ¾ ¾ 3.15 ¾ V VBAT-H Detection Voltage 2 3.6V ¾ ¾ 3.2 ¾ V 6 April 10, 2000 Preliminary Symbol Parameter Test Conditions VCC Conditions HT9015 Min. Typ. Max. Unit VBAT-L Detection Voltage 3 3.6V ¾ ¾ 3.05 ¾ V VBAT-H Detection Voltage 3 3.6V ¾ ¾ 3.10 ¾ V VBAT-L Detection Voltage 4 3.6V ¾ ¾ 2.78 ¾ V VBAT-H Detection Voltage 4 3.6V ¾ ¾ 2.82 ¾ V VOL Output Low Level Voltage 3.6V ISINK= 0.1mA ¾ 0.1 ¾ V ILEAK Output Leak Current 3.6V VALM= 3.6V ¾ 0 ¾ mA VTH Minimum Detection Level 3.6V f= 500Hz ¾ ¾ ¾ mVrms VOL Output Low Level Voltage 3.6V ISINK= 0.2mA ¾ 0.1 ¾ V ILEAK Output Leak Current 3.6V VDATA= 3.6V ¾ 0 ¾ mA VTH-H Noise Detection Level 3.6V ¾ ¾ 0.57 ¾ V VTH-L Noise Detection Level 3.6V ¾ ¾ 0.47 ¾ V VOL Noise Detection Level Voltage 3.6V ISINK= 0.2mA ¾ 0.1 ¾ V ILEAK Output Leak Current 3.6V VSIG= 3.6V ¾ 0 ¾ mA VTH-L RSSI Comparator Detection Voltage 3.6V Comparator Output L ® H ¾ 0.72 ¾ V VTH-H RSSI Comparator Detection Voltage 3.6V Comparator Output H ® L ¾ 0.8 ¾ V VHYS RSSI Comparator Hysteresis 3.6V ¾ ¾ 0.08 ¾ V PLL Detection Symbol dBmV=dBmV EMF (Open), Ta=25°C Parameter Test Conditions VCC Conditions Min. Typ. Max. Unit fIN Operating Frequency 3.6V ¾ ¾ 46.61 ¾ MHz VIN TX-PLL Input Sensitivity 3.6V ¾ ¾ 103 ¾ dBmV VLO Local Oscillator Input Sensitivity 3.6V fLO= 10.240MHz ¾ 110 ¾ dBmV ICP1 Charge Pump Output Current 3.6V VCP= 1.8V ¾ 200 ¾ mA ICP2 Charge Pump Output Current 3.6V VCP= 1.8V ¾ 400 ¾ mA ILEAK Charge Pump Leak Current 3.6V ¾ 0 ¾ mA fLO Local Oscillator Operating Frequency 3.6V VLO= 112dBmV ¾ 10.24 ¾ MHz 7 ¾ April 10, 2000 Preliminary HT9015 RX-VCO IF + MIX section fIN (MIX 1)=46.61MHz, fIN (IF)=455kHz, Df=3kHz fm= 1kHz, dBmV=dBmV EMF (Open), Ta=25°C Symbol Parameter Test Conditions VCC Conditions 3.6V ¾ KV Conversion Gain VVCO RX VCO Oscillation Level 3.6V fVCO= 25~55MHz Min. Typ. Max. Unit ¾ 1 ¾ MHz/V ¾ 110 ¾ dBmV 1st and 2nd Mixer, IF AMP Symbol Parameter Ta=25°C Test Conditions VCC Conditions Min. Typ. Max. Unit 12dB SINAD 12dB SINAD Sensitivity 3.6V Input 50W ¾ 20 ¾ dBmV fMIX1 Mixer Operating Frequency 3.6V 1STMIXER ¾ 46.61 ¾ MHz fMIX2 Mixer Operating Frequency 3.6V 2NDMIXER ¾ 10.7 ¾ MHz GVC Conversion Gain 3.6V Excluding Filter Loss ¾ 26 ¾ dB GIF IF AMP Gain 3.6V ¾ 75 ¾ dB VOD Demodulated Output 3.6V VIN (MIX 1)= 70dBmV ¾ 220 ¾ mVrms S/N S/N Ratio 3.6V VIN (MIX 1)= 70dBmV ¾ 55 ¾ dB AMR AM Rejection Ratio 3.6V VIN (MIX 1)= 70dBmV ¾ 40 ¾ dB RIN1 Input Impedance 3.6V 1st MIX IN ¾ 2.1 ¾ kW CIN1 Input Impedance 3.6V 1st MIX IN ¾ 3.5 ¾ pF RIN2 Input Impedance 3.6V 2nd MIX IN ¾ 5.8 ¾ kW CIN12 Input Impedance 3.6V 2nd MIX IN ¾ 2.5 ¾ pF RIN Input Resistance 3.6V IF IN ¾ 1.5 ¾ kW RO1 Output Resistance 3.6V 1st MIX OUT ¾ 330 ¾ W RO2 Output Resistance 3.6V 2nd MIX OUT ¾ 1.5 ¾ kW VRSSI1 RSSI Output Voltage 3.6V VIN (MIX 1)= 20dBmV ¾ 1 ¾ V VRSSI2 RSSI Output Voltage 3.6V VIN (MIX 1)= 60dBmV ¾ 2.4 ¾ V ¾ 8 April 10, 2000 Preliminary HT9015 Compressor + MIC AMP Symbol Parameter fIN=1kHz, Ta=25°C Test Conditions Conditions VCC Min. Typ. Max. Unit Vrefc Input Reference Level 3.6V VOM=-10dBV -10.5 dBV VOC Output Deviation 3.6V VOM=-30dBV -0.2 dB V4 MIC AMP Voltage Gain 3.6V tHDC ¾ 20 Total Harmonic Distortion 3.6V VOM=-10dBV ¾ 0.3 % VNOC Output Noise Level 3.6V Input-GND Short ¾ -61 dBV Vlim1 Limiting Level 3.6V COMP Out, VIM= 0dBV ¾ 1.3 ¾ VP-P Vlim2 Limiting Level 3.6V MIC Out, VIM= 0dBV ¾ 2.6 ¾ VP-P VMUTE Mute Output Level 3.6V ¾ -96 ¾ dBV ¾ Expander + PRE AMP + Receiver AMP Symbol Parameter dB Ta=25°C Test Conditions VCC Conditions Min. Typ. Max. Unit VrefE Input Reference Level 3.6V VOP=-10dBV ¾ -10 ¾ dBV VOE Output Deviation 3.6V VOP=-35dBV ¾ 0.5 ¾ dB GP3 PRE AMP Voltage Gain 3.6V ¾ 0 ¾ dB THD1 Total Harmonic Distortion 3.6V ¾ 0.5 ¾ % VMUTE Mute Output Level 3.6V ¾ ¾ -76 ¾ dBV GRNG2 PRE AMP Voltage Gain Setting Range 3.6V ¾ ¾ 0 ¾ dB GRNG1 Receiver AMP Voltage Gain Setting Range 3.6V ¾ ¾ 6 ¾ dB CTCE Crosstalk CE 3.6V VIM=-20dBV ¾ -95 ¾ dB GS Voltage Gain 3.6V ¾ 0 ¾ dB DRS Maximum Output Level 3.6V THD= 3% ¾ 3 ¾ VP-P ¾ RL= 150W VRI=-15dBV 9 April 10, 2000 Preliminary HT9015 Functional Description in the shift register is sent into the latch to control the block, see the input timing for serial data as shown below. The HT9015 is a signal chip RF IC for cordless phone applications. It has applications for 46/49MHz cordless phones as well as CT0 cordless phones that have frequency bands between 20MHz and 60MHz. This chip enables external components in the base set and hand set radio section application circuits to be reduced. Serial data format of four registers According to previous input timing Specs, the HT9015 can be easily set up using four registers. The TX divider determines the TX PLL locked frequency; the RX divider determines the RX PLL locked frequency; the REF divider determines the TX and RX PLL frequency reference which is also called channel space. The control register is an important unit which controls the radio link, voice control and power saving during base set and hand set communication. The HT9015 is manufactured or a special process called BiCMOS, or bipolar process and CMOS process. Because the RF and IF parts need high frequency actions such as mixer, VCO, IF amplifier and demodulator, those parts are implemented in high performance bipolar circuits. The other digital functions are designed using CMOS circuits. Sometimes this chip is known as ²COMBO², the meaning of COMBO is one chip combined with RF, IF and PLL parts. All data format contains 20 bits, but some registers need only 16 bits, They have a common field of 20 bits data format called ²code² which determine what data belongs to whom. See the table below. The HT9015 provides data latch interface controlled by a microcontroller. There are four internal registers inside the HT9015; TX (transmitter) divider, RX (receiver) Divider, REF (reference) divider and Control Register. All registers can be set through the data latch control interface. The data latch control interface contains DATA, CLK and STB control signals. Code Input timing for serial data 1 1 REF register 1 0 TX register 0 1 RX register 0 0 Control register Data is read on the timing of the rising edge of CLK. When STB receives a high signal, DATA ³ 1 m s C L K Register Four register selection ³ 0 .2 m s ³ 0 .2 m s ³ 0 .2 m s D A T A ³ 0 .1 m s ³ 0 .1 m s ³ 0 .2 m s S T B ³ 0 .2 m s O p e r a tio n S ta te P r e v io u s S ta te N e w S ta te Figure 1 Input timing for serial data 10 April 10, 2000 Preliminary HT9015 · REF register Divide number range is from 5 to 4095. This register includes TEST bits which must be set to 0. D o n 't C a r e T e s t 0 R 0 B C R 1 R 2 1 2 - b it R C o u n te r R 4 R 6 R 3 R 5 R 7 C o d e R 8 R 9 R 1 0 R 1 1 1 1 1 s t S T B Divide number: 2 3 11 R= R0 + R1 ´ 2 + R2 ´ 2 + R3 ´ 2 + ¼ + R11 ´ 2 BC bit is BATTERY ALARM detection setting. · TX register Divide number range is from 5 to 16383. D o n 't C a r e 1 4 - b it N N 0 N 1 N 2 N 3 N 4 N 5 N 6 S C o d e C o u n te r N 7 N 8 N 9 N 1 0 N 1 1 N 1 2 N 1 3 1 1 s t 0 S T B Divide number: 2 3 N= N0 + N1 ´ 2 + N2 ´ 2 + N3 ´ 2 + ¼ + N12 ´ 2 12 + N13 ´ 2 13 · RX register Divide number range is from 5 to 16383. D o n 't C a r e 1 4 - b it N N 0 N 1 N 2 N 3 N 4 N 5 N 6 C o d e C o u n te r N 7 N 8 N 9 N 1 0 N 1 1 N 1 2 N 1 3 1 s t 0 1 S T B Divide number: 2 3 12 N= N0 + N1 ´ 2 + N2 ´ 2 + N3 ´ 2 + ¼ + N12 ´ 2 13 + N13 ´ 2 · Control register This register includes battery saving control for the TX/RX circuits or MUTE controls for the commander block or changing threshold level for the battery alarm. D o n 't C a r e S IG T X L D 1 s t R X L D O U T R S S I T X N D L D , R S S I, N D S e le c tio n R F B a tte ry S a v in g A F R X C P M U T E C h a rg e C O M P P u m p M U T E C u rre n t 11 R F A F B a tte ry S a v in g B A T C P M U T E C h a rg e E X P P u m p M U T E C u rre n t B A 1 C o d e B A 2 B A T T E R Y A L A R M T h r e s h o ld 0 0 S T B April 10, 2000 Preliminary HT9015 ¨ Battery saving control 0 ¼¼¼¼Operation 1 ¼¼¼¼Battery saving Bit Control Block TX-RF TX-PLL TX-RF= 1 and RX-RF= 1 LOCAL OSC= OFF TX-AF MIC AMP, Compressor, Splatter RX-RF RX-VCO, RX-PLL, 1st MIX, 2nd MIX IF AMP, NOISE DET, DATA COMP, RSSI RX-AF Pre AMP, Expander, Receiver AMP ¨ MUTE control 0 ¼¼¼¼normal 1 ¼¼¼¼MUTE MUTE for Compressor output. These bits prevent the compander block going into a battery saving mode. Current consumption therefore does not decrease. ¨ Charge pump current control PLL loop performance such as lock-up time can be changed by these control bits. Bit Control Output 0 1 TX CP TX-PLL Charge Pump Output Current 200mA 400mA RX CP RX-PLL Charge Pump Output Current 200mA 400mA ¨ BATTERY ALARM detection setting There are has four threshold levels for low battery detection. These threshold levels are shown on the table below. (1) BC (1) (2) BA1 BA2 VBAT-L 0 0 0 3.00V 0 0 1 3.25V 0 1 0 3.30V 0 1 1 3.45V 1 0 0 1 1 1 (2) Battery Saving BC bit in REF divider Only for BATTERY ALARM block 12 April 10, 2000 Preliminary HT9015 ¨ SIG_OUT selection The SIG_OUT terminal generates combination states of RX and TX lock detectors. The RSSI and NOISE detector are shown in figure 2 below. SW1 and SW2 in Fig. 3 determine the output on SIG_OUT using selection bits in a control register according to the figure below. L D T X L D R X R S S I D e c id e S W 1 a n d L D O U T N D D e c id e S W 2 a n d D E T O U T E x a m p le : T X lo c k d e te c to r o p e r a tio n L D T X L D R X R S S I N D 1 0 0 0 Figure 2 SIG_OUT bits R X P L L S W 1 L O C K D E T E C T O R L D O U T S IG _ O U T R X L D T X L D T X P L L S W 2 D E T O U T IF A M P N O IS E D E T E C T O R R S S I R S S I In te rn a l R S S I D E T N D N _ R E C N _ F IL _ O U T N _ F IL _ IN A F O U T E x te rn a l Figure 3 Signal output block diagram 13 April 10, 2000 Preliminary HT9015 · Example of divider setting When the LOCAL OSC frequency is 10.240MHz, RX VCO has to oscillate at frequencies from 35.915MHz in 20kHz or 25kHz step. ¨ Reference frequency at the PHASE DETECTOR should be set to 5kHz. ¨ 10.240MHz ¸ 5kHz = 2048, \ R= 2048 ¨ Calculate dividing number N for RX divider ¨ 35.915MHz ¸ 5kHz = 7183, \ N (CH16)= 7183 ¨ 35.935MHz ¸ 5kHz = 7187, \ N (CH17)= 7187 ¨ Finally you set the following registers. R X D iv id e r fo r 7 1 8 3 C o d e N 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 s t 1 S T B R E F D iv id e r fo r R = 2 0 4 8 T e s t B C 1 1 0 C o d e 0 0 0 1 s t 0 0 0 0 0 0 0 1 1 1 S T B · The power saving arrangement is one of the features in the HT9015. This is achieved through an inside control register to arrange the power consumption of the three major parts (RF. IF. PLL). There are two-pair DC power supplies for the HT9015, VCC1-GND1 and VCC3-GND2. The DC power VCC1 provides operating voltage for the IF detector and the compander analog parts. The DC power VCC3 provides the operating voltage for the PLL and data latch control. It also has a built in 2.0V regulator VCC2 for the RX front end. See the power supply arrangement as shown on the table below. VCC1 GND1 1st MIX, 2nd MIX, IF AMP, QUAD, NOISE DET. RX-VCO DATA COMP, COMPANDER, RECEIVER AMP, SPLATTER. VCC3 GND2 RX-PLL, TX-PLL, LOCAL OSC, DATA LATCH CONTROL 14 April 10, 2000 Preliminary · Mixers Intermediate frequency (IF) decoder part A Mixer is a non linear device whose purpose is to convert radio frequencies (RF) to intermediate frequency (IF) (RF-to-IF frequency translation). In the frequency conversion process, RF signals are combined with the local oscillator frequency in a non linear device. The output of the mixer contains an infinite number of harmonic and cross-product frequencies which include the sum and the difference between the desired RF carrier and the local oscillator frequencies. The IF band-pass filter are tuned to the different frequencies. Therefore, the IF signal is filtered out by the BPF. In the HT9015 the double conversion method (Figure 4) is applied to produce the lower IF. The figure below shows a simplified block diagram for a double-conversion super heterodyne FM receiver. Heterodyne means to mix two frequencies together in a non linear device or to translate one frequency to another using non linear mixing. The super heterodyne receiver is an improvement over other receiver in gain, selectivity, and sensitivity characteristics. The super heterodyne receiver is divided into five parts: · RF section. Generally consists of a preselector and an amplifier stage. · Mixer conversion section. Includes a ra- dio-frequency oscillator stage (commonly known as a local oscillator) and a mixer conversion stage (commonly known as a frequency detector) to produce the IF signal. · The IF section. Generally consists of a series of IF amplifiers and bandpass filters and known as the IF strip. Most of the receiver gain and selectivity is achieved in the IF section. · The FM demodulator section: The quadrature FM demodulator uses a 90° phase shift, a single tuned circuit, and a product detector to demodulate the FM signals. · The audio amplifier section. The audio section comprises several cascaded audio amplifiers and one or more speakers. The number of amplifiers used depends on the audio signal power desired. The first IF is a relatively high frequency (10.7MHz), for good image-frequency rejection, while the second IF is a relatively low frequency (455kHz) that allows the IF amplifiers to have a relatively high gain and still not be susceptible to oscillations. 2 n d IF Q u a d ra tu re D e te c to r IF _ A M P 2 n d L o _ o s c ( C r y s ta l) R S S I L P F N _ F IL _ O U T 1 s t L o _ o s c (R X _ V C O ) 2 n d IF Figure 4 The illustration of mixers A F _ O U T 2 n d M ix e r C e r a m ic F ilte r N _ F IL _ IN 1 s t M ix e r (4 5 5 k H z ) 1 s t IF 2 n d L o _ o s c ( C r y s ta l) 1 s t L o _ o s c (R X _ V C O ) Q U A D 1 s t IF R F (1 0 .7 M H z ) C e r a m ic F ilte r R F IF _ O U T In te rn a l D E C IF _ IN 2 n d _ M ix in R F - a m p lifie r 1 s t_ M ix o u t P r e s e le c to r 2 n d _ M ix o u t R e c e iv e a n te n n a HT9015 N o is e F ilte r N o is e C O M P D _ C O M P _ IN D a ta C O M P R S S I C O M P D _ C O M P _ O U T R S S I Figure 5 Intermediate frequency decoder block 15 April 10, 2000 Preliminary · Limiting IF Amplifier, RSSI (Received Signal HT9015 · Quadrature detector Strength Indicator) and RSSI Comparator Once the signal leaves the IF section, it must be demodulated so that the baseband signal can be separated from the IF signal. This is accomplished by the quadrature detector. A quadrature detector (Figure 7) uses a 90° phase shifter (Ci), an L/C tuned circuit, and a phase comparator to demodulate FM signals. The basic function of the IF amp is to boost the IF signal and to help handle impulse noise. The IF limiter applies very high gain to the IF frequency such that the top and bottom of the waveform are clipped. This helps in reducing AM and noise intercepted upon reception. The limiting IF amplifier consists of four differential amplifiers (Figure 6). L C -T a n k IF -O U T D E C A M P 1 O F -IN A M P 2 A M P 3 Q u a d ra tu re D e te c to r A M P 4 In te rn a l 2 n d IF S (R S S I) Figure 6 Limiting IF Amplifier, RSSI and RSSI comparator V L D D C D iffe r e n tia l to S in g le - E n d e d C o n v e r te r L C -T a n k R D e m o d u la tio n S ig n a l IL 2 ¯ IL 1 ¯ L P F f0 = 4 7 k H z C i V O B u ffe r ¯ I1 ¯ IF _ A M P V I2 ¯ i I= I1 + I2 ¯ Figure 7 Quadrature detector 16 April 10, 2000 Preliminary HT9015 · Noise detector control register setting. The high state expresses noise level more than 0.4V and the low state expresses noise level under 0.4V. Figure 8 is a band pass filter which can detect noise energy on N_REC pin. There is also a pass through the noise comparator to determine two states on SIG_OUT pin by internal V B a n d - P a s s F ilte r F O = 3 1 k H z N o is e F ilte r N _ F IL _ IN E x te rn a l V O U T D D H ig h - P a s s F ilte r F C = 2 5 k H z R 5 A M P R 4 C 3 N _ F IL _ O U T N _ R E C R 3 A u d io S ig n a l C 1 N o is e C o m p a r a to r N o is e D e t. In te rn a l C 4 C 2 E x te rn a l R 1 R 2 Figure 8 Noise detector 17 April 10, 2000 Preliminary HT9015 Compander In the HT9015, the compressor will take a signal with a 75dB dynamic range (-5dB to -80dB), and reduce it to a 37.5dB dynamic range (-7.5dB to -45dB) by attenuating strong signals,while amplifying low level signals. The expander does the opposite in that the 37.5dB signal range is increased to a dynamic range of 75dB by amplifying strong signals and attenuating low level signals. The 0dB level is internally set at 316.227mVrms - that is the signal level which is neither amplified nor attenuated. See Figure 9 below. Through the action of the compander, the noise of the transmission medium is constant under -80dBV. The compander (compressor and expander) is composed of two variable gain circuits which provide compression and expansion of the signal dynamic range. In consideration of the wide band noise and maximum dynamic range which exist in the transmission medium, the general signal handling technique lowers the general communication quality by reducing the S/N ratio and generating a clipping phenomenon. However the compander improves the communication quality by automatically controlling the gain based on the input signal level to increase the valid dynamic range and to improve the S/N ratio. C o m p re s s o r In p u t C o m p re s s o r O u tp u t E x p a n d e r In p u t T r a n s m is s io n M e d iu m 0 d B V - 5 d B V - 1 0 .5 d B V 0 d B V - 7 .7 5 d B V - 1 5 .2 5 d B V - 2 0 d B V - 3 0 d B V - 4 0 d B V - 2 5 .2 5 d B V - 3 5 .2 5 d B V - 1 0 .5 d B V - 3 0 d B V - 4 0 d B V - 5 0 d B V - 4 5 .2 5 d B V - 7 0 d B V - 8 0 d B V - 5 d B V - 2 0 d B V - 5 0 d B V - 6 0 d B V E x p a n d e r O u tp u t - 6 0 d B V - 7 0 d B V N o is e - 8 0 d B V Figure 9 Illustration of compressed and extended signal 18 April 10, 2000 Preliminary HT9015 PLL erence frequency for the receiver (RX) and transmitter (TX) loops. The figure below shows a simplified block diagram of the programmable universal dual phase-locked loop (PLL). It provides accurate channel frequencies for cordless phone. This dual PLL is fully programmable through the mC serial interface and supports most country channel frequencies including USA, Spain, Australia, Korea, New Zealand, U.K., Netherlands, France, Taiwan, and China. The PLL contains one 14-bit programmable counter, one phase detector, charge pump, unlock detector and the 2nd local oscillator. The 12-bit programmable counter provides the ref- V C O _ C O N T V C O 1 V C O 2 R X _ O U T T X _ O U T R X _ V C O C h a rg e P U M P (R X ) C h a rg e P U M P (T X ) 1 4 - B it R X C o u n te r P h a s e D e te c to r (R X ) P h a s e D e te c to r (T X ) 1 2 - B it R E F C o u n te r L O C A L O s c illa to r 1 4 - B it T X C o u n te r D a ta L a tc h R e g is te r L O 2 L O 1 S T B D A T A C L K T X _ IN Figure 9 PLL block diagram 19 April 10, 2000 R F IN 4 6 .6 1 M H z V C C 2 C 1 0 1 1 0 0 0 0 p F C 9 L 1 0 C 1 3 4 5 4 4 V R E F 4 6 C F 1 1 0 .7 M H z R 9 3 3 0 W 4 5 5 k H z V C C 1 V C C 1 C 3 0 1 0 m F N _ R E C 2 N D M IX _ O U T V C C 1 IF _ IN D E C G N D 1 IF _ O U T Q U A D 3 3 V C C 1 C D 3 4 ~ 3 5 ~ 3 6 ~ 3 7 ~ 3 8 C 2 9 9 1 p F C 2 4 0 .1 m F 3 9 C 2 5 0 .1 m F C 1 9 1 0 0 0 p F 4 0 C 2 1 C 2 3 2 2 m F 0 .1 m F C 1 7 2 .2 m F 4 1 ~ 4 2 ~ 4 3 V C C 2 V C O -C O N T V C O 1 V C O 2 C _ R E C C T R X -O U T T X _ O U T V C C 3 S IG _ O U T C _ N F R 1 6 R 2 2 R 1 7 1 0 k W C 3 6 1 m F R 2 1 2 k W 1 9 M IC _ IN R 1 8 3 .3 k W P R E _ IN P R E _ O U T E X P _ O U T R E C E _ IN 2 7 2 6 2 5 2 0 2 1 2 2 2 3 R O 1 2 4 R O 2 B A T _ A L M R S S I D _ C O M P _ O U T 1 8 M IC _ O U T 1 7 R 2 0 2 0 k W T V C C 3 1 0 k W M IC C 3 8 1 m F R 2 4 2 0 k W R 2 7 1 0 0 k W 1 0 0 0 p F C 3 7 1 m F C 2 3 C 3 4 R 1 9 2 2 0 p F 2 2 0 p F 5 0 k W 3 0 N _ F IL _ IN 3 2 3 1 N _ F IL _ O U T 2 9 D _ C O M P _ IN 2 8 A F _ O U T 1 6 C O M P _ O U T 1 5 C 3 2 A u d io O u tp u t R 1 5 1 .5 k W 1 4 R 1 4 C 3 1 1 0 m F R 1 3 R 1 1 D A T I C 2 8 C 2 7 R 1 2 F IL _ IN 1 3 C 2 6 S T B F IL _ O U T 1 0 k W D A T A S T B 1 2 D A T A 1 1 C L K 1 0 C L K M ic r o c o n tr o lle r O U T R 1 0 1 0 0 k W 9 L O 2 8 L O 1 7 C 2 0 C 2 2 S IG H T 9 0 1 5 4 8 S S O P 2 N d M IX _ IN 4 7 4 8 C 1 5 C 1 0 0 .1 m F C 1 1 1 0 m F C 1 2 1 0 0 0 p F 2 .2 m F L 1 1 1 2 3 4 6 G N D 2 T X _ IN C 9 1 0 0 0 p F 5 E _ R E C T R 1 0 2 5 .1 k W C 1 4 1 0 m F R 1 1 2 1 0 k W C 8 0 .1 m F C 1 8 1 0 m F 1 S T M IX _ O U T 1 S T M IX _ IN C 1 0 2 0 .2 2 m F R 1 0 1 1 5 k W R 1 1 1 1 5 k W C 1 1 1 1 0 0 0 0 p F C 1 0 3 1 0 0 0 0 p F C 1 1 2 0 .2 2 m F C 1 1 3 1 0 0 0 0 p F V C O V C C 3 X 't a l 1 0 .2 4 0 M H z D A T O K e y b o a r d & L C D In te r fa c e R 2 7 1 0 0 k W V C C 1 C 3 9 1 m F R E C E IV E R V C C 1 R R 2 6 2 0 k W R 2 5 2 0 k W R 2 3 2 0 k W April 10, 2000 20 HT9015 Preliminary Application Circuits Preliminary HT9015 China CT0 frequency · Base set RX Counter Value TX Counter Value fIN-R Input (Ref. Freq.= (Ref. Freq.= Frequency (MHz) 5.00kHz) 5.00kHz (1st IF= 10.7MHz) Channel Number TX Channel Frequency (MHz) 1 45.250 9050 37.550 7510 2 45.275 9055 37.575 7515 3 45.300 9060 37.600 7520 4 45.325 9065 37.625 7525 5 45.350 9070 37.650 7530 6 45.375 9075 37.675 7535 7 45.400 9080 37.700 7540 8 45.425 9085 37.725 7545 9 45.450 9090 37.750 7550 10 45.475 9095 37.775 7555 · Hand set RX Counter Value TX Counter Value fIN-R Input (Ref. Freq.= (Ref. Freq.= Frequency (MHz) 5.00kHz) 5.00kHz (1st IF= 10.7MHz) Channel Number TX Channel Frequency (MHz) 1 48.250 9650 34.550 6910 2 48.275 9655 34.575 6915 3 48.300 9660 34.600 6920 4 48.325 9665 34.625 6925 5 48.350 9670 34.650 6930 6 48.375 9675 34.675 6935 7 48.400 9680 34.700 6940 8 48.425 9685 34.725 6945 9 48.450 9690 34.750 6950 10 48.475 9695 34.775 6955 21 April 10, 2000 Preliminary HT9015 U.S.A. CT0 frequency (10 channels) · Base set RX Counter TX Counter Value fIN-R Input (Ref. Freq.= Frequency (MHz) Value (Ref. Freq. = 5.00kHz) 5.00kHz (1st IF= 10.695MHz) Channel Number TX Channel Frequency (MHz) 1 46.610 9322 38.975 7795 2 46.630 9326 39.150 7830 3 46.670 9334 39.165 7833 4 46.710 9342 39.075 7815 5 46.730 9346 39.180 7836 6 46.770 9354 39.135 7827 7 46.830 9366 39.195 7839 8 46.870 9374 39.235 7847 9 46.930 9386 39.295 7859 10 46.970 9394 39.275 7855 Channel Number TX Channel Frequency (MHz) TX Counter Value (Ref. Freq.= 5.00kHz fIN-R Input Frequency (MHz) (1st IF= 10.7MHz) RX Counter Value (Ref. Freq. = 5.00kHz) 1 49.670 9934 35.915 7183 2 49.845 9969 35.935 7187 3 49.860 9972 35.975 7195 4 49.770 9954 36.015 7203 5 49.875 9975 36.035 7207 6 49.830 9966 36.075 7215 7 49.890 9978 36.135 7227 8 49.930 9986 36.175 7235 9 49.990 9998 36.235 7247 10 49.970 9994 36.275 7255 · Hand set 22 April 10, 2000 Preliminary HT9015 Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. 23 April 10, 2000