144 pin SO-DIMM SDRAM Modules HYS64V64220GBDL-7/7.5/8-D 512 MB PC100 / PC133 • u144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules for notebook applications • Two bank 64M x 64 non-parity module organisation • suitable for use in PC100 and PC133 applications • Performance: -7 -7.5 -8 PC133 2-2-2 PC133 3-3-3 PC100 2-2-2 Units fCK Clock frequency (max.) 133 133 100 MHz tAC Clock access time CAS latency = 2 & 3 5.4 5.4 6 ns • Single +3.3V(± 0.3V ) power supply • Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Decoupling capacitors mounted on substrate • All inputs, outputs are LVTTL compatible • Serial Presence Detect with E 2PROM • Uses sixteen 256Mbit SDRAM (32Mb x8 ) components in P-TFBGA packages • 8196 refresh cycles every 64 ms • Gold contact pad, JEDEC MO-190 outline dimensions • This module family is fully pin and functional compatible with the latest INTEL SO-DIMM specification • Importante Notice: This SO-DIMM module is based on 256Mbit SDRAM technology and can be used in applications only, where 256Mbit addressing is supported. INFINEON Technologies 1 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules This INFINEON module is an industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small Outline Dual In-line Memory Modules (SO-DIMM) which is organised as 64Mx64 high speed array in two memory banks designed for use in non-parity applications. These SO-DIMMs use back side protected P-TFBGA package technology. Decoupling capacitors are mounted on the board. The DIMMs use serial presence detects implemented via a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,6 mm long footprint. Product Spectrum 64M x 64 64M x 64 64M x 64 SDRAMs RowAddr. Bank Column Refresh used Select Addr. HYS64V64220GBDL-7-D 16 32Mx8 13 BA0, BA1 10 8k HYS64V64220GBDL-7.5-D 16 32Mx8 13 BA0, BA1 10 8k HYS64V64220GBDL-8-D 16 32Mx8 13 BA0, BA1 10 8k Period 64 ms 64 ms 64 ms Note: All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS64V64220GBDL-8-D, indicating Rev.D dies are used for SDRAM components. Card Dimensions Organisation 64M x 64 PCB-Board L-DIM-144-14 L x H x T [mm] 67.60 x 29.21 x 3.80 Pin Names A0-A12 Address Inputs BA0,BA1 Bank Selects DQ0 - DQ63 Data Input/Output RAS Row Address Strobe CAS Column Address Strobe WE Read / Write Input CKE0, CKE1 Clock Enable CLK0, CLK1 Clock Input DQMB0 - DQMB7 Data Mask CS0, CS1 Chip Select VDD Power (+3.3 Volt) Vss Ground SCL Clock for Presence Detect SDA Serial Data Out for Presence Detect N.C. No Connection Infineon Technologies 2 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules Pin Configuration PIN # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Front Side VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 Vss DQMB0 DQMB1 VDD A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 Vss NC NC CLK0 VDD RAS WE CS0 CS1 Infineon Technologies PIN # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Back Side PIN # VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 Vss DQMB4 DQMB5 VDD A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 DQ46 DQ47 Vss NC NC CKE0 VDD CAS CKE1 A12 (A13) 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 3 Front Side NC Vss NC NC VDD DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 VDD A6 A8 Vss A9 A10 VDD DQMB2 DQMB3 Vss DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 Vss SDA VDD PIN # 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back Side CLK1 Vss NC NC VDD DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 VDD A7 BA0 Vss BA1 A11 VDD DQMB6 DQMB7 Vss DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 Vss SCL VDD 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules CS1 CS0 CS CS CS CS DQMB0 DQM DQM DQMB4 DQM DQM DQ(7:0) DQ0-DQ7 DQ0-DQ7 DQ(39:32) DQ0-DQ7 DQ0-DQ7 DQMB1 DQM DQM DQMB5 DQM DQM DQ(15:8) DQ0-DQ7 DQ0-DQ7 D0 D4 DQ(47:40) DQ0-DQ7 D2 DQ0-DQ7 D6 DQMB2 DQM DQM DQMB6 DQM DQM DQ(23:16) DQ0-DQ7 DQ0-DQ7 DQ(55:48) DQ0-DQ7 DQ0-DQ7 DQMB3 DQM DQM DQMB7 DQM DQM DQ(31:24) DQ0-DQ7 D1 DQ0-DQ7 D5 DQ(63:56) DQ0-DQ7 D3 DQ0-DQ7 D7 CS A0-A12,BA0,BA1 CS CS D0 - D7 E2PROM (256wordx8bit) VDD D0 - D7 SA0 SA1 SA2 C VSS RAS, CAS, WE D0 - D7 D0 - D7 CKE0 D0 - D3 CKE1 D4 - D7 CLK0 CLK1 CS SCL SDA 8 Loads 8 Loads Note: 1. DQ wiring may differ from the description in this drawing, however DQ/DQMB/CKE/CS relationship is maintained as shown. 2. In this design each of the D0 - D7 components are represented by two 32M x 8 chips. These two chips effectively work as a single 32M x 16 device. 3. All resistors are 10 Ohm. Block Diagram for two bank 64M x 64 SDRAM DIMM - Module Infineon Technologies 4 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules Absolute Maximum Ratings Parameter Symbol Limit Values min. max. Unit Input / Output voltage relative to VSS VIN, VOUT – 1.0 4.6 V Power supply voltage on VDD VDD – 1.0 4.6 V Storage temperature range TSTG -55 +125 oC Power dissipation PD – 16 W Data out current (short circuit) IOS – 50 mA Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V Parameter Symbol Limit Values Unit min. max. Input high voltage VIH 2.0 VDD+0.3 V Input low voltage VIL – 0.5 0.8 V Output high voltage (IOUT = – 4.0 mA) VOH 2.4 – V Output low voltage (IOUT = 4.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 20 20 µA Output leakage current (DQ is disabled, 0 V < VOUT < VDD) IO(L) – 20 20 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit 64M x 64 max. Input capacitance (A0 to A11, BA0, BA1) CI1 85 pF Input capacitance (RAS, CAS, WE) CI2 85 pF Input Capacitance (CLK0, CLK1) CI3 70 pF Input capacitance (CS0, CS1) CI4 60 pF Input capacitance (DQMB0-DQMB7) CI5 15 pF Input capacitance (CKE0, CKE1) CI6 50 pF Input / Output capacitance (DQ0-DQ63) CIO 18 pF Input Capacitance (SCL,SA0-2) Csc 8 pF Input/Output Capacitance (SDA) Csd 10 pF Infineon Technologies 5 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules Operating Currents per memory bank (TA = 0 to 70oC, VDD = 3.3V ± 0.3V) (Recommended Operating Conditions unless otherwise noted) Symb. Parameter & Test Condition 64Mx64 512Mbyte Note PC133 PC100 ICC1 1840 1360 mA ICC2P 16 16 mA 240 mA 1 ICC2N 320 OPERATING CURRENT trc=trcmin., All banks operated in random access, all banks operated in ping-pong manner PRECHARGE STANDBY CURRENT in Power Down Mode tck = min. 1, 2 1 CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode tck = min. CS = VIH (min.), CKE>=Vih(min) NO OPERATING CURRENT CKE>=VIH(min.) ICC3N 400 360 mA 1 tck = min., CS = VIH(min), active state ( max. 4 banks) CKE<=VIL(max.) ICC3P 80 80 mA 1 BURST OPERATING CURRENT tck = min., Read command cycling ICC4 1200 800 mA 1, 2 AUTO REFRESH CURRENT tck = min., trc = trcmin. Auto Refresh command cycling mA 1 ICC5 1920 1760 ICC6 14 14 mA 1 SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V tck =infinity Notes: 1. These parameters depend on the cycle rate. These values are measured at 133 MHz operation frequency for PC133 and at 100MHz for PC100 modules. Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the data-out current is excluded. Infineon Technologies 6 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules AC Characteristics 9)10) TA = 0 to 70 oC; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Unit Limit Values -7 PC133222 min. -7.5 PC133333 max. min. -8 PC100222 max. min. max. Clock and Clock Enable Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK 7 7.5 – – 7.5 10 – – 8 10 Clock Frequency CAS Latency = 3 CAS Latency = 2 tCK – – 143 133 – – 133 100 – – Access Time from Clock CAS Latency = 3 CAS Latency = 2 tAC – – 5.4 5.4 – – 5.4 6 – – 6 6 ns ns – – ns ns 125 MHz 100 MHz 2, 3, 6 Clock High Pulse Width tCH 2.5 – 2.5 – 3 – ns Clock Low Pulse Width tCL 2.5 – 2.5 – 3 – ns Transition time tT 0.3 1.2 0.3 1.2 0.5 10 ns tIS 1.5 – 1.5 – 2 – ns 4 Input Hold Time tIH 0.8 – 0.8 – 1 – ns 4 CKE Setup Time tCKS 1.5 – 1.5 – 2 – ns 4 CKE Hold Time tCKH 0.8 – 0.8 – 1 – ns 4 Mode Register Set-up to Active delay tRSC 2 – 2 – 2 – CLK Power Down Mode Entry Time tSB 0 7 0 7.5 0 8 ns Row to Column Delay Time tRCD 15 – 20 – 20 – ns 5 Row Precharge Time tRP 15 – 20 – 20 – ns 5 Setup and Hold Times Input Setup Time Common Parameters Infineon Technologies 7 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules AC Characteristics 9)10) TA = 0 to 70 oC; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Unit Limit Values -7 PC133222 min. -7.5 PC133333 max. min. -8 PC100222 max. min. max. Row Active Time tRAS 37 100k 45 100k 48 100k ns 5 Row Cycle Time tRC 60 – 67 – 70 – ns 5 Row Cycle Time during Auto Refresh tRFC 63 Activate(a) to Activate(b) Command period tRRD 14 – 15 – 16 – ns CAS(a) to CAS(b) Command period tCCD 1 – 1 – 1 – CLK Refresh Period (8192 cycles) tREF – 64 – 64 – 64 Self Refresh Exit Time tSREX 1 – 1 – 1 Data Out Hold Time tOH 3 – 3 – 3 – ns Data Out to Low Impedance Time tLZ 0 – 0 – 0 – ns Data Out to High Impedance Time tHZ 3 7 3 7 3 8 ns DQM Data Out Disable Latency tDQZ – 2 – 2 – 2 CLK tWR 14 – 15 – 15 – ns 67 70 ns 5 Refresh Cycle ms CLK Read Cycle 2, 6 Write Cycle Last Data Input to Precharge 7 (Write without AutoPrecharge) Last Data Input to Activate CLK 8 tDAL,min (Write with AutoPrecharge) DQM Write Mask Latency Infineon Technologies tDQW 0 – 8 0 – 0 – CLK 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules Notes 1. For proper power-up see the operation section of the component sheet. 2. AC timing tests for LV-TTL versions have V IL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V. t CH 2.4 V 0.4 V 1 .4 V CLOCK tCL t IS tT t IH 1 .4 V IN P U T t AC tLZ tA C t OH O UTPUT 1.4 V I/O 50 pF tHZ IO.vsd Measurement conditions for tAC and tOH 3. If clock rising time is longer than 1 ns, a time ( tT /2 − 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (tT − 1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing period (counted in fractions as a whole number) 6. Access time from clock tAC is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time tOH is 1.8 ns for PC133 components with no termination and 0 pF load. 7. It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without Auto-Precharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tck greater or equal the specified twr value, where tck is equal to the actual system clock time 8. When a Write command with AutoPrecharge has been issued, a time of tdal(min) has be fullfilled before the next Activate Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tck is equal to the actual system clock time. 9. All AC characteristics shown are for SDRAM components. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 10.AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns Infineon Technologies 9 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules with the AC output load circuit shown.Specified tac and toh parameters are measured with a 50pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. Infineon Technologies 10 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules Serial Presence Detects A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus) SPD-Table: Byte# Description SPD Entry Value Hex 64Mx64 -7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-toback random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 SDRAM Access Time from Clock at CL=2 SDRAM Cycle Time at CL = 1 SDRAM Access Time from Clock at CL=1 Minimum Row Precharge Time Infineon Technologies 128 256 SDRAM 12 64Mx64 -7.5 80 08 04 0D 10 2 64 0 LVTTL 7.5ns / 10.0 ns 5.4ns / 6.0 ns 0A 02 40 00 01 75 54 75 54 none Self-Refresh, 7,6µs x8 n/a tccd = 1 CLK 00 82 08 00 01 1, 2, 4 & 8 2 2, & 3 CS latency = 0 Write latency = 0 non buffered/non reg. VDD tol +/- 10% 7.5ns / 10.0 ns 5.4ns / 6.0 ns 0F 04 06 01 01 00 75 54 not supported not supported 00 00 20 ns 0F 11 64Mx64 -8 A0 60 0E A0 60 FF FF FF FF 14 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules SPD-Table (cont’d): Byte# Description 28 Minimum Row Active to Row Active delay 29 Minimum RAS to CAS delay 30 Minimum Ras pulse width 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 36-61 Superset information 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufactures’s information (optional) 125 126 Frequency Specification 127 Details 128+ Unused storage locations Infineon Technologies SPD Entry Value Hex Hex Hex 14/15/16 ns 64Mx64 -7 0E 64Mx64 -7.5 0F 64Mx64 -8 10 15/20 ns 42/45 ns 256 MB 2 ns 1 ns 2 ns 1 ns 0F 2A 15 08 15 08 00 Revision 1.2 0E PC100 00 12 14 2D 40 15 08 15 08 FF 12 37 XX 64 C7 FF 32 20 10 20 10 FF 9A FF 2002-08-06 HYS64V64220GBDL-7/7.5/8-D 144 pin SO-DIMM SDRAM Modules Package Outlines 512 MByte SO-DIMM Module package (JEDEC MO-190) (144 pin, dual in-line memory module) 67.6 ± 0.15 3.8 max. Detail of Contacts 29.21 ± 0.25 2.55 0.15 63.6 0.6 heat spreader 1 (3.3) 23.2 59 61 32.8 143 1± 0.1 0.8 2.5 24.5 4.6 2 1.5 60 1.8 62 Detail of Chamfer 144 0.2 - 4 0.15 20 6 4 (3.7) 0.2 0.15 L-DIM-144-14 Note: All tolerances according to JEDEC standard Infineon Technologies 13 2002-08-06