IDT ICS8402AYILF

ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
General Description
Features
The ICS8402I is a general purpose,
Crystal-to-LVCMOS/LVTTL High Frequency
HiPerClockS™
Synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS8402I has a selectable TEST_CLK or
crystal inputs. The VCO operates at a frequency range of 250MHz
to 700MHz. The VCO frequency is programmed in steps equal to
the value of the input reference or crystal frequency. The VCO and
output frequency can be programmed using the serial or parallel
interfaces to the configuration logic. The low phase noise
characteristics of the ICS8402I make it an ideal clock source for
Gigabit Ethernet and SONET applications.
ICS
•
•
Two LVCMOS/LVTTL outputs
•
•
•
•
Output frequency range: 15.625MHz to 350MHz
•
•
•
•
•
RMS period jitter: 30ps (maximum)
Selectable crystal oscillator interface or LVCMOS/LVTTL
TEST_CLK
Crystal input frequency range: 12MHz to 40MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming counter and
output dividers
Cycle-to-cycle jitter: 100ps (maximum)
Full 3.3V or mixed 3.3V core/2.5V output supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
XTAL_IN
nP_LOAD
M0
M1
M2
32 31 30 29 28 27 26 25
VCO_SEL
XTAL_SEL
0
XTAL_IN
1
XTAL_OUT
PLL
XTAL_OUT
23
TEST_CLK
M7
3
22
XTAL_SEL
M8
4
21
VDDA
N0
5
20
S_LOAD
N1
6
19
S_DATA
nc
7
18
S_CLOCK
GND
8
17
MR
1
Q1
CONFIGURATION
INTERFACE
LOGIC
TEST
M0:M8
Q0
Q1
ICS8402I
32 Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
N0:N1
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
GND
Q0
OE0
÷2
÷4
÷8
÷16
VDDO
0
VDD
VCO
÷M
24
2
9 10 11 12 13 14 15 16
PHASE DETECTOR
MR
1
M6
OE1
OSC
M5
TEST
TEST_CLK
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M3
M4
OE1
VCO_SEL
OE0
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ICS8402AYI REV. A OCTOBER 16, 2007
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 25MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
during power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fVCO = fXTAL x M
The ICS8402I features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
fundamental crystal is used as the input to the on-chip oscillator.
The output of the oscillator is fed into the phase detector. A 25MHz
crystal provides a 25MHz phase detector reference frequency. The
VCO of the PLL operates over a range of 250MHz to 700MHz. The
output of the M divider is also applied to the phase detector.
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 25MHz reference
are defined as 10 ≤ M ≤ 28. The frequency out is defined as follows:
fout = fVCO = fXTAL x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly
to the M divider and N output divider on each rising edge of
S_CLOCK. The serial mode can be used to program the M and N
bits and test bits T1 and T0. The internal registers T0 and T1
determine the state of the TEST output as follows:
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVCMOS output buffers. The divider provides a 50% output duty
cycle.
The programmable features of the ICS8402I support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial. Figure 1 shows the
timing diagram for each mode. In parallel mode, the nP_LOAD
input is initially LOW. The data on inputs M0 through M8 and N0
and N1 is passed directly to the M divider and N output divider. On
the LOW-to-HIGH transition of the nP_LOAD input, the data is
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. As a result,
the M and N bits can be hardwired to set the M divider and N output
divider to a specific default state that will automatically occur
T1
T0
TEST Output
0
0
LOW
0
1
Shift Register Output
1
0
Output of M Divider
1
1
CMOS fOUT
SERIAL LOADING
S_CLOCK
S_DATA
T1
t
S_LOAD
S
t
T0
*Null N1
N0
M8
M7
M6 M5
M4
M3
M2
M1
M0
H
t
nP_LOAD
S
PARALLEL LOADING
M0:M8, N0:N1
M, N
nP_LOAD
t
S
t
H
Time
*NOTE: The NULL timing slot must be observed.
Figure 1. Parallel & Serial Load Operations
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
M5
Input
2, 3, 4, 28,
29, 30, 31, 32
M6, M7, M8, M0,
M1, M2, M3, M4
Input
5, 6
N0, N1
Input
7
nc
Unused
8, 16
GND
Power
No connect.
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
Pulldown LVCMOS/LVTTL interface levels.
Pulldown Determines output divider value as defined in Table 3C, Function Table.
LVCMOS/LVTTL interface levels.
9
TEST
Output
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
10
VDD
Power
Core supply pin.
11, 12
OE1, OE0
Input
13
VDDO
Power
Output supply pin.
14, 15
Q1, Q0
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Pullup
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in Tri-State. See Table 3D,
OE Function Table. LVCMOS / LVTTL interface levels.
17
MR
Input
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When Logic LOW, the internal dividers and the
Pulldown
outputs are enabled. Assertion of MR does not affect loaded M, N, and T
values. LVCMOS/LVTTL interface levels.
18
S_CLOCK
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
19
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
20
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
21
VDDA
Power
22
XTAL_SEL
Input
23
TEST_CLK
Input
24,
25
XTAL_OUT
XTAL_IN
Input
26
nP_LOAD
Input
27
VCO_SEL
Input
Analog supply pin.
Pullup
Selects between crystal oscillator or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS/LVTTL interface levels.
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into M
Pulldown divider, and when data present at N1:N0 sets the N output divider value.
LVCMOS/LVTTL interface levels.
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS8402AYI REV. A OCTOBER 16, 2007
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
Input Pullup Resistor
Minimum
Maximum
Units
4
pF
VDD, VDDO = 3.465V
13
pF
VDD = 3.465V, VDDO = 2.625V
11
pF
51
kΩ
51
kΩ
RPULLDOWN Input Pulldown Resistor
ROUT
Typical
VDDO = 3.465V
Output Impedance
5
VDDO = 2.625V
7
12
7
Ω
Ω
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA
Conditions
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
L
↑
Data
Data
L
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
L
H
X
X
L
↑
Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
L
H
X
X
↑
L
Data
Contents of the shift register are passed to the
M divider and N output divider.
L
H
X
X
↓
L
Data
M divider and N output divider values are latched.
L
H
X
X
L
X
X
Parallel or serial input do not affect shift registers.
L
H
X
X
H
↑
Data
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS8402AYI REV. A OCTOBER 16, 2007
ICS8402I
350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 3B. Programmable VCO Frequency Function Table
256
128
64
32
16
8
4
2
1
M Divide
M8
M7
M6
M5
M4
M3
M2
M1
M0
250
10
0
0
0
0
0
1
0
1
0
275
11
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
26
0
0
0
0
1
1
0
1
0
675
27
0
0
0
0
1
1
0
1
1
700
28
0
0
0
0
1
1
1
0
0
VCO Frequency
(MHz)
NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 25MHz.
Table 3C. Programmable Output DividerFunction Table
Inputs
Output Frequency (MHz)
N1
N0
N Divider Value
Minimum
Maximum
0
0
2
125
350
0
1
4
62.5
175
1
0
8
31.25
87.5
1
1
16
15.625
43.75
Table 3D. OE Function Table
Inputs
Output
OE0
OE1
Q0
Q1
0
0
Hi-Z
Hi-Z
0
1
Hi-Z
Enabled
1
0
Enabled
Hi-Z
1
1
Enabled
Enabled
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (LVCMOS)
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
32 LQFP Package
32 VFQFN Package
47.9°C/W (0 lfpm)
37°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V±5%, VDDO = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
125
mA
IDDA
Analog Supply Current
18
mA
IDDO
Output Supply Current
10
mA
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS8402AYI REV. A OCTOBER 16, 2007
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350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 4B. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
IIH
IIL
Test Conditions
Input
Low Voltage
Input
High Current
Input
Low Current
Minimum
Typical
Maximum
Units
2
VDD + 0.3
V
OE0, OE1, MR,
M0:M8, N0, N1,
S_CLOCK, S_DATA,
S_LOAD, nP_LOAD,
VCO_SEL, XTAL_SEL
-0.3
0.8
V
TEST_CLOCK
-0.3
1.3
V
TEST_CLOCK, MR,
M0:M4, M6:M8, N0, N1,
S_CLOCK, S_DATA,
S_LOAD, nP_LOAD
VDD = VIN = 3.465V
150
µA
M5, XTAL_SEL,
VCO_SEL, OE0, OE1
VDD = VIN = 3.465V
5
µA
TEST_CLOCK, MR,
M0:M4, M6:M8, N0, N1,
S_CLOCK, S_DATA,
S_LOAD, nP_LOAD
VDD = 3.465V, VIN = 0V
-5
µA
M5, XTAL_SEL,
VCO_SEL, OE0, OE1
VDD = 3.465V, VIN = 0V
-150
µA
VDDO = 3.465V
2.6
V
VDDO = 2.625V
1.8
V
VOH
Output
High Voltage
TEST; NOTE 1
VOL
Output
Low Voltage
TEST; NOTE 1
VDDO = 3.465 or 2.625V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
Table 5. Input Frequency Characteristics, TA = -40°C to 85°C
Symbol Parameter
fIN
Input
Frequency
Test Conditions
Minimum
Typical
Maximum
Units
TEST_CLK; NOTE 1
12
40
MHz
XTAL_IN, XTAL_OUT; NOTE 1
12
40
MHz
50
MHz
S_CLOCK
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 250MHz to
700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 21 ≤ M ≤ 58. Using the maximum input frequency of
40MHz, valid values of M are 7 ≤ M ≤ 17.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 6. Crystal Characteristics
Parameter
Test Conditions
Minimum
Maximum
Units
40
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Mode of Oscillation
Typical
Fundamental
Frequency
12
AC Electrical Characteristics
Table 7A. AC Characteristics, VDD = VDDO = 3.3V±5%, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum
Typical
Units
350
MHz
fOUT
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 3
40
100
ps
tjit(per)
Period Jitter, RMS; NOTE 1
8
30
ps
tsk(o)
Output Skew; NOTE 2, 3
80
ps
tR / tF
Output Rise/Fall Time
1.1
ns
tS
Setup Time
15.625
Maximum
20% to 80%
0.25
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
tH
Hold Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
S_CLOCK to S_LOAD
5
ƒ ≤ 300MHz
40
ns
60
%
1
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Table 7B. AC Characteristics, VDD = 3.3V±5%,VDDO = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
fOUT
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 3
Minimum
Typical
15.625
40
Maximum
Units
350
MHz
100
ps
tjit(per)
Period Jitter, RMS; NOTE 1
30
ps
tsk(o)
Output Skew; NOTE 2, 3
60
ps
tR / tF
Output Rise/Fall Time
1.0
ns
tS
Setup Time
20% to 80%
0.25
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
S_CLOCK to S_LOAD
5
ns
M, N to nP_LOAD
5
ns
S_DATA to S_CLOCK
5
ns
tH
Hold Time
odc
Output Duty Cycle
tLOCK
PLL Lock Time
S_CLOCK to S_LOAD
5
ƒ ≤ 300MHz
40
ns
60
%
1
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS8402AYI REV. A OCTOBER 16, 2007
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350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Parameter Measurement Information
2.05V±5%
1.65V±5%
1.25V±5%
SCOPE
VDD,
VDDA,
VDDO
SCOPE
VCC,
VCCAVCCO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
VDDO
2
-1.65V±5%
-1.25V±5%
3.3/3.3V LVPECL Output Load AC Test Circuit
3.3V/2.5V LVPECL Output Load AC Test Circuit
VOH
VREF
Qx
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Qy
tsk(o)
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
Period Jitter
Output Skew
V
V
DDO
2
DDO
2
tcycle n
➤
Q0, Q1
➤
DDO
V
V
DDO
tcycle n+1
2
Q0, Q1
2
t PW
t
➤
➤
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
odc =
PERIOD
t PW
x 100%
t PERIOD
Cycle-to-Cycle Jitter
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Output Duty Cycle/Pulse Width/Period
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350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
80%
Clock
Outputs
80%
20%
20%
tR
tF
Output Rise/Fall Time
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS8402I provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD, VDDA and VDDO should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 2
illustrates how a 10Ω resistor along with a 10µF and a 0.01µF
bypass capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 2. Power Supply Filtering
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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Crystal Input Interface
The ICS8402I has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 3 below
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error. The optimum C1 and
C2 values can be slightly adjusted for different board layouts.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 3. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
VCC
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VCC
R1
Ro
Rs
0.1µf
50Ω
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface
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Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVCMOS Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
TEST_CLK Input
For applications not requiring the use of the test clock, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the TEST_CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 5. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal and
electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as many
vias connected to ground as possible. It is also recommended that
the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz
copper via barrel plating. This is desirable to avoid any solder
wicking inside the via during the soldering process which may
result in voids in solder between the exposed pad/slug and the
thermal land. Precautions should be taken to eliminate any solder
voids between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For
further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias. The
vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
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Reliability Information
Table 8A. θJA vs. Air Flow Table for a 32 Lead LQFP
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 8B. θJA vs. Air Flow Table for a 32 Lead VFQFN
θJA vs. Air Flow
Linear Feet per Minute
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
37°C/W
32.4°C/W
29.0°C/W
Transistor Count
The transistor count for ICS8402I is: 3784
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Package Outline and Package Dimension
Package Outline - Y Suffix for 32 Lead LQFP
Table 9A. Package Dimensions for 32 Lead LQFP
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
A1
0.05
0.10
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
0.20
D&E
9.00 Basic
D1 & E1
7.00 Basic
D2 & E2
5.60 Ref.
e
0.80 Basic
L
0.45
0.60
0.75
θ
0°
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
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Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
L
N
e (Ty p.)
2 If N & N
1
Anvil
Singula tion
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
N &N
Odd
0. 08
C
D2
2
Th er mal
Ba se
D2
C
NOTE:The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package
dimensions are in Table 8 below.
Table 9B. Package Dimensions for 32 Lead VFQFN
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
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Ordering Information
Table 10. Ordering Information
Part/Order Number
8402AYI
8402AYIT
8402AYILF
8402AYILFT
8402AKI
8402AKIT
8402AKILF
8402AKILFT
Marking
ICS8402AYI
ICS8402AYI
ICS8402AYILF
ICS8402AYILF
ICS8402AKI
ICS8402AKI
ICS8402AKIL
ICS8402AKI
Package
32 Lead LQFP
32 Lead LQFP
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
32 Lead VFQFN
32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
Shipping Packaging
Tray
1000 Tape & Reel
Tray
1000 Tape & Reel
Tray
2500 Tape & Reel
Tray
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev
Table
Page
T9B
T10
1
6
12
13
13
14
16
17
A
Description of Change
Date
Pin Assignment - added 32 Lead VFQFN information.
Absolute Maximum Ratings - added 32 Lead VFQFN package thermal impedance.
Added LVCMOS to XTAL Interface section.
Added Recommendations for Unused Input/Output Pins section.
Added VFQFN EPAD Thermal Release Path section.
Added 32 Lead VFQFN Reliability Information.
Added 32 Lead VFQFN Package Dimensions Table and Package Outline
Ordering Information Table - added 32 Lead VFQFN ordering information.
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