Integrated Circuit Systems, Inc. ICS8532-01 LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8532-01 is a low skew, 1-to-17, Differential-to-3.3V LVPECL Fanout Buffer and a HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8532-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • 17 differential 3.3V LVPECL outputs Guaranteed output and part-to-part skew characteristics make the ICS8532-01 ideal for those clock distribution applications demanding well defined performance and repeatability. • Output skew: 50ps (maximum) ,&6 • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 500MHz • Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input • Part-to-part skew: 250ps (maximum) • Propagation delay: 2.5ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VCCO nQ5 Q5 nQ4 Q4 Q3 nQ3 CLK_SEL nQ2 1 Q0 - Q16 nQ0 - nQ16 Q2 PCLK nPCLK 0 nQ1 CLK nCLK Q1 Q0 Q LE nQ0 D CLK_EN VCCO 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 nc 2 38 Q6 nc 3 37 nQ6 VCC 4 36 Q7 CLK 5 35 nQ7 nCLK 6 34 Q8 CLK_SEL 7 33 nQ8 PCLK 8 32 Q9 nPCLK 9 31 nQ9 VEE 10 30 Q10 CLK_EN 11 29 nQ10 nc 12 28 nc VCCO ICS8532-01 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 VCCO Vcco VCCO Q11 nQ11 Q12 nQ12 Q13 nQ13 Q14 nQ14 Q15 nQ15 Q16 nQ16 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View 8532AY-01 www.icst.com/products/hiperclocks.htlm 1 REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 13, 26, 27, 39, 40 4 Name 2, 3, 12, 28 Type Description Power Output supply pins. Connect to 3.3V. VCC Power Positive supply pin. Connect to 3.3V. nc Unused 5 CLK Input Pulldown 6 nCLK Input Pullup 7 CLK_SEL Input Pulldown 8 PCLK Input Pulldown Pullup Inver ting differential LVPECL clock input. Pullup VCCO No connect. Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When HIGH, selects PCLK, nPCLK inputs. When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Non-inver ting differential LVPECL clock input. 9 nPCLK Input 10 VEE Power 11 CLK_EN Input 14, 15 nQ16, Q16 Output Negative supply pin. Connect to ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Differential output pair. LVPECL interface level. 16, 17 nQ15, Q15 Output Differential output pair. LVPECL interface level. 18, 19 nQ14, Q14 Output Differential output pair. LVPECL interface level. 20, 21 nQ13, Q13 Output Differential output pair. LVPECL interface level. 22, 23 nQ12, Q12 Output Differential output pair. LVPECL interface level. 24, 25 nQ11, Q11 Output Differential output pair. LVPECL interface level. 29, 30 nQ10, Q10 Output Differential output pair. LVPECL interface level. 31, 32 nQ9, Q9 Output Differential output pair. LVPECL interface level. 33, 34 nQ8, Q8 Output Differential output pair. LVPECL interface level. 35, 36 nQ7, Q7 Output Differential output pair. LVPECL interface level. 37, 38 nQ6, Q6 Output Differential output pair. LVPECL interface level. 41, 42 nQ5, Q5 Output Differential output pair. LVPECL interface level. 43, 44 nQ4, Q4 Output Differential output pair. LVPECL interface level. 45, 46 nQ3 Q3 Output Differential output pair. LVPECL interface level. 47, 48 nQ2, Q2 Output Differential output pair. LVPECL interface level. 49, 50 nQ1, Q1 Output Differential output pair. LVPECL interface level. 51, 52 nQ0, Q0 Output Differential output pair. LVPECL interface level. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLUP CLK, nCLK PCLK, Input Capacitance nPCLK CLK_EN, CLK_SEL Input Pullup Resistor RPULLDOWN Input Pulldown Resistor CIN 8532AY-01 Test Conditions Minimum Typical 51 51 www.icst.com/products/hiperclocks.htlm 2 Maximum Units 4 pF 4 pF 4 pF KΩ KΩ REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK_EN CLK_SEL Selected Source Q0 thru Q16 0 0 CLK, nCLK Disabled; LOW nQ0 thru nQ16 Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0 - nQ16 Q0 - Q16 FIGURE 1: CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK or PCLK nCLK or nPCLK Q0 thru Q16 nQ0 thru nQ16 0 1 LOW HIGH 1 0 HIGH LOW Input to Output Mode Polarity Differential to Differential Non Inver ting Differential to Differential Non Inver ting Single Ended to 0 Biased; NOTE 1 LOW HIGH Non Inver ting Differential Single Ended to 1 Biased; NOTE 1 HIGH LOW Non Inver ting Differential Single Ended to Biased; NOTE 1 0 HIGH LOW Inver ting Differential Single Ended to Biased; NOTE 1 1 LOW HIGH Inver ting Differential NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring the differential input to accept single ended levels. 8532AY-01 www.icst.com/products/hiperclocks.htlm 3 REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCCx 4.6V Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG -0.5V to VCC + 0.5V -0.5V to VCCO + 0.5V 40°C/W -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC VCCO Positive Supply Voltage 3.135 3.3 3.465 V Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 122 150 mA Typical Maximum Units 2 3.765 V -0.3 0.8 V TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Current VIL Input Low Current IIH Input High Current IIL Input Low Current Test Conditions Minimum CLK_EN, CLK_SEL CLK_EN, CLK_SEL CLK_SEL VIN = VCC = 3.465V 150 µA CLK_EN VIN = VCC = 3.465V 5 µA CLK_SEL VIN = 0V, VCC = 3.465V -5 µA CLK_EN VIN = 0V, VCC = 3.465V -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Units CLK VIN = VCC = 3.465V 150 µA nCLK VIN = VCC = 3.465V 5 µA CLK VIN = 0V, VCC = 3.465V -5 nCLK VIN = 0V, VCC = 3.465V -150 Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V. VPP 8532AY-01 Maximum www.icst.com/products/hiperclocks.htlm 4 µA µA 1.3 V VCC - 0.85 V REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions Minimum Typical VCC = VIN = 3.465V PCLK Maximum Units 150 µA nPCLK VCC = VIN = 3.465V PCLK VCC = 3.465V, VIN = 0V -5 5 µA µA nPCLK VCC = 3.465V, VIN = 0V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 0.3 1 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 1.5 VCC V VOH Output High Voltage; NOTE 3 VCCO - 1.4 VCCO - 1.0 V VOL Output Low Voltage; NOTE 3 VCCO - 2.0 VCCO - 1.7 V 0.85 V Maximum Units 500 MHz Peak-to-Peak Voltage Swing 0.6 VSWING NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Maximum Output Frequency Test Conditions Minimum ƒ≤ 500MHz Typical tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 1.3 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 250 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps odc Output Duty Cycle 0 ≤ ƒ≤ 266MHz 48 50 266 ≤ ƒ≤ 500MHz 47 50 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8532AY-01 www.icst.com/products/hiperclocks.htlm 5 2.5 ns 50 ps 52 % 53 % REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VCCO VCC SCOPE Qx LVPECL VCC = 2.0V VCCO = 2.0V nQx VEE = -1.3V ± 0.135V FIGURE 2 - OUTPUT LOAD TEST CIRCUIT VCC CLK, PCLK V PP Cross Points V CMR nCLK, nPCLK VEE FIGURE 3 - DIFFERENTIAL INPUT LEVEL Qx nQx Qy nQy tsk(o) FIGURE 4 - OUTPUT SKEW 8532AY-01 www.icst.com/products/hiperclocks.htlm 6 REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Qx PART 1 nQx Qy PART 2 nQy tsk(pp) FIGURE 5 - PART-TO-PART SKEW 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R FIGURE 6 - INPUT AND OUTPUT RISE AND F FALL TIME CLK, PCLK nCLK, nPCLK Q0 - Q16 nQ0 - nQ16 t PD FIGURE 7 - PROPAGATION DELAY CLK, PCLK, Qx nCLK, nPCLK, nQx Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 8 - odc & tPERIOD 8532AY-01 www.icst.com/products/hiperclocks.htlm 7 REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 9 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 9: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8532AY-01 www.icst.com/products/hiperclocks.htlm 8 REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8531-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8531-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.8mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 17 * 30.2mW = 513.4mW Total Power_MAX (3.465V, with all outputs switching) = 519.8mW + 513.4mW = 1033.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 0°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.1033W * 0°C/W = 0°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance qJA for 52-pin LQFP Forced Convection qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 0°C/W 0°C/W 0°C/W 0°C/W 0°C/W 0°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8532AY-01 www.icst.com/products/hiperclocks.htlm 9 REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 10. VCCO Q1 VOUT RL 50 VCCO - 2V Figure 10 - LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) L Pd_L = [(V OL_MAX • – (V CC_MAX - 2V))/R ] * (V CC_MAX L For logic high, VOUT = V OH_MAX -V OL_MAX =V ) – 1.0V CC_MAX Using VCC_MAX = 3.465, this results in VOH_MAX = 2.465V • For logic low, VOUT = V OL_MAX Using V CC_MAX =V CC_MAX – 1.7V = 3.465, this results in V OL_MAX = 1.765V Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 8532AY-01 www.icst.com/products/hiperclocks.htlm 10 REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE q by Velocity (Linear Feet per Minute) JA 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0°C/W 0°C/W 200 0°C/W 0°C/W 500 0°C/W 0°C/W NOTE: Most all modern PCB designs use multi-layered boards, so the data in the second row will pertain to most designs. TRANSISTOR COUNT The transistor count for ICS8532-01 is: 1398 8532AY-01 www.icst.com/products/hiperclocks.htlm 11 REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BCC MINIMUM NOMINAL MAXIMUM 52 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.22 0.32 0.38 c 0.09 -- 0.20 D 12.00 BASIC D1 10.00 BASIC D2 7.80 Ref. E 12.00 BASIC E1 10.00 BASIC E2 7.80 Ref. 0.65 BASIC e L 0.45 -- 0.75 q 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8532AY-01 www.icst.com/products/hiperclocks.htlm 12 REV. B AUGUST 9, 2001 ICS8532-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-17 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8532AY-01 ICS8532AY-01 52 Lead LQFP 160 per tray 0°C to 70°C ICS8532AY-01T ICS8532AY-01 52 Lead LQFP on Tape and Reel 500 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8532AY-01 www.icst.com/products/hiperclocks.htlm 13 REV. B AUGUST 9, 2001