ICSI ICS9214_07

ICS9214
Integrated
Circuit
Systems, Inc.
Rambus
TM
TM
XDR
Clock Generator
General Description
Features
The ICS9214 clock generator provides
the necessary clock
TM
signals to support the Rambus XDR memory subsystem
and Redwood logic interface. The clock source is a reference
clock that may or may not be modulated for spread spectrum.
The ICS9214 provides 4 differential clock pairs in a space
saving 28-pin TSSOP package and provides an off-the-shelf
high-performance interface solution.
•
•
Figure 1 shows the major components of the ICS9214 XDR
Clock Generator. These include the a PLL, a Bypass
Multiplexer and four differential output buffers. The outputs
can be disabled by a logic low on the OE pin. An output is
enabled by the combination of the OE pin being high, and 1
in its SMBus Output control register bit.
•
The PLL receives a reference clock, CLK_INT/C and outputs
a clock signal at a frequency equal to the input frequency
times a multiplier. Table 2 shows the multipliers selectable
via the SMBus interface. This clock signal is then fed to the
differential output buffers to drive the enabled clocks. Disabled
outputs are set to Hi-Z. The Bypass mode routes the input
clock, CLK_INT/C, directly to the differential output buffers,
bypassing the PLL.
•
•
•
•
•
400 – 500 MHz clock source
4 open-drain differential output drives with short term
jitter < 40ps
Spread spectrum compatible
Reference clock is differential or single-ended, 100 or
133 MHz
SMBus programmability for:
- frequency multiplier
- output enable
- operating mode
Supports frequency multipliers of: 3, 4, 5, 6, 8, 9/2,
15/2 and 15/4
Support systems where XDR subsystem is
asynchronous to other system clocks
2.5V power supply
Up to four ICS9214 devices can be cascaded on the same
SMBus. Table 3 shows the SMBus addressing and control for
the four devices.
Block Diagram
OE
RegA
BYPASS#/PLL
CLK_INT
CLK_INC
SMBCLK
Bypass
MUX
ODCLK_T0
ODCLK_C0
OE
RegB
ODCLK_T1
ODCLK_C1
PLL
OE
RegC
ODCLK_T2
ODCLK_C2
OE
RegD
ODCLK_T3
AVDD2.5
AGND
IREFY
AGND
CLK_INT
CLK_INC
VDD2.5
GND
SMBCLK
SMBDAT
OE
SMB_A0
SMB_A1
BYPASS#/PLL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ICS9214
Pin Configuration
OE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ODCLK_C3
28-Pin 4.4mm TSSOP
SMBDAT SMB_A0 SMB_A1
0809F–11/05/07
VDD2.5
ODCLK_T0
ODCLK_C0
GND
ODCLK_T1
ODCLK_C1
VDD2.5
GND
ODCLK_T2
ODCLK_C2
GND
ODCLK_T3
ODCLK_C3
VDD2.5
ICS9214
Integrated
Circuit
Systems, Inc.
Pin Descriptions
PIN #
1
2
PIN NAME
AVDD2.5
AGND
PIN TYPE
PWR
PWR
3
IREFY
IN
4
5
6
7
8
9
10
AGND
CLK_INT
CLK_INC
VDD2.5
GND
SMBCLK
SMBDAT
PWR
IN
IN
PWR
PWR
IN
I/O
11
OE
IN
12
13
SMB_A0
SMB_A1
IN
IN
14
BYPASS#/PLL
IN
15
VDD2.5
PWR
16
ODCLK_C3
OUT
17
ODCLK_T3
OUT
18
GND
PWR
19
ODCLK_C2
OUT
20
ODCLK_T2
OUT
21
22
GND
VDD2.5
PWR
PWR
23
ODCLK_C1
OUT
24
ODCLK_T1
OUT
25
GND
PWR
26
ODCLK_C0
OUT
27
ODCLK_T0
OUT
28
VDD2.5
PWR
DESCRIPTION
2.5V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
This pin establishes the reference current for the differential clock
pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current.
Analog Ground pin for Core PLL
"True" reference clock input.
"Complementary" reference clock input.
Power supply, nominal 2.5V
Ground pin.
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
SMBus address bit 0 (LSB)
SMBus address bit 1
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Power supply, nominal 2.5V
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
Ground pin.
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
Ground pin.
Power supply, nominal 2.5V
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
Ground pin.
"Complementary" side of open drain differential clock output. This
open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open drain
output needs an external resistor network..
Power supply, nominal 2.5V
0809F—11/05/07
2
ICS9214
Integrated
Circuit
Systems, Inc.
General SMBus serial interface information for the ICS9214
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D8 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controlle r (Host)
starT bit
T
Slave Address D8(H )
WR
W Rite
Controller (host) will send start bit.
Controller (host) sends the write address D8 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D9 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controlle r (Host)
T
starT bit
Slave Address D8(H )
WR
W Rite
ICS (Sla ve/Re ce ive r)
ICS (Sla ve/Re ce ive r)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D9(H )
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
0809F—11/05/07
3
Not acknowledge
stoP bit
ICS9214
Integrated
Circuit
Systems, Inc.
SMB Table: Output Control Register
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
27,26
24,23
20,19
17,16
Name
Test Mode
MULT2
MULT1
MULT0
ODCLK_T/C0
ODCLK_T/C1
ODCLK_T/C2
ODCLK_T/C3
Control
Function
Reserved for Vendor
Multiplier Select
Multiplier Select
Multiplier Select
Output Control
Output Control
Output Control
Output Control
Type
0
1
PWD1
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Enable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
0
0
0
1
1
1
1
1
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
0
0
0
See Table 2.
Disable = Output in high-impedance state
Enable = Output is switching
SMB Table: Frequency Multiplier Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 0
-
Test Mode
Reserved for Vendor
RW
Disable
Enable
0
Control
Function
Type
0
1
PWD
R
R
R
R
R
R
-
-
X
X
X
X
X
0
R
-
-
0
R
-
-
1
Byte 1
Pin #
Name
SMB Table: Revision & Vendor ID Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Pin #
-
Bit 1
Bit 0
Name
RID4
RID3
RID2
RID1
RID0
VID2
VID1
Revision ID
Vendor ID
VID0
NOTES:
1. PWD = Power Up Default
0809F—11/05/07
4
ICS9214
Integrated
Circuit
Systems, Inc.
PLL Multiplier
Table 2 shows the frequency multipliers in the PLL, selectable by programming the MULT0, MULT1 and MULT2 bits in the
SMBus Multiplier Control register. Power up default is 4.
Table 2. PLL Multiplier Selection
Byte 0
Output Frequency (MHz)
Frequency
Multiplier
CLK_INT/C =
100 MHz 1
CLK_INT/C =
133 MHz 1
3
4
3003
4002
400
533
0
5
500
667
1
6
600
800
0
0
8
800
-3
Bit 6
Bit 5
Bit 4
MULT2
0
0
MULT1
0
0
MULT0
0
1
0
1
0
1
1
1
0
1
9/2
450
600
1
1
0
15/2
750
-3
1
1
1
15/4
375
500
NOTES
1 Output frequencies are based on nominal input frequencies of 100 MHz and 133 MHz. The PLL
multipliers are also applicable to spread spectrum modulated input clocks.
2 Default muliplier value at power up
3 Outputs at these settings do not conform to the AC Output Characteristics, or are not supported.
4 Shaded areas are under development and are not yet supported
Device ID and SMBus Device Address
The device ID (SMB_A(1:0)) is part of the SMBus device address. The least significant bit of the address designates a write
or read operation. Table 3 shows the addresses for four ICS9214 devices on the same SMBus.
Table 3. SMBus Device Addresses
ICS9214
Device Operation
Write
0
Read
1
2
3
Hex Address
D8
D9
Write
DA
Read
DB
Write
DC
Read
DD
Write
DE
Read
DF
8-bit SMBus Device Address, Including Oper.
SMB_A1
SMB_A0
WR#/RD
0
0
0
1
0
1
1
0
1
1
11011
0809F—11/05/07
5
0
1
0
1
0
1
ICS9214
Integrated
Circuit
Systems, Inc.
Operating Modes
Table 4: Operating Modes
Bit 1
Bit 0
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Bit 2
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Byte 0
Byte 1
Bit 3
BYPASS#/
PLL
Bit 7
OE
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
02
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
12
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
12
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
12
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
12
ODCLK_T/C3 ODCLK_T/C2 ODCLK_T/C1 ODCLK_T/C0
Z
Z
Z
Z
Z
Z
Z
Z
Z
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
Z
Z
Reserved for Vendor Test
CLK_INT/C1
Z
Z
Z
Z
Z
CLK_INT/C
Z
CLK_INT/C
Z
CLK_INT/C
Z
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
Z
Z
Z
Z
Z
CLK_INT/C
Z
CLK_INT/C
Z
CLK_INT/C
Z
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
Notes
1 Bypass Mode
2 Power up default mode
0809F—11/05/07
6
Z
Z
CLK_INT/C
Z
CLK_INT/C
Z
CLK_INT/C
Z
CLK_INT/C
Z
CLK_INT/C
Z
CLK_INT/C
Z
CLK_INT/C
Z
CLK_INT/C
ICS9214
Integrated
Circuit
Systems, Inc.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . .
4.0 V
GND –0.5 V to VDD +0.5 V
0°C to +85°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
DC Characteristics - Inputs
TA = 0°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDD2.5, AVDD
2.375
2.625
V
125
mA
Supply Current
I DD2.5, I VDD
High-level input
VIHCLK
0.6
0.95
V
voltage
Low-level input
VILCLK
-0.15
0.15
V
voltage
CLK_INT, CLK_INC
Crossing point
VIXCLK
0.2
0.55
V
voltage
Difference in
crossing point
0.15
V
VIXCLK
voltage
Input threshold
0.35
0.5VDD2.5
V
VTH
voltage
High-level input
Singled-ended
VIHSE
voltage for singleVTH + 0.3
2.625
V
ended CLK_IN
CLK_IN1
Low-level input
voltage for singleVILSE
-0.15
VTH - 0.3
V
ended CLK_IN
High-level input
VIH
OE, SMB_A0,
1.4
2.625
V
voltage
SMB_A1,
Low-level input
VIL
BYPASS#/PLL
-0.15
0.8
V
voltage
High-level input
VIHSMB
1.4
3.4652
V
SMBCLK,
voltage - SMBus
SMBDAT
Low-level input
-0.15
0.8
V
VILSMB
voltage - SMBus
Notes:
1 When using singled-ended clock input, VTH is supplied to CLK_INTC as shown in Figure 2.
Duty cycle of singled-ended CLK_IN is measured at VTH
2 This range of SMBus input high voltages allows the 9214 to co-exist with 3.3V, 2.5V and 1.8V
devices on the same SMBus.
0809F—11/05/07
7
ICS9214
Integrated
Circuit
Systems, Inc.
DC Characteristics - Outputs
TA = 0°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
SYMBOL
MIN
TYP
MAX
PARAMETER
CONDITIONS
Power within spec to
tPU
3
Power up latency
outputs within spec
SMBus or Mode Select
1
tCO
3
transition to outputs valid
State transition latency
and within spec
Measured as shown in Fig.
Differential output
VOX
0.9
1.1
3
crossing voltage
Output Voltage Swing
Measured as shown in Fig.
VCOS
300
350
(peak-to-peak singled
3. Excludes over and
ended)
undershoot.
Measured at ODCLK_T/C
0.85
Absolute output low voltage VOLABS
pins
Reference Voltage for
VDD = 2.3V, VOUT = 1V
VISET
0.98
1.02
swing control current
Ratio of output low
IREF is equal to VISET/RRC.
current to reference
IOL/IREF
6.8
7
7.2
Tolerance of RRC <=+/-1%.
current at typical VDD2.5
Measured at ODCLK_T/C
Minimum current at
IOLABS
45
pins with termination per
VOLABS
Figure 3.
Low-level output voltage
VOLSMB
IOL = 4 mA
0.4
SMBus
Low-level output current
VOL= 0.8 V
IOLSMB
6
SMBus
Tristate output current
IOZ
Differential clock output pins
-
Notes:
There is no output latency or glitches if a value is written to an output register.
that is the same as its current contents.
0809F—11/05/07
8
50
UNITS
ms
ms
V
mV
V
V
-
mA
V
mA
µΑ
ICS9214
Integrated
Circuit
Systems, Inc.
AC Characteristics-Inputs
TA = 0°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
CLK_INT/CLK_INC cycle
time1
Cycle-to-Cycle Jitter
Input clock duty cycle
CLK_INT/CLK_INC rise and
fall time
Difference between input rise
and fall time on same pin of a
single device
Spread spectrum modulation
frequency
SYMBOL
Spread spectrum modulation
index
mINDEX3
Input clock slew rate
Input Capacitance5
Input Capacitance5
CLK_INT cycle time
SMBus clock frequency
CONDITION
t CYCLEIN
t cyc -t cyc 2
dtin
t R, t F
t R-F
over 10,000 cycles
20% to 80% of input
voltage
20% to 80% of input
voltage
fINM3
MIN
TYP
MAX
UNITS
7
11
ns
40
185
60
ps
%
175
700
ps
-
150
ps
30
33
kHz
0.6
%
0.54
%
1
4
V/ns
4
10
7
10
40
100
pF
pF
ns
kHz
Triangular modulation
t sl(I)
CINCLK
CIN
t CYCLETST
f SMB
Non-triangular modulation
20% to 80% of input
voltage
CLK_INT, CLK_INC
VI = V DD2.5 or GND
Bypass Mode
Notes:
1. Measured at (VIH(nom) - VIL(nom))/2 and is the absolute value of the worst case deviation.
2. Measured at crossing points for differential clock input or at VTH for single-ended clock input
3. If input modulation is used. Input modulation is not necessary.
4. The amount of allowed spreading for non-triangular modulation is determined
by the induced downstream tracking skew.
5. Capacitance measured at f = 1 MHz, DC bias = 0.9V, VAC <100mV.
0809F—11/05/07
9
ICS9214
Integrated
Circuit
Systems, Inc.
AC Characteristics-Outputs
TA = 0°C to +85°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER1
Output clock cycle time
Short term jitter (over 1 to
6 clock cycles)
Output Phase error when
tracking SSC
SYMBOL
tCYCLE
CONDITION
tJ2
f = 400 to 635 MHz
f = 635 to 800 MHz
Change in skew
Long term average output
duty cycle
Cycle-to-cycle duty cycle
error
Output rise and fall times
MIN
1.5
-
tERR,SSC
tSKEW
TA = 0°C to +85°C,
AVDD2.5, VDD2.5 =
2.5 V +/- 0.125V
3
DC
f = 400 to 635 MHz
f = 635 to 800 MHz
20% to 80% of output
voltage
tDCERR
tR, tF
TYP
MAX
2.5
40
30
UNITS
ns
ps
ps
-100
100
ps
-
15
ps
45
55
%
-
40
30
ps
ps
100
300
ps
100
ps
-
Ω
Difference between
output rise and fall time
20% to 80% of output
tR-F
on same pin of a single
voltage, f = 400 to 800 MHz
device
Dynamic output
VOL = 0.9 V
1000
ZOUT4
impedance
Notes:
1. Max and min output clock cycle times are based on nominal output frequencies
of 400 and 667 MHz respectively. For spread spectrum modulated input clocks,
the output clocks track the input modulation.
2. Output short-term jitter is the absolute value fo the worst case deviation and is
defined in the Jitter section.
3. tSKEW is the timing difference between any two of the four differential clocks and
is measured at common mode voltage.
4. Zout is defined at the output pins.
5. Guaranteed by design and characterization, not 100% tested in production
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Thermal Resistance Junction to Top of
Case
Maximum Case Temp
Symbol
Conditions
θJA
θJA
θJA
θJC
Still air
1 m/s air flow
3 m/s air flow
ΨJT
Still Air
Min.
Typ.
Max.
120
95
80
20
°C/W
°C/W
°C/W
°C/W
°C/W
4.5
120
0809F—11/05/07
10
Units
°C
ICS9214
Integrated
Circuit
Systems, Inc.
Clock Output Drivers
Figure 2 shows the clock driver equivalent circuit. The differential driver produces a specified voltage swing on the channel
by switching the currents going into ODCLK_T and ODCLK_C. The external resistor RRC at the IREFY pin sets the maximum
current. The minimum current is zero.
The voltage at the IREFY pin, VIREFY, is by design equal to 1 V nominally, and the driver current is seven times the current
flowing through RRC. So, the output low current can be estimated as IOL = 7/ RRC.
The driver output characteristics are defined together with the external resistors, R1, R2, and R3. The output clock signals are
specified at the measurement points indicated in Figure 2. Table 5 shows example values for the resistors.
R1, R2, and R3 and the clock driver output impedance, ZOUT, must match the impedance of the channel, ZCH , to minimize
secondary reflections. ZOUT is specified as 1000 Ohms, minimum to accomplish this. The effective impedance can be
estimated by:
(1000R1/(1000+R1)+R2) R3/(1000R1/(1000+R1)+R2+R3)
Pull-up resistor RT terminates the transmission line at the load to minimize clock signal reflection signal reflections. Table 5
shows the resistor values for establishing and effective source termination impedance of 49.2 Ohms to match a 50 Ohm
channel. The termination voltages are 2.5 V for VTS and 1.2 V for VT. The resistor values R1 = 38.3 Ohms, R2 = 19.1 Ohms, R3
= 54.9 Ohms and RRC = 200 Ohms can be used to match a 28 Ohm channel.
Table 5. Example Resistor Values and Termination Voltages for a 50 Ohm Channel1
Symbol
Parameter
Value
Tolerance
Unit
R1
Termination resistor
39.2
+/- 1%
Ω
R2
Termination resistor
66.5
+/- 1%
Ω
R3
Termination resistor
93.1
+/- 1%
Ω
RT
Termination resistor
49.9
+/- 1%
Ω
RRC
Swing control resistor
200
+/- 1%
Ω
VTS
VT
Source termination voltage
2.5
+/-5%
V
Termination voltage
1.2
+/-5%
V
Notes:
1 A different set of resistors is used in Figure 2 when testing
for maximum output current of the clock driver (IOLABS).
These resistors are: R1 = 34Ω, R2 = 31.8Ω, R3 = 48.7Ω,
RT=28Ω, RRC = 147Ω
Supply Voltage
CLK_INC
VTH
Input
Input
CLK_INT
CLK_INT
XDR
XDR
Clock Generator
Clock Generator
b. Single-ended input
a. Differential input
Figure 1. Differential and single-ended reference clock inputs
0809F—11/05/07
11
ICS9214
Integrated
Circuit
Systems, Inc.
Input Clock Signal
The ICS9214 receives either a differential or single-ended reference clock (CLK_INT/C). When the reference input clock is
from a differential clock source, it must meet the voltage levels and timing requirements listed in the DC Characteristics –
Inputs and AC Characteristics – Inputs tables.
For a singled-ended clock input, an external voltage divider and a supply voltage, as shown in Figure 2, provide a reference
voltage VTH at the CLK_INC pin to determine the proper switching point for CLK_INT. The range of VTH is specified in the DC
Characteristics – Inputs table.
VTS
R1
ODCLK_T
Measurement
Point
VT
ZCH
R2
RT
R3
Swing Current
Control
Differential Driver
VTS
ISET
Measurement
Point
R1
ODCLK_C
ZCH
R2
RRC
VT
RT
R3
Figure 2. Example System Clock Driver Equivalent Circuit
VH
80%
V(t)
20%
VL
tF
tR
Figure 3. Input and Output Voltage Waveforms
ODCLK_T
Vx+
Vx,nom
Vx-
ODCLK_C
Figure 4. Crossing-point Voltage
0809F—11/05/07
12
ICS9214
Integrated
Circuit
Systems, Inc.
Power Sequencing
Supply voltages for the ICS9214 must be applied before, or at the same time and external input and output signals.
tCYCLE,i
tJ = tCYCLE,
Figure 5. Cycle-to-cycle Jitter
t4CYCLE, i
tJ = t4CYCLE, i - t4CYCLE
Figure 6. Short-term Jitter
Cycle (i)
ODCLK_T
ODCLK_C
tPW- (i)
Cycle (i+1)
tPW+ (i)
tPW- (i+1)
tCYCLE (i)
tCYCLE (i+1)
tDC,ERR = tPW+(i) - tPW+ (i+1) and tPW-(i) - tPW-(i+1)
Figure 7. Cycle-to-cycle Duty Cycle Error
fNOM
(1-PM,IN)*fNOM
0.5/fM,IN
1/f M,IN
t
Figure 8. Input frequency Modulation
0809F—11/05/07
13
tPW+ (i+1)
ICS9214
Integrated
Circuit
Systems, Inc.
Phase Noise
The 9214 meets the single side band phase noise spectral purity for offset frequencies between 1 MHz and 100 MHz as
described by the equation:
10log[1+(50 x 106/f)2.4] -138 dBc/Hz
This equation is shown in Figure 9. Phase Noise Plot
-100
SSB Spectral Purity L(f)
-110
-120
-130
-140
-150
10 6
1 07
10 8
Offs et Freq u e ncy f , H z
10 9
Figure 9 : Phase Noise Plot
Sample points are for this equation are shown in Table 6. Phase Noise Data Points
Offset
Frequency
(MHz)
1
5
10
15
20
40
80
100
SSB Spectral
Purity
(dbc/Hz)
-97
-114
-121
-125.2
- 128
-133.7
-136.8
-137.3
Table 6 : Phase Noise Data Points
0809F—11/05/07
14
ICS9214
Integrated
Circuit
Systems, Inc.
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
(25.6 mil)
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
SEE VARIATIONS
6.40 BASIC
4.30
4.50
0.65 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
-0.10
In Inches
COMMON DIMENSIONS
MIN
MAX
-.047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE VARIATIONS
0.252 BASIC
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
0°
8°
-.004
VARIATIONS
N
28
D mm.
MIN
9.60
D (inch)
MAX
9.80
MIN
.378
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS9214yG LF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0809F—11/05/07
15
MAX
.386
ICS9214
Integrated
Circuit
Systems, Inc.
Revision History
Rev.
0.1
A
B
C
D
E
F
Issue Date Description
Updated SMBus table Byte 2, Bit 3 from:0 to:1.
Updated PLL Multiplier Selection Table, from: Byte 1 to: Byte 0, and Bit 2,1,0,
03/30/05
to: Bit 6,5,4.
Updated Ordering Information from "Lead Free" to "Annealed Lead Free"
Added Phase noise spec
Removed unsupported speeds from PLL Multiplier Selection,
Changed minimum output raise, fall times from 140ps to 100 ps
04/06/05 Compliant with Rev 0.81 of XCG spec.
1. Changed write address from D2 to a valid address (D8)
04/22/05 2. Changed read address from D3 to a valid address (D9)
11/11/05
04/07/06
11/17/06
11/05/07
Added the 15/4 entry in the gear table to the list of supported frequencies
Added Thermal Characteristics Table.
Updated Pin Description.
Updated to extended temperature range
0809F—11/05/07
16
Page #
4-5,15
Various
3
5
10
2
-