PD -96257
IRF8910GPbF
HEXFET® Power MOSFET
Applications
l Dual SO-8 MOSFET for POL
converters in desktop, servers,
graphics cards, game consoles
and set-top box
l
l
VDSS
20V
Lead-Free
Halogen-Free
13.4m:@VGS = 10V
1
8
D1
G1
2
7
D1
S2
3
6
D2
4
5
D2
S1
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
l 20V VGS Max. Gate Rating
RDS(on) max
G2
ID
10A
SO-8
Top View
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
20
V
VGS
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
± 20
8.3
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
PD @TA = 25°C
Power Dissipation
2.0
PD @TA = 70°C
Power Dissipation
1.3
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
ID @ TA = 25°C
ID @ TA = 70°C
10
c
A
82
W
W/°C
°C
0.016
-55 to + 150
Thermal Resistance
Parameter
RθJL
RθJA
Junction-to-Drain Lead
Junction-to-Ambient f
g
Typ.
Max.
Units
–––
42
°C/W
–––
62.5
Notes through
are on page 10
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1
7/10/09
IRF8910GPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS
∆ΒVDSS/∆TJ
RDS(on)
Min. Typ. Max. Units
20
–––
–––
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
–––
–––
0.015
10.7
–––
13.4
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 10A
VGS(th)
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage
–––
1.65
14.6
–––
18.3
2.55
VGS = 4.5V, ID = 8.0A
VDS = VGS, ID = 250µA
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
-4.8
–––
–––
1.0
IGSS
Gate-to-Source Forward Leakage
–––
–––
–––
–––
150
100
nA
Gate-to-Source Reverse Leakage
Forward Transconductance
–––
24
–––
–––
-100
–––
S
Total Gate Charge
Pre-Vth Gate-to-Source Charge
–––
–––
7.4
2.4
11
–––
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
–––
–––
0.80
2.5
–––
–––
Qgodr
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
–––
1.7
3.3
–––
–––
Qoss
td(on)
Output Charge
Turn-On Delay Time
–––
–––
4.4
6.2
–––
–––
nC
VDS = 10V, VGS = 0V
VDD = 10V, VGS = 4.5V
tr
td(off)
Rise Time
Turn-Off Delay Time
–––
–––
10
9.7
–––
–––
ns
ID = 8.2A
Clamped Inductive Load
tf
Ciss
Fall Time
Input Capacitance
–––
–––
4.1
960
–––
–––
Coss
Crss
Output Capacitance
Reverse Transfer Capacitance
–––
–––
300
160
–––
–––
gfs
Qg
Qgs1
Qgs2
Qgd
V
Conditions
Drain-to-Source Breakdown Voltage
V
VGS = 0V, ID = 250µA
e
e
mV/°C
µA VDS = 16V, VGS = 0V
VDS = 16V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
VDS = 10V, ID = 8.2A
VDS = 10V
nC
VGS = 4.5V
ID = 8.2A
See Fig. 6
VGS = 0V
pF
VDS = 10V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
IAR
Parameter
Single Pulse Avalanche Energy
Avalanche Current
c
Typ.
–––
–––
d
Max.
19
8.2
Units
mJ
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
2.5
ISM
(Body Diode)
Pulsed Source Current
–––
–––
82
VSD
trr
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
–––
–––
–––
17
1.0
26
V
ns
Qrr
Reverse Recovery Charge
–––
6.5
9.7
nC
2
c
Conditions
MOSFET symbol
A
showing the
integral reverse
D
G
S
p-n junction diode.
TJ = 25°C, IS = 8.2A, VGS = 0V
TJ = 25°C, IF = 8.2A, VDD = 10V
di/dt = 100A/µs
e
e
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IRF8910GPbF
100
100
10
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
8.0V
5.5V
4.5V
3.5V
3.0V
2.8V
2.5V
1
2.5V
0.1
BOTTOM
10
2.5V
≤60µs PULSE WIDTH
Tj = 25°C
0.01
0.1
1
Tj = 150°C
0.1
100
1
10
100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
100
1.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (Α)
≤60µs PULSE WIDTH
1
10
VGS
10V
8.0V
5.5V
4.5V
3.5V
3.0V
2.8V
2.5V
10
T J = 150°C
T J = 25°C
1
VDS = 10V
≤60µs PULSE WIDTH
0.1
1
2
3
4
5
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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ID = 10A
VGS = 10V
1.0
0.5
6
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRF8910GPbF
10000
6.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
ID= 8.2A
Ciss
1000
Coss
Crss
VDS= 16V
VDS= 10V
5.0
VGS, Gate-to-Source Voltage (V)
C, Capacitance(pF)
C oss = C ds + C gd
4.0
3.0
2.0
1.0
100
0.0
1
10
100
0
VDS, Drain-to-Source Voltage (V)
3
4
5
6
7
8
9
10
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100.00
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
2
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
T J = 150°C
10.00
T J = 25°C
0.10
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
1.00
10
100µsec
1msec
1
10msec
T A = 25°C
Tj = 150°C
Single Pulse
VGS = 0V
0.01
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1
1.6
0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF8910GPbF
10
2.5
VGS(th) Gate threshold Voltage (V)
9
ID, Drain Current (A)
8
7
6
5
4
3
2
1
2.0
ID = 250µA
1.5
1.0
0
25
50
75
100
125
-75
150
-50
-25
0
25
50
75
100
125
150
T J , Temperature ( °C )
T A , Ambient Temperature (°C)
Fig 9. Maximum Drain Current vs.
Ambient Temperature
Fig 10. Threshold Voltage vs. Temperature
100
Thermal Response ( Z thJA )
D = 0.50
0.20
10
0.10
0.05
0.02
1
τJ
0.01
0.1
SINGLE PULSE
( THERMAL RESPONSE )
R1
R1
τJ
τ1
R2
R2
τ2
τ1
τ2
R3
R3
τ3
τ3
R4
R4
τ4
τ4
Ci= τi/Ri
Ci= τi/Ri
R5
R5
τ5
Ri (°C/W)
τi (sec)
1.2647
0.000091
2.0415
0.000776
18.970
0.188739
23.415
0.757700
τC
τC
τ5
16.803
25.10000
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
0.01
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF8910GPbF
80
EAS , Single Pulse Avalanche Energy (mJ)
RDS(on) , Drain-to -Source On Resistance (mΩ)
40.00
ID = 10A
30.00
20.00
T J = 125°C
10.00
T J = 25°C
0.00
ID
TOP
3.4A
4.9A
BOTTOM 8.2A
70
60
50
40
30
20
10
0
3
4
5
6
7
8
9
10
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
VGS, Gate -to -Source Voltage (V)
Fig 13. Maximum Avalanche Energy
vs. Drain Current
Fig 12. On-Resistance vs. Gate Voltage
Current Regulator
Same Type as D.U.T.
V(BR)DSS
tp
15V
50KΩ
12V
.3µF
DRIVER
L
VDS
.2µF
D.U.T.
D.U.T
RG
+
- VDD
IAS
20V
VGS
tp
A
0.01Ω
+
V
- DS
VGS
I AS
3mA
IG
Fig 14. Unclamped Inductive Test Circuit
and Waveform
ID
Current Sampling Resistors
Fig 15. Gate Charge Test Circuit
LD
VDS
VDS
+
90%
V DD D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 16. Switching Time Test Circuit
6
10%
VGS
td(on)
tr
td(off)
tf
Fig 17. Switching Time Waveforms
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IRF8910GPbF
D.U.T
Driver Gate Drive
+
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRF8910GPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgs 2
Qgd
⎞ ⎛
⎞
+⎜I ×
× Vin × f ⎟ + ⎜ I ×
× Vin × f ⎟
ig
ig
⎝
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
8
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
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IRF8910GPbF
SO-8 Package Outline(Mosfet & Fetky)
Dimensions are shown in milimeters (inches)
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SO-8 Part Marking Information
(;$03/(7+,6,6$1,5)*3%)
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRF8910GPbF
SO-8 Tape and Reel
Dimensions are shown in milimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 0.57mH, RG = 25Ω, IAS = 8.2A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board.
Rθ is measured at T J of approximately 90°C.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.07/2009
10
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