IRF IRF7475PBF

PD - 95278
IRF7475PbF
HEXFET® Power MOSFET
Applications
l High Frequency Point-of-Load
Synchronous Buck Converter for
Applications in Networking &
Computing Systems.
l Lead-Free
VDSS
RDS(on) max
15m:@VGS = 4.5V
12V
1
8
S
2
7
S
3
6
4
5
S
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
G
Qg
19nC
A
A
D
D
D
D
SO-8
Top View
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
12
V
VGS
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
± 12
7.0
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
PD @TA = 25°C
Power Dissipation
2.5
ID @ TA = 25°C
ID @ TA = 100°C
11
c
PD @TA = 70°C
g
Power Dissipation g
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
A
88
W
1.6
W/°C
°C
0.02
-55 to + 150
Thermal Resistance
Parameter
RθJL
RθJA
Junction-to-Drain Lead
Junction-to-Ambient
f
Typ.
Max.
Units
–––
20
°C/W
–––
50
Notes  through ƒ are on page 10
www.irf.com
1
09/21/04
IRF7475PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
Drain-to-Source Breakdown Voltage
12
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.014
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
11.5
15
mΩ
–––
20
50
V
VGS = 0V, ID = 250µA
VGS = 4.5V, ID = 8.8A
VGS = 2.8V, ID = 5.5A
VGS(th)
Gate Threshold Voltage
0.6
–––
2.0
V
∆VGS(th)
Gate Threshold Voltage Coefficient
–––
3.2
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
µA
VDS = 9.6V, VGS = 0V
nA
VGS = 12V
IGSS
gfs
Qg
–––
–––
100
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
200
Gate-to-Source Reverse Leakage
–––
–––
-200
Forward Transconductance
22
–––
–––
f
f
VDS = VGS, ID = 250µA
VDS = 9.6V, VGS = 0V, TJ = 125°C
VGS = -12V
S
VDS = 6.0V, ID = 8.8A
nC
VGS = 4.5V
Total Gate Charge
–––
13
19
Qgs1
Pre-Vth Gate-to-Source Charge
–––
2.6
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
1.5
–––
Qgd
Gate-to-Drain Charge
–––
3.9
–––
ID = 7.0A
Qgodr
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
5.0
–––
See Fig. 16
Qsw
–––
5.4
–––
Qoss
Output Charge
–––
17
–––
td(on)
Turn-On Delay Time
–––
7.5
–––
VDD = 6.0V, VGS = 4.5V
tr
Rise Time
–––
33
–––
ID = 8.8A
td(off)
Turn-Off Delay Time
–––
13
–––
tf
Fall Time
–––
7.5
–––
Ciss
Input Capacitance
–––
1590
–––
Coss
Output Capacitance
–––
1310
–––
Crss
Reverse Transfer Capacitance
–––
260
–––
VDS = 6.0V
nC
ns
VDS = 10V, VGS = 0V
f
Clamped Inductive Load
VGS = 0V
pF
VDS = 6.0V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
dh
c
Typ.
Max.
Units
–––
180
mJ
–––
8.8
A
–––
0.25
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
11
ISM
(Body Diode)
Pulsed Source Current
–––
–––
88
showing the
integral reverse
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.3
V
S
p-n junction diode.
TJ = 25°C, IS = 8.8A, VGS = 0V
trr
Reverse Recovery Time
–––
42
63
ns
Qrr
Reverse Recovery Charge
–––
44
66
nC
ton
Forward Turn-On Time
2
ch
MOSFET symbol
A
D
G
f
TJ = 25°C, IF = 8.8A, VDD = 10V
di/dt = 100A/µs
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
www.irf.com
IRF7475PbF
100
VGS
TOP
10V
8.0V
4.5V
3.5V
3.0V
2.8V
2.25V
BOTTOM 2.0V
10
1
VGS
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
2.0V
10V
8.0V
4.5V
3.5V
3.0V
2.8V
2.25V
BOTTOM 2.0V
10
2.0V
1
20µs PULSE WIDTH
TJ = 25°C
0.1
0.1
20µs PULSE WIDTH
TJ = 150°C
0.1
1
10
100
0.1
1
VDS, Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
2.0
TJ = 150°C
TJ = 25°C
VDS = 10V
20µs PULSE WIDTH
ID = 11A
VGS = 4.5V
1.5
(Normalized)
RDS(on), Drain-to-Source On Resistance
100
ID, Drain-to-Source Current (A)
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
10
10
1.0
0.5
0.0
1
1
2
3
4
VGS, Gate-to-Source Voltage
Fig 3. Typical Transfer Characteristics
www.irf.com
5
-60
-40
-20
0
20
40
60
80
100
120
140
160
TJ, Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF7475PbF
6
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
10000
Ciss
Coss
1000
ID = 7.0A
VDS = 12V
VDS = 6.0V
5
4
3
2
1
Crss
100
0
1
10
100
0
5
VDS, Drain-to-Source voltage (V)
10
15
20
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
TJ = 150ºC
10
TJ = 25ºC
1
100
10µsec
10msec
1
TC = 25ºC
TJ = 150ºC
Single Pulse
VGS = 0V
0.1
0.1
0.0
0.5
1.0
1.5
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1msec
10
2.0
0.1
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
www.irf.com
IRF7475PbF
1.6
VGS(th), Gate Threshold Voltage (V)
ID , Drain Current (A)
12
9
6
3
0
1.4
ID = 250µA
1.2
1.0
0.8
25
50
75
100
125
150
-75
TC , Case Temperature ( ° C)
-50
-25
0
25
50
75
100
125
150
TJ, Temperature (°C)
Fig 10. Threshold Voltage Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
Thermal Response (Z thJA )
100
D = 0.50
0.20
10
0.10
0.05
PDM
0.02
1
t1
0.01
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJA + TA
SINGLE PULSE
(THERMAL RESPONSE)
0.1
0.00001
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com
5
IRF7475PbF
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
EAS , Single Pulse Avalanche Energy (mJ)
500
15V
ID
3.9A
7.0A
BOTTOM 8.8A
TOP
400
300
200
100
0
tp
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
V DS
Fig 12b. Unclamped Inductive Waveforms
VGS
RG
Current Regulator
Same Type as D.U.T.
RD
D.U.T.
+
-VDD
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
50KΩ
12V
.2µF
Fig 14a. Switching Time Test Circuit
.3µF
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
6
10%
VGS
td(on)
tr
t d(off)
tf
Fig 14b. Switching Time Waveforms
www.irf.com
IRF7475PbF
D.U.T
Driver Gate Drive
ƒ
+
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
D=
Period
P.W.
+
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
www.irf.com
7
IRF7475PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgs 2
Qgd
⎞ ⎛
⎞
+⎜I ×
× Vin × f ⎟ + ⎜ I ×
× Vin × f ⎟
ig
ig
⎝
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
www.irf.com
IRF7475PbF
SO-8 Package Outline
Dimensions are shown in millimeters (inches)
D
5
A
8
7
6
5
6
H
0.25 [.010]
1
2
3
A
4
MAX
MIN
.0532
.0688
1.35
1.75
A1 .0040
.0098
0.10
0.25
b
.013
.020
0.33
0.51
c
.0075
.0098
0.19
0.25
D
.189
.1968
4.80
5.00
E
.1497
.1574
3.80
4.00
e
.050 BASIC
1.27 BASIC
e1
6X
e
e1
C
.025 BASIC
0.635 BASIC
H
.2284
.2440
5.80
6.20
K
.0099
.0196
0.25
0.50
L
.016
.050
0.40
1.27
y
0°
8°
0°
8°
y
0.10 [.004]
0.25 [.010]
MAX
K x 45°
A
8X b
MILLIMETERS
MIN
A
E
INCHES
DIM
B
A1
8X L
8X c
7
C A B
F OOTPRINT
NOT ES :
1. DIMENS IONING & TOLERANCING PER ASME Y14.5M-1994.
8X 0.72 [.028]
2. CONT ROLLING DIMENS ION: MILLIMET ER
3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES].
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS -012AA.
5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .
MOLD PROTRUS IONS NOT TO EXCEED 0.15 [.006].
6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .
MOLD PROTRUS IONS NOT TO EXCEED 0.25 [.010].
6.46 [.255]
7 DIMENS ION IS T HE LENGT H OF LEAD FOR SOLDERING TO
A S UBST RAT E.
3X 1.27 [.050]
8X 1.78 [.070]
SO-8 Part Marking
EXAMPLE: T HIS IS AN IRF7101 (MOSFET )
INT ERNAT IONAL
RECT IFIER
LOGO
XXXX
F7101
DAT E CODE (YWW)
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
Y = LAS T DIGIT OF T HE YEAR
WW = WEEK
A = AS S EMBLY S IT E CODE
LOT CODE
PART NUMBER
www.irf.com
9
IRF7475PbF
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 4.7mH
R G = 25Ω, IAS = 8.8A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualifications Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.09/04
10
www.irf.com