IRF IRFIB5N50LPBF

PD - 95390
IRFIB5N50LPbF
SMPS MOSFET
HEXFET® Power MOSFET
Applications
• Zero Voltage Switching SMPS
VDSS RDS(on) typ. Trr typ. ID
• Telecom and Server Power Supplies
0.67Ω
500V
73ns 4.7A
• Uninterruptible Power Supplies
• Motor Control applications
• Lead-Free
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
TO-220 Full-Pak
• Higher Gate voltage threshold offers improved noise
immunity.
Absolute Maximum Ratings
ID @ TC = 25°C
Parameter
Continuous Drain Current, VGS @ 10V
Max.
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
3.0
IDM
16
Pulsed Drain Current
c
PD @TC = 25°C Power Dissipation
VGS
Linear Derating Factor
Gate-to-Source Voltage
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
TSTG
Storage Temperature Range
Units
4.7
d
A
42
W
0.33
±30
W/°C
V
13
-55 to + 150
V/ns
°C
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
10lb in (1.1N m)
x
Mounting torque, 6-32 or M3 screw
x
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
4.7
ISM
(Body Diode)
Pulsed Source Current
–––
–––
16
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.5
V
p-n junction diode.
TJ = 25°C, IS = 4.0A, VGS = 0V
trr
Reverse Recovery Time
–––
73
110
ns
TJ = 25°C, IF = 4.0A
–––
99
150
TJ = 125°C, di/dt = 100A/µs
–––
200
310
nC TJ = 25°C, IS = 4.0A, VGS = 0V
–––
360
540
TJ = 125°C, di/dt = 100A/µs
–––
6.7
10
Qrr
c
Reverse Recovery Charge
IRRM
Reverse Recovery Current
ton
Forward Turn-On Time
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MOSFET symbol
A
A
showing the
integral reverse
D
G
f
f
S
f
f
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
1
06/10/04
IRFIB5N50LPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.43
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
0.67
0.80
VGS(th)
Gate Threshold Voltage
3.0
–––
5.0
IDSS
Drain-to-Source Leakage Current
–––
–––
50
µA
VDS = 500V, VGS = 0V
–––
–––
2.0
mA
VDS = 400V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage
–––
–––
100
nA
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
2.0
–––
IGSS
RG
500
–––
–––
V
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
Ω
V
VGS = 10V, I D = 2.4A
f
VDS = VGS, ID = 250µA
VGS = 30V
VGS = -30V
Ω
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
S
Conditions
gfs
Qg
Forward Transconductance
2.8
–––
–––
VDS = 50V, ID = 2.4A
Total Gate Charge
–––
–––
45
Qgs
Gate-to-Source Charge
–––
–––
13
Qgd
Gate-to-Drain ("Miller") Charge
–––
–––
23
VGS = 10V, See Fig. 7 & 16
td(on)
Turn-On Delay Time
–––
13
–––
VDD = 250V
tr
Rise Time
–––
17
–––
td(off)
Turn-Off Delay Time
–––
26
–––
RG = 9.0Ω
tf
Fall Time
–––
10
–––
VGS = 10V, See Fig. 11a & 11b
Ciss
Input Capacitance
–––
1000
–––
VGS = 0V
Coss
Output Capacitance
–––
110
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
12
–––
Coss
Output Capacitance
–––
1360
–––
Coss
Output Capacitance
–––
31
–––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
75
–––
VGS = 0V,VDS = 0V to 400V
Coss eff. (ER)
Effective Output Capacitance
–––
55
–––
ID = 4.0A
nC
ns
pF
VDS = 400V
f
ID = 4.0A
f
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
g
(Energy Related)
Avalanche Characteristics
Symbol
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
–––
Max.
140
–––
4.0
A
–––
3.0
mJ
Units
mJ
Thermal Resistance
Typ.
Max.
Units
RθJC
Symbol
Junction-to-Case
Parameter
–––
3.0
°C/W
RθJA
Junction-to-Ambient
–––
65
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11).
‚ Starting TJ = 25°C, L = 18mH, RG = 25Ω,
IAS = 4.0A, dv/dt = 13V/ns. (See Figure 12a).
ƒ ISD ≤ 4.0, di/dt ≤ 280A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C.
2
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff.(ER) is a fixed capacitance that stores the same energy
as C oss while VDS is rising from 0 to 80% VDSS.
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IRFIB5N50LPbF
100
100
10
BOTTOM
1
VGS
15V
12V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
VGS
15V
12V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
0.1
5.5V
0.01
10
BOTTOM
1
5.5V
0.1
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
0.001
0.01
0.1
1
10
100
0.1
1
VDS, Drain-to-Source Voltage (V)
10
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
I D = 4.0A
2.5
TJ = 25 ° C
1
0.1
V DS= 50V
20µs PULSE WIDTH
0.01
5.0
6.0
7.0
8.0
V GS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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9.0
2.0
(Normalized)
I D, Drain-to-Source Current (A)
10
°C
RDS(on) , Drain-to-Source On Resistance
TJ = 150
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
100
120
140
160
°
Tj, Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRFIB5N50LPbF
100000
10000
9
8
Coss = Cds + Cgd
7
Energy (µJ)
C, Capacitance(pF)
10
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Ciss
1000
Coss
100
6
5
4
3
Crss
10
2
1
1
0
1
10
100
1000
0
VDS, Drain-to-Source Voltage (V)
200
300
400
500
600
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 6. Typ. Output Capacitance
Stored Energy vs. VDS
100
12
I D = 4.0A
VDS = 400V
VDS = 250V
VDS = 100V
I SD , Reverse Drain Current (A)
10
VGS , Gate-to-Source Voltage (V)
100
8
6
4
10
T J= 25 ° C
TJ = 150 ° C
1
2
V GS = 0 V
0.1
0
0.2
0
5
10
15
20
25
30
QG, Total Gate Charge (nC)
Fig 7. Typical Gate Charge vs.
Gate-to-Source Voltage
4
35
0.4
0.6
0.8
1.0
1.2
V SD,Source-to-Drain Voltage (V)
Fig 8. Typical Source-Drain Diode
Forward Voltage
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IRFIB5N50LPbF
5.0
OPERATION IN THIS AREA
LIMITED BY R DS(on)
4.0
10
ID , Drain Current (A)
ID, Drain-to-Source Current (A)
100
100µsec
1
1msec
Tc = 25°C
Tj = 150°C
Single Pulse
3.0
2.0
1.0
10msec
0.1
0.0
1
10
100
1000
10000
25
Fig 9. Maximum Safe Operating Area
V DS
VGS
RG
75
100
125
150
Fig 10. Maximum Drain Current vs.
Case Temperature
RD
VDS
90%
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 11a. Switching Time Test Circuit
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50
TC , Case Temperature ( °C)
VDS, Drain-to-Source Voltage (V)
10%
VGS
td(on)
tr
t d(off)
tf
Fig 11b. Switching Time Waveforms
5
IRFIB5N50LPbF
(Z thJC )
10
D = 0.50
1
Thermal Response
0.20
0.10
0.05
P DM
0.1
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 / t 2
J = P DM x Z thJC
+TC
1
10
t 1, Rectangular Pulse Duration (sec)
Fig 12. Maximum Effective Transient Thermal Impedance, Junction-to-Case
VGS(th) Gate threshold Voltage (V)
6.0
5.0
ID = 250µA
4.0
3.0
2.0
-75
-50
-25
0
25
50
75
100
125
150
T J , Temperature ( °C )
Fig 13. Threshold Voltage vs.Temperature
6
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IRFIB5N50LPbF
EAS , Single Pulse Avalanche Energy (mJ)
320
TOP
ID
1.8A
BOTTOM
2.5A
4.0A
240
160
80
0
25
50
75
100
125
150
( ° C)
Starting Tj, Junction Temperature
Fig 14. Maximum Avalanche Energy
vs. Drain Current
15V
V(BR)DSS
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
tp
tp
0.01Ω
A
I AS
Fig 15a. Unclamped Inductive Test Circuit
Fig 15b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
10 V
.2µF
.3µF
D.U.T.
QGS
+
V
- DS
QGD
VG
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 16a. Gate Charge Test Circuit
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Charge
Fig 16b. Basic Gate Charge Waveform
7
IRFIB5N50LPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. For N-Channel HEXFET® Power MOSFETs
8
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IRFIB5N50LPbF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
E X AM P L E :
T H IS IS AN IR F I8 4 0G
W IT H AS S E M B L Y
L O T COD E 3 4 3 2
AS S E M B L E D O N W W 24 1 9 9 9
IN T H E AS S E M B L Y L IN E "K "
P AR T N U M B E R
IN T E R N AT ION AL
R E CT I F IE R
L OG O
IR F I84 0G
9 24 K
34
Note: "P" in assembly line
position indicates "Lead-Free"
AS S E M B L Y
L O T COD E
32
D AT E CO D E
Y E AR 9 = 1 9 9 9
W E E K 24
L IN E K
TO-220AB FullPak package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.06/04
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9