IRF IRFU120ZPBF

PD - 95772A
IRFR120ZPbF
IRFU120ZPbF
AUTOMOTIVE MOSFET
HEXFET® Power MOSFET
Features
l
l
l
l
l
l
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
D
VDSS = 100V
RDS(on) = 190mΩ
G
ID = 8.7A
S
Description
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche
rating . These features combine to make this design an extremely
efficient and reliable device for use in Automotive applications and
a wide variety of other applications.
D-Pak
IRFR120Z
I-Pak
IRFU120Z
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
IDM
8.7
PD @TC = 25°C Power Dissipation
35
W
0.23
± 20
W/°C
V
18
mJ
Linear Derating Factor
VGS
Gate-to-Source Voltage
EAS (Thermally limited) Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
EAS (Tested )
d
c
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
35
h
20
See Fig.12a, 12b, 15, 16
g
-55 to + 175
°C
Mounting Torque, 6-32 or M3 screw
300 (1.6mm from case )
y
Parameter
RθJA
RθJA
Junction-to-Ambient
i
y
10 lbf in (1.1N m)
Thermal Resistance
Junction-to-Case
Junction-to-Ambient (PCB mount)
A
mJ
Soldering Temperature, for 10 seconds
RθJC
A
6.1
c
Typ.
Max.
–––
4.28
–––
40
–––
110
Units
°C/W
HEXFET® is a registered trademark of International Rectifier.
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1
12/06/04
IRFR/U120ZPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
Min. Typ. Max. Units
Conditions
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LD
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
100
–––
–––
2.0
16
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
0.084
150
–––
–––
–––
–––
–––
–––
6.9
1.6
3.1
8.3
26
27
23
4.5
–––
–––
190
4.0
–––
20
250
200
-200
10
–––
–––
–––
–––
–––
–––
–––
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
310
41
24
150
26
57
–––
–––
–––
–––
–––
–––
S
and center of die contact
VGS = 0V
VDS = 25V
ƒ = 1.0MHz
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 80V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 80V
gfs
IDSS
IGSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
V VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 5.2A
V VDS = VGS, ID = 250µA
S VDS = 25V, ID = 5.2A
µA VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
ID = 5.2A
nC VDS = 80V
VGS = 10V
VDD = 50V
ID = 5.2A
ns RG = 53 Ω
VGS = 10V
D
Between lead,
e
e
e
nH
pF
G
f
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
8.7
ISM
(Body Diode)
Pulsed Source Current
–––
–––
35
VSD
trr
Qrr
ton
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
24
23
1.3
36
35
2
c
Conditions
MOSFET symbol
A
V
ns
nC
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 5.2A, VGS = 0V
TJ = 25°C, IF = 5.2A, VDD = 50V
di/dt = 100A/µs
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFR/U120ZPbF
100
100
VGS
10
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
1
4.5V
0.1
60µs PULSE WIDTH
Tj = 25°C
0.01
10
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.5V
1
60µs PULSE WIDTH
Tj = 175°C
0.1
0.1
0
11
10
10
100
100
0.1
0
VDS, Drain-to-Source Voltage (V)
11
10
10
100
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
12
Gfs, Forward Transconductance (S)
100.0
ID, Drain-to-Source Current (Α)
VGS
T J = 175°C
10.0
1.0
T J = 25°C
VDS = 25V
60µs PULSE WIDTH
T J = 175°C
10
8
T J = 25°C
6
4
2
VDS = 10V
380µs PULSE WIDTH
0.1
4.0
5.0
6.0
7.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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8.0
0
0
2
4
6
8
ID, Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
Vs. Drain Current
3
IRFR/U120ZPbF
500
ID= 5.2A
VGS, Gate-to-Source Voltage (V)
400
C, Capacitance (pF)
20
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C oss = C ds + C gd
Ciss
300
200
100
Coss
Crss
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
1
VDS= 80V
VDS= 50V
VDS= 20V
16
10
0
100
6
8
10
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
ID, Drain-to-Source Current (A)
100.0
ISD, Reverse Drain Current (A)
4
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
10.0
T J = 175°C
1.0
T J = 25°C
10
100µsec
1
VGS = 0V
0.1
0.1
0.0
0.5
1.0
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
2
1.5
Tc = 25°C
Tj = 175°C
Single Pulse
1
1msec
10msec
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U120ZPbF
10
RDS(on) , Drain-to-Source On Resistance
(Normalized)
3.0
ID , Drain Current (A)
8
6
4
2
0
ID = 5.2A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
25
50
75
100
125
150
175
-60 -40 -20
T J , Junction Temperature (°C)
0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 10. Normalized On-Resistance
Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
Thermal Response ( Z thJC )
10
D = 0.50
1
0.20
0.10
τJ
0.05
0.02
0.01
0.1
R1
R1
τJ
τ1
τ1
R2
R2
τ2
τ2
R3
R3
τ3
τC
τ
τ3
Ci= τi/Ri
Ci= i/Ri
Ri (°C/W) τi (sec)
0.33747 0.000053
1.793
2.150
0.000125
0.000474
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.01
1E-006
1E-005
0.0001
0.001
0.01
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U120ZPbF
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
VGS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS, Single Pulse Avalanche Energy (mJ)
80
15V
ID
0.9A
1.2
BOTTOM 5.2A
TOP
60
40
20
0
25
50
75
100
125
150
175
Starting T J, Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGD
5.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
QGS
4.0
ID = 250µA
3.0
2.0
-75 -50 -25
VGS
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
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IRFR/U120ZPbF
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
Avalanche Current (A)
0.01
0.05
1
0.10
0.1
0.01
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
20
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 5.2A
16
12
8
4
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I av = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRFR/U120ZPbF
D.U.T
Driver Gate Drive
ƒ
+
-
„
•
•
•
•
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
*

RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
-
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRFR/U120ZPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRF R120
WIT H ASS EMBLY
LOT CODE 1234
AS SEMBLED ON WW 16, 1999
IN T HE ASS EMBLY LINE "A"
PART NUMBER
INTERNAT IONAL
RECT IF IER
LOGO
Note: "P" in as sembly line position
indicates "Lead-Free"
IRFU120
916A
12
34
ASS EMBLY
LOT CODE
DATE CODE
YEAR 9 = 1999
WEEK 16
LINE A
OR
PART NUMBER
INTERNAT IONAL
RECT IFIER
LOGO
IRFU120
12
ASS EMBLY
LOT CODE
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34
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WEEK 16
A = ASS EMBLY SIT E CODE
9
IRFR/U120ZPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: THIS IS AN IRF U120
WITH ASSEMBLY
LOT CODE 5678
ASSEMBLED ON WW 19, 1999
IN THE ASSEMBLY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRFU120
919A
56
78
ASSEMBLY
LOT CODE
Note: "P" in assembly line
position indicates "Lead-Free"
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
OR
INT ERNAT IONAL
RECTIFIER
LOGO
PART NUMBER
IRFU120
56
AS SEMBLY
LOT CODE
10
78
DATE CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WEEK 19
A = ASS EMBLY SIT E CODE
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IRFR/U120ZPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
„ Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
max. junction temperature. (See fig. 11).
‚ Limited by TJmax, starting TJ = 25°C, L = 1.29mH … Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
RG = 25Ω, IAS = 5.2A, VGS =10V. Part not
avalanche performance.
recommended for use above this value.
† This value determined from sample failure population. 100%
ƒ Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
tested to this value in production.
‡ When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994
 Repetitive rating; pulse width limited by
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
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11