INTERSIL ISL70417SEHEVAL1Z

Rad Hard 40V Quad Precision Low Power Operational
Amplifiers
ISL70417SEH
Features
The ISL70417SEH contains four very high precision amplifiers
featuring the perfect combination of low noise vs power
consumption. Low offset voltage, low IBIAS current and low
temperature drift making them the ideal choice for applications
requiring both high DC accuracy and AC performance. The
combination of high precision, low noise, low power and small
footprint provides the user with outstanding value and flexibility
relative to similar competitive parts.
• Electrically Screened to DLA SMD# 5962-12228
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
The ISL70417SEH is offered in a 14 lead hermetic ceramic
flatpack package. The device is offered in an industry standard
pin configuration and operates over the extended temperature
range from -55°C to +125°C.
Applications
• Precision Instrumentation
• Spectral Analysis Equipment
• Active Filter Blocks
• Low Input Offset Voltage . . . . . . . . . . . . . . . . . . ±110µV, Max.
• Superb Offset Temperature Coefficient . . . . . . 1µV/°C, Max.
• Input Bias Current. . . . . . . . . . . . . . . . . . . . . . . . . . ±5nA, Max.
• Input Bias Current TC . . . . . . . . . . . . . . . . . . . . ±5pA/°C, Max.
• Low Current Consumption . . . . . . . . . . . . . . . . . . . . . . . 440µA
• Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8nV/√Hz
• Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 40V
• Operating Temperature Range. . . . . . . . . . .-55°C to +125°C
• Radiation Environment
- SEL/SEB LETTH (VS = ±20V). . . . . . . . . 73.9 MeV•cm2/mg
- Total Dose, High Dose Rate . . . . . . . . . . . . . . . 300krad(Si)
- Total Dose, Low Dose Rate . . . . . . . . . . . . . . . 100krad(Si) *
* Product capability established by initial characterization. The
EH version is acceptance tested on a wafer by wafer basis to
50krad(Si) at low dose rate.
• Thermocouples and RTD Reference Buffers
• Data Acquisition
• Power Supply Control
6
4
C1
2
8.2nF
VOS (µV)
V+
-
VIN
R1
R2
1.84k
4.93k
ISL70417SEH
C2
-2
BIAS
OUTPUT
-4
+
3.3nF
GND
0
-6
VS = ±15V
V-8
0
SALLEN-KEY LOW PASS FILTER (fC = 10kHz)
FIGURE 1. TYPICAL APPLICATION
July 2, 2012
FN7962.0
1
50
100
150
krad(Si)
200
250
300
FIGURE 2. VOS SHIFT vs HIGH DOSE RATE RADIATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL70417SEH
Ordering Information
ORDERING
NUMBER
PART NUMBER
(Notes 2, 3)
5962R1222801VXC
TEMPERATURE RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL70417SEHVF
-55 to +125
14 Ld Flatpack
K14.A
ISL70417SEHF/PROTO
ISL70417SEHF/PROTO
-55 to +125
14 Ld Flatpack
K14.A
5962R1222801V9AX
ISL70417SEHVX
-55 to +125
DIE
ISL70417SEHX/SAMPLE
ISL70417SEHX/SAMPLE
-55 to +125
DIE
ISL70417SEHEVAL1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70417SEH. For more information on MSL please see tech brief TB363.
2
July 2, 2012
FN7962.0
ISL70417SEH
Pin Configuration
ISL70417SEH
(14 LD FLATPACK)
TOP VIEW
OUT_A
1
-IN_A
2
+IN_A
14
OUT_D
13
-IN_D
3
12
+IN_D
V+
4
11
V-
+IN_B
5
10
+IN_C
9
-IN_C
8
OUT_C
-IN_B
6
OUT_B
7
A
- +
- +
B
D
+ -
+ C
Pin Descriptions
ISL70417SEH
(14 LD FLATPACK)
PIN NAME
EQUIVALENT CIRCUIT
1
OUT_A
Circuit 2
Amplifier A output
2
-IN_A
Circuit 1
Amplifier A inverting input
3
+IN_A
Circuit 1
Amplifier A non-inverting input
4
V+
Circuit 3
Positive power supply
5
+IN_B
Circuit 1
Amplifier B non-inverting input
6
-IN_B
Circuit 1
Amplifier B inverting input
7
OUT_B
Circuit 2
Amplifier B output
8
OUT_C
Circuit 2
Amplifier C output
9
-IN_C
Circuit 1
Amplifier C inverting input
10
+IN_C
Circuit 1
Amplifier C non-inverting input
11
V-
Circuit 3
Negative power supply
12
+IN_D
Circuit 1
Amplifier D non-inverting input
13
-IN_D
Circuit 1
Amplifier D inverting input
14
OUT_D
Circuit 2
Amplifier D output
V+
500Ω
V+
500Ω
IN-
IN+
VCIRCUIT 2
3
V+
CAPACITIVELY
COUPLED
ESD CLAMP
OUT
V-
CIRCUIT 1
DESCRIPTION
V-
CIRCUIT 3
July 2, 2012
FN7962.0
ISL70417SEH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....42V
Maximum Supply Voltage (LET = 73.9 MeV•cm2/mg). . . . . . . . . . . ....40V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input current for Input Voltage >V+ or <V-. . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration (1 output at a time). . . . . . . . . . . . . . . . Indefinite
ESD Rating
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV
Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . . 2kV
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
14 Ld Flatpack (Notes 3, 4). . . . . . . . . . . . .
105
15
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX) . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V (±2.25V) to 30V (±15V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For θJC, the "case temp" location is the center of the ceramic on the package underside.
Electrical Specifications
VS ± 15V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total
ionizing dose of 50krad(Si) with exposure a low dose rate of <10mrad(Si)/s.
PARAMETER
VOS
DESCRIPTION
CONDITIONS
MIN
(Note 5)
Input Offset Voltage
TCVOS
Offset Voltage Drift
IB
Input Bias Current
-1
TYP
MAX
(Note 5)
UNIT
10
75
µV
110
µV
0.1
1
µV/°C
0.08
1
nA
5
nA
-5
TCIB
Input Bias Current Temperature
Coefficient
IOS
Input Offset Current
-5
1
5
pA/°C
-1.5
0.08
1.5
nA
3
nA
3
pA/°C
13
V
-3
TCIOS
VCM
CMRR
Input Offset Current Temperature
Coefficient
-3
Input Voltage Range
Guaranteed by CMRR test
-13
Common-Mode Rejection Ratio
VCM = -13V to +13V
120
0.42
145
dB
120
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±20V
120
dB
145
dB
120
dB
AVOL
Open-Loop Gain
VO = -13V to +13V, RL = 10kΩ to ground
3,000
14,000
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
13.5
13.7
V
13.2
RL = 2kΩ to ground
13.3
V
13.55
V
13.0
VOL
Output Voltage Low
RL = 10kΩ to ground
RL = 2kΩ to ground
4
V
-13.7
-13.55
-13.5
V
-13.2
V
-13.3
V
-13.0
V
July 2, 2012
FN7962.0
ISL70417SEH
Electrical Specifications
VS ± 15V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total
ionizing dose of 50krad(Si) with exposure a low dose rate of <10mrad(Si)/s. (Continued)
PARAMETER
IS
ISC
VSUPPLY
DESCRIPTION
CONDITIONS
MIN
(Note 5)
Supply Current/Amplifier
Short-Circuit Current
Supply Voltage Range
TYP
MAX
(Note 5)
UNIT
0.44
0.53
mA
0.68
mA
43
Guaranteed by PSRR
± 2.25
mA
± 20
V
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
AV = 1k, RL = 2kΩ
1.5
MHz
enVp-p
Voltage Noise VP-P
0.1Hz to 10Hz
0.25
µVP-P
en
Voltage Noise Density
f = 10Hz
10
nV/√Hz
en
Voltage Noise Density
f = 100Hz
8.2
nV/√Hz
en
Voltage Noise Density
f = 1kHz
8
nV/√Hz
en
Voltage Noise Density
f = 10kHz
8
nV/√Hz
in
Current Noise Density
f = 1kHz
0.1
pA/√Hz
Total Harmonic Distortion
1kHz, G = 1, VO = 3.5VRMS, RL = 2kΩ
0.0009
%
1kHz, G = 1, VO = 3.5VRMS, RL = 10kΩ
0.0005
%
0.5
V/µs
THD + N
TRANSIENT RESPONSE
SR
Slew Rate, VOUT 20% to 80%
AV = 11, RL = 2kΩ, VO = 4VP-P
0.3
0.2
tr, tf,
Small Signal
ts
tOL
OS+
OS-
V/µs
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 50mVP-P,
RL = 10kΩ to VCM
130
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 50mVP-P, RL = 10kΩ to VCM
130
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P, RL = 5kΩ to VCM
21
µs
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P, RL = 5kΩ to VCM
24
µs
Settling Time to 0.1%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P, RL = 5kΩ to VCM
13
µs
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P, RL = 5kΩ to VCM
18
µs
Output Positive Overload Recovery Time
AV = -100, VIN = 0.2VP-P, RL = 2kΩ to VCM
5.6
µs
Output Negative Overload Recovery Time AV = -100, VIN = 0.2VP-P, RL = 2kΩ to VCM
10.6
µs
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
15
%
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
15
Positive Overshoot
Negative Overshoot
5
450
ns
625
ns
600
ns
700
ns
33
%
%
33
%
July 2, 2012
FN7962.0
ISL70417SEH
Electrical Specifications VS ± 5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total
ionizing dose of 50krad(Si) with exposure a low dose rate of <10mrad(Si)/s.
PARAMETER
VOS
DESCRIPTION
CONDITIONS
MIN
(Note 5)
Input Offset Voltage
TCVOS
Offset Voltage Drift
IB
Input Bias Current
-1
TYP
MAX
(Note 5)
UNIT
10
150
µV
250
µV
0.1
1
µV/°C
0.18
1
nA
5
nA
-5
TCIB
Input Bias Current Temperature Coefficient
IOS
Input Offset Current
-5
1
5
pA/°C
-1.5
0.3
1.5
nA
3
nA
3
pA/°C
3
V
-3
TCIOS
VCM
CMRR
Input Offset Current Temperature Coefficient
-3
Input Voltage Range
-3
Common-Mode Rejection Ratio
VCM = -3V to +3V
120
0.42
145
dB
120
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±5V
120
dB
145
dB
120
dB
AVOL
Open-Loop Gain
VO = -3.0V to +3.0V
RL = 10kΩ to ground
3,000
14,000
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
3.5
3.7
V
3.2
RL = 2kΩ to ground
3.3
V
3.55
V
3.0
VOL
IS
ISC
Output Voltage Low
V
RL = 10kΩ to ground
-3.7
-3.5
-3.2
V
RL = 2kΩ to ground
-3.55
-3.3
V
-3.0
V
Supply Current/Amplifier
0.44
Short-Circuit Current
V
0.53
mA
0.68
mA
43
mA
AC SPECIFICATIONS
GBWP
Gain Bandwidth Product
AV = 1k, RL = 2kΩ
1.5
MHz
enp-p
Voltage Noise
0.1Hz to 10Hz
0.25
µVP-P
en
Voltage Noise Density
f = 10Hz
12
nV/√Hz
en
Voltage Noise Density
f = 100Hz
8.6
nV/√Hz
en
Voltage Noise Density
f = 1kHz
8
nV/√Hz
en
Voltage Noise Density
f = 10kHz
8
nV/√Hz
in
Current Noise Density
f = 1kHz
0.1
pA/√Hz
AV = 11, RL = 2kΩ, VO = 4VP-P
0.5
V/µs
TRANSIENT RESPONSE
SR
Slew Rate, VOUT 20% to 80%
6
July 2, 2012
FN7962.0
ISL70417SEH
Electrical Specifications VS ± 5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -55°C to +125°C; over a total ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 - 300krad(Si)/s; and over a total
ionizing dose of 50krad(Si) with exposure a low dose rate of <10mrad(Si)/s. (Continued)
PARAMETER
tr, tf,
Small Signal
DESCRIPTION
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 50mVP-P,
RL = 10kΩ to VCM
130
ns
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 50mVP-P, RL = 10kΩ
to VCM
130
ns
Settling Time to 0.1%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P,
RL = 5kΩ to VCM
12
µs
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = -1, VOUT = 4VP-P,
RL = 5kΩ to VCM
19
µs
Output Positive Overload Recovery Time
AV = -100, VIN = 0.2VP-P
RL = 2kΩ to VCM
7
µs
Output Negative Overload Recovery Time
AV = -100, VIN = 0.2VP-P
RL = 2kΩ to VCM
5.8
µs
OS+
Positive Overshoot
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
15
%
OS-
Negative Overshoot
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
15
%
ts
tOL
NOTE:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7
July 2, 2012
FN7962.0
ISL70417SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified.
100
100
VS = ±15V
VS = ±5V
50
VOS (µV)
VOS (µV)
50
0
-50
-100
-75
0
-50
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
150
-100
-75
-50
FIGURE 3. VOS vs TEMPERATURE
300
300
200
200
100
100
IB- (pA)
IB+ (pA)
125
150
0
-100
0
-100
-200
-200
-300
-300
-400
-400
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
VS = ±15V
400
-500
-75
150
-50
FIGURE 5. IB+ vs TEMPERATURE
-25
0
25
50
75
TEMPERATURE (°C)
100
125
150
FIGURE 6. IB- vs TEMPERATURE
500
500
400
400
VS = ±5V
300
300
200
200
100
100
IB- (pA)
IB+ (pA)
100
500
VS = ±15V
400
0
-100
0
-200
-300
-300
-400
-400
-50
-25
0
25
50
75
TEMPERATURE (°C)
FIGURE 7. IB+ vs TEMPERATURE
8
100
125
150
VS = ±5V
-100
-200
-500
-75
0
25
50
75
TEMPERATURE (°C)
FIGURE 4. VOS vs TEMPERATURE
500
-500
-75
-25
-500
-75
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
150
FIGURE 8. IB- vs TEMPERATURE
July 2, 2012
FN7962.0
ISL70417SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
500
500
400
VS = ±15V
300
300
200
200
100
100
IOS (pA)
IOS (pA)
400
0
-100
0
-100
-200
-200
-300
-300
-400
-400
-500
-75
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
-500
-75
150
VS = ±5V
-50
0
25
50
75
TEMPERATURE (°C)
100
125
150
FIGURE 10. IOS vs TEMPERATURE
FIGURE 9. IOS vs TEMPERATURE
0.7
25000
VO = ±13V
VS=±15V
0.6
VS=±5V
AVOL (V/mV)
Isupply (mA)
-25
0.5
VS=±2.25V
0.4
20000
15000
0.3
0.2
-70
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
10000
-75
130
-25
0
25
50
75
TEMPERATURE (°C)
100
125
150
FIGURE 12. AVOL vs TEMPERATURE
FIGURE 11. SUPPLY CURRENT PER AMP vs TEMPERATURE
-135
-50
-130
VS = ±2.25V TO ±20V
-135
CMRR (dB)
PSRR (dB)
-140
-140
-145
-150
VCM = ±13V
-155
-145
-70
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
FIGURE 13. PSRR vs TEMPERATURE
9
90
110
130
-160
-75
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
150
FIGURE 14. CMRR vs TEMPERATURE
July 2, 2012
FN7962.0
ISL70417SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
80
80
75
ISC+ @ ±15V
70
70
65
65
60
60
ISC- (mA)
ISC+ (mA)
75
55
50
55
50
45
45
40
40
35
35
30
-70
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
30
-70
130
100
-10
10
30
50
70
TEMPERATURE (°C)
90
110
130
VS = +5V
80
VS = ±15V
+125°C
60
60
40
+125°C
40
VOS (µV)
VOS (µV)
-30
100
80
+25°C
20
0
20
+25°C
0
-55°C
-55°C
-20
-20
-40
-40
-15
-10
-5
0
VCM (V)
5
10
14.2
14.1
14.0
-60
-5
15
-1
1
VS = +15V
RL = 10kΩ
-13.2
-13.3
13.8
-13.5
VOL (V)
-13.4
13.7
13.6
-13.6
-13.7
13.5
-13.8
13.4
-13.9
13.3
-14.0
13.2
-14.1
-30
5
-13.1
VS = +15V
RL = 10kΩ
-50
3
FIGURE 18. INPUT VOS vs INPUT COMMON MODE VOLTAGE,
VS = ±5V
13.9
13.1
-70
-3
VCM (V)
FIGURE 17. INPUT VOS vs INPUT COMMON MODE VOLTAGE,
VS = ±15
VOH (V)
-50
FIGURE 16. SHORT CIRCUIT CURRENT vs TEMPERATURE
FIGURE 15. SHORT CIRCUIT CURRENT vs TEMPERATURE
-60
ISC- @ ±15V
-10
10
30
50
70
TEMPERATURE (°C)
90
110
FIGURE 19. VOUT vs TEMPERATURE
10
130
-14.2
-70
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
130
FIGURE 20. VOUT vs TEMPERATURE
July 2, 2012
FN7962.0
ISL70417SEH
Typical Performance Curves
-13.1
14.2
VS = +15V
RL = 2kΩ
14.1
14.0
VS = +15V
RL = 2kΩ
-13.2
-13.3
13.9
-13.4
13.8
-13.5
VOL (V)
VOH (V)
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
13.7
13.6
-13.6
-13.7
13.5
-13.8
13.4
-13.9
13.3
-14.0
13.2
-14.1
13.1
-70
-14.2
-70
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
130
250
-10
INPUT NOISE VOLTAGE (nV/ÖHz)
150
100
50
0
-50
-100
-150 V+ = 36.4V
-200 Rg = 10, Rf = 100k
AV = 10,000
0
1
2
3
4
5
6
7
8
9
110
130
10
1
10
VS = ±18.2V
AV = 1
OPEN LOOP GAIN (dB)/PHASE (°)
100
1k
10k
FREQUENCY (Hz)
FIGURE 25. INPUT NOISE CURRENT SPECTRAL DENSITY
11
1k
10k
100k
FIGURE 24. INPUT NOISE VOLTAGE SPECTRAL DENSITY
1
10
100
FREQUENCY (Hz)
TIME (s)
INPUT NOISE CURRENT (pA/ÖHz)
90
VS = ±18.2V
AV = 1
1
10
FIGURE 23. INPUT NOISE VOLTAGE 0.1Hz to 10Hz
0.1
1
10
30
50
70
TEMPERATURE (°C)
100
200
INPUT NOISE VOLTAGE (nV)
-30
FIGURE 22. VOUT vs TEMPERATURE
FIGURE 21. VOUT vs TEMPERATURE
-250
-50
100k
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 10pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m
PHASE
GAIN
1
10
100
1k
10k 100k
1M 10M 100M
FREQUENCY (Hz)
FIGURE 26. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10kΩ,
CL = 10pF
July 2, 2012
FN7962.0
ISL70417SEH
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
220
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 100pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m
VS = ±2.5V
200
180
PHASE
VS = ±5V
160
140
CMRR (dB)
OPEN LOOP GAIN (dB)/PHASE (°)
Typical Performance Curves
GAIN
120
VS = ±15V
100
80
60
RL = INF
40
CL = 10pF
SIMULATION
20
1
10
100
1k
0
1m 10m 100m
10k 100k 1M 10M 100M
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 27. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10kΩ,
CL = 100pF
FIGURE 28. CMRR vs FREQUENCY, VS = ±2.25, ±5V, ±15V
120
70
110
60
100
PSRR+ AND PSRR- VS = ±2.25V
90
RL = INF
CL = 4pF
40
AV = +1
30
VCM = 1VP-P
GAIN (dB)
PSRR (dB)
70
50
10
30
20
AV = 10
Rg = 10k, Rf = 100k
AV = 1
PSRR+ AND PSRR- VS = ±15V
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 29. PSRR vs FREQUENCY, VS = ±5V, ±15V
FIGURE 30. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
4
2
Rf = Rg = 100k
2
RL = 10k
1
0
0
Rf = Rg = 10k
-2
-4
-1
GAIN (dB)
Rf = Rg = 1k
-6
Rf = Rg = 100
-8 VS = ±20V
RL = 10k
-10
CL = 4pF
-12
AV = +2
-14 VOUT = 50mVP-P
-16
10
Rg = OPEN, Rf = 0
-10
10
10M
VS = ±20V
CL = 4pF
RL = 10k
VOUT = 50mVP-P
AV = 100
0
0
NORMALIZED GAIN (dB)
40
10
20
-10
Rg = 1k, Rf = 100k
50
80
60
Rg = 100, Rf = 100k
AV = 1000
100
-3
-6
-7
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 31. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE
Rf/Rg
12
RL = 1k
-4
-5
1k
RL = 4.99k
-2
-8
10
VS = ±20V
RL = 499
CL = 4pF
AV = +1
RL = 100
VOUT = 50mVP-P
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 32. GAIN vs FREQUENCY vs RL
July 2, 2012
FN7962.0
ISL70417SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
12
2
VS = ±2.5V
RL = 10k
10
8
AV = +1
VOUT = 50mVP-P
-1
4
2
CL = 0.01µF
CL = 47pF
0
-2
CL = 100pF
CL = 470pF
-6
CL = 1000pF
100
10k
1k
100k
1M
VS = ±15V
-2
-3
VS = ±20V
-4
-5 CL = 4pF
RL = 10k
-6
AV = +1
-7 V
OUT = 50mVP-P
CL = 4pF
CL = 270pF
-4
-8
10
VS = ±5V
0
GAIN (dB)
GAIN (dB)
6
VS = ±2.25V
1
-810
10M
1k
100
FREQUENCY (Hz)
FIGURE 33. GAIN vs FREQUENCY vs CL
LARGE SIGNAL TRANSIENT RESPONSE (V)
160
120
VS = ±15V
RL-DRIVER CH. = OPEN
60
RL-RECEIVING CH. = 10k
CL = 4pF
40
AV = +1
20
VSOURCE = 1VP-P
0
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FIGURE 35. CROSSTALK, VS = ±15V
1.6
1.5
Slew Rate (V/uS)
1.4
SR+
1.3
1.2
1.1
SR-
1.0
0.9
0.8
0.6
-70
RL = 2k, 10k
CL = 7pF
AV = 1
VOut = 4VP-P
VS = ±5V, ±15V
0.7
-50
-30
-10
10
30
50
70
TEMPERATURE (°C)
90
110
FIGURE 37. SLEW RATE vs TEMPERATURE VS = ±5V, ±15V
13
10M
2.4
2.0
1.6
1.2
VS = ±15V, RL = 2k, 10k
0.8
0.4
0
VS = ±5V, RL = 2k, 10k
-0.4
-0.8
CL = 4pF
AV = +1
VOUT = 4VP-P
-1.2
-1.6
-2.0
-2.4
0
10
20
30
40
50
60
TIME (µs)
70
80
90
100
FIGURE 36. LARGE SIGNAL TRANSIENT RESPONSE vs RL VS = ±5V,
±15V
130
SMALL SIGNAL TRANSIENT RESPONSE (mV)
CROSSTALK (dB)
140
80
1M
FIGURE 34. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
180
100
10k
100k
FREQUENCY (Hz)
60
50
40
VS =±5, ±15V
30
RL = 10k
CL = 4pF
AV = +1
VOUT = 50mVP-P
20
10
0
-10
0
5
10
15
20
25
TIME (µs)
30
35
40
FIGURE 38. SMALL SIGNAL TRANSIENT RESPONSE, VS = ±5V, ±15V
July 2, 2012
FN7962.0
ISL70417SEH
VS = ±15V, VCM = 0V, RL = Open, TA = +25°C, unless otherwise specified. (Continued)
INPUT VOLTAGE (V)
0
14
0.24
12
0.20
10
-0.04
OUTPUT @ VS = ±15V
-0.08
8
RL = 2k
CL = 4pF
AV = -100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
-0.12
-0.16
-0.20
-0.24
6
4
0
-0.28
0
10
20
30
40
50
60
TIME (µs)
70
80
90
-2
100
RL = 2k
CL = 4pF
AV = -100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
0.12
0.08
0.04
-2
-4
-6
0
-8
-0.08
INPUT
OUTPUT @ VS = ±15V
-0.04
0
10
20
30
40
50
60
-10
70
80
90
-12
100
FIGURE 40. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V, ±15V
80
6
VS = ±15V
RL = 10k
AV = 1
VOUT = 50mVP-P
60
5
4
3
O
SH
O
O
T
VE
R
40
-
SH
O
O
T
+
50
VIN and VOUT (V)
70
VE
R
30
20
2
1
Vout @ -55°C
0
-1
Vout @ 25°C
-4
10
Vout @ 125°C
-5
1
10
100
1k
CAPACITANCE (pF)
10k
FIGURE 41. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V
14
100k
RL = 10k
CL = 7pF
AV = 1
VIn = ±5.9VP-P
-2
-3
O
OVERSHOOT (%)
0
TIME (µs)
FIGURE 39. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V, ±15V
0
2
OUTPUT @ VS = ±5V
0.16
2
OUTPUT @ VS= ±5V
4
OUTPUT VOLTAGE (V)
INPUT
INPUT VOLTAGE (V)
0.04
OUTPUT VOLTAGE (V)
Typical Performance Curves
-6
VS = ±5V
Vin
0
0.2
0.4
0.6
0.8
1
1.2
TIME (mS)
1.4
1.6
1.8
2
FIGURE 42. OUTPUT PHASE REVERSAL RESPONSE vs TEMPERATURE
July 2, 2012
FN7962.0
ISL70417SEH
Post High Dose Radiation Characteristics Unless otherwise specified, VS ± 15V, VCM = 0, VO = 0V, TA = +25°C. This data is
typical mean test data post radiation exposure at a high dose rate of 50 - 300rad(Si)/s. This data is intended to show typical parameter shifts due to high
dose rate radiation. These are not limits nor are they guaranteed
0.460
6
0.458
4
0.454
2
BIAS
VOS (µV)
Isupply (mA)
0.456
0.452
0.450
GND
0
-2
0.448
BIAS
GND
0.446
-4
0.444
-6
0.442
0.440
0
50
100
150
krad(Si)
200
250
-8
0
300
50
FIGURE 43. SUPPLY CURRENT PER AMP vs HIGH DOSE RATE
RADIATION
500
900
400
IB- (pA)
500
GND
400
300
100
GND
0
-100
300
200
-200
100
-300
0
50
100
150
krad(Si)
200
250
-400
300
0
50
100
150
krad(Si)
200
250
300
FIGURE 46. IB- vs HIGH DOSE RATE RADIATION
FIGURE 45. IB+ vs HIGH DOSE RATE RADIATION
0
-50
GND
-100
-150
IOS (pA)
IB+ (pA)
250
200
600
0
200
BIAS
300
BIAS
700
150
krad(Si)
FIGURE 44. VOS vs HIGH DOSE RATE RADIATION
1000
800
100
-200
-250
-300
BIAS
-350
-400
0
50
100
150
krad(Si)
200
250
300
FIGURE 47. IOSvs HIGH DOSE RATE RADIATION
15
July 2, 2012
FN7962.0
ISL70417SEH
Post Low Dose Radiation Characteristics Unless otherwise specified, VS ± 15V, VCM = 0, VO = 0V, TA = +25°C. This data is
typical mean test data post radiation exposure at a low dose rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to low
dose rate radiation. These are not limits nor are they guaranteed
110
0.7
90
0.6
70
BIAS
50
VOS (µV)
Isupply (mA)
0.5
0.4
GND
0.3
GND
30
10
-10
BIAS
-30
0.2
-50
-70
0.1
0
-90
-110
0
20
40
60
krad(Si)
80
100
0
5
4
4
1
1
IB- (pA)
2
0
GND
-3
-3
-4
-4
20
40
50
60
70
80
90
100
0
-1
-2
0
40
BIAS
-2
60
krad(Si)
80
-5
100
GND
0
20
40
60
krad(Si)
80
100
FIGURE 51. IB- vs LOW DOSE RATE RADIATION
FIGURE 50. IB+ vs LOW DOSE RATE RADIATION
3
2
1
IOS (pA)
IB+ (pA)
3
BIAS
2
-1
30
FIGURE 49. VOS vs LOW DOSE RATE RADIATION
5
-5
20
krad(Si)
FIGURE 48. SUPPLY CURRENT PER AMP vs LOW DOSE RATE
RADIATION
3
10
GND
0
-1
BIAS
-2
-3
0
20
40
60
krad(Si)
80
100
FIGURE 52. IOSvs LOW DOSE RATE RADIATION
16
July 2, 2012
FN7962.0
ISL70417SEH
Applications Information
V+
Functional Description
The ISL70417SEH contains four, low noise precision op amps.
These devices are fabricated in a new precision 40V
complementary bipolar DI process. A super-beta NPN input stage
with input bias current cancellation provides low input bias
current (180pA typical), low input offset voltage (13µV typical),
low input noise voltage (8nV/√Hz), and low 1/f noise corner
frequency (~8Hz). These amplifiers also feature high open loop
gain (14kV/mV) for excellent CMRR (145dB) and THD+N
performance (0.0005% @ 3.5VRMS, 1kHz into 2kΩ). A
complementary bipolar output stage enables high capacitive
load drive without external compensation.
Operating Voltage Range
The devices are designed to operate over the 4.5V (±2.25V) to
40V (±20V) voltage range and are fully characterized at 10V
(±5V) and 30V (±15V). The Power Supply Rejection Ratio typically
exceeds 140dB over the full operating voltage range and 120dB
minimum over the -55°C to +125°C temperature range. The
worst case common mode input voltage range over temperature
is 2V to each rail. With ±15V supplies, CMRR performance is
typically >130dB over-temperature. The minimum CMRR
performance over the -55°C to +125°C temperature range is
>120dB for power supply voltages from ±5V (10V) to ±15V (30V).
Input Performance
The super-beta NPN input pair provides excellent frequency
response while maintaining high input precision. High NPN beta
(>1000) reduces input bias current while maintaining good
frequency response, low input bias current and low noise. Input
bias cancellation circuits provide additional bias current
reduction to <5nA, and excellent temperature stabilization.
Figures 6 through 8 show the high degree of bias current stability
at ±5V and ±15V supplies that is maintained across the -55°C to
+125°C temperature range. The low bias current TC also
produces very low input offset current TC, which reduces DC
input offset errors in precision, high impedance amplifiers.
The +25°C maximum input offset voltage (VOS) is 75µV at ±15V
supplies. Input offset voltage temperature coefficients (VOSTC) is a
maximum of ±1.0µV/°C. The VOS temperature behavior is smooth
(Figures 3 through 4) maintaining constant TC across the entire
temperature range.
- 500Ω
VIN
+ 500Ω
VOUT
RL
V-
FIGURE 53. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
The series resistors limit the high feed-through currents that can
occur in pulse applications when the input dV/dT exceeds the
0.5V/µs slew rate of the amplifier. Without the series resistors, the
input can forward-bias the anti-parallel diodes causing current to
flow to the output resulting in severe distortion and possible diode
failure.
Figure 36 provides an example of distortion free large signal
response using a 4VP-P input pulse with an input rise time of <1ns.
The series resistors enable the input differential voltage to be
equal to the maximum power supply voltage (40V) without
damage.
In applications where one or both amplifier input terminals are at
risk of exposure to high voltages beyond the power supply rails,
current limiting resistors may be needed at the input terminal to
limit the current through the power supply ESD diodes to 20mA
max.
Output Current Limiting
The output current is internally limited to approximately ±45mA
at +25°C and can withstand a short circuit to either rail as long
as the power dissipation limits are not exceeded. This applies to
only 1 amplifier at a time for the quad op amp. Continuous
operation under these conditions may degrade long term
reliability. Figures 15 and 16 show the current limit variation with
temperature.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL70417SEH is immune to output phase reversal,
even when the input voltage is 1V beyond the supplies.
Input ESD Diode Protection
Power Dissipation
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, series connected
500Ω current limiting resistors and an anti-parallel diode pair
across the inputs (Figure 53).
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
T JMAX = T MAX + θ JA xPD MAXTOTAL
(EQ. 1)
where:
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
17
July 2, 2012
FN7962.0
ISL70417SEH
• PDMAX for each amplifier can be calculated using Equation 2:
V OUTMAX
PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × ---------------------------R
L
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the application
18
July 2, 2012
FN7962.0
ISL70417SEH
Package Characteristics
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 30kÅ
Weight of Packaged Device
0. 6043 Grams (Typical)
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Potential: Unbiased
Case Isolation to Any Lead: 20 x 109 Ω (min)
PROCESS
Dielectrically Isolated Complementary Bipolar - PR40
ASSEMBLY RELATED INFORMATION
Die Characteristics
SUBSTRATE POTENTIAL
Die Dimensions
Floating
2028µm x 2568µm (80mils x 101mils)
Thickness: 483µm ± 25µm (19mils ± 1 mil)
ADDITIONAL INFORMATION
Interface Materials
WORST CASE CURRENT DENSITY
< 2 x 105 A/cm2
GLASSIVATION
Type: Nitrox
Thickness: 15kÅ
Metallization Mask Layout
-IN_A
OUT_A
OUT_D
-IN_D
+IN_A
+IN_D
PLACE HOLDER
V+
V-
+IN_B
+IN_C
-IN_B
19
OUT_B
OUT_C
-IN_C
July 2, 2012
FN7962.0
ISL70417SEH
TABLE 1. DIE LAYOUT X-Y COORDINATES
PAD NAME
PAD NUMBER
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
BOND WIRES
PER PAD
OUT_A
3
-256
1152
70
70
1
-IN_A
4
-661
1152
70
70
1
+IN_A
5
-867.5
948.5
70
70
1
V+
9
-880.5
0
70
70
1
+IN_B
13
-867.5
-948.5
70
70
1
-IN_B
14
-661
-1152
70
70
1
OUT_B
15
-256
-1152
70
70
1
OUT_C
16
256
-1152
70
70
1
-IN_C
17
661
-1152
70
70
1
+IN_C
18
867.5
-948.5
70
70
1
V-
22
880.5
0
70
70
1
+IN_D
26
867.5
948.5
70
70
1
-IN_D
1
661
1152
70
70
1
OUT_D
2
256
1152
70
70
1
NOTE:
6. Origin of coordinates is the center of die.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
July 2, 2012
FN7962.0
ISL70417SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Revision.
DATE
REVISION
July 2, 2012
FN7962.0
CHANGE
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL70417SEH
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
21
July 2, 2012
FN7962.0
ISL70417SEH
Package Outline Drawing
Ceramic Metal Seal Flatpack Packages (Flatpack)
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
A
e
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
INCHES
PIN NO. 1
ID AREA
-A-
D
-B-
S1
b
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
D
-
0.390
0.15
-
9.91
3
E1
0.004
M H A-B S
D S
0.036
Q
M H A-B S
D S
C
E
-D-
A
-C-
E
0.235
0.260
E1
-
0.290
5.97
E2
0.125
-
3.18
-
-
E3
0.030
-
0.76
-
7
0.015
0.20
-
6.60
-
7.11
3
-HE2
L
E3
SEATING AND
BASE PLANE
-
c1
L
E3
e
k
LEAD FINISH
BASE
METAL
(c)
b1
M
0.050 BSC
0.008
1.27 BSC
-
0.38
2
L
0.270
0.370
6.86
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.005
-
0.13
M
-
0.0015
-
-
0.04
6
-
M
(b)
SECTION A-A
N
14
14
Rev. 0 5/18/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify
pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of
dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead
dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced
by 0.0015 inch (0.038mm) maximum when solder dip lead finish is
applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
22
July 2, 2012
FN7962.0