STMICROELECTRONICS L7986TA

L7986TA
3 A step-down switching regulator
Datasheet − production data
Features
■
3 A DC output current
■
4.5 V to 38 V input voltage
■
Output voltage adjustable from 0.6 V
■
250 kHz switching frequency, programmable
up to 1 MHz
■
Internal soft-start and enable
■
Low dropout operation: 100% duty cycle
■
Voltage feed-forward
■
Zero load current operation
■
Overcurrent and thermal protection
■
HSOP8 package
■
Guarantee overtemperature range (-40 °C to
125 °C)
The input voltage can range from 4.5 V to 38 V,
while the output voltage can be set starting from
0.6 V to VIN.
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.
■
Automotive:
– Car audio, car infotainment
■
Industrial:
– PLD, PLA, FPGA, chargers
■
Networking: XDSL, modems, DC-DC modules
■
Computer:
– Optical storage, hard disk drive, printers
■
LED driving
This is information on a product in full production.
Description
The L7986TA is a step-down switching regulator
with 3.7 A (min.) current limited embedded power
MOSFET, so it is able to deliver up to 3 A current
to the load depending on the application
conditions.
Applications
October 2012
HSOP8 exposed pad
The HSOP package with exposed pad allows the
reduction of RthJA down to 40 °C/W.
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43
Contents
L7986TA
Contents
1
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
7
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5.1
Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3
Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5
Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6
Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4
Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4.1
Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.2
Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.7
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1
Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2
Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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L7986TA
Contents
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Pin settings
L7986TA
1
Pin settings
1.1
Pin connection
Figure 1.
1.2
Pin description
Table 1.
4/43
Pin connection (top view)
Pin description
N.
Type
1
OUT
Description
Regulator output
2
SYNCH
Master/slave synchronization. When it is left floating, a signal with a
phase shift of half a period, with respect to the power turn-on, is present
at the pin. When connected to an external signal at a frequency higher
than the internal one, the device is synchronized by the external signal,
with zero phase shift.
Connecting together the SYNCH pin of two devices, the one with a higher
frequency works as master and the other as slave; so the two powers
turn-ons have a phase shift of half a period.
3
EN
A logical signal (active high) enables the device. With EN higher than 1.2
V the device is ON and with EN lower than 0.3 V the device is OFF.
4
COMP
5
FB
Feedback input. By connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from VOUT to the FB pin.
6
FSW
The switching frequency can be increased connecting an external
resistor from the FSW pin and ground. If this pin is left floating, the device
works at its free-running frequency of 250 kHz.
7
GND
Ground
8
VCC
Unregulated DC input voltage.
Error amplifier output to be used for loop frequency compensation.
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L7986TA
2
Maximum ratings
Maximum ratings
Table 2.
Absolute maximum ratings
Symbol
3
Parameter
Vcc
Input voltage
OUT
Output DC voltage
Value
Unit
45
-0.3 to VCC
FSW, COMP, SYNCH
Analog pin
-0.3 to 4
EN
Enable pin
-0.3 to VCC
FB
Feedback voltage
-0.3 to 1.5
PTOT
Power dissipation
at TA < 60 °C
HSOP
V
2
W
TJ
Junction temperature range
-40 to 150
°C
Tstg
Storage temperature range
-55 to 150
°C
Thermal data
Table 3.
Symbol
RthJA
Thermal data
Parameter
Maximum thermal resistance
junction-ambient (1)
HSOP8
Value
Unit
40
°C/W
1. Package mounted on demonstration board.
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Electrical characteristics
4
L7986TA
Electrical characteristics
TJ=-40 °C to 125 °C, VCC=12 V, unless otherwise specified.
Table 4.
Electrical characteristics
Values
Symbol
Parameter
Test condition
Unit
Min.
VCC
Operating input voltage
range
VCCON
Turn-on VCC threshold
VCCHYS
VCC UVLO hysteresis
RDSON
MOSFET on resistance
ILIM
Maximum limiting current
Typ.
4.5
Max.
38
4.5
0.1
TJ=25 °C
3.7
V
0.4
200
400
4.2
4.7
mΩ
A
3.5
4.7
Oscillator
FSW
Switching frequency
VFSW
FSW pin voltage
D
FADJ
210
250
275
1.254
Duty Cycle
0
Adjustable switching
frequency
RFSW=33 kΩ
KHz
V
100
1000
%
KHz
Dynamic characteristics
VFB
Feedback voltage
4.5 V<VCC<38 V
0.582
0.6
0.618
V
2.4
mA
30
μA
DC characteristics
IQ
IQST-BY
Duty Cycle=0, VFB=0.8
V
Quiescent current
Total standby quiescent
current
20
Enable
Device OFF level
VEN
EN threshold voltage
IEN
EN current
0.3
V
Device ON level
1.2
EN=VCC
7.5
10
8.2
9.7
μA
Soft-start
FSW pin floating
TSS
6/43
Soft-start duration
FSW=1 MHz,
RFSW=33 kΩ
Doc ID 022098 Rev 3
7.4
ms
2
L7986TA
Electrical characteristics
Table 4.
Electrical characteristics (continued)
Values
Symbol
Parameter
Test condition
Unit
Min.
Typ.
Max.
Error amplifier
VCH
High level output voltage
VFB<0.6 V
VCL
Low level output voltage
VFB>0.6 V
Source COMP pin
VFB=0.5 V, VCOMP=1 V
19
mA
Sink COMP pin
VFB=0.7 V, VCOMP=1 V
30
mA
Open-loop voltage gain
(1)
100
dB
IO SOURCE
IO SINK
GV
3
V
0.1
Synchronization function
VS_IN,HI
High input voltage
VS_IN,LO
Low input voltage
tS_IN_PW
2
3.3
V
1
Input pulse width
VS_IN,HI=3 V,
VS_IN,LO=0 V
100
VS_IN,HI=2 V,
VS_IN,LO=1 V
300
ISYNCH,LO
Slave sink current
VSYNCH=2.9 V
VS_OUT,HI
Master output amplitude
ISOURCE=4.5 mA
tS_OUT_PW
Output pulse width
SYNCH floating
ns
0.7
2
1
mA
V
110
ns
Protection
TSHDN
Thermal shutdown
150
Hysteresis
30
°C
1. Guaranteed by design.
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Functional description
5
L7986TA
Functional description
The L7986TA is based on a “voltage mode”, constant frequency control. The output voltage
VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V) providing
an error signal that, compared to a fixed frequency sawtooth, controls the on- and off-time of
the power switch.
The main internal blocks are shown in the block diagram in Figure 2. They are:
●
A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed-forward are implemented.
●
The soft-start circuitry to limit inrush current during the startup phase.
●
The voltage mode error amplifier.
●
The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch.
●
The high-side driver for embedded P-channel power MOSFET switch.
●
The peak current limit sensing block, to handle overload and short-circuit conditions.
●
A voltage regulator and internal reference. It supplies internal circuitry and provides a
fixed internal reference.
●
A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
●
A thermal shutdown block, to prevent thermal runaway.
Figure 2.
Block diagram
VCC
REGULATOR
TRIMMING
UVLO
&
EN
BANDGAP
EN
1.254V
3.3V
PEAK
CURRENT
LIMIT
0.6V
COMP
THERMAL
SOFTSTART
SHUTDOWN
DRIVER
S
E/A
Q
PWM
R
OUT
OSCILLATOR
FB
8/43
FSW
GND
Doc ID 022098 Rev 3
SYNCH
&
PHASE SHIFT
SYNCH
L7986TA
5.1
Functional description
Oscillator and synchronization
Figure 3 shows the block diagram of the oscillator circuit. The internal oscillator provides a
constant frequency clock. Its frequency depends on the resistor externally connect to the
FSW pin. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as
shown in Figure 5 by an external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 4.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feed-forward is implemented (Figure 4.b) in order
to keep the PWM gain constant versus the switching frequency (see Section 6.4 for PWM
gain expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pins together. When SYNCH pins are connected, the device with a
higher oscillator frequency works as master, so the slave device switches at the frequency
of the master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor (see the L5988D datasheet).
Figure 3.
Oscillator circuit block diagram
Clock
FSW
Clock
Generator
Synchronization
SYNCH
Ramp
Generator
Sawtooth
The device can be synchronized to work at a higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 4.c). This change must be taken into account when the loop stability is studied. To
minimize the change of the PWM gain, the free-running frequency should be set (with a
resistor on the FSW pin) only slightly lower than the external clock frequency. This preadjusting of the frequency changes the sawtooth slope in order to render the truncation of
sawtooth negligible, due to the external synchronization.
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Functional description
10/43
L7986TA
Figure 4.
Sawtooth: voltage and frequency feed-forward; external synchronization
Figure 5.
Oscillator frequency vs. FSW pin resistor
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L7986TA
5.2
Functional description
Soft-start
The soft-start is essential to assure correct and safe startup of the step-down converter. It
avoids inrush current surge and makes the output voltage increase monothonically.
The soft-start is performed by a staircase ramp on the non-inverting input (VREF) of the error
amplifier. So the output voltage slew rate is:
Equation 1
R1
SR OUT = SR VREF ⋅ ⎛ 1 + --------⎞
⎝
R2⎠
where SRVREF is the slew rate of the non-inverting input, while R1and R2 is the resistor
divider to regulate the output voltage (see Figure 6). The soft-start staircase consists of 64
steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So
the soft-start time and then the output voltage slew rate depend on the switching frequency.
Figure 6.
Soft-start scheme.
Soft-start time results:
Equation 2
32 ⋅ 64
SS TIME = -------------------Fsw
For example, with a switching frequency of 250 kHz the SSTIME is 8 ms.
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Functional description
5.3
L7986TA
Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier, therefore, with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
Table 5.
Uncompensated error amplifier characteristics
Parameter
Value
Low frequency gain
100 dB
GBWP
4.5 MHz
Slew rate
7 V/μs
Output voltage swing
0 to 3.3 V
Maximum source/sink current
17 mA/25 mA
In continuous conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. If the zero introduced by the output capacitor helps to compensate the double
pole of the LC filter, a type II compensation network can be used. Otherwise, a type III
compensation network must be used (see Section 6.4 for details of the compensation
network selection).
Anyway, the methodology to compensate the loop is to introduce zeroes to obtain a safe
phase margin.
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L7986TA
5.4
Functional description
Overcurrent protection
The L7986TA implements overcurrent protection by sensing current flowing through the
power MOSFET. Due to the noise created by the switching activity of the power MOSFET,
the current sensing is disabled during the initial phase of the conduction time. This avoids an
erroneous detection of a fault condition. This interval is generally known as “masking time”
or “blanking time”. The masking time is about 200 ns.
If the overcurrent limit is reached, the power MOSFET is turned off implementing pulse-bypulse overcurrent protection. In the overcurrent condition, the device can skip turn-on pulses
in order to keep the output current constant and equal to the current limit. If, at the end of the
“masking time”, the current is higher than the overcurrent threshold, the power MOSFET is
turned off and one pulse is skipped. If, at the following switching on, when the “masking
time” ends, the current is still higher than the overcurrent threshold, the device skips two
pulses. This mechanism is repeated and the device can skip up to seven pulses. While, if at
the end of the “masking time”, the current is lower than the overcurrent threshold, the
number of skipped cycles is decreased by one unit (see Figure 7).
So, the overcurrent/short-circuit protection acts by switching off the power MOSFET and
reducing the switching frequency down to one eighth of the default switching frequency, in
order to keep constant the output current around the current limit.
This kind of overcurrent protection is effective if the output current is limited. To prevent the
current from diverging, the current ripple in the inductor during the on-time must not be
higher than the current ripple during the off-time. That is:
Equation 3
V IN – V
– R DSON ⋅ I OUT – DCR ⋅ IOUT
V OUT + V F + R DSON ⋅ I OUT + DCR ⋅ I OUT
OUT
------------------------------------------------------------------------------------------------------------------------ ⋅ D = ---------------------------------------------------------------------------------------------------------------------- ⋅ (1 – D )
L ⋅ F SW
L ⋅ F SW
If the output voltage is shorted, VOUT≅ 0, IOUT=ILIM, D/FSW=TON_MIN, (1-D)/FSW≅ 1/FSW. So,
from Equation 3, the maximum switching frequency that guarantees to limit the current
results:
Equation 4
( V F + DCR ⋅ I
)
1
LIM
F *SW = ------------------------------------------------------------------------------------- ⋅ ------------------------( V IN – ( R DSON + DCR ) ⋅ I LIM ) T ON_MIN
With RDSon=300 mΩ, DRC=0.08 Ω, the worst condition is with VIN=38 V, ILIM=3.7 A; the
maximum frequency to keep the output current limited during the short-circuit results 88
kHz.
The pulse-by-pulse mechanism, which reduces the switching frequency down to one eighth
the maximum FSW, adjusted by the FSW pin, that assures a full effective output current
limitation, is 88 kHz*8 = 706 kHz.
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Functional description
L7986TA
If, with VIN=38 V, the switching frequency is set higher than 706 kHz, during short-circuit
condition the system finds a different equilibrium with higher current. For example, with
FSW=800 kHz and the output shorted to ground, the output current is limited around:
Equation 5
V IN ⋅ F *SW – V F ⁄ T ON_MIN
I OUT = -------------------------------------------------------------------------------------------------------------------------- = 4.2A
( DRC ⁄ T ON_MIN ) + ( R DSON + DCR ) ⋅ F *SW
where FSW* is 800 kHz divided by eight.
Figure 7.
5.5
Overcurrent protection
Enable function
The enable feature allows to put the device into standby mode. With the EN pin lower than
0.3 V the device is disabled and the power consumption is reduced to less than 30 μA. With
the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an internal
pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is
disabled. The pin is also VCC compatible.
5.6
Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 °C. Once the junction temperature returns to about 120 °C, the
device restarts in normal operation. The sensing element is very close to the PDMOS area,
so ensuring an accurate and fast temperature detection.
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L7986TA
Application information
6
Application information
6.1
Input capacitor selection
The capacitor connected to the input must be capable of supporting the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So, the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 6
I RMS = I O ⋅
2
2
2⋅ D
D
D – ------------------ + ------2
η
η
where Io is the maximum DC output current, D is the duty cycle, η is the efficiency.
Considering η=1, this function has a maximum at D=0.5 and it is equal to Io/2.
In a specific application, the range of possible duty cycles must be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 7
V OUT + V F
D MAX = --------------------------------------V INMIN – V SW
and
Equation 8
V OUT + V F
D MIN = ---------------------------------------V INMAX – V SW
where VF is the forward voltage on the freewheeling diode and VSW is the voltage drop
across the internal PDMOS.
The peak-to-peak voltage across the input capacitor can be calculated as:
Equation 9
IO
V PP = ------------------------------ ⋅
C IN ⋅ F SW
D
⎛1 – D
----⎞ ⋅ D + ---- ⋅ ( 1 – D ) + ESR ⋅ I O
⎝
η
η⎠
where ESR is the equivalent series resistance of the capacitor.
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Application information
L7986TA
Given the physical dimension, ceramic capacitors can well meet the requirements of the
input filter sustaining a higher input RMS current than electrolytic/tantalum types. In this
case the equation of CIN as a function of the target VPP can be written as follows:
Equation 10
IO
C IN = ------------------------------- ⋅
V PP ⋅ F SW
D
⎛1 – D
----⎞ ⋅ D + ---- ⋅ ( 1 – D )
⎝
η
η⎠
neglecting the small ESR of ceramic capacitors.
Considering η=1, this function has its maximum in D=0.5, therefore, given the maximum
peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is:
Equation 11
IO
C IN_MIN = -------------------------------------------------------2 ⋅ V PP_MAX ⋅ F SW
Typically CIN is dimensioned to keep the maximum peak-to-peak voltage in the order of 1%
of VINMAX
In Table 6 some multi-layer ceramic capacitors suitable for this device are reported.
Table 6.
Input MLCC capacitors
Manufacture
Series
Cap value (μF)
Rated voltage (V)
UMK325BJ106MM-T
10
50
GMK325BJ106MN-T
10
35
GRM32ER71H475K
4.7
50
Taiyo Yuden
Murata
A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that
additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability
on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to
1 µF.
6.2
Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value, in order to have the expected current ripple, must be selected.
The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current.
In the continuous current mode (CCM), the inductance value can be calculated by the
following equation:
Equation 12
V IN – V OUT
V OUT + V F
ΔI L = -------------------------------- ⋅ T ON = ----------------------------- ⋅ T OFF
L
L
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L7986TA
Application information
where TON is the conduction time of the internal high-side switch and TOFF is the conduction
time of the external diode (in CCM, FSW=1/(TON + TOFF)). The maximum current ripple, at
fixed VOUT, is obtained at maximum TOFF which is at minimum duty cycle (see Section 6.1 to
calculate minimum duty). So, by fixing ΔIL=20% to 30% of the maximum output current, the
minimum inductance value can be calculated:
Equation 13
V OUT + V F 1 – D MIN
L MIN = ----------------------------- ⋅ -----------------------ΔI MAX
F SW
where FSW is the switching frequency, 1/(TON + TOFF).
For example, for VOUT=5 V, VIN=24 V, IO=3 A and FSW=250 kHz, the minimum inductance
value to have ΔIL=30% of IO is about 18 μH.
The peak current through the inductor is given by:
Equation 14
ΔI
I L, PK = I O + --------L
2
So, if the inductor value decreases, then the peak current (that must be lower than the
minimum current limit of the device) increases. According to the maximum DC output
current for this product family (3 A), the higher the inductor value, the higher the average
output current that can be delivered, without triggering the overcurrent protection.
In Table 7 some inductor part numbers are listed.
Table 7.
Inductors
Manufacturer
Series
Inductor value (μH)
Saturation current (A)
MSS1038
3.8 to 10
3.9 to 6.5
MSS1048
12 to 22
3.84 to 5.34
PD Type L
8.2 to 15
3.75 to 6.25
PD Type M
2.2 to 4.7
4 to 6
CDRH6D226/HP
1.5 to 3.3
3.6 to 5.2
CDR10D48MN
6.6 to 12
4.1 to 5.7
Coilcraft
Wurth
SUMIDA
6.3
Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge or discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor must be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.
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Application information
L7986TA
Equation 15
ΔI MAX
ΔV OUT = ESR ⋅ ΔI MAX + -------------------------------------------8⋅ C
⋅ f
OUT
SW
Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR
value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. Section 6.4 illustrates how to consider its effect in the system
stability.
For example, with VOUT=5 V, VIN=24 V, ΔIL=0.9 A (resulting from the inductor value), in order
to have a ΔVOUT=0.01·VOUT, if the multi-layer ceramic capacitors are adopted, 10 µF are
needed and the ESR effect on the output voltage ripple can be neglected. In the case of
non-negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into
account its ESR value. So, in case of 330 µF with ESR=30 mΩ, the resistive component of
the drop dominates and the voltage ripple is 28 mV.
The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth, the output capacitor provides the current to the load. So, if the high slew
rate load transient is required by the application, the output capacitor and system bandwidth
must be chosen in order to sustain the load transient.
In Table 8 some capacitor series are listed.
Table 8.
Output capacitors
Manufacturer
Series
Cap value (μF)
Rated voltage (V)
ESR (mΩ)
GRM32
22 to 100
6.3 to 25
<5
GRM31
10 to 47
6.3 to 25
<5
ECJ
10 to 22
6.3
<5
EEFCD
10 to 68
6.3
15 to 55
SANYO
TPA/B/C
100 to 470
4 to 16
40 to 80
TDK
C3225
22 to 100
6.3
<5
MURATA
PANASONIC
6.4
Compensation network
The compensation network must assure stability and good dynamic performance. The loop
of the L7986TA is based on the voltage mode control. The error amplifier is a voltage
operational amplifier with high bandwidth. So, by selecting the compensation network the
E/A is considered as ideal, that is, its bandwidth is much larger than the system one.
The transfer functions of the PWM modulator and the output LC filter are studied (see
Figure 9). The transfer function of the PWM modulator, from the error amplifier output
(COMP pin) to the OUT pin, results:
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Application information
Equation 16
V IN
G PW0 = --------Vs
where VS is the sawtooth amplitude. As seen in Section 5.1, the voltage feed-forward
generates a sawtooth amplitude directly proportional to the input voltage, that is:
Equation 17
V S = K ⋅ V IN
In this way the PWM modulator gain results constant and equal to:
Equation 18
V IN
1
G PW0 = --------= ---- = 18
Vs
K
The synchronization of the device with an external clock provided trough the SYNCH pin
can modify the PWM modulator gain (see Section 5.1 to understand how this gain changes
and how to keep it constant in spite of the external synchronization).
Figure 8.
The error amplifier, the PWM modulator, and the LC output filter
VCC
VS
VREF
FB
PWM
E/A
OUT
COMP
L
ESR
GPW0
GLC
COUT
The transfer function on the LC filter is given by:
Equation 19
s
1 + ----------------------------2π ⋅ f zESR
G LC ( s ) = ----------------------------------------------------------------------------------2
s
s
- + ⎛ -----------------------⎞
1 + ---------------------------------⎝ 2π ⋅ f ⎠
2π ⋅ Q ⋅ f
LC
LC
where:
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Application information
L7986TA
Equation 20
1
f LC = -----------------------------------------------------------------------------------,
ESR
2π ⋅ L ⋅ C OUT ⋅ 1 + ---------------R OUT
1
f zESR = --------------------------------------------------2π ⋅ ESR ⋅ C OUT
Equation 21
R OUT ⋅ L ⋅ C OUT ⋅ ( R OUT + ESR )
Q = ------------------------------------------------------------------------------------------------------- ,
L + C OUT ⋅ R OUT ⋅ E SR
V OUT
R OUT = --------------I OUT
As seen in Section 5.3, two different kinds of network can compensate the loop. In the
following two paragraphs the guidelines to select the type II and type III compensation
network are illustrated.
6.4.1
Type III compensation network
The methodology to stabilize the loop consists of placing two zeroes to compensate the
effect of the LC double pole, therefore increasing phase margin; then, to place one pole in
the origin to minimize the dc error on regulated output voltage; and finally, to place other
poles far from the zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the type III
compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low
ESR (<1 mΩ), with very high frequency zero, so a type III network is adopted to compensate
the loop.
In Figure 9 the type III compensation network is shown. This network introduces two zeroes
(fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:
Equation 22
1
f Z1 = ------------------------------------------------------- ,
2π ⋅ C 3 ⋅ ( R 1 + R 3 )
1
f Z2 = -----------------------------------2π ⋅ R 4 ⋅ C 4
Equation 23
f P0 = 0,
20/43
1
f P1 = ------------------------------------,
2π ⋅ R 3 ⋅ C 3
Doc ID 022098 Rev 3
1
f P2 = --------------------------------------------------C4 ⋅ C 5
2π ⋅ R 4 ⋅ ---------------------C4 + C5
L7986TA
Application information
Figure 9.
Type III compensation network
In Figure 10 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))
and the open-loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn.
Figure 10. Open-loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1.
Choose a value for R1, usually between 1 kΩ and 5 kΩ.
2.
Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 24
BW
R 4 = ---------- ⋅ K ⋅ R 1
f LC
where K is the feed-forward constant and 1/K is equal to 18.
3.
Calculate C4 by placing the zero at 50% of the output filter double pole frequency (fLC):
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L7986TA
Equation 25
1
C 4 = ---------------------------------π ⋅ R 4 ⋅ f LC
4.
Calculate C5 by placing the second pole at four times the system bandwidth (BW):
Equation 26
C4
C 5 = ------------------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1
5.
Set also the first pole at four times the system bandwidth and also the second zero at
the output filter double pole:
Equation 27
R1
R 3 = -----------------------------,
4 ⋅ BW
-------------------- – 1
f LC
1
C 3 = ------------------------------------------------2π ⋅ R 3 ⋅ 4 ⋅ BW
The suggested maximum system bandwidth is equal to the switching frequency divided by
3.5 (FSW/3.5), anyway, lower than 100 kHz if the FSW is set higher than 500 kHz.
For example, with VOUT=5 V, VIN=24 V, IO=3 A, L=18 μH, COUT=22 μF, and ESR<1 mΩ, the
type III compensation network is:
Equation 28
R 1 = 4.99kΩ,
R 2 = 680Ω,
R 3 = 200Ω,
R 4 = 2kΩ,
C 3 = 3.3nF,
C 4 = 22nF,
C 5 = 220pF
In Figure 11 the module and phase of the open-loop gain is shown. The bandwidth is about
58 kHz and the phase margin is 50 °.
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Application information
Figure 11. Open-loop gain Bode diagram with ceramic output capacitor
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6.4.2
L7986TA
Type II compensation network
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency lower than the desired bandwidth (that is: 2π∗ESR∗COUT>1/BW), this zero helps
stabilize the loop. Electrolytic capacitors show non-negligible ESR (>30 mΩ), so with this
kind of output capacitor the type II network combined with the zero of the ESR allows to
stabilize the loop.
In Figure 12 the type II network is shown.
Figure 12. Type II compensation network
The singularities of the network are:
Equation 29
1
f Z1 = ------------------------------------ ,
2π ⋅ R 4 ⋅ C 4
f P0 = 0,
1
f P1 = --------------------------------------------------C 4 ⋅ C5
2π ⋅ R 4 ⋅ ---------------------C4 + C5
In Figure 13 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))
and the open-loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)) are drawn.
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Application information
Figure 13. Open-loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1.
Choose a value for R1, usually between 1 kΩ and 5 kΩ, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
2.
Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 30
2
VS
⎛ f ESR⎞
BW
R 4 = ⎜ -------------⎟ ⋅ ------------- ⋅ --------- ⋅ R 1
f
f
V
⎝ LC ⎠
ESR
IN
where fESR is the ESR zero:
Equation 31
1
f ESR = -------------------------------------------------2π ⋅ ESR ⋅ COUT
and Vs is the sawtooth amplitude. The voltage feed-forward keeps the ratio Vs/Vin constant.
3.
Calculate C4 by placing the zero one decade below the output filter double pole:
Equation 32
10
C 4 = ------------------------------------2π ⋅ R 4 ⋅ f LC
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Application information
4.
L7986TA
Then calculate C3 in order to place the second pole at four times the system bandwidth
(BW):
Equation 33
C4
C 5 = ------------------------------------------------------------------------2π ⋅ R 4 ⋅ C 4 ⋅ 4 ⋅ BW – 1
For example, with VOUT=5 V, VIN=24 V, IO=3 A, L=18 μH, COUT=330 μF, and ESR=35 mΩ,
the type II compensation network is:
Equation 34
R 1 = 1.1kΩ,
R 2 = 150Ω,
R 4 = 4.99kΩ,
C 4 = 82nF,
C 5 = 68pF
In Figure 14 the module and phase of the open-loop gain is shown. The bandwidth is about
21 kHz and the phase margin is 45 °.
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Application information
Figure 14. Open-loop gain Bode diagram with electrolytic/tantalum output capacitor
6.5
Thermal considerations
The thermal design is important to prevent the thermal shutdown of the device if junction
temperature goes above 150 °C. The three different sources of losses within the device are:
a)
conduction losses due to the non-negligible RDSon of the power switch; these are
equal to:
Equation 35
2
P ON = R DSON ⋅ ( I OUT ) ⋅ D
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Application information
L7986TA
where D is the duty cycle of the application and the maximum RDSon overtemperature is 220
mΩ. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but
actually it is quite higher in order to compensate the losses of the regulator. So the
conduction losses increase compared with the ideal case.
b)
switching losses due to power MOSFET turn-on and turn-off; these can be
calculated as:
Equation 36
( T RISE + T FALL )
P SW = V IN ⋅ I OUT ⋅ ---------------------------------------------- ⋅ Fsw = VIN ⋅ I OUT ⋅ T SW ⋅ F SW
2
where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS)
and the current flowing into it during turn-on and turn-off phases, as shown in Figure 15.
TSW is the equivalent switching time. For this device the typical value for the equivalent
switching time is 40 ns.
c)
quiescent current losses, calculated as:
Equation 37
P Q = V IN ⋅ I Q
where IQ is the quiescent current (IQ=2.4 mA).
The junction temperature TJ can be calculated as:
Equation 38
T J = T A + Rth JA ⋅ PTOT
where TA is the ambient temperature and PTOT is the sum of the power losses just seen.
RthJA is the equivalent thermal resistance junction to ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The RthJA measured on the demonstration board described in the following
paragraph is about 40 °C/W for the HSOP package.
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Application information
Figure 15. Switching losses
6.6
Layout considerations
The PC board layout of the switching DC/DC regulator is very important to minimize the
noise injected in high impedance nodes and interference generated by the high switching
current loops.
In a step-down converter the input loop (including the input capacitor, the power MOSFET
and the freewheeling diode) is the most critical one. This is due to the fact that the high
value pulsed currents are flowing through it. In order to minimize the EMI, this loop must be
as short as possible.
The feedback pin (FB) connection to the external resistor divider is a high impedance node,
so the interferences can be minimized by placing the routing of the feedback node as far as
possible from the high current paths. To reduce the pick-up noise, the resistor divider must
be placed very close to the device.
To filter the high frequency noise, a small bypass capacitor (220 nF - 1 µF) can be added as
close as possible to the input voltage pin of the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.
In Figure 16 a layout example is shown.
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Figure 16. Layout example
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6.7
Application information
Application circuit
In Figure 17 the demonstration board application circuit is shown.
Figure 17. Demonstration board application circuit
Table 9.
Component list
Reference
Part number
Description
Manufacturer
C1
UMK325BJ106MM-T
10 μF, 50 V
Taiyo Yuden
C2
GRM32ER61E226KE15
22 μF, 25 V
Murata
C3
3.3 nF, 50 V
C4
33 nF, 50 V
C5
100 pF, 50 V
C6
470 nF, 50 V
R1
4.99 kΩ, 1%, 0.1 W 0603
R2
1.1 kΩ, 1%, 0.1 W 0603
R3
330 Ω, 1%, 0.1 W 0603
R4
1.5 kΩ, 1%, 0.1 W 0603
R5
180 kΩ, 1%, 0.1 W 0603
D1
STPS3L40
3 A DC, 40 V
STMicroelectronics
L1
MSS1038-103NL
10 μH, 30%, 3.9 A,
DCRMAX=35 mΩ
Coilcraft
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Application information
L7986TA
Figure 18. PCB layout: L7986TA (component side)
Figure 19. PCB layout: L7986TA (bottom side)
Figure 20. PCB layout: L7986TA (front side)
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Application information
Figure 21. Junction temperature vs. output
current
VQFN
Figure 22. Junction temperature vs. output
current
HSOP
VQFN
VOUT=5V
HSOP
VOUT=5V
VOUT=3.3V
VOUT=3.3V
VOUT=1.8V
VOUT=1.8V
VIN=24V
FSW=250KHz
TAMB=25 C
Figure 23. Junction temperature vs. output
current
VIN=12V
FSW=250KHz
TAMB=25 C
Figure 24. Efficiency vs. output current
95
VQFN
Vo=5.0V
FSW=250kHz
HSOP
90
VOUT=3.3V
85
VOUT=1.8V
Eff [%]
VOUT=1.2V
80
75
70
VIN=5V
FSW=250KHz
TAMB=25 C
Vin=12V
Vin=18V
Vin=24V
65
60
0.100
0.600
1.100
1.600
2.100
2.600
3.100
Io [A]
Figure 25. Efficiency vs. output current
Figure 26. Efficiency vs. output current
95
85
75
80
70
75
65
70
65
Vo=1.8V
FSW=250kHz
80
E ff [%]
Eff [%]
85
Vo=3.3V
FSW=250kHz
90
60
55
60
50
Vin=5V
Vin=5V
Vin=12V
55
50
0.100
Vin=24V
0.600
1.100
1.600
2.100
2.600
3.100
Vin=12V
45
40
0.100
Io [A]
Vin=24V
0.600
1.100
1.600
2.100
2.600
3.100
Io [A]
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Application information
L7986TA
Figure 27. Load regulation
Figure 28. Line regulation
3.3600
3.350
Io=1A
Vin=5V
3.345
3.3550
Vin=12V
Io=2A
Io=3A
3.340
3.3500
3.335
3.3450
VOUT [V]
VOUT [V]
Vin=24V
3.330
3.3400
3.325
3.3350
3.320
3.3300
3.315
3.3250
3.310
3.3200
5.0
3.305
0.00
0.50
1.00
1.50
2.00
2.50
10.0
15.0
20.0
25.0
30.0
35.0
40.0
VIN [V]
3.00
Io [A]
Figure 29. Load transient: from 0.4 A to 3 A
Figure 30. Soft-start
IL 0.5A/div
1A/div
VOUT
200mV/div
AC coupled
VOUT 0.5V/div
1V/div
VIN=24V
VOUT=3.3V
COUT=47uF
L=10uH
FSW=520k
IL 1A/div
Time base 1ms/div
Time base 200us/div
Figure 31. Short-circuit behavior VIN=12 V
Figure 32. Short-circuit behavior VIN=24 V
SYNCH
SYNCH
5V/div
5V/div
OUT
OUT
5V/div
5V/div
VOUT
VOUT
1V/div
1V/div
IL
IL
1A/div
1A/div
Timebase 10us/div
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L7986TA
Application ideas
7
Application ideas
7.1
Positive buck-boost
The L7986TA can implement the step-up/down converter with a positive output voltage.
Figure 33. shows the schematic: one power MOSFET and one Schottky diode are added to
the standard buck topology to provide 12 V output voltage with input voltage from 4.5 V to 38
V.
Figure 33. Positive buck-boost regulator
The relationship between input and output voltage is:
Equation 39
D
V OUT = V IN ⋅ ------------1–D
so the duty cycle is:
Equation 40
V OUT
D = ------------------------------V OUT + V IN
The output voltage isn’t limited by the maximum operating voltage of the device (38 V),
because the output voltage is sensed only through the resistor divider. The external power
MOSFET maximum drain to source voltage must be higher than the output voltage; the
maximum gate to source voltage must be higher than the input voltage (in Figure 33, if VIN is
higher than 16 V, the gate must be protected through a Zener diode and resistor)
The current flowing through the internal power MOSFET is transferred to the load only
during the off-time, so according to the maximum DC switch current (3.0 A), the maximum
output current for the buck-boost topology can be calculated from the following equation.
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Application ideas
L7986TA
Equation 41
I OUT
I SW = ------------- < 3 A
1–D
where ISW is the average current in the embedded power MOSFET in the on-time.
To choose the right value of the inductor and to manage transient output current, which for a
short time can exceed the maximum output current calculated by Equation 41, also the peak
current in the power MOSFET must be calculated. The peak current, shown in Equation 42,
must be lower than the minimum current limit (3.7 A).
Equation 42
I OUT
I SW,PK = ------------- ⋅
1–D
r
1 + --- < 3.7A
2
V OUT
2
r = -------------------------------------------- ⋅ ( 1 – D )
I OUT ⋅ L ⋅ F SW
where r is defined as the ratio between the inductor current ripple and the inductor DC
current:
So, in the buck-boost topology the maximum output current depends on the application
conditions (firstly input and output voltage, secondly switching frequency and inductor
value).
In Figure 34 the maximum output current for the above configuration is depicted varying the
input voltage from 4.5 V to 38 V.
The dashed line considers a more accurate estimation of the duty cycles given by Equation
43, where power losses across diodes, external power MOSFET, and internal power
MOSFET are taken into account.
Figure 34. Maximum output current according to max. DC switch current (3.0 A):
VO=12 V
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Application ideas
Equation 43
V OUT + 2 ⋅ V D
D = -------------------------------------------------------------------------------------------------V IN – V SW – V SWE + V OUT + 2 ⋅ VD
where VD is the voltage drop across the diodes, VSW and VSWE across the internal and
external power MOSFET.
7.2
Inverting buck-boost
The L7986TA can implement the step-up/down converter with a negative output voltage.
Figure 33. shows the schematic to regulate -5 V: no further external components are added
to the standard buck topology.
The relationship between input and output voltage is:
Equation 44
D
V OUT = – V IN ⋅ ------------1–D
so the duty cycle is:
Equation 45
V OUT
D = ------------------------------V OUT – V IN
As in the positive one, in the inverting buck-boost the current flowing through the power
MOSFET is transferred to the load only during the off-time. So according to the maximum
DC switch current (3.0 A), the maximum output current can be calculated from Equation 41,
where the duty cycle is given by Equation 45 Equation 45.
Figure 35. Inverting buck-boost regulator
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L7986TA
The GND pin of the device is connected to the output voltage so, given the output voltage,
input voltage range is limited by the maximum voltage the device can withstand across VCC
and GND (38 V). Therefore, if the output is -5 V the input voltage can range from 4.5 V to 33
V.
As in the positive buck-boost, the maximum output current according to application
conditions is shown in Figure 36. The dashed line considers a more accurate estimation of
the duty cycles given by Equation 46, where power losses across diodes and the internal
power MOSFET are taken into account.
Equation 46
V OUT – V D
D = ------------------------------------------------------------------– V IN – V SW + VOUT – V D
Figure 36. Maximum output current according to switch max. peak current (3.0 A):
VO=-5 V
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8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 10.
HSOP8 mechanical data
mm
Dim
Min.
Typ.
A
Max.
1.70
A1
0.00
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
4.80
4.90
5.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
0.150
1.27
h
0.25
0.50
L
0.40
1.27
k
0.00
8.00
ccc
0.10
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Package mechanical data
L7986TA
Figure 37. Package dimensions
$MM4YP
%MM4YP
!-V
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9
Ordering information
Ordering information
Table 11.
Order code
Order code
Package
Packaging
L7986TA
HSOP8
Tube
L7986TATR
HSOP8
Tape and reel
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Revision history
10
L7986TA
Revision history
Table 12.
42/43
Document revision history
Date
Revision
Changes
25-Oct-2011
1
Initial release.
01-Mar-2012
2
Section 8: Package mechanical data has been updated.
16-Oct-2012
3
In Section 5.6 changed temperature value from 130 to 120 °C
Doc ID 022098 Rev 3
L7986TA
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