Ordering number : ENN7204 Monolithic Linear IC LA70100M SECAM Chroma-Signal Processor IC for VCR Overview Package Dimensions LA70100M is a SECAM method chroma-signal processor for VCR applications, realizing reduction in external parts count and adjustment free due to integrated band-pass filter, SECAM discrimination circuit, and BELL filter. unit : mm 3073C-MFP30SD (375mil) [ LA70100M ] Features • Integrates all filters required. • Automatic adjustment BELL filter fo. • Integrates SECAM discrimination circuit. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Symbol Conditions VCC max Pd max Ratings Unit 7.0 Ta≤65°C *440 V mW Operating temperature Topr -10 to +65 °C Storage temperature Tstg -40 to +150 °C * 114.3mm×76.1mm×1.6mm when mounted on a grass epoxy PCB. Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. N2206 / 92502 RM (IM) No.7204-1/16 LA70100M Recommended Operating Conditions at Ta = 25°C Parameter Symbol Supply voltage Conditions Ratings Unit VCC Allowable operating voltage range VCCOP 5.0 V 4.8 to 5.2 V Electrical Characteristics at Ta = 25°C, VCC = 5V Parameter Symbol In Out Conditions Recording mode ( T2 = 4.43MHz, 400mVp-p T29 = Comp.Sync T17 = 0V REC mode current drain 4.3MHz BPF Characteristics-1 T23 ICCR T16 VF4C T16 T18 GF4L1 T16 T18 typ max Unit T4 = OPEN ) T16 = 4.286MHz, 200mVp-p T24 4.3MHz BPF Characteristics-2 Ratings min T9 = 5V T16 = 4.286MHz, 200mVp-p 40 50 60 mA 145 180 215 mVp-p -30 -20 dB -10 -5 dB -24 -18 dB 4.243 4.286 4.329 92 110 132 mVp-p -7.5 -6.5 -5.5 dB -7.5 -6.5 -5.5 dB 1.0608 1.0715 1.0822 14 18 22 mVp-p 5.0 6.0 7.0 dB 5.0 6.0 7.0 dB 144 180 220 mVp-p -40 -30 dB -36 -30 dB Same condition as above. However, frequency of T16 is 1.1MHz Measure T18 ratio to V4FC. 4.3MHz BPF Characteristics-3 4.3MHz BPF Characteristics-4 GF4L2 T16 T18 GF4H T16 T18 FBLR T18 T20 4.3MHz BELL Center frequency Same condition as above. However, frequency of T16 = 2.2MHz Same condition as above. However, frequency of T16 = 7.5MHz T18 = 4 to 5MHz, 200mVp-p SW20 = ON (3.9K pull-down) ( see notes-1 ) MHz Measure during other timing than V-sync 4.3MHz BELL Characteristics-1 T18 = 4.286MHz, 200mVp-p, BIAS = 4.6V VBLRC T18 T20 SW20 = ON (3.9K pull-down) Measure during other timing than V-sync 4.3MHz BELL Characteristics-2 Same condition as above. However, GBLRL T18 T20 frequency of T18 is FBLR-250kHz Measure T18 ratio to VBLRC 4.3MHz BELL Characteristics-3 GBLRH T18 T20 FEQR T12 T11 Anti-BELL Center frequency Same condition as above. However, frequency of T18 is FBLR+250kHz SW11 = ON (3.9K pull-down) ( see notes-3 ) T12 = 1 to 2MHz, 200mVp-p, BIAS = 4.6V MHz Measure during other timing than V-sync Anti-BELL Characteristics-1 VEQRC T12 T11 GEQRL T12 T11 Anti-BELL Characteristics-2 Same condition as above. However, frequency of T12 is 1.0715MHz Same condition as above. However, frequency of T12 is FEQR-62.5kHz Measure T12 ratio to VEQRC Anti-BELL Characteristics-3 REC Chroma signal output level Chroma spurius spectrum-1 GEQRH T12 T11 VOR T16 T12 Same condition as above. However, frequency of T12 is FEQR+62.5kHz T1 = 5V, T16 = 4.4MHz, 200mVp-p Same condition as above. GSR1 T16 T12 GSR2 T16 T12 Sync gate start time TRGB T16 T12 T1 = 5V, T9 = 5V ( see notes-7 ) 1.1 1.6 2.1 µs Sync gate release time TRGE T16 T12 T16 = 4.286MHz, 200mVp-p 3.6 4.1 4.6 µs BGP-1 start time TBGB1 T29 T28 T9 = 5V ( see notes-10 ) 5.7 6.2 6.7 µs Chroma spurius spectrum-2 Measure 2.2MHz ratio to VOR at T12 Same condition as above. Measure 3.3MHz ratio to VOR at T12 BGP-2 start time TBGB2 T29 T28 Same condition as above. However, T4 = 5V 6.1 6.6 7.1 µs BGP-3 start time TBGB3 T29 T28 Same condition as above. However, T4 = 0V 5.3 5.8 6.3 µs BGP width TBGW T29 T28 ( see notes-10 ) 2.3 2.8 3.3 µs 7 10 13 kΩ 0.5 V 4.2 V SECAM DET outout resistance R26 T28 T27 = 5V ( see notes-11 ) SECAM DET characteristics-1 VSCMR1 T16 T28 T16 = SECAM color-bar ( see notes-12 ) SECAM DET characteristics-2 VSCMR2 T16 T28 T16 = PAL color-bar ( see notes-13 ) Regulator voltage VREG T13 4.5 3.8 V 4.0 Continued on next page. No.7204-2/16 LA70100M Continued from preceding page. Parameter Symbol In Out Forced SECAM mode control voltage range Conditions Ratings min typ Unit max T27 = 3V VTHSM T1 T16 T12 T16 = 4.286MHz, 200mVp-p Measure voltage range of T1 when signal 4.0 4.2 VCC V 0 0.5 1.0 V 48 60 72 mA 90 120 150 mVp-p -1 0 1 dB -1 0 1 dB -3 0 3 dB -30 -20 dB -35 -25 dB 1.0608 1.0715 1.0822 80 100 120 mVp-p -6.5 -5.5 -4.5 dB -6.5 -5.5 -4.5 dB 4.243 4.286 4.329 MHz output from T12. Forced Except-SECAM mode control voltage range T27 = 4V VTHMM T1 T16 T12 T16 = 4.286MHz, 200mVp-p Measure voltage range of T1 when T12 is mute. Playback mode ( T2 = 4.43MHz, 400mVp-p T29 = Comp.Sync T17 = 5V, T10/T4 = OPEN ) PB mode current drain AGC characteristics-1 T23 ICCP T14 VAGC T14 T12 GAGC1 T14 T12 T14 = 1.0715MHz, 50mVp-p T24 AGC characteristics-2 T14 = 1.0715MHz, 50mVp-p T9=5V, T1=5V Voltage of T15 is V15R. Same condition as above. However, level of T14 is 100mVp-p Measure T14 ratio to VAGC AGC characteristics-3 GAGC2 T14 T12 GF1L T14 T12 1.1MHz BPF Characteristics-1 Same condition as above. However, level of T14 is 25mVp-p V15 = V15R ( see notes-4 ) T14 = 500kHz, 50mVp-p Measure T14 ratio to VAGC 1.1MHz BPF Characteristics-2 1.1MHz BPF Characteristics-3 GF1H1 T14 T12 GF1H2 T14 T12 1.1MHz BELL Center frequency Same condition as above. However, frequency of T14 is 2.2MHz Same condition as above. However, frequency of T14 is 3.3MHz T15 = V15R ( see notes-4 ) FEQP T14 T11 T14 = 1 to 1.2MHz, 50mVp-p ( see notes-5 ) SW11 = ON (3.9K pull-down) MHz Measure during other timing than V-sync 1.1MHz BELL Characteristics-1 VEQPC T14 T11 GEQPL T14 T11 1.1MHz BELL Characteristics-2 Same condition as above. However, frequency of T14 is 1.0715MHz Same condition as above. However, frequency of T14 is FEQP-62.5kHz Measure T14 ratio to VEQPC 1.1MHz BELL Characteristics-3 Same condition as above. However, GEQPH T14 T11 FBLP1 T18 T20 Anti-BELL Center frequency-2 FBLP2 T18 T20 Same condition as above. However, T10 = 0V 4.283 4.326 4.619 MHz Anti-BELL Center frequency-3 FBLP3 T18 T20 Same condition as above. However, T10 = 5V 4.323 4.366 4.659 MHz T20 T18 = 4.286MHz, 200mVp-p, BIAS = 4.6V 32 40 48 mVp-p 5.0 6.0 7.0 dB 5.0 6.0 7.0 dB 105 130 160 mVp-p -45 -35 dB -28 -20 dB Anti-BELL Center frequency-1 Anti-BELL characteristics-1 VBLPC T18 Anti-BELL characteristics-2 frequency of T14 is FEQP+62.5kHz ( see notes-6 ) T18 = 4 to 5MHz, 200mVp-p, BIAS = 4.6V Same condition as above. However, GBLPL T18 T20 frequency of T18 is FBLP1-250kHz Measure T18 ratio to VBLPC Anti-BELL characteristics-3 Same condition as above. However, GBLPH T18 T20 frequency of T18 is FBLP1+250kHz Measure T18 ratio to VBLPC PB Chroma signal output level T1 = 5 V, VOP T14 T18 GSP1 T14 T18 GSP2 T14 T18 Sync gate start time TPGB T14 T18 T1 = 5V, T9 = 5V ( see notes-9 ) 1.2 1.7 2.3 µs Sync gate release time TPGE T14 T18 T14 = 1.0715MHz, 50mVp-p 4.7 5.2 5.7 µs T25 T14 = 1.0625/1.1016MHz, 50mVp-p T26 ( see notes-14 ) 150 180 T25 T14 = 627kHz, 50mVp-p. (see notes-14) Chroma spurius spectrum-1 Chroma spurius spectrum-2 Phase Det output voltage-1 Phase Det output voltage-2 VSCPD1 T14 VSCPD2 T14 T26 T14 = 1.0715MHz, 50mVp-p Same condition as above. However,. measure 2.2MHz ratio to VOP at T18 Same condition as above. However,. measure 3.3MHz ratio to VOP at T18 mV 100 mV Continued on next page. No.7204-3/16 LA70100M Continued from preceding page. Parameter SECAM detection characteristics-1 SECAM detection characteristics-2 R/P control threshold voltage Symbol VSCMP1 VSCMP2 In Out V25 T28 V26 V25 T28 V26 VTRP T17 VCLK T2 Ratings Conditions min ( see notes-15 ) max 4.5 condition Unit V ( see notes-15 ) Minimum voltage of T16 under normal PB Clock input level typ 0.5 V 2.3 2.5 2.7 V 100 200 800 mVp-p 1.8 2.0 2.2 Vp-p 3.2 3.5 3.8 V T2 = Sign Wave (4.433619MHz), SW9 = ON T9 Minimum voltage of T9 at phase locked T2 with T8. Sync signal input threshold level SECAM DET comparator threshold voltage VTHS T29 T28 VTCOMP T27 T28 Minimum voltage of T29 at BGP outputs normally from T28. T9 = 5V Minimum applied voltage of T27 at T28 = H. Supplemental Description (Note 1) REC mode BELL center frequency (FBLR1, FBLR2, FBLR3) : Input a sine wave (200mVpp, 4 to 5MHz) to T16 and measure the amplitude at T20. Assign to FBLR1 (T10=OPEN), FBLR2 (T10=0V), FBLR3 (T10=5V) the frequency at T16 where the amplitude is maximized. SECAM standard color bar signal (75%) DB DR T16 4.40625MHz 214.5mVpp 4.25MHz 166.7mVpp 1.5µs T29 Fig.1 (Note 3) REC EQ (1.1MHz A-BELL) center frequency (FEQR) : Observe the waveform at T11 when T12=sine wave (200mVpp, 4 to 5MHz, BIAS=4V) is input and assign to FEQR the frequency at T11 where the amplitude is minimized. (Note 4) Assign to V15R the voltage of T15 at the time of VAGC measurement. (Note 5) PB EQ (1.1MHz BELL) center frequency (FEQP) : Input a sine wave (50mVpp, 1 to 1.2MHz) to T14 and assign to FEQP the frequency at T14 where the signal level of T11 is maximized. (Note 6) PB 4.3MHz A-BELL center frequency (1 FBLP1) / (2 FBLP2) / (3 FBLP3) : Input a sine wave (200mVpp, 1 to 1.2MHz, BIAS=4V)) to T18 and assign to FBQP1 (T10=OPEN), FBQP2 (T10=0V), FBEQP3 (T10=5V) the frequency at T18 where the signal level at T20 is minimized. No.7204-4/16 LA70100M (Note 7) REC mode sync gate start time, release time (TRGB, TRGE) : Input Copm. Sync to T29 and assume the sync gate start time (TRGB) as the time from which the signal at T12 attenuates until the signal at T29 rises and assume the sync gate release time (TRGE) as the time from which the horizontal sync signal rises till the signal at T12 increases (Fig. 2). 64µs T29 (C.SYNC) TRGB TRGE T12 Fig.2 REC mode sync gate timing (Note 9) PB mode sync gate start time, release time (TRGB, TPGE) : Input Comp.sync to T29 and assume the sync gate start time (TRGB) as the time from which the siganl at T18 attenuates until the horizontal sync signal rises and assume the sync gate release time (TPGE) as the time from which the horizontal sync signal rises until the signal at T18 starts increasing. 64µs T29 (C.SYNC) TPGB TPGE T18 (PB-OUT) Fig.3 PB mode sync gate timing (Note 10) BGP start time, BGP width (Fig. 4) T9=5V (TEST MODE) T29 (C.SYNC) TBGW TBGB T28 (BGP-OUT) 1V Fig.4 BGP timing No.7204-5/16 LA70100M VCC R28 (Note 11) Output impedance of SECAM DET (R28) Assign to V28 as when generating 100µA from pin 28 by adding 5V to pin 27 and take “H”, and calculate R28. R28= 28 5(V) - V28 100µA Fig.5 (Note 12) The sync signal at T29 must lag behind the SECAM color bar signal synchronization by 1.5µs (Fig. 1). (Note 13) The sync signal at T29 must lag behind the PAL color bar signal synchronization by 1.5µs (Fig. 6). PAL color bar signal 100% T16 1Vpp 1.5µs 4.433619MHz 21.5% T29 Fig.6 (Note 14) PB mode phase detection output differential voltage : VSAPD1 : Assign to VPD1 the DC voltage at T25 when a sine wave of 1.0625MHz is input to T14 and VPD2 the DC voltage at T26 when a sine wave of 1.1016MHz is input. VSCPD1=VPD2 - VPD1 VSAPD2 : Assign to VPD3 and VPD4 the voltage at T25 and T26, respectively, when a sine wave of 627kHz is input to T14. VSCPD2=VPD4 - VPD3 (Note 15) PB mode SECAM detection characteristics VSCMP1 / VSCMP2 : VSCMP1 : Apply the above-mentioned VPD1 and VPD2 to T25 and T26, respectively and measure the voltage at T28. VSCMP2 : Apply the above-mentioned VPD3 and VPD4 to T25 and T26, respectively and measure the voltage at T28. No.7204-6/16 LA70100M Functional Description (1) REC mode 4.3MHz BPF VIDEO SIGNAL INPUT 16 MONITOR OUTPUT MONITOR OUTPUT 20 11 4.3MHz BELL SYNC GATE 1/4 DIVIDER LIM 1.1MHz BPF 1.1MHz A-BELL REC MUTE 12 LOW CHROMA SIGNAL OUTPUT 19 1.107MHz 4.286MHz Fig.1 Signal flow in REC mode Video signals which have been input to Pin 16, pass through the 4.3MHz BPF with unnecessary component (ex. sync signal) removed, and the component of chroma signal is extracted. And the characteristics during transmission are made flat through a 4.3MHz-BELL filter. The center frequency of this filter has automatically been adjusted to be 4.286MHz. After that, the limiter amplifier limits the amplitude, and the chroma signal frequency is converted to 1/4 by a divide-by-four circuit. Though the limiter amplifier amplifies the noise of non-signal parts of the converted signal during synchronization, the sync gate circuit cleans the peripherals of the sync signal. Still more, since this signal has rectangle waveforms, it contains unnecessary component of frequency. To remove it, the signal passes through a 1.1MHz BPF and then is input to 1.1MHz-A-BELL filter. The center frequency of this filter is automatically adjusted to 1.0715MHz, and has opposite characteristics to BELL characteristics. Afterwards, unnecessary components around the sync signal are muted, low-band chroma signal is output to Pin 12 through a buffer. (2) PB mode MONITOR OUTPUT MONITOR OUTPUT 20 11 14 AGC 1.1MHz AMP BPF PB BELL LOW CHROMA SIGNAL INPUT 15 X2 2.2MHz BPF X2 2.2MHz TRAP 4.3MHz BPF LIM VM SYNC GATE 4.3MHz BPF 4.3MHz A-BELL PB MUTE 18 PB CHROMA SIGNAL OUTPUT 19 AGC DET 1.107MHz 4.286MHz Fig.2 Signal flow in PB mode The low chroma signal that has been input from Pin 14 enters AGC amplifier and is controlled so that the output level of 4 times multiplier be constant. Then it passes through the 1.1MHz BPF with unnecessary components removed before input to 1.1MHz-BELL filter. The center frequency of this filter has automatically been adjusted to be 1.0715MHz. Next, this signal passes through the 4 times multiplier composed of a 2× multiplier + 2.2 MHz BPF + 2× multiplier + 2.2MHz TRAP + 4.3MHz BPF with unnecessary component of frequency generated in multiplier removed. The first 2× multiplier has auto carrier leak balancer allowing beat obstruction reduced. Next, this signal is limited pulse amplitude by limiting amplifier, then noises around the sync signal owing to limited amplifier are cleaned by the sync gate circuit. This signal has a rectangle waveform and contains unnecessary components of frequency. To remove it, the signal passes through a 4.3MHz BPF before input to 4.3MHz-BELL filter. The center frequency of this filter is automatically adjusted to 4.286MHz, allowing the BELL characteristics to the state during transmission. Afterwards, unnecessary components around the sync signal are muted, low-band chroma signal is output to Pin 18 through a buffer. No.7204-7/16 LA70100M (3) CLK INPUT, AFC for BELL ADJUST CLOCK 2 BUFF AFC for EACH FILTER ADJUST 4.43MHz VCO 4.43MHz CLOCK 3 Fig.3 Input a frequency of 4.433619MHz sine wave or rectangle waveform signal of PAL fsc to CLK input terminal. This signal is used for automatically adjusting the BELL filter and generating timing pulse for AFC and for sync gate. AFC circuit automatically adjusts the frequency characteristics for each BPF. (4) SYNC GATE CIRCUIT 4.43MHz CLOCK Composite sync 29 SYNC SEPA C.SYNC V.SYNC CONTROL LOGIC SYNC GATE/MUTE SECAM DET SAMPLE HOLD-1, 2 BELL ADJUST SECAM DET SAMPLE HOLD-3 C.sync SYNC GATE MUTE C.sync V-MUTE BELL ADJUST GATE 700µs Fig.4 Vertical sync signal is extracted by a synchronous separate circuit from Composite Sync signal that has been input from Pin 29, and is conducted to BELL/A-BELL filter automatic adjusting circuit. Additionally, SYNC GATE pulse and sample hold pulse are generated by the logic circuit. (5) BGP generator circuit BGP is used for killer circuit in REC Mode, AGC circuit in PB Mode, and SECAM discrimination circuit. In BP Mode, AGC circuit detects the scale of the signal of BGP duration (ID) so that the output of 4 times multiplier circuit be constant. In SECAM discrimination circuit, BGP is used for making the S/H pulse (SP9, SP2 in Figure 9) mentioned later. Controlling Pin 4 can convert the timing for Composite Sync that is input to Pin 27. The width of BGP is determined by the constant of the inside of IC to about 2.5 µs. And BGP timing can be monitored by Pin 28 in test mode (Pin 9 voltage = 5V). No.7204-8/16 LA70100M (6) REC-BELL filter, PB-A-BELL filter 4.3MHz A-BELL FILTER CHARACTERISTICS 4.3MHz BELL FILTER CHARACTERISTICS It is an internal filter of which center frequency is fitted to 4.286MHz by automatic adjusting circuit (described later) that uses input frequency (fsc), thus prevents this filter from affected by external components. (7) REC-A-BELL filter, PB-BELL filter 1.1MHz A-BELL CHARACTERISTICS 1.1MHz BELL CHARACTERISTICS It is an internal filter of which center frequency is fitted to 1.0715MHz by automatic adjusting circuit (described later) that uses input frequency (fsc), thus prevents this filter from affected by external components. (8) BELL/A-BELL filter frequency automatic adjustment MODE CONTROL 4.43MHz CLOCK C.SYNC V.SYNC 4.286MHz PROGRAMABLE DIVIDER BELL/A-BELL COUNTER OSC DIFFERENCE CLOCK for COUNT UP GATE CLOCK for COUNT DOWN CONTROL ENABLE LOGIC CLOCK for COUNT DOWN GATE CLOCK for COUNT UP DIFFERENCE 1.0715MHz PROGRAMABLE BELL/A-BELL DIVIDER DIVIDER COUNTER OSC DIVIDER CONTROL VOLTAGE CONTROL D0 D1 D2 D3 D4 D5 UP/DOWN COUNTER UP/DOWN COUNTER D0 D1 D2 D3 D4 D5 VOLTAGE CONTROL CONTROL MODE CONTROL Fig.8 (a) No.7204-9/16 LA70100M C.sync VD 4.3MHz/1.1MHz OSC ENOSC 700µs ENABLE Fig.8 (b) During a period when the color signal processing is left untouched (for about 700 µs from the start of vertical sync signal), center frequency of BELL filter is automatically adjusted. MODE CONTROL sets each BELL/A-BELL filter into VCO mode after vertical sync signal is input, then the OSC oscillates at 4.3MHz or 1.1MNz. Oscillation output is divided respectively by a programmable divider and outputs the timing pulse that corresponds to oscillation frequency with control logic. This pulse is compared with the timing pules acquired by dividing 4.43MHz CLK and generates UP or DOWN CLK corresponding to the amount of discrepancies for oscillation frequency 4.286MHz/1.0715MHz. That is input to UP/DOWN counter to increase and decrease the counter value. When ENABLE pulse is generated the outputs D0 to D5 are rewritten, and the control voltage varies so that the oscillation frequency approach 4.286MHz/1.0715MHz. This operation repeats whenever the vertical sync signal is input and stops when the frequency difference becomes to a specified value ( ±43kHz / ±10.7kHz ). (9) SECAM + 27 DET S/H-3 21 + 25 S/H-1 SAMPLE HOLD PULSE S/H-1 28 SECAM DET OUT LOGIC COMP SENS CONTROL Vref 30 CTL S/H-3 PHASE DET 90 DEG 4.3MHz BPF LIM S/H-2 SAMPLE HOLD PULSE BELL ADJUST PULSE 26 from MAIN SIGNAL LINE S/H-2 Fig.9(a) Chroma signal SP1 Voltage V2 128µs VL SP2 SP3 V1 Same as ESOSC at fig.8 (b) V1 VS1 V2 VS2 Fig.9 (b) 4.25MHz (4.28MHz) 4.40625MHz Frequency Fig.9 (c) The color signal with the amplitude limited by limiting circuit varies the phase according to the signal frequency after it passes through a 4.3MHz BPF. DC voltage according to the phase can be acquired by shifting this output phase by further 90° and inputting it to a phase detector with the original signal. The characteristic of the output of a phase detector is as shown in the figure 9 (b), as the voltage limiting circuit operates at S/H-3 in order to prevent the malfunction caused by unwanted signals. This limiting circuit voltage is the phase detector output DC voltage to which the signals of 4.286MHz VCO is input used on BELL filter automatic adjusting circuit. Then it is possible to operate the limiting circuit exactly at a frequency more than 4.286 MHz and to prevent the false discrimination during MESECAM signal input. After that, input to two sample & hold circuits, the sampling pulse is shown like pulses correspond to BGP of NTSC and PAL generated every 1H as SP1 and SP2 in figure 9 (b). The SECAM color signal has ID signals of 4.25MHz and 4.40625MHz generated every 1H on the part that corresponds to this BGP, each phase detection output causes the level difference as V1, V2 in figure 9 (b). When this difference is sampled by SP1 and SP2 the waveform becomes as VS1 and VS2 in the figure 9 (b), and when it is hold by external capacitor it becomes as V1 and V2. Input to a comparator after detecting the difference of these two voltages, smoothing it to stable with the external capacitor connected to Pin 27. In addition, applying more than 1V DC voltage to Pin 30 allows the amplification of the level difference to be varied. When the smooth value of V1-V2 exceeds 3.5V, SECAM signal is detected with a high-level output from the Pin 28. This discrimination circuit uses a rule that the output of a phase detector differs every 1H as shown in the figure 9 (b) (c) to detect a SECAM signal. PAL signal always outputs high since its burst is constant and doesn’t vary phase detection output. No.7204-10/16 LA70100M MODE control [ Output mute control ] Forcibly applying a DC voltage to pin-1 allows REC-OUT and PB-OUT muting control. pin-1 voltage output mode ( pin-12, pin-18 ) Forced SECAM 5V AUTO ( internal detect ) SECAM : Active OPEN Except SECAM : mute Forced mute 0V [ TEST mode control ] pin use monitor output use monitor input ⎯ pin-11 1.1MHz BELL/A-BELL (11 to GND:3.9k) pin-12 1.1MHz BPF (pin-9 : 5V) 1.1MHz BELL/A-BELL input (4V BIAS+SIG) pin-18 4.3MHz BPF (pin-9 : 5V) 4.3MHz BELL/A-BELL input (4V BIAS+SIG) pin-20 4.3MHz BELL/A-BELL (20 to GND:3.9k) ⎯ pin-28 BGP out (pin-9 : 5V) ⎯ [ BGP position control ] [ 4.3M BELL offset control* ] pin-4 add voltage BGP position pin-10 add voltage offset frequency L (0V) -400ns L (0V) +40kHz OPEN (2.5V) ±0ns OPEN (2.5V) ±0kHz H (5V) +400ns H (5V) +80kHz *Active only in PB mode [ REC / PB mode control ] pin-17 add voltage mode L (0V) REC mode H (5V) PB mode Block diagram / application 20 19 to MUTE to SYNC GATE to PB AGC to REC KILLER 1.1MHz BFP BELL 1.1MHz BELL PB ANTI BELL 11 12 BGP DELAY CTL H:+400n M:0n L:-400n 4.3MHz BELL FO CTL H:+80k M: 0k L: +40k * PB ONLY REC MUT REC-C OUT 1/4 PB 2.2MH z ANTI BELL REC Buffer 4.3MHz BELL FO CTL FO CTL 9 10 LIM PB REC SYNC GATE 4.3MHz BFP REG 4.0V 13 AGC AMP 14 AGC DET 15 + 0.47µF 8 TEST MODE VCO MONIT 7 GND 6 + GND2 BAL 5 X2 2.2MHz TRAP 1µF 4 2.2MHz BFP AGC FILTER CHROMA 1.1MHz No Connect AFC FILTER BGP DELAY 1kΩ + 1µF MODE CTL H:SECAM 4.43MHz M:AUTO DET L:EXCEPT SECAM CW 3 SYNC GATE 0.01µF PB-IN X2 Filter Adj. 0.01µF CLK IN 0.01µF MODE 2 PB REC 4.43MHz VCO 1 REC 4.3MHz BFP CONTROL LOGIC AFC PB-H ANTI BELL 2.2MHz TRAP PB REG to MUTE Buffer 4.3MHz BELL ANTI BELL BELL MONIT1 MODE CTL BELL REC 0.1µF BGP GEN REC / PB PB MUTE REC-OUT SYNC GATE GEN / V-SEP 18 Buffer SECAM DET REC IN REC : 0V PB : 5V 16 17 0.01µF + 21 PB-OUT 22 LIM EXC 23 S/H C3 24 BELL MONIT4 0.47µF 0.01µF PB OUT RP CTL REC-IN VCC 5V No Connect 2200pF 25 VCC2 2200pF 26 S/H C1 + 27 S/H C2 28 DET C 29 SECAMDET OUT 30 SYNC-IN SECAM DET SENS 2.2µF VCC 5V VCC C.SYNC IN SECAM HI PB-C IN No.7204-11/16 LA70100M Pin Description Pin Name DC voltage Signal waveform 1 MODE CTL 2.5V DC Input/output form Note VCC 10kΩ 100kΩ 1 100kΩ Pin No. 2 CLK IN 2.5V VCC 4.43MHz, 400mVp-p 2 500Ω 5kΩ 20kΩ AFC FILTER 3.5V 4.0V DC VCC 1kΩ 20kΩ 3 200Ω 1 to 5V VCC DC 4 5 6 2kΩ 50kΩ 50kΩ BGP DELAY 200Ω 60kΩ 7kΩ 4 3 No Connect BAL 1.2V VCC DC 2kΩ ( Balancer ) 500Ω 2kΩ 6 0V 0V TEST MODE 2.1V VCC Normal : DC ( VCO MONITOR ) VCO monitor : CW Normal : open VCO monitor : insert resistor to GND (4.43MHz, 450mVp-p) 20kΩ GND 9 1kΩ 9 TEST mode ON : pull-up to VCC 30kΩ 8 200Ω GND2 200Ω 7 Continued on next page. No.7204-12/16 LA70100M Continued from preceding page. Pin No. Pin Name DC voltage Signal waveform 10 F0 CTL 2.5V DC Input/output form 100kΩ (4.3MHz BELL OFFSET) 10 11 BELL MONIT 1 Note VCC 2.7V 100kΩ 10kΩ VCC Normal : DC Normal : open 500Ω (1.1MHz BELL MONIT) BELL monitor : CW BELL monitor : insert resistor to GND 500Ω (1.1MHz, 300mVp-p) 11 REC OUT REC : 2.2V ( TEST SIG I/O ) PB : GND VCC 1.1MHz, 700mVp-p TEST input : signal with 4V bias 200Ω 12 12 1kΩ 20kΩ 100Ω 13 REG 4.0V VCC DC 13 14 PB IN 2.5V 1.1MHz, 50mVp-p VCC 14 1kΩ 2kΩ 10kΩ AGC FILTER VCC/2 ±VBE VCC DC 15 8kΩ 3kΩ 2kΩ 25kΩ 2kΩ 15 2.5V Composite VIDEO VCC 1.0Vp-p 1kΩ 10kΩ 1kΩ REC IN 16 8kΩ 16 Continued on next page. No.7204-13/16 LA70100M Continued from preceding page. Pin No. Pin Name DC voltage Signal waveform 17 R/P CTL 0 to VCC DC Input/output form 1kΩ 17 PB OUT PB : 1.95V ( TEST SIG I/O ) REC : GND VCC TEST input : signal with 4V bias 200Ω 18 4.3MHz, 400mVp-p Note VTH = VCC/2 VCC 18 1kΩ 20kΩ 100Ω 19 LIM EXC 2.3V VCC DC 1kΩ 20kΩ 19 10pF BELL MONIT 4 2.7V VCC Normal : DC (4.3MHz BELL MONIT) BELL monitor : CW Normal : open 500Ω 20 BELL monitor : insert resistor to GND 500Ω (4.3MHz, 400mVp-p) 20 21 S/H C3 2.5V DC VCC 10kΩ (when connecting capacitor) 1kΩ 2kΩ 21 22 No Connect 23 VCC 5V 24 VCC2 5V DC 25 S/H C1 2.5V DC DC VCC 10kΩ (when connecting capacitor) 1kΩ 2kΩ 25 Continued on next page. No.7204-14/16 LA70100M Continued from preceding page. Pin No. Pin Name DC voltage Signal waveform 26 S/H C2 2.5V DC Input/output form Note VCC 10kΩ (when connecting capacitor) 1kΩ 2kΩ 26 2 to 5V VCC DC 30kΩ DET C 30kΩ 1kΩ 27 2kΩ SECAM DET OUT 0V/5V DC (0V or 5V) Normal mode VCC 10kΩ 28 20kΩ 1kΩ 27 (BGP MONITOR ) 28 BGP pulse At TEST mode 5V 0V SYNC IN Threshold voltage VCC 30kΩ 2.0V Composite sync 29 2.0V DC VCC 30kΩ SECAM DET SENS 30 1kΩ 20kΩ 30 2kΩ 50kΩ 29 No.7204-15/16 LA70100M Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 2002. Specifications and information herein are subject to change without notice. PS No.7204-16/16