SANYO LA76850

Ordering number : ENA0017
Monolithic Linear IC
LA76850
Black & White Television IC
Overview
LA76850 is a Black & White Television IC.
Functions
• I2C Bus Control VIF/SIF/Y/Deflection/Implemented in a Single Chip
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Maximum supply current
Allowable power dissipation
Symbol
Conditions
Ratings
Unit
V8 max
7.0
V
V27 max
7.0
V
I16 max
14
V
I20 max
35
V
1.1
mW
Pd max
Ta ≤ 65°C *
Operating temperature
Topg
-10 to +65
°C
Storage temperature
Tstg
-55 to +150
°C
* Provided with a glass epoxy board (114.3×76.1×1.6 mm)
Operating Conditions at Ta = 25°C
Parameter
Recommended supply voltage
Recommended supply current
Operating supply voltage range
Operating supply current range
Symbol
Conditions
Ratings
Unit
V8
5.0
V
V27
5.0
I16
9
mA
I20
29
mA
V
V8 op
4.7 to 5.3
V27 op
4.7 to 5.3
V
I16 op
7 to 11
mA
I20 op
24 to 33
mA
V
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
N2206 / N1105 MS OT B8-7024 No.A0017-1/31
LA76850
Electrical Characteristics Ta = 25°C, VCCL = V8 = V27 = 5.0V, ICC = I16 = 9mA, ICC = I20 = 27mA
Parameter
Symbol
Conditions
min
typ
max
unit
[Circuit voltage, current]
IF supply current
I8
V8 = 5V, V3 = 2.5V
67
mA
RGB supply voltage
V16
I16 = 9mA
8.0
V
Horizontal supply voltage
V20
I25 = 27mA
5.0
V
Video supply current
I27
I27 = 5V
65
mA
8.5
9
Vdc
0
0.3
[VIF block]
Maximum RFAGC voltage
VRFH
CW = 80dBµ, DAC = 0
Minimum RFAGC voltage
VRFL
CW = 80dBµ, DAC = 63
0.7
90
Vdc
RF AGC Delay Pt (@DAC = 0)
RFAGC0
DAC = 0
dBµ
RF AGC Delay Pt
RFAGC63
DAC = 63
80
dBµ
Output-3dB
46
dBµ
(@DAC = 63)
Input sensitivity
Vi
No-signal video output voltage
VOn
No signal
3.4
3.7
4.0
Vdc
Sync signal tip level
VOtip
CW = 80dBµ
1.1
1.4
1.7
Vdc
1.57
2.05
2.52
Vp-p
45
Video output amplitude
VO
80dBµ, AM = 78%, fm = 15kHz
Video S/N
S/N
CW = 80dBµ
40
C-S beat level
IC-S
V4.43MHz/V1.07MHz
35
Differential gain
DG
80dBµ, 87.5% Video MOD
5.0
10.0
%
Differential phase
DP
80dBµ, 87.5% Video MOD
1.0
10.0
deg
dB
dB
Maximum AFT output voltage
VAFTH
CW = 80dBµ, frequency variations
4.3
4.7
5
Vdc
Minimum AFT output voltage
VAFTL
CW = 80dBµ, frequency variations
0.0
0.3
0.7
Vdc
AFT detection sensitivity
VAFTS
CW = 80dBµ, frequency variations
8.0
15.0
22.0
mV/kHz
APC pull-in range (U)
fPU
1.5
MHz
APC pull-in range (L)
fPL
1.5
MHz
NT Trap1 (4.5MHz)
NTR1
-30
dB
NT Trap1 (4.8MHz)
NTR2
-20
dB
BG Trap1 (5.5MHz)
BTR1
-30
dB
BG Trap2 (5.85MHz)
BTR2
-20
dB
I Trap1 (6.0MHz)
ITR1
-30
dB
I Trap1(6.55MHz)
ITR2
-17
dB
DK Trap1(6.5MHz)
DTR1
-30
dB
[SIF block]
FM detection output voltage
FM limiting sensitivity
FM detection output
SOADJ
FM = ±30kHz
SLS
Output -3dB
SF
fm = 100kHz
245
310
390
mVrms
53
dBµ
-0.5
5.0
8.0
dB
f characteristics
FM detection output distortion
STHD
FM = ±30kHz
AM rejection ratio
SAMR
AM = 30%
40
dB
SSN
DIN.Andio
51.5
dB
SIF S/N
1.0
%
PAL de-emph time constant
SPTC
2.4
3.0
3.6
dB
PAL/NT Difference of voltage
SGD
-1.5
0.0
+1.5
dB
SNTC
1.9
2.5
3.1
dB
gain
NT de-emph time constant
Continued on next page.
No.A0017-2/31
LA76850
Continued from preceding page.
Parameter
Symbol
Conditions
min
typ
max
unit
[AUDIO block]
Maximum gain
AGMAX
Variable range
ARANGE
Frequency characteristics
Mute
AF
AMUTE
Distortion
ATHD
1kHz500mVrms
-2.0
0.5
60
74
20kHz
-3.0
0.0
20kHz
70
+3.0
3.0
0.5
ASN
DIN. Audio
65
Crosstalk
ACT
1kHz
70
dB
dB
1kHz, 500mVrms, Vol: MAX
S/N
dB
dB
73
%
dB
dB
[Video block]
Video signal input 1DC voltage
VIN1DC
Video signal input 1AC voltage
VIN1AC
Video overall gain
2.2
2.5
2.8
1
V
Vp-p
CONT127
12.0
14.0
16.0
dB
CONT63
-6.5
-5.0
-3.5
dB
CONT0
-18.0
-15.0
-12.0
dB
-6.0
-3.0
0.0
dB
-6.0
-3.0
0.0
dB
CtrapP
-36.0
-26.0
-22.0
dB
CtrapN
-36.0
-26.0
-22.0
dB
ClampG1
95.0
100.0
105.0
%
5.0
8.0
11.0
dB
dB
(Contrast max)
Contrast adjustment
characteristics
(Normal/max)
Contrast adjustment
characteristics
(Min/max)
Video frequency
BW1
Characteristics 1 NTSC
Video frequency
BW2
characteristics 2 PAL
Chroma trap amount PAL
Chroma trap amount NTSC
DC transmission amount
1.8MHz/100kHz
Filter sys = 0000
2.2MHz/100kHz
Filter sys = 0010
Sharpness variability range
Sharp32T2
F = 2.7MHz, FILTER SYS = 0010
(trap 2 mid)
Sharp63T2
F = 2.7MHz, FILTER SYS = 0010
8.5
11.5
13.5
Sharp0T2
F = 2.7MHz, FILTER SYS = 0010
-6.5
-3.5
-0.5
dB
Sharp63T5
F = 3.0MHz, FILTER SYS = 0000
8.5
11.5
13.5
dB
Sharp0T5
F = 3.0MHz, FILTER SYS = 0000
-6.5
-3.5
-0.5
dB
(trap 2 max)
(trap 2 min)
Y APF = 1
Y APF = 1
Y gamma effective point 1
YG1
YGAMMA = 01
89.0
93.0
97.0
%
Y gamma effective point 2
YG2
YGAMMA = 10
85.0
89.0
93.0
%
Y gamma effective point 3
YG3
YGAMMA = 11
80.0
84.0
88.0
%
Horizontal/vertical blanking
RGBBLK
0.1
0.4
0.7
V
OSD Fast SW threshold
FSTH
0.7
0.9
1.1
V
OSD output level
OSDH
140
175
210
IRE
BRT63
2.3
2.8
3.3
V
BRT63H
3.0
3.3
3.6
V
output level
[OSD block]
Digital osd = 1
Osd cont = 63
[RGB output (cutoff drive) block]
Brightness control (Normal)
Brightness control (Normal-H)
Hi brightness (max)
Low brightness (min)
BRT127
20
25
30
IRE
BRT0
-30
-25
-20
IRE
Bright control Resolution
Vbiassns
16
mV
Sub-bias control Resolution
Vsbiassns
7
mV
/Bit
/Bit
Continued on next page.
No.A0017-3/31
LA76850
Continued from preceding page.
Parameter
Symbol
Conditions
min
typ
max
unit
FH
15500
15670
15900
Hz
fH PULL
±400
Horizontal output pulse width
Hduty
36.1
37.6
39.1
µs
Horizontal output pulse
V Hsat
0
0.2
0.4
V
Vertical free-running cycle 50
VFR50
312.0
312.5
313.0
H
Vertical free-running cycle 60
VFR60
262.0
262.5
263.0
H
Horizontal output pulse phase
HPHCENpal
9.5
10.5
11.5
µs
Horizontal output pulse phase
HPHCENnt
9.5
10.5
11.5
µs
Horizontal position
HPHrange
[Deflection block]
Horizontal free-running
frequency
Horizontal pull-in range
Hz
saturation voltage
±2.4
5bit
µs
adjustment range
Horizontal position adjustment
HPHstep
350.0
ns
maximum variability width
Horizontal blanking left @0
BLKL0
BLKL:000
7500
8300
9100
ns
Horizontal blanking left @7
BLKL7
BLKL:111
10800
11600
12400
ns
Horizontal blanking right @0
BLKR0
BLKR:000
1800
2600
3400
ns
Horizontal blanking right @7
BLKR7
BLKR:111
-1100
-300
500
ns
Sand castle pulse crest value H
SANDH
5.3
5.6
5.9
V
Sand castle pulse crest value M1
SANDM1
3.7
4.0
4.3
V
Sand castle pulse crest value M2
SANDM2
1.7
2.0
2.3
V
Sand castle pulse crest value L
SANDL
0.1
0.4
0.7
V
Burst gate pulse width
BGPWD
2.5
3.0
3.5
µs
Burst gate pulse phase
BGPPH
4.9
5.4
5.9
µs
Hstop
3.30
3.60
3.90
V
Horizontal output stop voltage
<Vertical screen size adjustment>
Vertical ramp output amplitude
Vspal64
VSIZE: 1000000
0.85
0.95
1.05
Vp-p
Vsnt64
VSIZE: 1000000
0.85
0.95
1.05
Vp-p
Vspal0
VSIZE: 0000000
0.41
0.51
0.61
Vp-p
vsnt0
VSIZE: 0000000
0.41
0.51
0.61
Vp-p
Vspal127
VSIZE: 1111111
1.15
1.30
1.45
Vp-p
Vspal127
VSIZE: 1111111
1.15
1.30
1.45
Vp-p
PAL@64
Vertical ramp output amplitude
NTSC@64
Vertical ramp output amplitude
PAL@0
Vertical ramp output amplitude
NTSC@0
Vertical ramp output amplitude
PAL@127
Vertical ramp output amplitude
NTSC@127
Continued on next page.
No.A0017-4/31
LA76850
Continued from preceding page.
Parameter
Symbol
Conditions
min
typ
max
unit
<High-voltage dependent vertical size correction>
Vertical size correction @0
Vsizecomp
VCOMP: 000
0.89
0.93
0.97
ratio
Vdcpal32
VDC: 100000
2.25
2.40
2.55
Vdc
Vdcnt32
VDC: 100000
2.25
2.40
2.55
Vdc
Vdcpal0
VDC: 000000
1.85
2.00
2.15
Vdc
Vdcpal0
VDC: 000000
1.85
2.00
2.15
Vdc
Vdcpal63
VDC: 111111
2.65
2.80
2.95
Vdc
Vdcpal63
VDC:111111
2.65
2.80
2.95
Vdc
Vertical linearity @16
Vlin16
VLIN: 10000
0.85
1.00
1.15
ratio
Vertical linearity @0
Vlin0
VLIN: 00000
1.17
1.32
1.47
ratio
Vertical linearity @31
Vlin31
VLIN: 11111
0.57
0.72
0.87
ratio
Vertical S-shaped correction @16
Vscor16
VSC: 10000
0.75
0.90
1.05
ratio
Vertical S-shaped correction @0
Vscor0
VSC: 00000
1.08
1.23
1.38
ratio
Vertical S-shaped correction @31
Vscor31
VSC: 11111
0.49
0.64
0.79
ratio
<Vertical screen position adjustment>
Vertical ramp DC voltage
PAL@32
Vertical ramp DC voltage
NTSC@32
Vertical ramp DC voltage
PAL@0
Vertical ramp DC voltage
NTSC@0
Vertical ramp DC voltage
PAL@63
Vertical ramp DC voltage
NTSC@63
Package Dimensions
unit : mm
3170A
No.A0017-5/31
LA76850
Application Circuit Example
No.A0017-6/31
LA76850
Test Conditions Ta = 25°C, VCC = V8 = V31 = V43 = 5.0V, l18 = 19mA, ICC = l25 = 27mA
Parameter
Symbol
Test point
Input signal
Test method
Bus conditions
[Circuit voltage, current]
RGB supply voltage (pin 20)
V20
No signal
20
RGB supply voltage (pin 16)
IF supply current (pin 8)
V16
I8
(CDDICC)
Apply a current of 27mA to pin 20 and
Initial
measure the voltage at pin 20.
No signal
16
Apply a current of 19mA to pin 16 and
Initial
measure the voltage at pin 16.
No signal
Apply a voltage of 5.0V to pin 8 and measure
Initial
the incoming DC current (mA).
8
(IF AGC 2.5V applied)
Video/vertical supply current
(pin 27)
I27
(DEFICC)
No signal
27
Apply a voltage of 5.0V to pin 27 and
Initial
measure the incoming DC current (mA).
NoA0017-7/31
LA76850
VIF Block Input Signals
1. Input signals must all be input to the PIF IN (pin 6) in the Test Circuit.
2. All input signal voltage values are the levels at the VIF IN (pin 6) in the Test Circuit.
3. Signal contents and signal levels
4. Bus conditions: VIF SYS = "01", S.TRAP.SW = "1", OVER.MOD.SW = "0"
Input signal
Waveform
Conditions
SG1
38.9MHz
CW
34.47MHz
SG2
CW
SG3
33.4MHz
CW
SG4
Frequency variable
CW
SG5
38.9MHz
87.5% Video Mod.
10-stairstep wave
(Subcarrier: 4.43MHz)
SG6
38.9MHz
fm = 15kHz, AM = 78%
SG7
38.9MHz, 80dBµ
50IRE
87.5% Video Mod.
50IRE Luma
(Carrier: variable)
50IRE Luma
NoA0017-8/31
LA76850
VIF Block Test Conditions
Input signal
Maximum RF AGC
Symbol
VRFH
Test point
4
voltage
Minimum RF AGC
RFAGC0
RFAGC63
(@DAC = 63)
Input sensitivity
Bus conditions
RF.AGC = "000000"
4
SG1
Measure the DC voltage at pin 4.
RF.AGC = "111111"
Obtain the input level at which the DC voltage at
RF.AGC = "000000"
80dBµ
(@DAC = 0)
RF AGC Delay Pt
Test method
Measure the DC voltage at pin 4.
80dBµ
VRFL
voltage
RF AGC Delay Pt
Input signal
SG1
Vi
4
4
29
SG1
pin 4 becomes 4.5V.
SG1
Obtain the input level at which the DC voltage at
RF.AGC = "111111"
pin 4 becomes 4.5V.
SG6
Using an oscilloscope, observe the level at pin 29
and obtain the input level at which the waveform's
p-p value becomes 1.4Vp-p.
No-signal
VOn
video output
29
No signal
Set IF AGC = “1” and measure the DC voltage at
pin 29.
voltage
Sync signal tip
VOtip
29
level
Video output
Measure the DC voltage at pin 29.
80dBµ
VO
29
amplitude
Video S/N
SG1
S/N
29
SG6
Using an oscilloscope, observe the level at pin 29
80dBµ
and measure the waveform’s p-p value.
SG1
Measure the noise voltage (Vsn) at pin 29 with an
80dBµ
RMS voltmeter through a 10kHz to 5.0MHz
band-pass filter and calculate 20 log (1.43/Vsn).
C-S beat level
IC-S
29
SG1
Input a 80dBµ SG1 signal and measure the DC
SG2
voltage (V3) at pin 3. Mix SG1 = 74dBµ, SG2 = 64
SG3
dBµ, and SG3 = 64 dBµ to enter the mixture in the
VIF IN. Apply V3 to pin 3 from an external DC
power supply. Using a spectrum analyzer,
measure the difference between pin 29’s 4.43MHz
component and 1.07MHz component.
Differential gain
DG
29
SG5
Using a vector scope, measure the level at Pin 29.
80dBµ
Differential phase
Maximum AFT
DP
VAFTH
output voltage
29
10
SG5
Using a vector scope, measure the level at Pin 29.
80dBµ
SG4
Set and input the SG4 frequency to 37.9MHz to be
80dBµ
input. Measure the DC voltage at pin 10 at that
moment.
Minimum AFT
VAFTL
output voltage
10
SG4
Set and input the SG4 frequency to 39.9MHz to be
80dBµz
input. Measure the DC voltage at pin 10 at that
SG4
Adjust the SG4 frequency and measure
80dBµz
frequency deviation ∆f when the DC voltage at pin
moment.
AFT detection
sensitivity
VAFTS
10
10 changes from 1.5V to 3.5V.
VAFTS = 2000/∆f [mV/kHz]
Continued on next page.
NoA0017-9/31
LA76850
Continued from preceding page.
Input signal
APC pull-in
Symbol
fPU, fPL
Test point
29
range (U), (L)
Input signal
Test method
SG4
Connect an oscilloscope to pin 29 and adjust the
80dBµ
SG4 frequency to a frequency higher than
Bus conditions
38.9MHz to bring the PLL into unlocked mode.
(A beat signal appears.) Lower the SG4 frequency
and measure the frequency at which the PLL locks
again. In the same manner, adjust the SG4
frequency to a lower frequency to bring the PLL
into unlocked mode. Higher the SG4 frequency
and measure the frequency at which the PLL locks
again.
NT Trap1 (4.5MHz),
NTR1
2 (4.8MHz)
NTR2
BG Trap1 (5.5MHz),
BTR1
2 (5.85MHz)
BTR2
I Trap1 (6.0MHz)
ITR1
2 (6.55MHz)
ITR2
DK Trap1 (6.5MHz)
DTR1
29
SG7
Determine the output level difference between
SIF.SYS = "00"
carrier frequencies of 1Mhz, 4.5MHz and 4.8MHz.
(Reference:1MHz)
29
SG7
Determine the output level difference between
SIF.SYS = "01"
carrier frequencies of 1Mhz, 5.5MHz and
5.85MHz. (Reference:1MHz)
SG7
29
Determine the output level difference between
SIF.SYS = "10"
carrier frequencies of 1MHz, 6.0MHz and
6.55MHz. (Reference:1MHz)
SG7
29
Determine the output level difference between
SIF.SYS = "11"
carrier frequencies of 1MHz and 6.5MHz.
(Reference:1MHz)
NoA0017-10/31
LA76850
SIF Block (FM block) Input Signals and Test Conditions
Unless otherwise specified, the following conditions apply when each measurement is made.
1. Bus control condition:
IF.AGC.SW = "1", SIF.SYS = "01", DEEM-TC = "0", FM.GAIN = "0", A.MONI.SW = "0", A2.SW = "0"
2. SW:IF1 = "ON", 24pin = 5V
3. Input signals are input to pin 54 and the carrier frequency is 5.5MHz.
Input signal
FM detection
Symbol
SOADJ
output voltage
Test point
2
Input signal
Test method
90dBµ,
Measure the 400 Hz component (SV1: mVrms) of
fm = 400Hz,
the FM detection output at pin 2.
Bus conditions
FM =
±30kHz
FM limiting
SLS
sensitivity
FM detection
SF
output f characteristics
2
2
(fm=100kHz)
FM detection output
STHD
distortion
2
fm = 400Hz,
Measure the input level (dBµ) at which the 400Hz
FM =
component of the FM detection output at pin 2
±30kHz
becomes -3dB relative to SV1.
90dBµ,
Set SW: IF1 = "OFF".
fm = 100kHz
Measure (SV2: mVrms) the FM detection output of
FM =
pin 2. Calculate as follows:
±30kHz
SF = 20*LOG (SV1/SV2) [dB]
90dBµ,
Measure the distortion factor of the 400Hz
fm = 400Hz,
component of the FM detection output at pin 2.
FM =
±30kHz
AM rejection
SAMR
ratio
2
90dBµ,
Measure the 400Hz component (SV3: mVrms) of
fm = 400Hz,
the FM detection output at pin 2.
AM = 30%
Assign the measured value to SV3 and
calculate as follows:
SAMR = 20*log (SV1/SV3) [dB]
SIF.S/N
SSN
2
90dBµ,
Measure the noise level (DIN AUDIO, SV4:
CW
mVrms) at pin 2. Calculate as follows:
SSN=20*log(SV1/SV4) [dB]
PAL de-emph time
SPTC
constant
2
90dBµ,
Measure the 3.18kHz component (SV5: mVrms) of
fm =
the FM detection output at pin 2 and calculate as
3.18KHz
follows:
FM =
SNTC = 20*LOG (SV1/SV5) [dB]
±30KHz
PAL/NT
SGD
Difference of voltage
2
gain
fo = 4.5MHz
Measure the 400Hz component (SV6: mVrms) of
SIF.SYS = "00"
90dBµ,
the FM detection output at pin 2 and calculate as
DEEM-TC = "1"
fm = 400Hz
follows:
FM.GAIN = "1"
FM =
SNTC = 20*LOG (SV1/SV6) [dB]
±15KHz
NT de-emph
time constant
SNTC
2
fo = 4.5MHz
Measure the 2.12kHz component (SV7: mVrms) of
SIF.SYS = "00"
90dBµ,
the FM detection output at pin 2 and calculate as
DEEM-TC = "1"
fm =
follows:
FM.GAIN = "1"
2.12kHz
SNTC = 20*LOG (SV6/SV7) [dB]
FM =
±15kHz
NoA0017-11/31
LA76850
Audio Block Input Signals and Test Conditions
Unless otherwise specified, the following conditions apply when each measurement is made.
1. Bus control condition:
AUDIO.MUTE = "0", A.MONI.SW = "0", AUDIO.SW = "1", VOL.FIL = "0", SIF.SYS = "01", IF.AGC.SW = "1"
2. Input 5.5MHz, 90dBµ and CW at pin 54.
3. Enter an input signal from pin 51.
Input signal
Maximum gain
Symbol
AGMAX
Test point
1
Input signal
Test method
Bus conditions
1kHz, CW
Measure the 1kHz component (V1: mVrms) at
VOLUME =
500mVrms
the pin 1 and calculate as follows:
"1111111"
AGMAX = 20*LOG(V1/500) [dB]
Variable range
ARANGE
1
1kHz, CW
Measure the 1kHz component (V2: mVrms) at
VOLUME =
500mVrms
the pin 1 and calculate as follows:
"0000000"
ARANGE = 20*LOG(V1/V2) [dB]
Frequency
AF
characteristics
1
20kHz, CW
Measure the 20kHz component (V3: mVrms) at
VOLUME =
500mVrms
the pin 1 and calculate as follows:
"1111111"
AF = 20*Log(V3/V1) [dB]
Mute
Distortion
S/N
AMUTE
ATHD
ASN
1
1
1
20kHz, CW
Measure the 20kHz component (V4: mVrms) at
VOLUME =
500mVrms
the pin 1 and calculate as follows:
"1111111"
AMUTE = 20*Log(V3/V4) [dB]
AUDIO.MUTE = ”1”
1kHz, CW
Measure the distortion of the 1kHz component at
VOLUME =
500mVrms
the pin 1.
"1111111"
No signal
Measure the noise level (DIN AUDIO, V5: mVrms)
VOLUME =
at the pin 1 and calculate as follows:
"1111111"
ASN = 20*log(V1/V5) [dB]
Crosstalk
ACT
1
1kHz, CW
Measure the 1kHz component (V6: mVrms) at
VOLUME =
500mVrms
the pin 1 and calculate as follows:
"1111111"
ACT = 20*LOG(V1/V6) [dB]
AUDIO.SW = "0"
NoA0017-12/31
LA76850
Video Block Input Signals
Y IN inpt signal 100IRE: 714mV
Bus control bit conditions: Initial test state
0IRE signal (L-0): NTSC standard sync signal
PEDESTAL LEVEL
H SYNC
4.7µs
(H/V SYNC:40IRE: 286mV)
XIRE signal (L-X)
XIRE (X = 0 to 100)
0IRE
CW signal (L-CW)
20IRE CW signal
50IRE
BLACK STRETCH 0IRE signal (L-BK)
50µs
100IRE
5µs
(Point A)
OSD IN Input signal
OSD Input signal 1 (0-1)
to each 20µs
0.35V
A B
0.7V
0.0VDC
OSD Input signal 2 (0-2)
20µs
30µs
1.0VDC
0.0VDC
NoA0017-13/31
LA76850
Video Block Test Conditions
Input signal
Symbol
Video signal input
VIN1DC
1DC voltage
Video signal input
VIN1AC
1 AC voltage
Video overall gain
Test point
Input signal
L-100
28
Bus conditions
VIDEO SW:1
the pedestal.
Pin 28 recommended input level
28
CONT127
L-50
17
(Contrast max)
Test method
Input signals to pin 28 and measure the voltage of
Measure the output signal’s 50IRE amplitude
CONTRAST:
(CNTHB Vp-p) and calculate
1111111
CONT127 = 20log (CNTHB/0.357).
Contrast
CONT63
L-50
17
adjustment
Measure the output signal’s 50IRE amplitude
CONTRAST:
(CNTCB Vp-p) and calculate
0111111
CONT63 = 20log (CNTCB/0.357).
characteristics
(normal/max)
Contrast
CONT0
L-50
17
adjustment
characteristics
Measure the output signal’s 50IRE amplitude
CONTRAST:
(CNTLB Vp-p) and calculate
0000000
CONT0 = 20log (CNTLB/0.357).
(min/max)
Video frequency
BW1
L-CW
17
Characteristics 1
(NTSC)
With the input signal’s continuous
FILTER SYS: 0000
Wave = 100kHz, measure the output signal’s
SHARPNESS:
continuous wave amplitude (PEAKDC Vp-p).
000000
With the input signal’s continuous
wave = 1.8MHz, measure the output signal’s
continuous wave amplitude (CW1.8 Vp-p).
Calculate BW1 = 20Log (CW1.8/PEAKDC).
Video frequency
BW2
L-CW
17
Characteristics 2
(PAL)
With the input signal’s continuous
FILTER SYS: 0010
wave = 2.2MHz, measure the output signal’s
SHARPNESS:
continuous wave amplitude (CW2.2 Vp-p).
000000
Calculate BW2 = 20Log (CW2.2/PEAKDC).
Chroma trap amount
CtraPP
L-CW
17
PAL
With the input signal’s continuous
FILTER SYS: 010
wave = 4.43MHz, measure the output signal’s
Sharpness: 000000
continuous wave amplitude (F0P Vp-p).
Calculate CtraP = 20Log (F0P/PEAKDC).
Chroma trap amount
CtraPN
L-CW
17
NTSC
With the input signal’s continuous
FILTER SYS: 000
wave = 3.58MHz, measure the output signal’s
Sharpness: 000000
continuous wave amplitude (F0N Vp-p).
Calculate CtraN = 20Log (F0N/PEAKDC).
DC transmission
ClampG1
L-0
17
amount
Measure the output signal’s 0IRE DC level
Brightness:
(BRTPL V).
0000000
CONTRAST:
1111111
L-100
Measure the output signal’s 0IRE DC level
Brightness:
(DRVPH V) and 100IRE amplitude (DRVH Vp-p)
0000000
and calculate ClampG = 100 ×
Contrast:
(1+(DRVPH - BRTPL)/DRVH).
1111111
DCREST = 00
BLK.ST.DEF = 1
WPL = 0
Sharpness variable
Sharp32T2
L-CW
17
range (PAL)
With the input signal’s continuous
Filter Sys:0010
wave = 2.7MHz, measure the output signal’s
Sharpness: 100000
continuous wave amplitude (F02S32 Vp-p).
Calculate Sharp32T3 = 20Log
(F02S32/PEAKDC).
(max)
Sharp63T2
L-CW
17
With the input signal’s continuous
Filter Sys:0010
wave = 3MHz, measure the output signal’s
Sharpness: 111111
continuous wave amplitude (F02S63 Vp-p).
Calculate Sharp63T2 = 20Log
(F02S63/PEAKDC).
(min)
Sharp0T2
L-CW
17
With the input signal’s continuous
Filter Sys:0010
wave = 3MHz, measure the output signal’s
Sharpness: 000000
continuous wave amplitude (F02S0 Vp-p).
Calculate Sharp0T2 = 20Log (F02S0/PEAKDC).
Continued on next page.
NoA0017-14/31
LA76850
Continued from preceding page.
Input signal
Y gamma effective
Symbol
Test point
YG1
Input signal
L-100
17
point1
Test method
Measure the output amplitude (0 to 100 IR) when
Bus conditions
Y GAMMA = 1
the Y gamma is 0 (GAM0). Then set Y gamma to 1
and measure the output amplitude (0 to 100 IR)
again (GAM1).
Calculate YG1 = (GAM1/GAM0) × 100.
Y gamma effective
YG2
L-100
17
point12
Measure the output amplitude (0 to 100 IR) when
Y GAMMA = 2
the Y gamma is 0 (GAM0). Then set Y gamma to 2
and measure the output amplitude (0 to 100 IR)
again (GAM2).
Calculate YG2 = (GAM2/GAM0) × 100.
Y gamma effective
YG3
L-100
17
point1
Measure the output amplitude (0 to 100 IR) when
Y GAMMA = 3
the Y gamma is 0 (GAM0). Then set Y gamma to 3
and measure the output amplitude (0 to 100 IR)
again (GAM3).
Calculate YG3 = (GAM3/GAM0) × 100.
Horizontal/vertical
RGBBLK
L-100
17
blanking output
Measure the DC level (RGBBLK V) for the output
signal’s blanking period.
level
[OSD block]
Bus control bit conditions:
Contrast: 0111111
Contrast = 63, Brightness = 63
Brightness:
0111111
OSD
FSTH
17
Fast SW threshold
L-0
Apply voltage to pin 15 and measure the voltage at
Pin 14A: O-2
O-2
pin 15 at the point where the output signal switches
applied
to the OSD signal.
OSD output
OSDH
L-50
17
level
Measure the output signal’s 50IRE amplitude
Osd cont = 0111111
(CNTCB Vp-p).
Digital osd = 1
L-0
Measure the OSD output amplitude
Pin 15: 3.5V
O-2
(OSDHB Vp-p).
Pin 14A: O-2
Calculate OSDH =
applied
50 × (OSDHB/CNTCB)
[Y output block] (Cutoff, drive block)
Bus control bit conditions: Contrast = 127
Contrast:
1111111
Brightness control
BRT63
L-0
17
(normal)
Measure the 0IRE DC levels of the
Brightness:
respective output signals of Y output
01111111
(17)
Brightness control
BRT63H
Brightness control
L-0
17
(normal-H)
BRT127
L-0
17
(max)
Measure the 0IRE DC level of the output Signal of
Brightness:
Y output (17) and assign the Measured value to
0111111
BRTPC.
Sub Bias: 1111111
Measure the 0IRE DC level of the output Signal of
Brightness:
Y output (17) and assign the Measured value to
1111111
BRTPH.
Sub Bias: 1111111
Calculate BRT127 =
50×(BRTPH-BRTPC)/CNTHB.
Brightness control
BRT0
L-0
17
(min)
Measure the 0IRE DC level of the output
Brightness:
Signal of Y output (17) and assign the
0000000
Measured value to BRTPL.
Sub Bias: 1111111
Calculate BRT0 =
50× (BRTPL-BRTPC)/CNTHB.
Bright control
Vsiassns
L-50
17
resolution
Measure the 0IRE DC levels (BTPM V) of the
Brightness:
respective output signals of Y output (17).
0000000
Vbiassns = (BRTPH-BTPM)/127
Sub Bias:
1111111
Sub-bias control
resolution
Vsbiassns
L-50
17
Measure the 0IRE DC levels (SBTPM V) of the
Brightness:
respective output signals of Y output (17).
0111111
Vsbiassns = (BRTPCH-SBTPM)/127
Sub Bias: 0000000
NoA0017-15/31
LA76850
Deflection Block Input Signals
Unless otherwise specified, the following conditions apply when each measurement is made.
1. VIF, SIF blocks: No signal
2. C input: No. signal
3. Sync input: A horizontal/vertical composite sync signal
PAL:
NTSC:
43IRE, horizontal sync signal (15.625kHz) and vertical sync signal (50kHz)
40IRE, horizontal sync signal (15.734264kHz) and vertical sync signal (59.94kHz)
Note: No burst signal, chroma signal shall exist below the pedestal level.
Signal unsuitable
for Y input
Signal suitable
for Y input
Chroma signal
Burst signal
4. Bus control conditions: Initial conditions unless otherwise specified.
5. The delay time from the rise of the horizontal output (pin 22 output) to the fall of the FBP IN (pin 23 input) is 9µs.
6. Pin 13 (vertical size correction circuit input terminal) is connected to VCC (5.0V).
NoA0017-16/31
LA76850
Deflection Block Test Conditions
Input signal
Symbol
Horizontal free-running
fH
Test point
22
frequency
Input signal
Test method
Bus conditions
Y IN:
Connect a frequency counter to the output of pin
No signal
22 (H out) and measure the horizontal free-running
frequency.
Horizontal output
Hduty
22
pulse length
Y IN:
Measure the voltage for the pin 22 horizontal
Horizontal/
output pulse’s low-level period.
vertical sync
signal
PAL
Horizontal output pulse
V Hsat
22
saturation voltage
Y IN:
Measure the voltage for the pin 22 horizontal
Horizontal/
output pulse’s low-level period.
vertical sync
signal
PAL
Vertical free-running
VFR50
period 50 (PAL)
VFR60
18
Y IN:
Measure the vertical output period T at pin 18
CDMODE: 001
No signal
T×15.625kHz (PAL)
(PAL)
T×15.734kHz (NTSC)
CDMODE: 002
Vertical free-running
(NTSC)
period 60 (NTSC)
Vertical output
2.5V
T
Horizontal output pulse
HPHCEN
(PAL)
22
(NTSC)
28
Y IN:
Measure the delay time from to the rise of the pin
Horizontal/
22 horizontal output pulse to the fall of the Y IN
vertical sync
horizontal sync signal.
signal
PAL
HPHCEN
NTSC
20IRE
2.5V
Horizontal output
Horizontal position
adjustment range
HPHrange
22
28
Y IN:
With H PHASE: 0 and 31, measure the delay time
H PHASE: 00000
Horizontal/
from the rise of the pin 22 horizontal output pulse
H PHASE: 11111
vertical sync
to the fall of the Y IN horizontal sync signal and
signal
calculate the difference from H PHCEN.
PAL
Measuring
20IRE
2.5V
Horizontal output
Continued on next page.
NoA0017-17/31
LA76850
Continued from preceding page.
Input signal
Horizontal position
Symbol
Test point
HPHstep
22
adjustment maximum
variable width
28
Input signal
Test method
Bus conditions
Y IN:
With H PHASE: 0 to 31 varied, measure the delay
H PHASE: 00000
Horizontal/
time from to the rise of the pin 22 horizontal output
to
vertical sync
pulse to the fall of the Y IN horizontal sync signal
H PHASE: 11111
signal
and calculate the variation at each step. Retrieve
PAL
data for maximum variation.
Measuring
20IRE
2.5V
Horizontal output
Horizontal blanking
BLKL0
22
left variable range@0
Y IN:
Measure the time T from the left end of Hsync at
Horizontal/
pin 28 Y IN to the left end of blanking at pin 17
vertical sync
BlueOUT with BLKL = 000.
signal
28
PAL
Y IN
Hsync
BLKL: 000
T
Blue
Horizontal blanking
left variable range@7
BLKL7
17
28
Y IN:
Measure the time T from the left end of Hsync at
Horizontal/
pin 28 Y IN to the left end of blanking at pin 17
vertical sync
BlueOUT with BLKL = 111.
signal
PAL
Y IN
Hsync
BLKL:111
T
Blue
Continued on next page.
NoA0017-18/31
LA76850
Continued from preceding page.
Input signal
Horizontal blanking
Symbol
Test point
BLKR0
17
right variable range@0
28
Input signal
Test method
Bus conditions
Y IN:
Measure the time T from the left end of Hsync at
Horizontal/
pin 28 Y IN to the left end of blanking at pin 17
vertical sync
BlueOUT with BLKR = 000.
signal
Y IN
T
BLKR:000
Hsync
PAL
Blue
Horizontal blanking
BLKR7
right variable range@7
17
28
Y IN:
Measure the time T from the left end of Hsync at
Horizontal/
pin 28 Y IN to the left end of blanking at pin 17
vertical sync
BlueOUT with BLKR = 111.
signal
Y IN
T
BLKR:111
Hsync
PAL
Blue
Sand castle pulse crest
SANDH
23
value H
Y IN:
Measure the supply voltage at point H of the pin 23
Horizontal/
FBP IN wave form for Hsync period.
H
vertical sync
signal
PAL
Sand castle pulse crest
SANDM1
23
value M1
Y IN:
Measure the supply voltage at point M1 of the pin
Horizontal/
23 FBP IN wave form for Hsync period.
vertical sync
M1
signal
PAL
Sand castle pulse crest
SANDL
23
value L
Y IN:
Measure the supply voltage at point L of the pin 23
Horizontal/
FBP IN wave form for Hsync period.
vertical sync
signal
PAL
L
Sand castle pulse crest
value M2
SANDM2
23
Y IN:
Measure the supply voltage at point M2 of the pin
Horizontal/
23 FBP IN wave form for Vsync period.
vertical sync
signal
PAL
L
Continued on next page.
NoA0017-19/31
LA76850
Continued from preceding page.
Input signal
Symbol
Burst gate pulse length
BGPWD
Test point
23
Input signal
Test method
Bus conditions
Y IN:
Measure the BGP width T of the pin 28 FBP IN
Horizontal/
wave form for Hsync period.
vertical sync
T
signal
PAL
Burst gate pulse
BGPPH
23
I phase
Y IN:
Measure the time from the left end of Hsync at pin
Horizontal/
42 Y IN to the left end of the pin 23 FBP IN wave
vertical sync
form for Hsync period.
signal
42
PAL
Hsync
Y IN
T
FBPIN
Horizontal output stop
voltage
Hstop
20
22
Y IN:
Decrease the current from a source connected to
Horizontal/
pin 20 and measure the pin 20 voltage at which
vertical sync
HOUT stops.
signal
Continued on next page.
NoA0017-20/31
LA76850
Continued from preceding page.
Input signal
Symbol
Test point
Input signal
Test method
Bus conditions
<Vertical screen size correction>
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 24 (22:NTSC) and line
PAL@64
vertical sync
310 (262:NTSC).
NTSC@64
signal
Calculate as follows:
PAL
Vspal64 = Vline310-Vline24
NTSC
Vsnt64 = Vline262-Vline22
Vertical ramp output
Vspal64
Amplitude
Vsnt64
18
Vertical ramp output
Line 310
Line 24
Vertical ramp output
Vspal0
amplitude PAL@0
Vsnt0
18
NTSC@0
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 24 (22:NTSC) and line
vertical sync
310 (262:NTSC).
signal
Calculate as follows:
PAL
Vspal0 = Vline310-Vline24
NTSC
Vsnt0 = Vline262-Vline22
VSIZE: 0000000
Vertical ramp output
Line 310
Line 24
Vertical ramp output
Vspal127
amplitude PAL@127
Vsnt127
18
NTSC@127
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 24 (22: NTSC) and line
vertical sync
310 (262: NTSC).
signal
Calculate as follows:
PAL
Vspal27 = Vline310-Vline24
NTSC
Vsnt127 = Vline262-Vline22
VSIZE: 1111111
Vertical ramp output
Line 310
Line 24
<High-voltage dependent vertical size correction>
Vertical size
correction@0
Vsizecomp
18
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at the line 24 and line 310
vertical sync
with VCOMP = 000. Calculate as follows:
signal
Va = Vline310-Vline24
PAL
Apply 4.1V to pin 13 and measure the voltage at
VCOMP: 000
the line 24 and line 310 again. Calculate as
follows:
Va = Vline310-Vline24
Calculate as follows:
Vsizecomp = Vb/Va
Vertical ramp output
Line 310
Line 24
Continued on next page.
NoA0017-21/31
LA76850
Continued from preceding page.
Input signal
Symbol
Test point
Input signal
Test method
Bus conditions
<Vertical screen position adjustment>
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 167. (PAL)
PAL@32
vertical sync
Monitor the pin 18 vertical ramp output and
NTSC@32
signal
measure the voltage at line 142. (NTSC)
Vertical ramp DC
Vdcpal32
voltage
Vdcnt32
18
PAL
NTSC
Vertical ramp output
Line 167
Vertical ramp DC
Vdcpal0
voltage
Vdcnt0
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 167. (PAL)
PAL@0
vertical sync
Monitor the pin 18 vertical ramp output and
NTSC@0
signal
measure the voltage at line 142. (NTSC)
18
VDC: 000000
PAL
NTSC
Vertical ramp output
Line 167
Vertical ramp DC
Vdcpal63
voltage
Vdcnt63
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 167. (PAL)
PAL@63
vertical sync
Monitor the pin 18 vertical ramp output and
NTSC@63
signal
measure the voltage at line 142. (NTSC)
18
PAL
NTSC
VDC: 111111
Vertical ramp output
Line 167
Continued on next page.
NoA0017-22/31
LA76850
Continued from preceding page.
Input signal
Vertical linearity@16
Symbol
Test point
Vlin16
18
Input signal
Test method
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 24, line 167 and 310.
vertical sync
Assign the respective measured values to Va, Vb
signal
and Vc. Calculate as follows:
PAL
Vlin16 = (Vb-Va)/(Vc-Vb)
Vertical ramp output
Bus conditions
Line 310
Line 167
Line 24
Vertical linearity@0
Vlin0
18
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 24, line 167 and 310.
vertical sync
Assign the respective measured values to Va, Vb
signal
and Vc. Calculate as follows:
PAL
Vlin0 = (Vb-Va)/(Vc-Vb)
Vertical ramp output
VLIN: 00000
Line 310
Line 167
Line 24
Vertical linearity@31
Vlin31
18
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 24, line 167 and 310.
vertical sync
Assign the respective measured values to Va, Vb
signal
and Vc. Calculate as follows:
PAL
Vlin31 = (Vb-Va)/(Vc-Vb)
Vertical ramp output
VLIN: 11111
Line 310
Line 167
Line 24
Continued on next page.
NoA0017-23/31
LA76850
Continued from preceding page.
Input signal
Symbol
Vertical S-shaped
VScor16
Test point
18
correction @16
Input signal
Test method
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 36, line 60, line 155,
vertical sync
line 179, line 274 and 298. Assign the
signal
respective measured values to Va, Vb, Vc, Vd, Ve
PAL
and Vf. Calculate as follows:
Bus conditions
VS: 10000
VScor16 = 0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc)
Line 298
Vertical ramp output
Line 179
Line 60
Line 274
Line 155
Line 36
Vertical S-shaped
VScor0
correction @0
18
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at the line 36, line 60, line
vertical sync
155, line 179, line 274 and line 298
signal
with VSC = 00000.
PAL
Assign the respective measured values to Va, Vb,
Vc, Vd, Ve and Vf. Calculate as follows:
VScor0 = 0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc)
Line 298
Vertical ramp output
Line 179
Line 60
Line 274
Line 155
Line 36
Vertical S-shaped
correction @31
VScor31
18
Y IN:
Monitor the pin 18 vertical ramp output and
Horizontal/
measure the voltage at line 36, line 60, line 155,
vertical sync
line 179, line 274 and 298. Assign the
signal
respective measured values to Va, Vb, Vc, Vd, Ve
PAL
and Vf. Calculate as follows:
VSC: 11111
VScor16 = 0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc)
Line 298
Vertical ramp output
Line 179
Line 60
Line 274
Line 155
Line 36
NoA0017-24/31
LA76850
Control Register Bit Allocation Map
Control Register Bit Allocations (continued)
Sub
MSB
Address
DA0
00010000
DATA BITS
DA1
DA2
DA3
OSD
DA4
LSB
DA5
DA6
DA7
OSD Contrast
Cnt.Test
0
10001
1
0
10010
10011
10100
10110
0
0
0
0
0
0
0
0
0
0
Sharpness
0
0
*
*
*
*
*
*
*
*
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
*
*
*
*
*
*
*
*
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
0
1
0
*
Trap Test
(0)
10101
0
Coring Gain(W/Defeat)
Filter.Sys
1
Gray Mode
0
0
Cross B/W
0
*
*
*
*
*
0
0
0
(0)
(0)
(0)
(0)
(0)
VBLK SW
FBPBLK.
*
Y_APF
*
*
(0)
0
0
0
(0)
(0)
*
*
*
*
*
*
(0)
(0)
(0)
(0)
(0)
(0)
Pre/Over-shoot adj.
SW
0
1
Y Gamma Start
10111
0
11000
11001
11010
11011
11100
11101
0
*
*
*
*
*
*
*
*
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Cont.
Digital
Brt.Abl.
Mid.Stp.Def
RGB Temp
Test
OSD
Def
0
0
0
0
0
1
0
0
*
*
*
*
*
*
*
*
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
*
*
*
*
*
*
*
*
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
0
0
0
0
0
0
OVER.
VOL.FIL
Bright.Abl.Threshold
SW
*
Volume
0
RF.AGC
MOD.SW
11110
0
0
FM.Mute
deem.TC
0
0
1
0
VIDEO.LEVEL
11111
1
0
0
0
VIF.Sys.SW
0
0
SIF.Sys.SW
0
0
FM.Gain
IF.AGC
0
1
0
1
0
*
*
*
*
*
(0)
(0)
(0)
(0)
(0)
(Bits are transmitted in this order.)
NoA0017-25/31
LA76850
Control Register Truth Table
Register Name
0 HEX
1 HEX
T.Disable
Tset Enable
Test Disable
AFC gain&gate
Auto (Gain)
Gain:Fast
Auto (Gate)
Non-Gate
V Reset Timing
Normal
1/4H Shift
Audio.Mute
Active
Mute
Video.Mute
Active
Mute
Sync.Kill
Sync active
Sync killed
Vsepup
normal
Vsepup
V.KILL
Vrt active
Vrt killed
Vertical Test
Normal
Vrt S Corr
Drive.Test
Normal
Test Mode
Half Tone
Half Tone Def
Blank.Def
S.TRAP.SW
Min (Dark)
→
Half Tone on
Half Tone off
Blanking
No Blank
Bypass ON
Bypass OFF
OSD Cnt.Test
Normal
Test Mode
Coring Gain(w/Defeat)
Defeat
Min
Color.Test
Normal
Test Mode
Video.SW
Internal Mode
External Mode
Gray Mode
Normal
Gray OSD
Cross B/W
Normal
Black
G-Y Angle
240deg
253deg
VBLK SW
24H to 262H (NTSC)
29H to 256H (NTSC)
25H to 309H (PAL)
30H to 304H (PAL)
FBPBLK.SW
2 HEX
3 HEX
Vrt Lin
Vrt Size
→
Max
→
Max
White
Cross
FBP not or
FBP or
Y APF
Y Trap
Y APF
Pre/Over-shoot adj.
Normal
+10ns
+20ns
+30ns
→
Max
45.75MHz
39.5MHz
Y Gamma Start
Y Gamma off
Min
Digital OSD
Analogue
Digital
Brt.ABL.Def
Brt ABL On
Brt ABL Off
Mid.Stp.Def
Mid Stp On
Mid Stp Off
RGB Temp SW
-1Vbe
Flat
circuit OFF
circuit ON
VOL.FIL
Normal
Filte OFF
FM.Mute
Active
Mute
de-em TC.
50µs
75µs
38.0MHz
38.9MHz
OVER.MOD.(circuit)SW
VIF.Sys.SW
FM Gain
50kHz dev.
25kHz dev
IF.AGC
AGC active
AGC defeat
Pre-shoot Adj.
Over-shoot Adj.
Individual Operation
Normal
Pre/Over SW
Hlock.Vdet
VIDEO.LEVEL.OFFSET
direction: Minus
Center
direction: Plus
NoA0017-26/31
LA76850
Control Register Truth Table
COUNT DOWN MODE
50Hz/60Hz MODE
Standard/Non-Standard MODE
0 HEX
Auto
Auto
1 HEX
50Hz
Auto
2 HEX
60Hz
Auto
3 HEX
Auto
Auto
4 HEX
Auto
Non-Standard
5 HEX
50Hz
Non-Standard
6 HEX
60Hz
Non-Standard
7 HEX
Auto
Non-Standard
Filter System
Y Filter
Chroma Filter
3.58MHz Trap
Peaked 3.58MHz BPF
1 HEX
3.58MHz Trap
Symmetrical 3.58MHz BPF
2 HEX
4.43MHz Trap
Peaked 4.43MHz BPF
3 HEX
4.43MHz Trap
Symmetrical 4.43MHz BPF
4 HEX
6.0MHz Trap
Peaked 3.58MHz BPF
5 HEX
6.0MHz Trap
Symmetrical 3.58MHz BPF
6 HEX
6.0MHz Trap
Peaked 4.43MHz BPF
7 HEX
6.0MHz Trap
Symmetrical 4.43MHz BPF
8-15HEX
4.286MHz Trap
Symmetrical 4.43MHz BPF
0 HEX
Snd.Trap & FM.Det
A2.SW
SIF.Sys.SW
Snd.Trap
FM.det
0 HEX
0 HEX
4.5MHz
4.5MHz
1 HEX
5.5MHz
5.5MHz
2 HEX
6.0MHz
6.0MHz
3 HEX
6.5MHz
6.5MHz
0 HEX
-----------
-----------
1 HEX
5.5NHz
5.74MHz
2 HEX
-----------
-----------
3 HEX
-----------
-----------
A.MONI.SW
AUDIO.SW
1pin Output
2pin Output
0 HEX
0 HEX
Internal
Internal
1 HEX
External
1 HEX
0 HEX
Internal
1 HEX
Audio Monitor Output
1 HEX
Internal
External
External
(before VOLUME)
Status Byte Truth Table
Register
0 HEX
1 HEX
RF.AGC
RF.AGC.OUT = "L"
RF.AGC.OUT = "H"
IF.LOCK
IF.PLL Lock
IF.PLL Unlock
V.TRI
V.Triger Undetected
V.Triger Detected
50/60
50
60
Non-Standard
Standard
ST/NONST
NoA0017-27/31
LA76850
Initial Conditions
Initial Test Conditions
Register Name
Initial Test Conditions (continued)
Value
Register Name
Value
T.Disable
1 HEX
VBLK SW
0 HEX
AFC gain&gate
0 HEX
FBPBLK.SW
1 HEX
H.FREQ
3F HEX
Y_APF
0 HEX
V Reset Timing
0 HEX
Pre/Over-shoot Adj.
0 HEX
Audio.Mute
0 HEX
Y Gamma
0 HEX
Video.Mute
0 HEX
Digitsl OSD
0 HEX
H.PHASE
10 HEX
Brt.Abl.Def
0 HEX
Sync.Kill
0 HEX
Mid.Stp.Def
0 HEX
V.SIZE
40 HEX
RGB Temp SW
0 HEX
VSEPUP
0 HEX
Bright.Abl.Threshold
4 HEX
V.KILL
0 HEX
Volume
00 HEX
V.POSI
20 HEX
OVER.MOD.SW
0 HEX
H BLK L
4 HEX
VOL.FIL
0 HEX
H BLK R
4 HEX
RF.AGC
20 HEX
V.LIN
10 HEX
FM.Mute
0 HEX
V.SC
00 HEX
deem.TC
0 HEX
V.TEST
0 HEX
VIF.Sys.SW
1 HEX
V.COMP
7 HEX
SIF.Sys.SW
1 HEX
COUNT.DOWN.MODE
0 HEX
FM.Gain
0 HEX
RGB Test 4
0 HEX
IF.AGC
0 HEX
Half Tone
1 HEX
VIDEO.LEVEL
4 HEX
Half Tone Def
1 HEX
Pre/Over SW
0 HEX
A2 SW
0 HEX
H lock.Vdet
0 HEX
Blank.Def
0 HEX
VIDEO.LEVEL.OFFSET
1 HEX
Sub.Bias
40 HEX
IF.TEST1
0 HEX
A.MONI.SW
0 HEX
OVER.MOD.LEVEL
8 HEX
Bright
40 HEX
Coring Gain (w/Defeat)
0 HEX
S.TRAP.SW
1 HEX
Sharpness
00 HEX
Contrast
40 HEX
Trap.Test
4 HEX
OSD Cnt.Test
0 HEX
Filter.Sys
2 HEX
OSD Contrast
0 HEX
Gray Mode
0 HEX
Cross B/W
0 HEX
NoA0017-28/31
LA76850
Control Register Descriptions
Register Name
Bits
General Description
T Disable
1
Disable the Test SW & enable Audio/Video Mute SW
AFC Gain & gate
1
Select horizontal first loop gain & H-sync gating on/off
H Freq.
6
Align ES Sample horizontal frequency
V Reset Timing
1
Select Vertical Reset Timing
Audio Mute
1
Disable audio outputs
Video Mute
1
Disable video outputs
H PHASE
5
Align sync to flyback phase
Sync Kill
1
Force free-run mode
Vertical Size
7
Align vertical amplitude
Vsep.up
1
Select vertical sync. separation sensitivity
Vertical Kill
1
Disable vertical output
V POSI (Vertical DC)
6
Align vertical DC bias
H BLK L
3
H-Blanking Control (Left side of the screen)
H BLK R
3
H-Blanking Control (Right side of the screen)
V LIN (Vertical Linearity)
5
Align vertical linearity
Vertical S-Correction
5
Align vertical S-correction
Vertical Test
2
Select vertical DAC test modes
Vertical Size Compensation
3
Align vertical size compensation
Count Down Mode
1
Select vertical countdown mode
Half Tone
2
Adjust half tone DC level
Half Tone Defeat
1
Half tone defeat SW
A2.SW
1
Select 5.74MHz FM.Det
Blank Def
1
Disable RGB output blanking
Sub Bias
7
Align common RGB DC level
A.MONI.SW
1
Select FM Output/Selected Audio Output
Brightness Control
7
Customer brightness control
S.TRAP.SW
1
Select Snd Trap bypass
Contrast Control
7
Customer contrast control
OSD Contrast Test
1
Enable OSD Contrast DAC test mode
OSD Contrast Control
2
Align OSD AC level
Coring Gain Select
2
Select Coring Gain (0hex: Defeat)
Sharpness Control
6
Customer sharpness control
Trap.Test
3
Trap Test
Filter System
3
Select Y/C Filter mode
Gray Mode
1
OSD Gray Tone Enable
Cross B/W
2
Service Test Mode (normal/Black/White/Cross)
Vertical Blanking SW
1
Select VBLK Period
FBPBLK.SW
1
Enable RGB Blanking or FBP
Y APF Enable SW
1
(with Defeat)
Select the frequency caracteristic of 3.58MHzTrap.
It is useful for 3.58MHzTrap or APF
Pre/Over-shoot Adjustmant
2
Select Pre-shoot Width
Y Gamma Start
2
Enable luminance coring
DC Restoration Select
2
Select Luma DC Restoration
Cont Test
1
Enable contrast DAC test mode
Digital OSD SW
1
Select Digital/Analogue OSD
Bright ABL Defeat
1
Disable brightness ABL
Bright Mid Stop Defeat
1
Disable brightness mid stop
RGB Temp SW
1
Select temprature caracteristic of RGB Output
Bright ABL Threshold
3
Align brightness ABL threshold
Volume Control
7
Customer volume control
OVER.MOD.SW
1
Select overmodulation circuit ON/OFF
Continued on next page.
NoA0017-29/31
LA76850
Continued from preceding page.
Register Name
Bits
General Description
Volume Filter Defeat
1
Disable volume DAC filter
RF AGC Delay
6
Align RF AGC threshold
FM Mute
1
Disable FM outputs
de-em TC.
1
Select de-emphasis Time Constant
VIF System SW
2
Select 38.0/38.9/39.5/45.75
SIF System SW
2
Select 4.5/5.5/6.0/6.5
FM Gain
1
Select FM Output Level
IF AGC Defeat
1
Disable IF and RF AGC
Video Level
3
Align IF video level
FM Level
5
Align FM output level
Pre/Over SW
1
Select control for Pre/Over-shoot Adjustmant
H Lock Vdet
1
Select vertical sync. Operation
VIDEO.LEVEL.OFFSET
2
Align IF video level
IF TEST1
1
Select test modes
OVER.MOD.LEVEL
4
Align overmodulation performance
NoA0017-30/31
LA76850
Read Status Description
RF.AGC
0: RF AGC = low, 1: RF AGC = high. See the separately provided documentation (Application Note) for details.
IF.LOCK
0: IF.PLL = Locked, 1: IF.PLL = Unlocked
V.TRI
Returns the output of the VCD internal vertical trigger detection circuit to the bus. The state of the internal memory is updated every vertical
period.
1HEX: Detected
50/60
Returns the output of the VCD internal 50/60 Hz detection output to the bus.
ST/NONST
Returns to the bus whether a standard (262.5H) VCD or a nonstandard internal vertical trigger detection circuit output VCD is used.
Returns the FF output determined by the VCD internal mode in real time.
1HEX: Standard
H.Lock
Performs FBP and Hsync phase detection, integrates that output, and detects at a point about 40H after the HVCO locks.
Returns, in real time, the state with respect to bus reads.
1Hex: Locked
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Any and all information described or contained herein are subject to change without notice due to
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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
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This catalog provides information as of November, 2005. Specifications and information herein are subject to
change without notice.
This catalog provides information as of November, 2005. Specifications and information herein are subject
to change without notice.
PS NoA0017-31/31