Ordering number : ENN5841 Monolithic Linear IC LA7615 Single-Chip NTSC Color TV IC Overview Package Dimensions The LA7615 is an NTSC color TV IC that supports computer control over an I2C bus. In addition to improved quality and increased functionality in color TV products, this IC supports the development of a TV set product line in software and the simplification of end product design. The provision of an I2C bus means that this product can also respond to desires for increased total manufacturing productivity, including improved automation of computer controlled production lines. unit: mm 3071-DIP64S [LA7615] 33 0.25 19.05 16.8 64 1 Functions 32 0.95 Features 0.48 1.78 • Pursuit of higher integration levels The LA7615 integrates VIF, SIF, luminance, chrominance, and deflection (horizontal and vertical synchronization) circuits, A/V switching, and power supply control on a single chip. • Bus control for reduced external component counts and mechanical adjustment points All the LA7615 signal-processing circuits can be controlled and adjusted digitally over the I2C bus. All adjustments, both those required during manufacture and the user controls, can be controlled over the I2C bus, and both function selection and characteristics settings can be performed in software over the I 2 C bus. This increases flexibility in designing a product line of TV sets and also enhances productivity by allowing mixed production runs. While this device supports multifunction and good performance, it is also economical in that it achieves reduced power and reduced pin count. 1.01 0.51min 4.0 • I2C bus control, VIF, SIF, Y, C, and deflection circuits integrated on a single chip. 3.2 5.0max 57.2 SANYO: DIP64S Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 91799RM (OT) No. 5841-1/39 LA7615 Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit V2 max 9.6 V V17 max 9.6 V V32 max 9.6 V V60 max 9.6 V Maximum supply current I24 max 30 mA Allowable power dissipation Pd max Maximum supply voltage Ta ≤ 65°C 1.5 W Operating temperature Topr –10 to +65 °C Storage temperature Tstg –55 to +150 °C Ratings Unit Operating Conditions at Ta = 25°C Parameter Recommended supply voltage Recommended supply current Operating supply voltage range Operating supply current range Symbol Conditions V2 7.6 V V17 7.6 V V32 7.6 V V60 7.6 V I24 24 mA V2 op 7.3 to 7.9 V V17 op 7.3 to 7.9 V V32 op 7.3 to 7.9 V V60 op 7.3 to 7.9 V I24 op 20 to 30 mA Functional Description <VIF/SIF Functions> In addition to a PLL synchronous detection system, the IF block also adopts a split system in which the VIF signal and the SIF signal are processed separately. • Low-level VCO The LA7615 achieves a significant reduction in beat generation due to interference by lowering the VCO oscillator level from that used in earlier ICs. • Adjustment-free VCO coil implemented using bus control By compensating for manufacturing variations in the VCO coil using bus control, the LA7615 eliminates coil adjustment from the manufacturing line. • Built-in 4.5 MHz trap The LA7615 incorporates an on-chip trap that also provides a video equalizer function. Thus the number of external trap, inductor, and capacitor components is reduced. • Built-in SIF FM detector: 4.5 MHz quadrature detection • The video signal and FM demodulated signal levels can be controlled from the serial bus. The improved precision associated with controlling the output level over the serial bus makes it easier to design the interface with the following stage. • Built-in buzz canceler Allows high performance to be maintained even during stereo reception. • Built-in video switch (INT/EXT(AUX) switching circuit) Built-in AUX input switching circuit means that the dedicated switching ICs required can be reduced. Also, the ability to control this switch from the serial bus makes it easier to design the peripheral wiring pattern. • Dedicated IF video signal output pin The provision of this pin makes it easier to design end products that support PIP and similar features. <Luminance and Chrominance Circuits> These blocks have been designed to minimize the use of external components as much as possible. The filter circuits are now integrated on the same chip, and not only the adjustment circuits, but also the function selection and characteristics modifications functions can be controlled over the serial bus. As a result, basically all the signal processing from input to output can be performed with only the addition of the chrominance circuit VCO crystal and the APC filter circuit. No. 5841-2/39 LA7615 Furthermore, this IC also supports high image quality systems and responds to needs from a diverse range of end products. • Two independent inputs for the luminance and chrominance signals and switching between the Y1/C1 and Y2/C2 inputs • Video muting on/off switch • Built-in filters (The filter f0 adjustment function can be used to select the filter characteristics.) Chrominance system: Bandpass filter (symmetric and asymmetric types) Luminance system: Color trap and delay line <f0 Mode Selection> Mode f0 = Y signal Chroma signal Trap f0 *Total delay BPF *Total 500 ns delay 0 3.58 MHz 500 ns Asymmetric (peaking type) 515 ns 1 4.2 MHz 510 ns 2 5.0 MHz 520 ns Symmetric 535 ns 3 10.0 MHz 265 ns Bypass 265 ns *: Reference values <Luminance System Circuit> • Built-in high image quality variable-type luminance system filter (color trap and delay line) Luminance filter mode selection (f0 adjustment) Four modes are provided: 3.58 MHz trap, 4.2 MHz trap, 5.0 MHz wide, and 10.0 MHz high band. • Peaking (sharpness) control Aperture type control implemented using the delay line The emphasis frequency is automatically selected according to the f0 mode using the delay line. One of the four frequencies 2.2, 2.6, 3.0, or 4.9 MHz is emphasized according to which of the f0 modes (3.58 MHz trap, 4.2 MHz trap, 5.0 MHz wide, or 10.0 MHz high band) is used. • Adaptive coring For low-level signals, the above peaking is suppressed to reduce the image contamination due to that peaking. The coring level is automatically adjusted according to the amplitude of the input signal. • Black stretch circuit: Can be turned on or off under control of the serial bus interface. • SYO (Selected luminance (Y) output) One of the Y1/Y2 inputs is selected, and that input signal is output as the sync separator circuit signal directly. However, the DC level of that signal is clamped at 1/2 VCC. Also, this signal can be used for closed captions or as a velocity modulation. • Support for analog/digital OSD Amplitude level limiting is applied to digital input signals internally to the IC. • Contrast and brightness controls • ABL (automatic beam limiter) Three-pin system (IB IN, BRT ABL FILT, and CONTRAST ABL FILT pins), mode switching under control of serial bus data. • R, G, and B output drive and bias adjustments • Sub-bias (brightness) control The DC level of each of the R, G, and B signals can be adjusted over a 4-step (2-bit) range. <Chrominance Circuit> • Built-in chrominance bandpass filter Chrominance system filter mode selection: bandpass filter peaking/symmetric type selection and chrominance bandpass filter bypass on/off setting • Auto Flesh: Flesh tone correction (on/off) • Overload (on/off) Limits the saturation of the color when the ratio of the burst and color signals is large, i.e. when the color is highly saturated. • Color phase and saturation controls • Demodulation angle: 104° No. 5841-3/39 LA7615 <Deflection Circuits> Dedicated sync separator circuit input pin The horizontal deflection circuit adopts a dual AFC circuit, and the horizontal oscillator uses the 32fH (503 kHz) pulse signal as the horizontal decrement counter clock. The following are the main settings for the horizontal output system that can be controlled over the serial bus interface. These settings support even more efficient end product design. • AFC gain (first loop gain control) • APC gain (second loop gain control) • Horizontal duty cycle • Horizontal phase *: The vertical deflection circuit adopts a decrement counter system, and provides constantly adjustment-free and stable vertical synchronization for any type of signal, from TV on air, to weak reception conditions, to VCR signals. Furthermore, this circuit uses an internal capacitor to implement a ramp generator, and allows the corrections described later in this document to be applied to correct image distortion and other problems due to manufacturing variations in the TV tube itself. <Horizontal Circuit Functions> • High-stability adjustment-free horizontal oscillator that uses a ceramic oscillator element • Dual AFC circuit • Multi-mode control of the AFC gain (first loop gain) • Horizontal duty and phase controls • Geometrical distortion correction: East-west DC (horizontal size) East-west amplitude (horizontal pin-cushion distortion correction) Corner pin East-west corner 1 East-west corner 2 Tilt adjustment • Sync killer <Vertical Circuit Functions> • Forcible non-standard mode support (standard mode: 262.5 H) • Vertical size/linearity and vertical DC (vertical position) adjustments, vertical S-curve correction • V-comp adjustment (Corrects for changes in the vertical size due to variations in the luminance.) • Vertical killer <Power System> PWM circuits have come to be widely used in TV set power supplies in recent years. This IC integrates parts of the power supply circuit (the pulse generator and its control system) and allows the supply voltage (high B) to be adjusted over the serial bus. No. 5841-4/39 LA7615 Bus Control General Functions ON/OFF SW 1 bit Video muting switch 1 bit VIF/SIF Video signal switching 1 bit RF AGC delay 6 bits IF AGC SW 1 bit PLL tuning 7 bits APC detector adjustment 6 bits AFT defeat switch 1 bit Noise inverter defeat switch 1 bit Video level 3 bits Sound 4.5 MHz trap 4 bits FM level 4 bits F0 fast (FM detection speed) 1 bit Luminance/Chrominance Systems Y/C input selection (one of two inputs) switch 1 bit Luminance (Y) F0 adjustment (filter control) 2 bits Chrominance signal bandpass filter mode switch 1 bit Chrominance signal bandpass filter bypass switch 1 bit Black stretch on/off switch 1 bit Peaking (sharpness) control 5 bits Coring on/off switch 1 bit Auro flesh on/off 1 bit Overload switch 1 bit Contrast control 6 bits Brightness control 6 bits Tint control 7 bits Saturation control 7 bits RGB bias adjustment 6 bits each RGB bias adjustment 7 bits each Sub-brightness control 2 bits each Brightness ABL operating point control 3 bits Brightness ABL mode defeat switch 1 bit each Emergency ABL defeat switch 1 bit Deflection System AFC gain (sync killer) 2 bits APC gain 2 bits Horizontal duty adjustment 2 bits Horizontal phase adjustment 4 bits Geometrical distortion correction EAST-WEST DC 5 bits EAST-WEST AMPLITUDE 4 bits East-west corner 1/2 3 bits each Tilt adjustment 4 bits Vertical linearity adjustment 4 bits Vertical S-curve correction 4 bits Vertical size adjustment 7 bits Vertical DC adjustment 6 bits Standard/nonstandard mode switch 1 bit VERTICAL KILL 1 bit V-COMP adjustment 3 bits DAC REF. (+B TRIM) 4 bits Others: Status Register POWER ON RESET 1 bit X-ray protection switch 1 bit Horizontal lock detection 1 bit AFT and RF AGC status discrimination 2 bits each No. 5841-5/39 LA7615 Vertical Linearity Narrow Wide Wide Narrow A10048 Vertical S-Curve Correction Wide Narrow Narrow Wide Wide Narrow A10049 Tilt A10050 East-West Amp A10051 Corner Pin East-west corner 1 East-west corner 2 The distortion correction operation is symmetric left to right. A10052 No. 5841-6/39 LA7615 Bus : Control Register Bit Allocation Map Control Register Bit Allocations IC address Sub address MSB IC Add7 → Add0 ¥ Add7 → Add0 Bit 7 1011 1010 0000 0000 Data bits Bit 6 Bit 5 1 Bit 4 LSB Bit 3 Bit 2 On/Off 0001 1 APC gain 0010 1 Hor duty cycle 0011 1 BNI defeat 0100 1 IF AGC defeat defeat 0101 1 VCO free running 0110 1 4.5 MHz trap 0111 1 Video 1000 1 Vertical 1001 1 1010 1 1011 1 Vertical comp. 1100 1 Vertical size 1101 1 1110 1 1111 1 (b1) (b1) Bit 0 Video AFC gain/sync kill mute (b1) (b0) (b2) (b1) (b0) B+ trim (b0) (b3) Horizontal phase (b0) (b3) (b2) (b1) (b0) (b5) (b4) (b3) (b2) (b1) (b0) AFT FM level (b4) (b3) (b2) (b1) (b0) (b5) (b4) (b3) (b2) (b1) (b0) (b2) (b1) (b0) (b2) (b1) (b0) (b4) (b3) (b2) (b1) (b0) (b4) (b3) (b2) (b1) (b0) (b3) (b2) (b1) (b0) (b2) (b1) (b0) (b3) (b2) (b1) (b0) (b3) (b2) (b1) (b0) (b2) (b1) (b0) (b1) (b0) RF AGC delay (b6) (b3) IF APC offset adjust. switch (b5) Vertical DC kill (b5) Countdown mode (b1) Bit 1 East-west DC (b0) (b4) East-west amp (b3) (b2) (b6) East-west tilt (b1) (b0) (b5) (b4) Vertical linearity (b3) FM mode switch Vertical S-correction (b3) East-west bottom corner (b2) (b1) (b2) East-west top corner (b0) (b2) (b1) (b0) Bits are transmitted in this order No. 5841-7/39 LA7615 Bus : Control Register Bit Allocation Map Control Register Bit Allocations (cont) IC address Sub address MSB IC Add7 → 0 Add7 → Add0 Bit 7 1011 1010 0001 Data bits Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (b5) (b4) (b3) (b2) (b1) (b0) (b5) (b4) (b3) (b2) (b1) (b0) (b5) (b4) (b3) (b2) (b1) (b0) (b4) (b3) (b2) (b1) (b0) (b4) (b3) (b2) (b1) (b0) (b4) (b3) (b2) (b1) (b0) 0000 1 Red bias 0001 1 Green bias 0010 1 Blue bias 0011 1 Red drive 0100 1 Green drive 0101 1 Blue drive 0110 1 (b6) (b6) (b6) (b5) (b5) (b5) Blue sub bias (b1) Red sub bias (b0) 0111 1 Brightness control 1000 1 Pix control 1001 1 Coring 1010 1 F0 select 1011 1 Tint control 1100 1 Color control 1101 1 1110 1 Test register 1 1111 1 Test regster 3 (b5) (b5) switch (b6) (b6) (b3) (b3) LSB Bit 5 Green sub bias Y/C (b1) (b0) (b1) (b0) switch (b4) (b3) (b2) (b1) (b0) (b4) (b3) (b2) (b1) (b0) Peaking control (b4) (b3) (b2) (b1) (b0) Chroma Auto Chrom Over (b1) (b0) BPF flesh bypass load (b5) (b4) (b3) (b2) (b1) (b0) (b2) (b1) (b0) (b5) (b4) (b3) ABL Mid Stp EMG defeat defeat defeat Bright ABL threshold (b2) (b1) (b0) Test register 2 (b2) (b2) (b1) (b0) (b1) (b2) (b1) (b0) Black Stretch Blanking Reserved (b0) defeat defeat Bit 3 Bit 2 Bit 1 Bits are transmitted in this order Table 8 : Status Register Bit Allocation Map Status Register Bit Allocations IC address Sub address MSB IC Add7 → Add0 Add7 → Add0 Bit 7 Bit 6 Bit 5 Bit 4 0001 Pon XRay Horiz On/off 1011 1010 0000 Data bits LSB AFT status Bit 0 RF AGC status lock 0001 1 1 1 1 1 1 1 1 No. 5841-8/39 LA7615 Bus : Control Register Truth Table Control Register Truth Table Register On/off Video mute AFC gain/sync Kill 0 HEX 1 HEX 2 HEX Off On na 3 HEX na Active Mute na na Sync Kill Low gain (auto mode) Mid gain High gain BNI defeat Enable BNI Defeat na na IF AGC defeat Enable AGC Defeat na na AFT defeat Enable AFT Defeat na na IF video Aux video na na Vertical active Vertical Killed na na Countdown mode Standard Non-standard 50 Hz 48 Hz FM mode switch Normal Fast na na Y1/C1 IN Y2/C2 IN na na Video switch Vertical Kill Y/C switch Coring switch Defeat Enable na na 3.58 Trap 4.20 Trap 5.00 APF 10.0 APF Symmetrical Peaker na na Off On na na BPF Bypass na na Off Active na na Bright ABL defeat Enable Defeat na na Bright mid stop defeat Enable Defeat na na Emergency ABL defeat Enable Defeat na na F0 select Chrom BPF Autoflesh Chroma bypass Over load Black Str defeat Enable Defeat na na Blanking defeat Enable Defeat na na 3 HEX Bus : Status Register Truth Table Status Register Truth Table Register 0 HEX 1 HEX 2 HEX POR Inactive Low standby detected na na XRP Inactive XRP fault detected na na Horizontal lock Locked Unlocked na na Off On na na IF frequency in high IF frequency in range na IF frequency is low RF AGC voltage is Low. RF AGC voltage is in range. na RF AGC voltage is High. On/off AFT RF AGC No. 5841-9/39 LA7615 Initial Condition Function On/off 1 HEX Video mute 0 HEX AFC gain & sync Kill 1 HEX APC gain 3 HEX B+ trim 8 HEX Horizontal duty 1 HEX Horizontal phase 8 HEX BNI defeat 0 HEX RF AGC delay 20 HEX IF AGC defeat 0 HEX AFT defeat 0 HEX FM level 10 HEX IF VCO free running 40 HEX 4.5 trap 8 HEX Video level 4 HEX Video switch 0 HEX IF APC offset 20 HEX Vertical Kill 0 HEX Vertical DC 20 HEX Countdown mode East/west DC 0 HEX 10 HEX East/west amplitude 8 HEX Vertical comp. 0 HEX East/west tilt 8 HEX Vertical size 40 HEX Vertical linearity 8 HEX FM mode switch 0 HEX Vertical S-correction 8 HEX East/west bottom 0 HEX East/west top corner Red bias 0 HEX 00 HEX Green bias 00 HEX Blue bias 00 HEX Red drive 3F HEX Green drive 3F HEX Blue drive 3F HEX Blue sub bias 2 HEX Red sub bias1 2 HEX Green sub bias 2 HEX Y/C switch 0 HEX Brightness control 20 HEX Pix control 20 HEX Coring switch Peaking control F0 select 0 HEX 00 HEX 1 HEX Chroma BPF 0 HEX Autoflesh 0 HEX Chroma bypass 0 HEX Over load 0 HEX Tint control 40 HEX Color control 40 HEX Bright ABL defeat 0 HEX Bright mid stop 0 HEX Emergency ABL defeat 0 HEX Bright ABL threshold 0 HEX Test registers 1, 2, 3 0 HEX Black strech defeat 1 HEX Blanking defeat 0 HEX No. 5841-10/39 time ≥ 2ms 3.0VDC ON/OFF =0 6.3VDC Initialize TR1 to TR2 ON/OFF =1 Initialize TR3 to TR31 7.3VDC After Standby Vcc reaches 3.0VDC, the microcontroller has to wait 2ms in order to intitialize the HC Interface in LA7615. Registers (TR3-TR31) Run.Vcc stable Pon BIT (STATUS) XRP BIT (STATUS) Video.Mute BIT Registers (TR1-TR2) ON/OFF BIT Standby Vcc Mute =0 A10053 LA7615 Power Up Sequence <Reference> No. 5841-11/39 LA7615 Electrical Characteristics at Ta = 25°C, VCC = V2 = V17 = V32 = V60 = 7.6 V, ICC = I24 = 24 mA Parameter Symbol Conditions Ratings min typ Unit max [Circuit Voltages and Currents] Horizontal supply voltage HVCC IF power supplly current (V2) I2 (IFICC) Vertical supply current (V17) IF AGC : 5 V 7.2 7.6 8 V 28 43 58 mA I17 (DEFICC) 10 13 16 mA Video/chrominance supply current (V32) I32 (YCICC) 65 85 105 mA FM supply current (V60) I60 (FMICC) 5.5 8.5 11.5 mA [VIF Block] No signal AFT output voltage V14 With no input signal 2.8 3.8 4.8 Vdc No signal video output voltage V53 With no input signal 4.7 4.9 5.1 Vdc APC pull-in range (U) fPU After APC, PLL, and D/A converter adjustment 1 MHz APC pull-in range (L) fPL After APC, PLL, and D/A converter adjustment 1 MHz Maximum RF AGC voltage V4H CW = 91 dBµ, DAC = 0 Minimum RF AGC voltage V4L CW = 91 dBµ, DAC = 63 RF AGC Delay Pt (@DAC = 0) RFAGC0 DAC = 0 RF AGC Delay Pt (@DAC = 63) RFAGC63 DAC = 63 7.7 8.2 9.0 0 0.2 0.4 96 Vdc Vdc dBµ 86 dBµ Maximum AFT output voltage V14H CW = 93 dBµ, frequency change 6.2 6.5 7.6 Vdc Minimum AFT output voltage V14L CW = 93 dBµ, frequency change 0.5 0.9 1.2 Vdc Sf CW = 93 dBµ, frequency change 33 25 17 mV/kHz AFT detection sensitivity 4.5 MHz attenuation TRAP V100 kHz/V4.5 MHz –35 –32 dB Video output amplitude VO53 93 dBµ, 87.5% Video MOD 1.8 2 2.2 Vp-p V53TIP 93 dBµ, 87.5% Video MOD 2.4 2.6 2.8 Vdc 43 46 dBµ Synchronizing signal tip level Output –3 dB Input sensitivity VIN Vide/sync ratio (@100 dBµ) V/S 100 dBµ, 87.5% Video MOD 2.5 3 Differential gain DG 93 dBµ, 87.5% Video MOD 2 10 % Differential phase DP 93 dBµ, 87.5% Video MOD 2 10 deg Video signal-to-noise ratio S/N CW = 93 dBµ 920 kHz beat level I920 V3.58 MHz/V920 kHz 2.4 55 58 –57 dB –50 dB dB [SIF Block] [1st.SIF] 4.5 MHz conversion gain SGG 21 26 31 4.5 MHz output level SVO 91 96 101 dB First SIF maximum input SVM –1 0 +1 dB SOADJ 414 424 434 mVrms 50 dBµ 100k Hz [SIF Block] FM detection output voltage FM limiting sensitivity SLS FM detector output bandwidth SF FM detector output distortion STHD AM rejection ratio SAMR 40 dB SSN 74 dB SIF. Signal-to-noise ratio 50 1 % [Chrominance Block] ACC amplitude characteristics 1 ACCM1 Input: +6 dB/0 dB, 0 dB = 40 IRE 0.8 1.0 1.2 times ACC amplitude characteristics 2 ACCM2 Input: –14 dB/0 dB 0.8 1.0 1.1 times B-Y/Y amplitude ratio CLRBY 75 100 120 % Color control characteristics 1 CLRMN Color: max/normal 1.7 2.0 2.3 times Color control characteristics 2 CLRMN Color: max/min 33 40 50 dB Color control sensitivity CLRSE 1 2 4 %/bit Tint center TINCEN TINT NOM –10 +5 deg Tint control max TINMAX TINT max 30 45 60 deg Tint control min TINMIN TINT min –60 –45 –30 deg Tint control sensitivity TINSE 0.7 2.0 deg/bit Demodulated output ratio: B-Y/R-Y BR 1.06 1.19 Demodulated output ratio: G-Y/R-Y GR 0.34 0.40 1.32 0.46 Continued on next page. No. 5841-12/39 LA7615 Continued from preceding page. Parameter Symbol Conditions Ratings min typ Unit max Demodulation angle B-Y/R-Y ANGBR 99 104 109 deg Demodulation angle G-Y/R-Y ANGGR –146 –136 –127 deg –32 –26 Killer operating point KILL Chrominance VCO free-running frequency CVCOF Chrominance pull-in range (+) PULIN+ Chrominance pull-in range (–) PULIN– 0 dB = 40IRE Deviation from 3.579545 MHz –250 –22 dB +250 Hz –350 Hz 350 Hz Auto Flesh characteristics: 73° AF073 8 20 30 deg Auto Flesh characteristics: 118° AF118 –7 0 +7 deg Auto Flesh characteristics: 163° AF163 –30 –20 –8 deg Overload characteristics 1 OVL1 3.2 4.7 Overload characteristics 2 OVL2 4.2 6.8 Overload characteristics 3 OVL3 4.5 8.5 [Chrominance Bandpass Filter Block] Peaking amplitude characteristics: 3.08 MHz CPE308 Referenced to 3.48 MHz –5 –3 –1 dB Peaking amplitude characteristics: 3.88/3.28 MHz CPE Referenced to 3.28 MHz –0.5 +1.5 +3.5 dB Peaking amplitude characteristics: 4.08/3.08 MHz CPE05 Referenced to 3.08 MHz –5.0 2.5 –1 dB Bandpass amplitude characteristics: 3.08 MHz CBP308 Referenced to 3.48 MHz –5 –3 –1 dB Bandpass amplitude characteristics: 3.88/3.28 MHz CBP Referenced to 3.28 MHz –2 0 +2 dB Bandpass amplitude characteristics: 4.08/3.08 MHz CBP05 Referenced to 3.08 MHz –2.5 0 +2.5 dB [Video Block] Video overall gain (at maximum contrast) CONT63 10 12 14 dB Contrast adjustment characteristics (normal/max) CONT32 –7.5 –6.0 –4.5 dB Contrast adjustment characteristics (min/max) CONT0 –15 –12 –9 dB Yf03 –6.0 –3.5 0.0 dB dB Video frequency characteristics: f0 = 3 Chrominance trap level: f0 = 0 DC restoration Luminance delay: f0 = 1 Maximum black stretch gain Black stretch threshold (40 IRE ∆black) Sharpness variation range –23 –15 ClampG 95 100 105 % YDLY 480 505 530 ns BKSTmax 12 16 20 IRE BKSTTH –2 0 +2 IRE Ctrap (normal) Sharp16 4 6 8 dB (max) Shaprp31 9.0 11.5 14.0 dB Shapr0 –6.0 –3.5 –1.0 dB RGBBLK 1.4 1.7 2.0 V (min) Horizontal/vertical blanking output level [OSD Block] FSTH 1.7 1.9 2.2 V RGB output level: red ROSDH 120 165 200 IRE RGB output level: green GOSDH 70 120 140 IRE RGB output level: blue BOSDH 85 120 155 IRE Analog OSD output level RRGB 1.12 1.4 1.68 Ratio LRRGB 45 50 60 OSD fast switch threshold Gain matching Linearity % Continued on next page. No. 5841-13/39 LA7615 Continued from preceding page. Parameter Symbol Analog OSD green output level Gain matching Linearity Ratings min typ Unit max GRGB 0.8 1.0 1.2 LGRGB 45 50 60 % BRGB 0.8 1.0 1.2 Ratio LBRGB 45 50 60 % Analog OSD blue output level Gain matching Linearity Conditions Ratio [RGB Output (cutoff and drive) Block] Brightness control (normal) BRT32 2.0 2.35 2.7 V High brightness (max) BRT63 15 20 25 IRE Low brightness (min) BRT60 –25 –20 –5 IRE Vbias0 1.6 2.0 2.4 V Vbias128 2.8 3.2 3.6 V Cutoff control (min) (bias control) (max) Cutoff contrad Resolution Vbiassns 3 4 6 mV/bit Sub-bias control resolution Vsbiassns 160 220 280 mV/bit RGBout63 2.4 3.0 3.6 Vp-p RGBout0 7 9 11 dB 10 15 IRE 15.634 15.734 15.834 kHz Drive adjustment: maximum output Output attenuation [Deflection Block] Sync separator circuit sensitivity Ssync ∆fH Horizontal free-running frequency deviation ±400 Hz Horizontal pull-in range fH PULL Horizontal output pulse width @0 Hduty0 ON time, Hduty : 0 36.0 37.5 39.0 µs Horizontal output pulse width @1 Hduty1 ON time, Hduty : 1 34.3 35.8 37.5 µs Horizontal output pulse width @2 Hduty2 ON time, Hduty : 2 32.5 34.0 35.5 µs Horizontal output pulse width @3 Hduty3 ON time, Hduty : 3 30.5 32.0 33.5 µs Horizontal output pulse saturation voltage VHsat Horizontal output pulse phase Horizontal position adjustment range Horizontal position adjustment maximum variation 9.5 HPHCEN HPHrange 4 bits 10.5 0.4 V 11.5 µs 350 ns ±2 HPHstep µs X-ray protection circuit operating voltage VXRAY 2.7 3.0 3.3 V POR circuit operating voltage VPOR 5.5 6.3 6.7 V [Vertical Screen Size Adjustment] Vertical ramp output amplitude @64 Vsize64 VSIZE : 1000000 1.44 1.74 2.04 Vp-p Vertical ramp output amplitude @0 Vsize0 VSIZE : 0000000 0.72 1.02 1.32 Vp-p Vsize127 VSIZE : 1111111 2.14 2.44 2.64 Vp-p VCOMP : 11 0.96 0.97 0.98 ratio Vertical ramp output amplitude @127 [High Voltage Dependency Vertical Size Correction] Vertical size correction @3 Vsizecomp [Vertical Screen Position Adjustment] Vertical ramp DC voltage @32 Vdc32 VDC : 1000000 3.686 3.876 4.484 Vdc Vertical ramp DC voltage @0 Vdc0 VDC : 0000000 3.344 3.557 3.762 Vdc Vertical ramp DC voltage @63 Vdc63 VDC : 1111111 4.104 4.294 4.484 Vdc Vlin8 VLIN : 1000 0.93 0.985 1.04 ratio Vertical linearity @0 Vlin0 VLIN : 0000 0.77 0.84 0.92 ratio Vertical linearity @15 Vlin15 VLIN : 1111 1.13 1.18 1.25 ratio Vertical S-curve correction @8 VScor8 VS : 1000 0.77 0.84 0.92 ratio Vertical S-curve correction @0 VScor0 VS : 0000 0.92 1.00 1.08 ratio Vertical S-curve correction @15 VScor15 VS : 1111 0.62 0.72 0.78 ratio Vertical linearity @8 Continued on next page. No. 5841-14/39 LA7615 Continued from preceding page. Parameter Symbol Conditions Ratings min typ max Unit [Horizontal Size Adjustment] East/west DC voltage @16 EWdc16 EWDC : 10000 3.60 4.00 4.40 Vdc East/west DC voltage @0 EWdc0 EWDC : 00000 2.70 3.05 3.40 Vdc East/west DC voltage @31 EWdc31 EWDC : 11111 4.80 5.10 5.40 Vdc [Pin cushion Distortion Correction] East/west parabola amplitude @8 EWamp8 EWAMP : 1000 0.58 0.73 0.88 Vp-p East/west parabola amplitude @0 EWamp0 EWAMP : 0000 0.15 0.30 0.45 Vp-p East/west parabola amplitude @15 EWamp15 EWAMP : 1111 0.95 1.15 1.35 Vp-p East/west parabola tilt @8 EWtilt4 EWTILT : 1000 –0.14 0 +0.14 V East/west parabola tilt @0 EWtilt0 EWTILT : 0000 –0.37 –0.23 –0.09 V East/west parabola tilt @15 EWtilt7 EWTILT : 1111 0.09 0.23 0.37 V [Trapezoidal Distortion Correction] [Corner Distortion Correction] East/west parabola corner, top EWcorTOP CORTOP : 111-000 0.15 0.25 0.35 V East/west parabola corner, bottom EWcorTOP CORBOTTOM : 111-000 0.15 0.25 0.35 V [Sandcastle Output] Burst gate pulse peak value VBGP 5.0 5.7 6.5 V Burst gate pulse phase TdBGP 4.6 5.1 5.6 µs Burst gate pulse width PWBGP 2.35 2.85 3.35 µs VBLK 3.4 3.9 4.4 V Blanking pulse peak value [D/A Converter Output] Pin 30 D/A converter voltage @0 VDAC0 +B TRIM : 0000 2.75 3.00 3.25 V Pin 30 D/A converter voltage @8 VDAC8 +B TRIM : 1000 3.15 3.40 3.65 V Pin 30 D/A converter voltage @15 VDAC15 +B TRIM : 1111 3.55 3.80 4.05 V Circuit Voltage and Current Test Conditions at Ta = 25°C, VCC = V2 = V17 = V32 = V60 = 7.6 V, ICC = I24 = 24 mA Parameter Symbol Test point Input signal Test procedure Bus condition [Circuit Voltage and Current] Horizontal supply voltage HVCC IF current drain (pin 2) I2 (IFICC) Vertical current drain (pin 17) I17 (DEFICC) Video, chrominance, current drain (pin 32) FM power supply current (pin 60) Apply a 24-mA current to pin 24 and measure Initial the voltage on pin 24 at that time. 24 Apply 7.6 V to pin 2 and measure the DC current (in mA) that flows into the IC. (With 5 V applied to the IF AGC) Initial 17 Apply 7.6 V to pin 17 and measure the DC current (in mA) that flows into the IC. Initial I32 (YCVCC) 32 Apply 7.6 V to pin 32 and measure the DC current (in mA) that flows into the IC. Initial I60 (FMVCC) 60 Apply 7.6 V to pin 60 and measure the DC current (in mA) that flows into the IC. Initial 2 No signal No signal No. 5841-15/39 LA7615 VIF Block - Input Signals and Test Conditions 1. All input signals are input to VIF IN in the test circuit diagram. 2. The input signal voltages are all taken to be the voltage at VIF IN in the test circuit diagram. 3. The signals and their levels are as follows. Input signal Input signal Waveform Condition SG1 45.75 MHz CW A10054 SG2 42.17 MHz CW A10055 SG3 41.25 MHz CW A10056 SG4 Variable frequency CW A10057 SG5 45.75 MHz 87.5% video modulation 10-step waveform (subcarrier: 3.58 MHz) A10058 SG6 45.75 MHz 40 IRE 87.5% video modulation 50 IRE Sweep signal (APL: 50 IRE, sweep signal level: 40 IRE) A10059 SG7 45.75 MHz 87.5% video modulation 100 IRE Flat field signal A10060 4. Before testing, adjust the D/A converter in the order presented below. Parameter Test point Input signal Adjustment APC DAC 14 No signal, with pin 11 connected to ground Set the pin 14 DC voltage to be as close to 3.8 V as possible. PLL DAC 14 SG1, 93 dBµ Set the pin 14 DC voltage to be as close to 3.8 V as possible. Video level DAC 53 SG7, 93 dBµ Set the pin 53 output level to be 2.0 ±0.2 Vpp. Trap 53 SG6, 93 dBµ Lower the D/A converter from its maximum (15) and set the circuit so that the 4.5 MHz component is at least –32 dB below the 100 kHz component. No. 5841-16/39 LA7615 (Test Conditions) Parameter Symbol Test point Input signal Test procedure Bus condition [VIF Block] No signal AFT output voltage V14 14 No signal Connect the pin 11 to ground and measure the pin 14 DC voltage. The adjusted values from item 4. No signal video output voltage V53 53 No signal Connect the pin 11 to ground and measure the pin 53 DC voltage. The adjusted values from item 4. Monitor pin 53 with an oscilloscope, and modify SG4 to have a frequency higher than 45.75 MHz so that the PLL goes to the unlocked state. (Beating should appear at this point.) Gradually decrease the SG4 frequency until the PLL circuit locks, and measure the lock frequency. Also, and modify SG4 to have a frequency lower than 45.75 MHz so that the PLL goes to the unlocked state. Gradually increase the SG4 frequency until the PLL circuit locks, and measure the lock frequency. The adjusted values from item 4. 53 SG4 93 dBµ APC pull-in range (U), (L) fPU, fPL Maximum RF AGC voltage V4H 4 SG1 91 dBµ Set the RF AGC D/A converter to 0 and measure the The adjusted values pin 4 DC voltage. from item 4. Minimum RF AGC voltage V4L 4 SG1 91 dBµ Set the RF AGC D/A converter to 63 and measure the pin 4 DC voltage. The adjusted values from item 4. Video output amplitude VO53 53 SG7 93 dBµ Monitor the pin 53 with an oscilloscope, and measure the peak-to-peak value of the waveform. The adjusted values from item 4. RF AGC Delay Pt (@DAC = 0) RFAGC0 4 SG1 Set the RF AGC D/A converter to 0 and determine the input level such that the pin 4 DC voltage becomes 3.8 ±0.5 V. The adjusted values from item 4. RF AGC Delay Pt (@DAC = 63) RFAGC63 4 SG1 Set the RF AGC D/A converter to 63 and determine the input level such that the pin 4 DC voltage becomes 3.8 ±0.5 V. The adjusted values from item 4. Input sensitivity VIN 53 SG7 Monitor the pin 53 with an oscilloscope, and measure the peak-to-peak value of the waveform. The adjusted values Gradually decrease the input level and determine the from item 4. input level such that the output goes down to a level lower than the video amplitude (VO 53) by –3 dB. Video/Sync ratio (@100 dBµ) V/S 53 SG7 100 dBµ Monitor the pin 53 with an oscilloscope, and measure the peak-to-peak values of the sync waveform (Vs) and the luminance signal (Vy) to determine the ratio Vy/Vs. The adjusted values from item 4. Differential gain DG 53 SG5 93 dBµ Measure the pin 53 with a vectorscope. The adjusted values from item 4. Differential phase DP 53 SG5 93 dBµ Measure the pin 53 with a vectorscope. The adjusted values from item 4. Video signal-to-noise ratio S/N 53 SG1 93 dBµ Pass the noise voltage signal generated at pin 53 The adjusted values through a 4 to 10 MHz bandpass filter and measure that signal(Vsn) with an rms voltmeter. Determine the from item 4. value of the formula 20log(1.43/Vsn). Synchronizing signal tip level V53 TIP 53 SG1 93 dBµ Measure the pin 53 DC voltage. The adjusted values from item 4. 4.5 MHz attenuation TRAP 53 SG6 93 dBµ Measure the values of the 100 kHz and 4.5 MHz components and determine their ratio. The adjusted values from item 4. 920 kHz beat level I920 53 SG1 SG2 SG3 Input the 93 dBµ SG1 signal, and measure the pin 11 DC voltage (V11). Mix the three signals SG1 = 87 dBµ, SG2 = 82 dBµ, and SG3 = 63 dBµ, and input The adjusted values that signal to VIF IN. Apply the voltage V11 to pin 11 from item 4. using an external power supply. Measure the difflerence of the 3.58 MHz and 920 kHz components using a spectrum analyzer. Maximum AFT output voltage V14H 14 SG4 93 dBµ 44.75 MHz Measure the pin 14 DC voltage. Minimum AFT output voltage V14L 14 SG4 93 dBµ 46.75 MHz Measure the pin 14 DC voltage. AFT detection sensitivity Sf 14 SG4 93 dBµ Gradually change the SG4 frequency and determined the frequency change ∆f required to change the pin 14 DC voltage from 2.5 V to 5.0 V. Sf = 2500/∆f [mV/kHz] No. 5841-17/39 LA7615 First SIF Block - Input Signals and Test Conditions For each of the test items, set up the following conditions unless otherwise specified. 1. PIF.IN: 45.75 MHz, 93 dBµ, CW 2. Bus control conditions: Set the following 4 items to their adjusted values. (See the VIF block test description for details on the adjustment procedure.) • APC DET.ADJ • PLL tuning • 4.5 MHz trap • Video level 3. Apply the input signal to the pin 12, using a signal with a frequency of 41.25 MHz CW. Parameter Symbol Test point Input signal Test procedure 4.5 MHz conversion gain SCG 59 60 dBµ Measure the pin 59 output 4.5 MHz component (mV rms). Let SV1 be this measured value and perform the following calculation. SCG = 20 × log(SV1 × 1000) – 60 [dB] 4.5 MHz output level SVO 59 88 dBµ Measure the pin 59 output 4.5 MHz component (mV rms). Let SV2 be this measured value and perform the following calculation. SCO = 20 × log(SV2 × 1000) [dB] First SIF maximum input SVM 59 96 dBµ Measure the pin 59 output 4.5 MHz component (mV rms). Let SV3 be this measured value and perform the following calculation. SCM = 20 × log(SV3/SV1) [dB] Bus condition SIF Block - Input Signals and Test Conditions For each of the test items, set up the following conditions unless otherwise specified. 1. Connect pin 13 (SIF AGC) to ground. 2. Bus control conditions: IF.AGC.SW = 1. 3. SW:IF1 = off 4. Apply the input signal to pin 61. The carrier frequency should be 4.5 MHz. Parameter Symbol Test point Input signal Test procedure Bus condition FM detector output voltage SOADJ 5 90 dBµ, fm = 1 kHz, FM = ±25 kHz Adjust the D/A converter (FM.LEVEL) so that the pin 5 FM detector output 1 kHz component is as close to 424 mV rms as possible. Measure the output (mV rms) at that time. Let SV1 be the measured value at this time. FM limiting sensitivity SLS 5 fm = 1 kHz, FM = ±25 kHz Determine the input level (dBµ) such that the pin 5 FM detector output 1 kHz component is down –3 dB from SV1. FM.LEVEL = adjusted value. FM detector output bandwidth SF 5 90 dBµ, FM ±25 kHz Determine the modulation frequency bandwidth (Hz) for a –3 dB drop in the pin 5 FM detector output 1 kHz component with respect to SV1. FM.LEVEL = adjusted value. FM detector output distortion STHD 5 90 dBµ, fm = 1 kHz, FM ±25 kHz 5 90 dBµ, fm = 1 kHz, AM = 30% Measure (in mV rms) the pin 5 FM detector output 1 kHz component. Let SV2 be the measured value at this time and perform the following calculation. SAMR = 20 × log(SV1/SV2) [dB] FM.LEVEL = adjusted value. 90 dBµ, CW Set the SW:IF1 switch to the on state. Measure the noise level (mV rms) on pin 5. Let SV3 be the measured value at this time and perform the following calculation. SSN = 20 × log(SV1/SV3) [dB] FM.LEVEL = adjusted value. AM rejection ratio SIF signal-to-noise ratio SAMR SSN 5 Determine the distortion in the pin 5 FM detector output 1 kHz component. FM.LEVEL = adjusted value. No. 5841-18/39 LA7615 Video Block - Input Signals and Test Conditions [Input Signals] <CIN input signal> *: chrominance burst signal: 40 IRE <YIN input signal> 0 IRE signal (L-0): NTSC standard synchronizing signal [ 100 IRE : 714 mV ] Pedestal level H SYNC 4.7 µs (H/V SYNC : 40 IRE : 286 mV) A10061 X IRE signal (L-X) X IRE (X = 0 to 100) 0 IRE A10062 CW signal (L-CW) 20 IRE CW signal 50 IRE A10063 Black stretch 0 IRE signal (L-BK) 50 µs 100 IRE 5 µs (Point A) A10064 <R/G/B IN input signal> RGB input signal 1 (O-1) 20 µs each 0.7 V A B 0.35 V 0.0 VDC A10065 RGB input signal 2 (O-2) 20 µs 30 µs 1.0 VDC 0.0 VDC A10066 No. 5841-19/39 LA7615 (Test Conditions) Parameter Symbol Test point Input signal Test procedure Bus bits/input signal [Video Block] Overall video gain (at maximum contrast) CONT63 38 L-50 Measure the output signal 50 IRE amplitude (CNTHB TR24: Contrast Vp-p) and calculate CONT63 = 20log(CNTHB/0.357). 111111 Contrast adjustment characteristics (normal/max) CONT32 38 L-50 Measure the output signal 50 IRE amplitude (CNTCB Vp-p) and calculate CONT32 = 20log(CNTCB/0.357). Contrast adjustment characteristics (normal/max) CONT0 38 L-50 Measure the output signal 50 IRE amplitude (CNTLB Vp-p) and calculate CONT0 = 20log(CNTLB/0.357). TR24: Contrast 000000 Video frequency characteristics f0 = 1 (sharp 0) Yf03 L-CW With the input signal CW = 100 kHz, measure the amplitude of the CW signal in the output signal (PEAKDC Vp-p). TR26: F0 Adjust 01 With the input signal CW = 10 MHz, measure the amplitude of the CW signal in the output signal (F03 Vp-p). TR26: F0 Adjust 11 TR25: Sharpness 01111 38 f0 = 3 (sharp 15) Calculate Yf3 = 20log(F03/PEAKDC). Chrominance trap level f0 = 0 (sharp 0) Ctrap 38 L-CW With the input signal CW = 3.58 MHz, measure the amplitude of the CW signal in the output signal (F00 Vpp). TR26: F0 Adjust 00 Calculate Ctrap = 20·log(F00/PEAKDC). ClampG DC restoration Luminance delay f0 = 1 Maximum black stretch gain YDLY BKSTmax L-0 Measure the output signal 0 IRE DC level (BRTPL (V)). TR23: Brightness 000000 TR24: Contrast 111111 L-100 Measure the output signal 0 IRE DC level (DRVPH (V)) and the 100 IRE amplitude (DRVH Vpp). Calculate ClampG = 100 × (1 + (DRVPH – BRTPL)/DRVH)). TR23: Brightness 000000 TR24: Contrast 111111 L-50 Measure the time difference (amount of delay) between the rise of the input signal 50 IRE amplitude, and rise of the output signal 50 IRE amplitude. 38 38 38 L-BK Measure the 0 IRE DC level at point A in the output signal when the black stretch function is defeated (black stretch off). (BKST1 (V)) TR31: BKST Defeat 1 Measure the 0 IRE DC level at point A in the output signal when the black stretch function is on. (BKST2 (V)) TR31: BKST Defeat 0 Calculate BKSTmax = 2 × 50 × (BKST1 – BKST2)/CNTHB. Black stretch threshold ∆black(40 IRE ∆black) BKSTTH∆ 38 L-40 Measure the 40 IRE DC level in the output signal when the black stretch function is on. (BKST3 (V)) TR31: BKST Defeat 0 Measure the 40 IRE DC level in the output signal when the black stretch function is defeated (black stretch off). (BKST4 (V)) TR31: BKST Defeat 1 Calculate BKSTTH∆ = 50 × (BKST4 – BKST3)/CNTHB. Sharpness (peaking) variability characteristics (normal) L-CW Sharp16 With the input signal CW = 2.2 MHz, measure the amplitude of the CW signal in the output signal (F00S16 Vp-p). TR26: F0 Adjust 00 TR25: Sharpness 10000 Calculate Sharp16 = 20log(F00S16/PEAKDC). (maximum) Sharp31 38 L-CW With the input signal CW = 2.2 MHz, measure the amplitude of the CW signal in the output signal (F00S31 Vp-p). TR25: Sharpness 11111 Calculate Sharp31 = 20log(F00S31/PEAKDC). (minimum) L-CW Sharp0 With the input signal CW = 2.2 MHz, measure the amplitude of the CW signal in the output signal (F00S0 Vp-p). TR25: Sharpness 00000 Calculate Sharp0 = 20log(F00S0/PEAKDC). Horizontal/vertical blanking output level RGBBLK 38 L-100 Measure the DC level of the output signal during the blanking period (RGBBLK (V)). Continued on next page. No. 5841-20/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Bus bits/input signal [OSD Block] OSD fast switching threshold FSTH ROSDH RGB red output level 38 36 L-0 O-2 Gradually increase the pin 39 voltage starting at 1.5 V, and determine the pin 39 voltage at the point where the output signal switches to the OSD signal. L-50 Measure the 50 IRE amplitude in the output signal. (CNTCR Vp-p). L-0 O-2 Measure the OSD output amplitude (OSDHR Vp-p). Pin 42: Apply signal O-2. Pin 39: Apply 3.5 V. Pin 40: Apply signal O-2. Calculate ROSDH = 50 × (OSDHR/CNTCR). RGB green output level GOSDH 37 L-50 Measure the 50 IRE amplitude in the output signal. (CNTCG Vp-p). L-0 O-2 Measure the OSD output amplitude (OSDHG Vpp). Pin 39: Apply 3.5 V. Pin 41: Apply signal O-2. Calculate GOSDH = 50 × (OSDHG/CNTCG). BOSDH RGB blue output level 38 L-50 Measure the 50 IRE amplitude in the output signal. (CNTCB Vp-p). L-0 O-2 Measure the OSD output amplitude (OSDHB Vp-p). L-0 O-1 Measure the amplitudes at point A (the 0.35 V component of the input signal O-1) and point B (the 0.7 V component of the input signal O-1) in the output signal and record these as RGBLR and RGBHR (Vp-p) respectively. Pin 39: Apply 3.5 V. Pin 42: Apply signal O-2. Calculate BOSDH = 50 × (OSDHB/CNTCB). 36 Analog OSD red output level Gain matching RRGB Linearity LRRGB Analog OSD green output level Calculate RRGB = RGBLR/CNTCR. Calculate LRRGB = 100 × (RGBLR/RGBHR). 37 L-0 O-1 Measure the amplitudes at point A (the 0.35 V component of the input signal O-1) and point B (the 0.7 V component of the input signal O-1) in the output signal and record these as RGBLG and RGBHG (Vp-p) respectively. Gain matching GRGB Calculate GRGB = RGBLG/CNTCG. Linearity LGRGB Calculate LGRGB = 100 × (RGBLG/RGBHG). 38 Analog OSD blue output level Pin 39: Apply 3.5 V. Pin 40: Apply signal O-1. L-0 O-1 Measure the amplitudes at point A (the 0.35 V component of the input signal O-1) and point B (the 0.7 V component of the input signal O-1) in the output signal and record these as RGBLB and RGBHB (Vp-p) respectively. Gain matching BRGB Calculate BRGB = RGBLB/CNTCB. Linearity LBRGB Calculate LBRGB = 100 × (RGBLB/RGBHB). Pin 39: Apply 3.5 V. Pin 34: Apply signal O-1. Pin 39: Apply 3.5 V. Pin 41: Apply signal O-1. [RGB Output Block] (Cutoff and Drive Blocks) 36 Brightness control (normal) BRT32 37 38 (maximum) BRT63 BRT0 Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as BRTPCR, BRTPCG, and BRTPCB (V), respectively. TR24: Contrast 111111 Calculate BRT63 = (BRTPCR + BRTPCG + BRTPCB)/3. Measure the output signal 0 IRE DC level of the B output (pin 38) (BRTPHB). 38 (minimum) L-0 TR23: Brightness 111111 Calculate BRT63 = 50 × (BRTPHB – BRTPCB) / CNTHB. Measure the output signal 0 IRE DC level of the B output (pin 38) (BRTPLB). TR23: Brightness 000000 Calculate BRT0 = 50 × (BRTPLB – BRTPCB) / CNTHB. Continued on next page. No. 5841-21/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Bus bits/input signal Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as Vbias0* (V), where * : R, G, and B, respectively. TR24: CONTRAST 111111 TR22: SUB-BIAS R, G, B 000000 [RGB Output Block] (Cutoff and Drive Blocks) Bias (cutoff) control (minimum) (maximum) Vbias0 L-50 Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as Vbias128* (V), where * : R, G, and B, respectively. Vbias128 Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as BAS80* (V), where * : R, G, and B, respectively. Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as BAS48* (V), where * : R, G, and B, respectively. TR16: R BIAS 0110000 TR17: G BIAS 0110000 TR18: B BIAS 0110000 TR24: CONTRAST 11111 38 Bias (cutoff) control resolution TR18: B BIAS 111111 TR24: CONTRAST 111111 TR22: SUB-BIAS R, G, B 111111 TR16: R BIAS 1010000 TR17: G BIAS 1010000 TR18: B BIAS 1010000 TR24: CONTRAST 111111 36 37 TR16: R BIAS 111111 TR: G BIAS 111111 Vbiassns Vbiassns * = (BAS80 * – BAS48 *)/32 Sub-bias control resolution Vsbiassns L-50 Measure the output signal 0 IRE DC levels of the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as SBTPM* (V), where * : R, G, and B, respectively. TR22: SUB-BIAS R, G, B 101010 Vsbiassns * = (BRTPC * – SBTPM *) Maximum drive adjustment output Measure the output signal 100 IRE DC amplitudes of TR24: CONTRAST 111111 the R output (pin 36), G output (pin 37), and B output (pin 38) and record these as DRVH* (Vpp), where * : TR23: Brightness 000000 R, G, and B, respectively. RGBout63 36 37 Output attenuation RGBout0 38 L-100 TR24: CONTRAST 111111 TR23: Brightness 000000 Measure the output signal 100 IRE DC amplitudes of the R output (pin 36), G output (pin 37), and B output TR19: R DRIVE 000000 (pin 38) and record these as DRVL* (Vpp), where * : TR20: G DRIVE R, G, and B, respectively. 000000 TR21: B DRIVE 000000 RGBout0 * = 20 log(DRVH */DRVL *) No. 5841-22/39 LA7615 Chrominance Block - Input Signals and Test Conditions For each of the test items, set up the following conditions unless otherwise specified. 1. VIF and SIF blocks: No signal 2. Deflection block: Input a horizontal/vertical composite sync signal and verify that the deflection block is locked on the synchronizing signal. (See the section on input signals and test conditions for the deflection block.) 3. Bus control conditions: All conditions set to their initial values, unless otherwise specified. 4. Connect a crystal oscillator circuit to pin 16. Adjust the impedance (Z) of the series capacitance and resistance as shown below. Z = 0 deg @ 3.579545 MHz ±10 Hz –40 ±1 deg @3.579345 MHz 5. Luminance (Y) input: No signal 6. Chrominance (C) input: Input the signal to the C1IN pin (pin 51). 7. The method for calculating the demodulation angle is shown below. B-Y axis angle = tan – 1 (B(0)/B(270)) + 270° R-Y axis angle = tan – 1 (R(180)/R(90)) + 90° G-Y axis angle = tan – 1 (G(270)/G(180)) + 180° R-Y axis 90° R (90) R (180) B (270) 0° 180° B (0) G (180) B-Y axis G (270) 270° G-Y axis A10067 8. The method for calculating the AF angle is shown below. BR · · · · The B-Y/R-Y demodulation output ratio θ · · · · · · ANGBR: the B-Y/R-Y demodulation angle AFXXX = tan – 1 R – Y/B – Y × BR – Cosθ ——————————— Sinθ No. 5841-23/39 LA7615 [Input Signal] C-1 40 IRE Burst 0° 90° 180° 270° 3.58 MHz A10068 77IRE X IRE signal (L-X) 0 IRE A10069 40IRE 62.5IRE Burst 3.58 MHz 364° C-2 A10070 C-3 40 IRE Burst 3.48 MHz (However, when a frequency is specified, that frequency is to be used.) CW A10071 C-4 40 IRE 28° 73° 118° 163° A10072 35 µs C-5 Burst 3.48 MHz Chroma A10073 No. 5841-24/39 LA7615 (Test Conditions) Parameter Symbol Test point Input signal Test procedure Bus condition [Chrominance Block] C-1 0 dB +6 dB Measure the output amplitude when the chrominance input is set to 0 dB and the output amplitude when the input is reduced by – 6 dB, and calculate the ratio. ACCM1 = 20log(+6 dB data/0 dB data) C-1 –14 dB Measure the output amplitude when the chrominance input is set to –14 dB and calculate the ratio. ACCM2 = 20log(–14 dB data/0 dB data) YIN: L77 C-1: No signal Measure the luminance (Y) output level(V1). C-2 Next, apply a signal to the CIN input (with only a sync applied to the Y input) and measure the output level (V2). Calculate the following formula. CLRBY = 100 × (V2/V1) +15% C-3 Measure V1: the output amplitude when the color control is maximum, and V2: the output amplitude when the color control is normal (Color control: 1000000) and calculate CLRMN = V1/V2. TR28: Color Control 1111111 C-3 Measure V3: the output amplitude when the color control is minimum and calculate CLRMM = 20·log(V1/V3). TR28: Color Control 0000000 TR28: Color Control 1011010 Color Ctontrol 0100110 Bout ACC amplitude characteristics 1 ACCM1 38 Bout ACC amplitude characteristics 2 B-Y/Y amplitude ratio Color control characteristics 1 Color control characteristics 2 ACCM2 CLRBY CLRMN CLRMM 38 38 38 38 1000000 Color control sensitivity CLRSE 38 C-3 Measure V4: the output amplitude when the color control is 90, and V5: the output amplitude when the color control is 38. Calculate the following formula. CLRSE = 100 × (V4 – V5) / (V2 × 52) Tint center TINCEN 38 C-1 Measure each section of the output waveform and calculate the angle of the B-Y axis. TR27: TINT 0111111 TR27: TINT 1111111 Tint control (max) TINMAX 38 C-1 Measure each section of the output waveform and calculate the angle of the B-Y axis. Calculate the following formula. TINMAX = (the B-Y axis angle) – TINCEN Tint control (min) TINMIN 38 C-1 Measure each section of the output waveform and calculate the angle of the B-Y axis. Calculate the following formula. TINMIN = (the B-Y axis angle) – TINCEN TR27: TINT 0000000 Tint control sensitivity TINSE 38 C-1 Measure A1: the angle when the tint control is 85, and A2: the angle when the tint control is 42. Calculate the following formula. TINSE = (A1 – A2)/43 TR27: TINT 1010101 0101010 Demodulation output ratio B-Y/R-Y BR C-3 Measure Vb: the BOUT output amplitude and Vr: the ROUT output amplitude, and calculate BR = Vb/Vr. TR28: Color Control 1000000 Demodulation output ratio G-Y/R-Y GR C-3 Measure Vg: the GOUT output amplitude and calculate GR = Vg/Vr. TR28: Color Control 1000000 38 36 37 Continued on next page. No. 5841-25/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal 38 Demodulation angle B-Y/R-Y ANGBR Test procedure C-1 Measure the BOUT and ROUT output levels and calculate the angle between the B-Y and R-Y axes. Calculate ANGBR = (R-Y angle) – (B-Y angle). 36 Bus condition Demodulation angle G-Y/R-Y ANGGR 37 C-1 Measure the GOUT output level and calculate the angle between the G-Y and R-Y axes. Calculate ANGGR = (R-Y angle) – (G-Y angle). Killer operating point KILL 38 C-3 Gradually decrease the amplitude of the input signal and measure the input level when the output level falls less than 150 mVpp. Chrominance VCO free-running frequency CVCOF 16 CIN No signal Measure the oscillator frequency f and calculate the following formula. CVCOF = f – 3579545 (Hz) Chrominance pull-in range (+) PULIN+ 38 C-1 Gradually decrease the input signal subcarrier frequency starting at 3.579545 MHz + 1000 Hz, and measure frequency at the point the output waveform locks. Chrominance pull-in range (–) PULIN– 38 C-1 Gradually raise the input signal subcarrier frequency starting at 3.579545 MHz – 1000 Hz, and measure frequency at the point the output waveform locks. C-4 With Auto Flesh = 0, measure the level that corresponds to a BOUT and ROUT output waveform of 73° and calculate TR26: Auto Flesh : the angle AF073A. **** 0 ** With Auto Flesh = 1, measure the angle AF073B in the TR26: Auto Flesh : same manner. **** 1 ** Calculate the following formula. AF073 = AF073B – AF073A C-4 With Auto Flesh = 0, measure the level that corresponds to a BOUT and ROUT output waveform of 118° and calculate the angle AF118A. With Auto Flesh = 1, measure the angle AF118B in the same manner. Calculate the following formula. AF118 = AF118B – AF118A TR26: Auto Flesh : **** 0 ** TR26: Auto Flesh : **** 1 ** C-4 With Auto Flesh = 0, measure the level that corresponds to a BOUT and ROUT output waveform of 163° and calculate the angle AF163A. With Auto Flesh = 1, measure the angle AF163B in the same manner. Calculate the following formula. AF163 = AF163B – AF163A TR26: Auto Flesh : **** 0 ** TR26: Auto Flesh : **** 1 ** C-5 Measure V1: the output amplitude when the input signal burst level is set to 40 IRE and the chrominance level is set to 8 IRE, and V2: the output amplitude when the input signal burst level is set to 40 IRE and the chrominance level is set to 40 IRE. Calculate the following formula. OVL1 = V2/V1 38 Auto Flesh characteristics 73° AF073 36 38 Auto Flesh characteristics 118° AF118 36 38 Auto Flesh characteristics 163° AF163 36 Overload characteristics 1 OVL1 36 TR26: OverLoad : ****** 1 Continued on next page. No. 5841-26/39 LA7615 Continued from preceding page. Parameter Overload characteristics 2 Overload characteristics 3 Symbol OVL2 OVL3 Test point 36 36 Input signal Test procedure Bus condition C-5 Measure V3: the output amplitude when the input signal burst level is set to 40 IRE and the chrominance level is set to 80 IRE. Calculate the following formula. OVL2 = V3/V1 C-5 Measure V4: the output amplitude when the input signal burst level is set to 20 IRE and the chrominance level is set to 80 IRE. Calculate the following formula. OVL3 = V4/V1 C-3 Measure V0: the output amplitude. Next, set the input chrominance signal (CW) frequency to 3.08 MHz and measure V1: the output amplitude. Calculate the following formula. CPE308 = 20log(V1/V0) TR26: CHR.BPF: ***1*** TR26: CHR.BPF: ***1*** TR26: Overload ******1 TR26: Overload ******1 [Chrominance Bandpass Filter Characteristics] Peaking amplitude characteristics: 3.08 MHz CPE308 38 Peaking amplitude characteristics: 3.88/3.28 MHz CPE 38 C-3 Measure V2: the output amplitude when the input chrominance signal (CW) frequency is 3.28 MHz, and V3: the output amplitude when the input chrominance signal (CW) frequency is 3.88 MHz. Calculate the following formula. CPE = 20log(V3/V2) Peaking amplitude characteristics: 4.08/3.08 MHz CPE05 38 C-3 Measure V4: the output amplitude when the input chrominance signal (CW) frequency is 4.08 MHz. Calculate the following formula. CPE05 = 20log(V4/V1) TR26: CHR.BPF: ***1*** C-3 Measure V5: the output amplitude. Next, measure V6: the output amplitude when the input chrominance signal (CW) frequency is set to 3.08 MHz. Calculate the following formula. CPE308 = 20log(V6/V5) TR26: CHR.BPF: ***0*** C-3 Measure V7: the output amplitude when the input chrominance signal (CW) frequency is 3.28 MHz, and V8: the output amplitude when the input chrominance signal (CW) frequency is 3.88 MHz. Calculate the following formula. CPE = 20log(V8/V7) TR26: CHR.BPF: ***0*** C-3 Measure V9: the output amplitude when the input chrominance signal (CW) frequency is set to 4.08 MHz. Calculate the following formula. CPE05 = 20log(V9/V6) TR26: CHR.BPF: ***0*** Bandpass amplitude characteristics: 3.08 MHz Bandpass amplitude characteristics: 3.88/3.28 MHz Bandpass amplitude characteristics: 4.08/3.08 MHz CBE308 CBE CBE05 38 38 38 No. 5841-27/39 LA7615 Deflection Block - Input Signals and Test Conditions For each of the test items, set up the following conditions unless otherwise specified. 1. VIF and SIF blocks: No signal 2. Luminance (Y) input and chrominance (C) input: No signal 3. Sync input: Horizontal/vertical composite sync signal (DC offset: 3.8 V, 40 IRE. Other timing and other parameters must conform to the FCC broadcast standards.) Caution: There must be no burst or chrominance signal under the pedestal level. Signal inappropriate for use as a sync input Signal appropriate for use as a sync input Chrominance signal Burst signal A10074 4. Bus control conditions: All conditions set to their initial values, unless otherwise specified. 5. The delay time from the rise of the horizontal output (the pin 26 output) to the rise of the F.B.P IN (pin 27 input) must be 9 µs. 6. The pin 18 (the vertical size correction circuit input pin) voltage must be VCC (7.6 V). 7. Pin 28 (the x-ray protection circuit input pin) must be connected to ground. Notes: Perform the following operations if the horizontal output pulse signal was stopped. 1. Set the bus on/off bit to off (0) temporarily, and then set it to on (1) again. (If the x-ray protection circuit and/or the PON-RES circuit operate, an IC internal latch circuit will be set. The on/off bit must be set to off (0) to reset that latch circuit, even if the horizontal output signal is not output. Since the PONRES circuit operates when the horizontal supply voltage rises, the on/off bit must be set to off (0).) 2. Note on video muting If the horizontal output pulse signal was stopped, after performing the operation described in paragraph 1 above, clear the video muting bit to 0. (This is because the video muting bit is forcibly set to 1 when the on/off bit is set to 0 or when either the x-ray protection circuit or the PON-RES circuit operate. This also applies at power on.) No. 5841-28/39 LA7615 Parameter Symbol Test point Input signal Test procedure Bus condition [Deflection Block] Sync separator circuit sensitivity Horizontal free-running frequency deviation Horizontal pull-in range Ssync ∆fH fH PULL Horizontal output pulse width @0 Hduty 0 Horizontal output pulse width @1 Hduty 1 Horizontal output pulse width @2 Hduty 2 Horizontal output pulse width @3 Hduty 3 Horizontal output pulse saturation voltage VHsat SYNC IN: horizontal and vertical synchronizing signal Gradually decrease the level of the synchronizing signal input to SYNC IN (pin 44) and measure the level of the synchronizing signal when the synchronization is unlocked. 26 SYNC IN: no signal Connect the pin 26 output (Hout) to a frequency counter and measure the horizontal free-running frequency. Calculate the following formula. ∆fH = <measured value> – 15.743 kHz 44 SYNC IN: horizontal and vertical synchronizing signal Monitor the horizontal synchronizing signal input to SYNC IN (pin 44) and the pin 26 output (Hout) with an oscilloscope. Vary the frequency of the horizontal synchronizing signal and measure the pull-in range. 26 SYNC IN: horizontal and vertical synchronizing signal Measure the low-level period in the pin 26 horizontal pulse waveform. HDUTY: 00 26 SYNC IN: horizontal and vertical synchronizing signal Measure the low-level period in the pin 26 horizontal pulse waveform. HDUTY: 01 26 SYNC IN: horizontal and vertical synchronizing signal Measure the low-level period in the pin 26 horizontal pulse waveform. 26 SYNC IN: horizontal and vertical synchronizing signal Measure the low-level period in the pin 26 horizontal pulse waveform. 26 SYNC IN: horizontal and vertical synchronizing signal Measure the voltage during low-level period in the pin 26 horizontal pulse waveform. 44 HDUTY: 11 Measure the delay time from the rise of the pin 26 horizontal output pulse waveform to the fall of the SYNC IN horizontal synchronizing signal. Horizontal output pulse phase HPHCEN 26 44 SYNC IN: horizontal and vertical synchronizing signal HPHCEN 20 IRE Horizontal output 3.8V A10075 Continued on next page. No. 5841-29/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Bus condition Measure the delay time from the rise of the pin 26 horizontal output pulse to the fall of SYNC IN horizontal synchronizing signal with HPHASE set to both 0 and 15 and calculate the difference with respect to HPHCEN. Measurement Horizontal position adjustment range 26 HPHrange 44 SYNC IN: horizontal and vertical synchronizing signal HPHASE: 0000 HPHASE: 1111 20 IRE Horizontal output 3.8V A10076 Measure the delay time from the rise of the pin 26 horizontal output pulse to the fall of SYNC IN horizontal synchronizing signal while varying HPHASE from 0 to 15, and measure the amount of variation at each step. Find the step with the largest value of the data. Maximum horizontal position adjustment variability HPHstep 26 44 SYNC IN: horizontal and vertical synchronizing signal Measurement HPHASE: 0000 to HPHASE: 1111 20 IRE Horizontal output A10077 X-ray protection circuit operating VXRAY voltage 26 28 24 POR circuit operating voltage VPOR 26 SYNC IN: horizontal and vertical synchronizing signal Connect a DC voltage source to pin 28, and gradually increase that voltage starting at 0 V. Measure the pin 28 DC voltage at the point the pin 26 horizontal output pulse stops. SYNC IN: horizontal and vertical synchronizing signal Replace the current source connected to pin 24 with a DC voltage source, and gradually decrease the voltage starting at 7.3 V. Measure the pin 24 DC voltage at the point the pin 26 horizontal output pulse stops. [Vertical Screen Size Adjustment] Vertical ramp output amplitude @64 Vsize64 19 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line and at the 262nd line. Calculate the following formula. Vsize64 = Vline262 – Vline22 Vertical ramp output 262nd line 22nd line A10078 Continued on next page. No. 5841-30/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Bus condition Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line and at the 262nd line. Calculate the following formula. Vsize0 = Vline262 – Vline22 Vertical ramp output amplitude @0 Vsize0 19 SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output VSIZE: 0000000 262nd line A10079 22nd line Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line and at the 262nd line. Calculate the following formula. Vsize0 = Vline262 – Vline22 Vertical ramp output amplitude @127 Vsize127 19 SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output VSIZE: 1111111 262nd line 22nd line A10080 [High-Voltage Dependency Vertical Size Correction] Vertical size correction @7 (maximum) Vsizecomp 19 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line and at the 262nd line. Calculate Va from the following formula. Va = Vline262 – Vline22 Next, apply 3.8 V to pin 18, and once again measure the voltages at the 22nd line and at the 262nd line. Calculate Vb from the following formula. Vb = Vline262 – Vline22 Finally, calculate Vsizecomp from the following formula. Vsizecomp = (Va – Vb)/Va × 100 VCOMP: 111 [Vertical Screen Position Adjustment] Monitor the pin 19 vertical ramp output and measure the voltage at the 142nd line. Vertical ramp DC voltage @32 Vdc32 19 SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output 142nd line A10081 Monitor the pin 19 vertical ramp output and measure the voltage at the 142nd line. Vertical ramp DC voltage @0 Vdc0 19 SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output VDC: 000000 142nd line A10082 Continued on next page. No. 5841-31/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Bus condition Monitor the pin 19 vertical ramp output and measure the voltage at the 142nd line. Vertical ramp DC voltage @63 Vdc63 19 SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output VDC: 111111 142nd line A10083 Vertical linearity @8 Vlin8 19 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line, the 142nd line, and the 262nd line. Let Va, Vb, and Vc be these measurements, and calculate the following formula. Vline8 = (Vb – Va)/(Vc – Va) 262nd line Vertical ramp output 142nd line 22nd line Vertical linearity @0 Vlin0 19 SYNC IN: horizontal and vertical synchronizing signal A10084 Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line, the 142nd line, and the 262nd line. Let Va, Vb, and Vc be these measurements, and calculate the following formula. Vline0 = (Vb – Va)/(Vc – Va) 262nd line VLIN: 0000 Vertical ramp output 142nd line A10085 22nd line Vertical linearity @15 Vlin15 19 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 19 vertical ramp output and measure the voltages at the 22nd line, the 142nd line, and the 262nd line. Let Va, Vb, and Vc be these measurements, and calculate the following formula. Vline15 = (Vb – Va)/(Vc – Va) 262nd line Vertical ramp output VLIN: 1111 142nd line 22nd line A10086 Continued on next page. No. 5841-32/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Bus condition Monitor the pin 19 vertical ramp output and measure the voltages at the 32nd line, the 52nd line, the 132nd line, the 152nd line, the 232nd line, and the 252nd line. Let Va, Vb, Vc, Vd, Ve, and Vf be these measurements, and calculate the following formula. VScor8 = 0.5[(Vb – Va) + (Vf – Ve)] / (Vd – Vc) Vertical S-curve correction @8 VScor8 19 SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output 252nd line 232nd line 152nd line VS: 1000 132nd line 52nd line 32nd line A10087 Monitor the pin 19 vertical ramp output and measure the voltages at the 32nd line, the 52nd line, the 132nd line, the 152nd line, the 232nd line, and the 252nd line. Let Va, Vb, Vc, Vd, Ve, and Vf be these measurements, and calculate the following formula. VScor0 = 0.5[(Vb – Va) + (Vf – Ve)] / (Vd – Vc) Vertical S-curve correction @0 VScor0 19 SYNC IN: horizontal and vertical synchronizing signal Vertical ramp output 252nd line 232nd line 152nd line 132nd line 52nd line 32nd line Vertical S-curve correction @15 VScor15 19 SYNC IN: horizontal and vertical synchronizing signal A10088 Monitor the pin 19 vertical ramp output and measure the voltages at the 32nd line, the 52nd line, the 132nd line, the 152nd line, the 232nd line, and the 252nd line. Let Va, Vb, Vc, Vd, Ve, and Vf be these measurements, and calculate the following formula. VScor15 = 0.5[(Vb – Va) + (Vf – Ve)] / (Vd – Vc) VS: 1111 Vertical ramp output 252nd line 232nd line 152nd line 132nd line 52nd line 32nd line A10089 Continued on next page. No. 5841-33/39 LA7615 Parameter Symbol Test point Input signal Test procedure Bus condition [Horizontal Size Adjustment] Monitor the pin 21 east/west output (parabola waveform output) and measure the voltage at the 142nd line. East/west DC voltage @16 EWdc16 21 SYNC IN: horizontal and vertical synchronizing signal East/west output 142nd line A10090 Monitor the pin 21 east/west output (parabola waveform output) and measure the voltage at the 142nd line. East/west DC voltage @0 EWdc0 21 SYNC IN: horizontal and vertical synchronizing signal East/west output 142nd line EWDC: 00000 A10091 Monitor the pin 21 east/west output (parabola waveform output) and measure the voltage at the 142nd line. East/west DC voltage @31 EWdc31 21 SYNC IN: horizontal and vertical synchronizing signal East/west output 142nd line EWDC: 11111 A10092 [Pin-Cushion Distortion Correction] East/west parabola amplitude @8 EWamp8 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 142nd line. Let Va and Vb be these measurements, and calculate the following formula. EWamp8 = Vb – Va East/west output 142nd line 22nd line A10093 East/west parabola amplitude @0 EWamp0 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 142nd line. Let Va and Vb be these measurements, and calculate the following formula. EWamp0 = Vb – Va East/west output EWAMP: 0000 142nd line 22nd line A10094 Continued on next page. No. 5841-34/39 LA7615 Continued from preceding page. Parameter East/west parabola amplitude @15 Symbol EWamp15 Test point 21 Input signal SYNC IN: horizontal and vertical synchronizing signal Test procedure Bus condition Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 142nd line. Let Va and Vb be these measurements, and calculate the following formula. EWamp15 = Vb – Va EWAMP: 1111 East/west output 142nd line 22nd line A10095 [Trapezoidal Distortion Correction] East/west parabola tilt @8 EWtilt8 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 262nd line. Let Va and Vb be these measurements, and calculate the following formula. EWamp8 = Va – Vb East/west output 262nd line 22nd line A10096 East/west parabola tilt @0 EWtilt0 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 262nd line. Let Va and Vb be these measurements, and calculate the following formula. EWtilt0 = Va – Vb EWTILT: 0000 East/west output 262nd line 22nd line A10097 East/west parabola tilt @15 EWtilt15 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltages at the 22nd line and at the 262nd line. Let Va and Vb be these measurements, and calculate the following formula. EWtilt15 = Va – Vb EWTILT: 1111 East/west output 262nd line 22nd line A10098 Continued on next page. No. 5841-35/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Bus condition [Corner Distortion Correction] East/west parabola corner: Top EWcortop 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltage at the 22nd line under the conditions with CORTOP set to 111 and to 000. Let Va and Vb be these measurements. Calculate the following formula. EWcortop = Va – Vb CORTOP: 111-000 East/west output 22nd line A10099 East/west parabola corner: Bottom EWcorbot 21 SYNC IN: horizontal and vertical synchronizing signal Monitor the pin 21 east/west output (parabola waveform output) and measure the voltage at the 262nd line under the conditions with CORBOT set to 111 and to 000. Let Va and Vb be these measurements. Calculate the following formula. EWcorbot = Va – Vb CORBOTTOM: 111-000 East/west output 262nd line A10100 [Sandcastle Output] Measure the pin 29 output burst gate pulse peak value. Burst gate pulse peak value VBGP 29 SYNC IN: horizontal and vertical synchronizing signal Pin 29 output VBGP BGP A10101 Measure the delay time from the rise of the horizontal synchronizing signal to the rise of the pin 29 burst gate pulse. Burst gate pulse phase TdBGP 29 44 SYNC IN: horizontal and vertical synchronizing signal Horizontal synchronizing signal TdBGP BGP Pin 29 output A10102 Measure the width of the pin 29 burst gate pulse. Burst gate pulse width PWBGP 29 SYNC IN: horizontal and vertical synchronizing signal Pin 29 output BGP PWBGP A10103 Continued on next page. No. 5841-36/39 LA7615 Continued from preceding page. Parameter Symbol Test point Input signal Test procedure Bus condition Measure the peak value of the pin 29 output blanking pulse. Blanking pulse peak value VBLK 29 SYNC IN: horizontal and vertical synchronizing signal Pin 29 output VBLK Blanking pulse A10104 [D/A Converter Output] Pin 30 D/A converter output voltage @0 VDAC0 30 Measure the pin 30 D/A converter output DC voltage. Pin 30 D/A converter output voltage @8 VDAC8 30 Measure the pin 30 D/A converter output DC voltage. Pin 30 D/A converter output voltage @15 VDAC15 30 Measure the pin 30 D/A converter output DC voltage. +BTRIM: 0000 +BTRIM: 1111 No. 5841-37/39 100 kΩ R75 1744 3.9 kΩ C118 FM DISCRI 1 + IF VCC 2 0.01 µF 2 100 µF + + 3 AUX VIDEO IN 3 C3 R2 75 Ω 0.01 µF C2 C1 0.01 µF R76 C59 R1 64 63 62 VCO VCO F0 TANK1 TANK2 FILTER M L102 R74 1 µF 1 µF +9 V R5 100 Ω 4 RF AGC OUT 4 61 SND IF IN + 59 SND IF OUT 5 6 PIF WB AUDIO APC OUT FILTER 5 6 60 FM VCC R4 1 µF IF1 C58 50 Ω 50 kΩ + 7.5 kΩ 0.01 µF 0.01 µF C56 C7 0.01 µF C55 C6 + IF GND 7 58 BUS GND PIF IN1 8 T101 M PIF IN2 9 57 56 EQ VIDEO FILTER OUT C8 1 µF R3 C4 150 Ω 0.47 µF 24 kΩ C9 VIF IN 9 R7 R6 PIF AGC1 10 55 BUS DATA 100 pF C52 100 pF C53 R69 C10 100 Ω 53 + +7.6 V PIF AGC2 11 11 + 12 SIF AGC 13 13 +7.6 V 51 R64 49 CHROMA KILLER + +7.6 V 14 48 C2 IN 48 47 R59 + * Tr1 V101 766-2 +9 V +9 V VERT VCC 17 + 16 17 75 Ω 46 44 + +7.6 V HORIZ RES 22 18 + 19 + 0.47 µF C25 +7.6 V RAMP ALC FILTER 20 E-W OUT 21 SIZE COMP 18 VERT OUT 19 43 BLACK LEVEL DET + 47 46 45 44 Y2 SELECTED SYNC IN Y ADAPTIVE IN OUT CORING + LA7615 50 Y1 IN + +7.6 V AFT CHROMA XTAL OUT APC 14 15 16 51 C1 IN 50 R57 *: Used for adjusting the characteristics of the crystal oscillator. + SIF IN 12 54 53 52 BUS SELECTED TEST IT CLOCK VIDEO OUT FILTER R68 R10 C11 R70 0.01 µF 16 Ω R9 16 Ω R8 0.01 µF 50 Ω 68 Ω R67 0.047 µF 820 Ω R11 C12 50 Ω C13 R12 0.01 µF 100 Ω 0.022 µF C51 R65 10 µF R13 75 Ω C49 100 kΩ 0.01 µF C15 3 kΩ 54 750 Ω R17 1T363 C119 6.2 kΩ 10 µF C17 560 Ω 55 R26 2 kΩ 1 µF 75 Ω R63 C48 75 Ω R60 C45 R56 470 kΩ C43 0.01 µF 100 Ω 1 µF R58 1 kΩ 100 pF R16 R61 100 pF 0.01 µF 1 µF C42 56 C16 470 Ω 0.01 µF R14 100 kΩ C14 R62 15 kΩ 100 Ω 1 µF R62 15 kΩ C47 16 pF R25 R22 R21 0.033 µF C19 CHR1 1.6 kΩ R18 R15 2.2 µF C46 C22 C21 3.3 kΩ 7.5 kΩ C117 100 µF 0.01 µF 10 kΩ R27 C23 + 21 42 41 41 GRN IN + 40 RED IN + 40 39 39 FAST SWITCH IN 38 BLU OUT 38 16 kΩ 37 GRN OUT 37 +7.6 V + 16 1 R37 8.2 kΩ R34 5 kΩ WIDTH (12US) +7.6 V C30 26 1500 pF DELAY2 (9US) 24 + 15 2 5 6 NC 14 12 11 10 7 9 8 NC 28 R46 SAND CASTLE OUT 29 36 RED OUT 36 29 C37 + 30 DAC OUT 30 IB IN 31 31 + +7.6 V VID CHROMA VCC 32 35 34 33 BRT CONTRAST VID/ ABL (PIX) CHROMA FILT GND ABL FILT + 32 0.01 µF 16 kΩ A10105 (Includes two monostable multivibrators.) 13 LC4528B 3 +7.6 V 4 +7.6 V HORIZ HORIZ STANDBY AFC HORIZ X VCC FILTER OUT FLYBACK RAY GND 23 24 25 26 27 28 42 BLU IN + C29 R36 59 C24 75 Ω C39 0.01 µF C50 10 kΩ 10 µF R51 1 µF C38 1.8 kΩ 1 µF C31 60 R38 100 pF C44 0.47 µF R53 1 µF C27 R33 R32 R28 75 Ω 5 kΩ 10 kΩ R52 1 µF C40 10 µF C28 8.2 kΩ C26 C41 680 kΩ 75 Ω R50 47 pF 0.033 µF C22 10 µF R47 R42 R49 1100 Ω R40 1 kΩ 22 µF R54 CSB503F (44) 75 Ω 2.2 kΩ R41 1 µF R43 R48 1 kΩ C36 C34 1 kΩ + 2200 pF C35 16 kΩ 10 kΩ 1.5 µF 100 µF 61 LA7615 Test Circuit Diagram No. 5841-38/39 LA7615 Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1999. Specifications and information herein are subject to change without notice. PS No. 5841-39/39