SANYO LC874096A

Ordering number : ENA0122
LC8740C8A
LC8740B2A
LC874096A
CMOS IC
Internal 128K/112K/96K-byte ROM (Program ROM/CGROM),
2048-byte RAM, 1024-byte CGROM,
and 704×10-bit CRT Display RAM
8-bit 1-chip Microcontroller
Overview
The SANYO LC8740C8A/B2A/96A is a closed caption TV controlling 8-bit microcomputer that, centered around a
CPU running at a minimum bus cycle time of 71ns, integrates on a single chip a number of hardware features such as
128K/112K/96K-byte ROM (size-variable program ROM and CGROM), 2048-byte RAM, 1024-byte CGRAM,
704×10-bit CRT display RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit
timer/counter (may be divided into 8-bit timers/counters, two 8-bit timers with a prescaler, a base timer serving as
a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/
reception capabilities), two channels of asynchronous/synchronous SIO interface (bus mode selectable), a UART
interface (full duplex), an 8-bit 8-channel AD converter, one 14-bit PWM channel, three 8-bit PWM channels, a closed
caption data slicer, closed caption compatible OSD, a system clock frequency divider and ROM correction function.
Features
„Internal ROM
• 131072 × 8 bits (LC8740C8A)
• 114688 × 8 bits (LC8740B2A)
• 98304 × 8 bits (LC874096A)
„Internal RAM
• General-purpose RAM:
• Character generator RAM:
• CRT display RAM:
• ROM correction RAM:
2K bytes
1K bytes
704 × 10 bits
256 bytes
„Minimum Bus Cycle Time
• 71ns (14.1MHz)
Note: The bus cycle time here refers to the ROM read speed.
„Minimum Instruction Cycle Time
• 212ns (14.1MHz)
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
Ver.1.02
N2906HKIM 20060911-S00001 No.A0122-1/25
LC8740C8A/B2A/96A
„OSD
• Screen size
• Display RAM size
Display area
Control area
• Font types
: 36 characters × 16 lines
: 704 words (1 word=10 bits)
: 36 words × 16 lines
: 8 words × 16 lines
: 16 × 32 font, 512 types (16 CGRAM fonts, including 4 fixed fonts)
An arbitrary number of characters can be generated as 16 × 17 or 8 × 9 font characters.
• Display colors
: 4096 colors
Character text, background, borders, and full background can be displayed.
• Display mode specifiable on a line basis.
Normal, 4-color pixel map, 16-color pixel map, and caption text modes
• Vertical display start line and horizontal display start position specifiable on a line basis.
• Shutter function (specifying the display start or stop line) and scroll functions specifiable on a line basis.
• Horizontal character spacing (9 to 16 dots)*1 and vertical character spacing (1 to 32 dots) specifiable on a line basis.
• Character size selectable from 16 character sizes on a line basis*1
(Horizontal×Vertical) = (1×1), (1×2), (2×1), (2×2), (2×4)
(4×2), (4×4), (4×8), (1.5×1), (1.5×2)
(3×1), (3×2), (3×4), (6×2), (6×4), (6×8)
• Cursor display function (4/16 pixel colors)
• Multilayer display
• Full screen display area specifiable.
• OSD clock selectable (normal speed mode/high speed mode/external input)
• Interlace/progressive scan selectable
*1: The supported range varies depending on the active display mode. Refer to the user's guide for details.
„Data Slicer Function (closed caption format)
• Extracts closed caption data and XDS data.
• NTSC/PAL selectable and line specifiable.
„Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 41 (P1n, P2n, P3n, P70 to P73, P8n, PC0 to PC4)
Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
„Timers
• Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler + with an 8-bit prescaler 8-bit timer/counter
Mode 1: 16-bit timer/counter with an 8-bit prescaler
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
No.A0122-2/25
LC8740C8A/B2A/96A
„High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 28.2MHz (at a main clock of 14.1MHz).
2) Can generate output real-time.
„SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle =4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface (bus mode 1 system)
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO6: 8-bit asynchronous/synchronous serial interface (bus mode 2 system)
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
„UART
• Full duplex
• 7/8/9 data bits selectable
• 1 stop bit
• Built-in baudrate generator
„AD Converter: 8 bits × 8 channels
„PWM: 14-bit PWM × 1 channel
8-bit PWM × 3 channels
„Remote Control Receiver Circuit (sharing with P73, INT3, and T0IN pins)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
„Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
„High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
No.A0122-3/25
LC8740C8A/B2A/96A
„Interrupts
• 21 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L
4
0001BH
H or L
INT3/base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit/data slicer/SIO6
9
00043H
H or L
ADC/vertical sync (VS)/scan line
10
0004BH
H or L
Port 0/T4/T5
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
„Subroutine Stack Levels: 1024 levels maximum (the stack is allocated in RAM.)
„Oscillation Circuits
• RC oscillation circuit (internal): For system clock
• VCO oscillation circuit (internal): For system clock generation and CRT display
• Crystal oscillation circuit:
For low-speed system clock, base timer, and PLL reference
„System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 212ns, 424ns, 848ns, 1.7µs, 3.4µs, 6.8µs, 13.6µs, 27.1µs, and
54.3µs (at a main clock rate of 14.1MHz).
„Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The VCO, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level
(3) Having an interrupt source established at port 0
„ROM Correction Function
• Executes the correction program on detection of a match with the program counter value.
• Correction program area size: 256 bytes (4 vector addresses)
„Package Form
• QIP64E(14×14):
• DIP64S(600mil):
Lead-free type
Lead-free type
„Development Tools
• Flash ROM version:
LC87F40C8A (Onchip debugger function is included.)
• Onchip debugger interface board: TCB87 (Type B)
No.A0122-4/25
LC8740C8A/B2A/96A
Package Dimensions
unit : mm (typ)
3159A
33
32
64
17
14.0
49
1
17.2
48
0.8
17.2
14.0
16
0.35
0.8
0.15
0.1
3.0max
(2.7)
(1.0)
SANYO : QIP64E(14X14)
Package Dimensions
unit : mm (typ)
3300
33
1
32
0.2
13.8
64
15.24
57.2
(4.25)
0.51min
3.8
5.1max
0.95
1.78
(1.01)
0.5
SANYO : DIP64S(600mil)
No.A0122-5/25
LC8740C8A/B2A/96A
P06
P07
P20/SO1
P21/SI1/SB1
P22/SCK1
P23
P24/UTX
P25/URX
P26/OSDCKI
P27/BL2
VSS2
VDD2
P10/SO0
P11/SI0/SB0
P12/SCK0
P13
Pin Assignments
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P14/PWMA
49
32
P05
P15/PWMB
50
31
P04
P16/PWMC
51
30
P03
P17/PWMD
52
29
P02
BL1
53
28
P01
27
P00
26
PC4
25
PC3
24
PC2
23
PC1
B
54
G
55
R
56
HSB
57
VSB
58
VSS1
59
22
PC0
XT1
60
21
P37
XT2
61
20
P36
LC8740C8A
LC8740B2A
LC874096A
P33/SB6
9 10 11 12 13 14 15 16
P32/SCK6
8
P31/SI6/SB6
7
P30/SO6
6
P87/AN7
5
P86/AN6
4
P85/AN5
3
P84/AN4
2
P83/AN3
1
P82/AN2
17
P81/AN1
64
P80/AN0
FILT
P73/INT3/T0IN
P34/SCK6
P72/INT2/T0IN
P35
18
P71/INT1/T0HCP
19
63
P70/INT0/TOLCP
62
CVIN
VDD1
RESB
Top view
SANYO : QIP64E(14×14)
“Lead-free Type”
No.A0122-6/25
LC8740C8A/B2A/96A
HSB
1
64
R
VSB
2
63
G
VSS1
3
62
B
XT1
4
61
BL1
XT2
5
60
P17/PWMD
VDD1
6
59
P16/PWMC
RESB
7
58
P15/PWMB
FILT
8
57
P14/PWMA
CVIN
9
56
P13
P70/INT0/T0LCP
10
55
P12/SCK0
P71/INT1/T0HCP
11
54
P11/SI0/SB0
P72/INT2/T0IN
12
53
P10/SO0
P73/INT3/T0IN
13
52
VDD2
P80/AN0
14
51
VSS2
P81/AN1
15
50
P27/BL2
P82/AN2
16
49
P26/OSDCKI
P83/AN3
17
48
P25/URX
P84/AN4
18
47
P24/UTX
P85/AN5
19
46
P23
P86/AN6
20
45
P22/SCK1
P87/AN7
21
44
P21/SI1/SB1
P30/SO6
22
43
P20/SO1
P31/SI6/SB6
23
42
P07
P32/SCK6
24
41
P06
LC8740C8A
LC8740B2A
LC874096A
P33/SB6
25
40
P05
P34/SCK6
26
39
P04
P35
27
38
P03
P36
28
37
P02
P37
29
36
P01
PC0
30
35
P00
PC1
31
34
PC4
PC2
32
33
PC3
Top view
SANYO : DIP64S(600mil)
“Lead-free Type”
No.A0122-7/25
LC8740C8A/B2A/96A
System Block Diagram
Interrupt control
IR
Standby control
RC
VCO
ROM correct
Clock
generator
X'tal
PLA
ROM
PLL
PC
SIO0
Bus interface
SIO1
Port 0
ACC
SIO6
Port 1
B register
Timer 0
Port 2
C register
Timer 1
Port 3
ALU
Timer 4
Port 7
Timer 5
Port 8
PSW
Base timer
Port C
RAR
PWM
ADC
RAM
Data slicer
INT0 to INT3
noise filter
Stack pointer
UART
CGROM
Watchdog timer
OSD
VRAM
No.A0122-8/25
LC8740C8A/B2A/96A
Pin Description
Pin Name
I/O
Description
Option
VSS1
VSS2
-
- power supply pin
No
VDD1
VDD2
-
+ power supply pin
No
Port 0
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P14: PWMA output
P15: PWMB output
P16: PWMC output
P17: PWMD output
Port 2
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20: SIO1 data output
P21: SIO1 data input/bus I/O
P22: SIO1 clock I/O
P24: UART transmit
P25: UART receive
P26: External OSD clock input
P27: Fast blanking 2 control signal output
Port 3
P30 to P37
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P30: SIO6 data output
P31: SIO6 data input/bus I/O
P32: SIO6 clock I/O
P33: SIO6 bus I/O
P34: SIO6 clock I/O
Continued on next page.
No.A0122-9/25
LC8740C8A/B2A/96A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input
P73: INT3 input (with noise filter input)/timer 0 event input/timer 0H capture input
Interrupt acknowledge type
Port 8
I/O
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising &
H Level
L Level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
P80 to P87
• Shared pins
AD converter input: AN0 (P80) to AN7 (P87)
Port C
I/O
• 5-bit I/O port
Yes
• I/O specifiable in 1-bit units
PC0 to PC4
• Pull-up resistors can be turned on and off in 1-bit units.
RES
Input
XT1
Input
XT2
I/O
FILT
Output
Reset pin
No
• 32.768kHz crystal oscillator input pin
No
• 32.768kHz crystal oscillator output pin
No
• Internal PL filter pin
No
CVIN
Input
• Video input pin
No
VS
Input
• Vertical sync input pin
No
HS
Input
• Horizontal sync input pin
No
R
Output
• Red (R) RGB video output pin
No
G
Output
• Green (G) RGB video output pin
No
B
Output
• Blue (B) RGB video output pin
No
BL1
Output
• Fast blanking 1 control output pin
No
No.A0122-10/25
LC8740C8A/B2A/96A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port name
P00 to P07
P10 to P17
Option Selected
in Units of
1 bit
1 bit
Option Type
Pull-up Resistor
1
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
P20 to P27
2
P30 to P37
Output Type
Nch-open drain
Programmable
P70
-
No
Nch-open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
P80 to P87
-
No
Nch-open drain
No
PC0 to PC4
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1 Connect the IC as shown below to minimize the noise input to the VDD1 pin.
Be sure to electrically short the VSS1 and VSS2 pins.
LSI
VDD1
Power
supply
VDD2
VSS1
VSS2
No.A0122-11/25
LC8740C8A/B2A/96A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Maximum supply
VDD max
VDD1, VDD2
VDD1=VDD2
voltage
Input voltage
VI(1)
XT1, RES , HS, VS
CVIN
Output voltage
VO(1)
XT2, BL1, R, G, B
FILT
Input/output
VIO(1)
voltage
min
typ
max
unit
-0.3
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
-0.3
VDD+0.3
V
Ports 0, 1, 2, 3
Ports 7, 8
Port C
High level output current
Peak output
IOPH(1)
Ports 0, 1, 2, 3, C
CMOS output select
BL
Per 1 applicable pin
IOPH(2)
Ports 71 to 73
Per 1 applicable pin
IOPH(3)
R, G, B
OSD is digital mode
current
(Note 1-1)
Per 1 applicable pin
-5
-10
Total output
ΣIOAH(1)
Port 7
Total of all applicable pins
-25
current
ΣIOAH(2)
Port 0, 2, 3, C
Total of all applicable pins
-25
ΣIOAH(3)
Ports 1
Total of all applicable pins
R, G, B, BL
Peak output
Low level output current
-10
IOPL(1)
Ports 0, 1, 2, 3, C
IOPL(2)
Ports 7, 8
Per 1 applicable pin
IOPL(3)
R, G, B
OSD is digital mode
current
(Note 1-1)
-25
mA
Per 1 applicable pin
20
BL
10
20
Per 1 applicable pin
Total output
ΣIOAL(1)
Ports 7, 8
Total of all applicable pins
20
current
ΣIOAL(2)
Ports 0, 2, 3, C
Total of all applicable pins
45
ΣIOAL(3)
Port 1
Total of all applicable pins
45
R, G, B, BL
Allowable power
Pd max
dissipation
Operating ambient
QIP64E(14×14)
Ta=-10 to +70°C
Topr
temperature
Storage ambient
390
DIP64S(600mil)
Tstg
temperature
mW
880
-10
+70
-55
+125
°C
Note 1-1: The average current per applicable pit must not exceed 10mA
No.A0122-12/25
LC8740C8A/B2A/96A
Allowable Operating Conditions at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Operating
VDD(1)
VDD1=VDD2
0.211µs≤tCYC≤200µs
VHD
VDD1=VDD2
RAM and register contents
supply voltage
Memory
sustaining
sustained in HOLD mode
min
typ
max
4.5
5.5
2.0
5.5
0.3VDD
VDD
unit
supply voltage
High level
VIH(1)
input voltage
Ports 0, 1, 2, 3
P71 to P73, 8, C
P70 port input/
4.5 to 5.5
interrupt side
+0.7
HS, VS
VIH(2)
Port 70 watchdog
timer side
VIH(3)
Low level
VIL(1)
input voltage
XT1, RES
4.5 to 5.5
0.9VDD
4.5 to 5.5
0.75VDD
4.5 to 5.5
VSS
4.5 to 5.5
VSS
4.5 to 5.5
VSS
1Vp-p
VDD
V
VDD
Ports 0, 1, 2, 3
P71 to P73, 8, C
P70 port input/
0.1VDD
+0.4
interrupt side
HS, VS
VIL(2)
Port 70 watchdog
timer side
CVIN input
VIL(3)
XT1, RES
VCVIN
CVIN
5.0
amplitude
Instruction
tcyc(1)
cycle time
(Note 2-1)
All functions
tcyc(2)
Except for OSD and data slicer
(Note 2-1)
functions
External OSD
FEXOS(1)
clock
FEXOS(2)
P26/OSDCKI
frequency
DUTY50±5%
SCON1=0
of external
SCON1=1
FmVCO1
Internal VCO1 oscillator
frequency
FmVCO2
Internal VCO2
CKSEL0=0
Oscillator (Note 2-3)
CKSEL0=1
range
(Note 2-2)
FmRC
FsX'tal
XT1, XT2
32.768kHz crystal oscillation mode
See Fig. 1.
1Vp-p
1Vp-p
+3dB
0.211
200
µs
14.28
15.44
28.56
30.88
4.5 to 5.5
0.212
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
Vp-p
µs
0.211
4.5 to 5.5
Internal RC oscillator
+0.4
0.25VDD
0.213
4.5 to 5.5
OSD clock (Note 2-3)
Oscillation
-3dB
0.15VDD
MHz
14.08
14.15
14.22
14.28
14.75
15.44
28.56
29.5
30.88
0.3
1.0
2.0
32.768
MHz
kHz
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmVCO1 at a division ratio of 1/1 and 6/FmVCO1
at a division ratio of 1/2.
Note 2-2: See Table 1 for the oscillation constants
Note 2-3: SCAN1 is Hsync frequency switch bit. CKSEL0 is OSD clock frequency switch bit.
(Refer to the LC874000 user's manual for details. )
No.A0122-13/25
LC8740C8A/B2A/96A
Electrical Characteristics at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High level input
IIH(1)
current
Ports 0, 1, 2, 3
Output disabled
Ports 7, 8
Pull-up resistor off
Port C
VIN=VDD
(including output Tr's off leakage
min
typ
max
unit
4.5 to 5.5
1
4.5 to 5.5
1
current)
Low level input
IIH(2)
RES, HS, VS
VIN=VDD
IIL(1)
Ports 0, 1, 2, 3
Output disabled
Ports 7, 8
Pull-up resistor off
Port C
VIN=VSS
(including output Tr's off leakage
current
4.5 to 5.5
-1
4.5 to 5.5
-1
4.5 to 5.5
VDD-1
µA
current)
High level output
IIL(2)
RES, HS, VS
VIN=VSS
VOH(1)
Ports 0, 1, 2, 3, 8
IOH=-1.0mA
voltage
Low level output
Port C
VOH(2)
P71 to P73
IOH=-0.4mA
4.5 to 5.5
VDD-1
VOH(3)
R, G, B
IOH=-5mA
4.5 to 5.5
VDD-1
VOH(4)
BL1,
IOH=-5mA
P27/BL2
When BL2 is output
4.5 to 5.5
VDD-1
Ports 0, 1, 2, 3, 8
IOL=10mA
4.5 to 5.5
1.5
Port C
IOL=1.6mA
4.5 to 5.5
0.4
VOL(2)
Port 7
IOL=1mA
4.5 to 5.5
0.4
VOL(3)
R, G, B
IOL=5mA
4.5 to 5.5
0.4
VOL(4)
BL1,
IOL=5mA
P27/BL2
When BL2 is output
4.5 to 5.5
0.4
Ports 0, 1, 2, 3, 7
VOH=0.9VDD
VOL(1)
voltage
Pull-up resistance
Rpu
Ports 8, C
Hysteresis voltage
VHYS
4.5 to 5.5
15
V
40
70
kΩ
RES
4.5 to 5.5
Ports 1, 2, 3, 7
0.35
V
HS, VS
Bus terminal short
RBS
circuit resistance for
• P31, P33
• P32, P34
130
internal
300
Ω
10
pF
communication
Pin capacitance
CP
All pins
For pins other than that under test:
VIN=VSS
f=1MHz
4.5 to 5.5
Ta=25°C
No.A0122-14/25
LC8740C8A/B2A/96A
Serial I/O Characteristics at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Period
tSCK(1)
Low level
tSCKL(1)
Pin/
SCK0(P12)
Specification
Conditions
Remarks
VDD[V]
See Fig. 5.
max
unit
1
tSCKH(1)
1
pulse width
tSCKHA(1a)
Input clock
typ
2
pulse width
High level
min
• Continuous data transmission/
reception mode
• OSD inactive
4.5 to 5.5
4
tCYC
• See Fig. 5.
• (Note4-1-2)
• Continuous data transmission/
tSCKHA(1b)
reception mode
6
Serial clock
• OSD active
• See Fig. 5.
• (Note4-1-2)
Period
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 5.
Low level
tSCKL(2)
1/2
pulse width
Output clock
High level
tSCK
tSCKH(2)
1/2
pulse width
tSCKHA(2a)
• Continuous data transmission/
reception mode
4.5 to 5.5
• OSD inactive
tSCKH(2)
+2tCYC
• See Fig. 5.
tSCKHA(2b)
reception mode
tSCKH(2)
+2tCYC
• See Fig. 5.
Serial input
SI0(P11),
SB0(P11)
Data hold time
tCYC
tSCKH(2)
+(16/3)
tCYC
• Must be specified with respect
0.03
to rising edge of SIOCLK.
• See Fig. 5.
thDI(1)
4.5 to 5.5
0.03
Input clock
Output
tdD0(1)
delay time
SO0(P10),
SB0(P11)
• Continuous data transmission/
(1/3)tCYC
reception mode
+0.05
• (Note4-1-3)
tdD0(2)
• Synchronous 8-bit mode
tdD0(3)
µs
1tCYC
• (Note4-1-3)
4.5 to 5.5
Output clock
Serial output
tsDI(1)
+(10/3)
tCYC
• Continuous data transmission/
• OSD active
Data setup time
tSCKH(2)
+0.05
(Note4-1-3)
(1/3)tCYC
+0.05
Note4-1-1: This standard value is a theory value. Be sure to ensure the margin according to busy condition.
Note4-1-2: When using the serial clock in continuous data transmission/reception mode, the time to the first falling
edge of the serial clock after it sets SIORUN in “H” state is more extended than tSCLKHA.
Note4-1-3: It is defined for the falling edge of SIOCLK. In open drain output, it is defined as the time to start the output
change. See Fig. 5.
No.A0122-15/25
LC8740C8A/B2A/96A
2. SIO1, 6 Serial I/O Characteristics (Note 4-2-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Input clock
tSCK(3)
SCK1(P22),
See Fig. 5.
Low level
tSCKL(3)
4.5 to 5.5
pulse width
High level
Period
Low level
1
SCK1(P22),
• CMOS output selected
SCK6(P32, 34)
• See Fig. 5.
tSCKL(4)
2
4.5 to 5.5
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SI1(P21),
SB1(P21),
SI6(P31),
Data hold time
thDI(2)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 5.
SB6(P31, P33)
0.03
4.5 to 5.5
0.03
Output delay time
Serial output
tsDI(2)
unit
1
pulse width
High level
max
tCYC
tSCKH(3)
tSCK(4)
typ
2
SCK6(P32, 34)
pulse width
Output clock
Serial clock
Period
min
tdD0(4)
SO1(P20),
SB1(P21),
SO6(P30),
SB6(P31, P34)
µs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output state
4.5 to 5.5
1/3tCYC
+0.05
change in open drain output
mode.
• See Fig. 5.
Note4-2-1: This standard value is a theory value. Be sure to ensure the margin according to busy condition.
No.A0122-16/25
LC8740C8A/B2A/96A
Pulse Input Conditions at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timers 0 and 1 are
INT2(P72),
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are
4.5 to 5.5
2
tCYC
4.5 to 5.5
64
4.5 to 5.5
256
4.5 to 5.5
200
4.5 to 5.5
1
enabled.
tPIL(5)
RES
Resetting is enabled.
tPIH(6)
HS, VS
• Display position controllable (Note)
• The active edge of HS and VS
tPIL(6)
1
unit
enabled.
tPIH(4)
constant is 1/128
4.5 to 5.5
max
enabled.
tPIH(3)
constant is 1/32
typ
enabled.
tPIH(2)
constant is 1/1
min
must be apart at least 1 tCYC.
µs
• See Fig. 7.
Falling time
tTHL
HS
See Fig. 7. (Note 5-1)
External OSD
tOSCKI
OSDCKI(P26)
See Fig. 8.
4.5 to 5.5
100
4.5 to 5.5
clock input
10
ns
ns
frequency
Note 5-1: When the falling edge of HS is affected by the noise, the start position of OSD can slip off. Note that the
signal lines with rapid state change or with large current should be allocated away from HS line.
AD Converter Characteristics at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Resolution
N
AN0(P80)
Absolute
ET
to AN7(P87)
TCAD
time
AD conversion time=32×tCYC
(when ADCR2=0) (Note 6-2)
4.5 to 5.5
(when ADCR2=1) (Note 6-2)
VAIN
4.5 to 5.5
4.5 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
4.5 to 5.5
input current
IAINL
VAIN=VSS
4.5 to 5.5
max
unit
8
bit
±1.5
4.5 to 5.5
AD conversion time=64×tCYC
Analog input
typ
4.5 to 5.5
(Note 6-1)
accuracy
Conversion
min
13.50
97.92
(tCYC=
(tCYC=
0.422µs)
3.06µs)
13.50
97.92
(tCYC=
(tCYC=
0.211µs)
1.53µs)
VSS
VDD
1
LSB
µs
V
µA
-1
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0122-17/25
LC8740C8A/B2A/96A
Analog mode RGB Characteristics at Ta=-10°C to +70°C, VSS1=VSS2=0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
min
Output resistance
Analog output
R, G, B
VDD=5.0V
VARO
R, G, B
VDD=5.0V
tST
R, G, B
70%DC level
typ
max
kΩ
20
%
50
ns
deflection
Time seting
unit
2.5
10pf load
4/16(V)
VARO
70%Vp-p
3/16(V)
Vp-p
30%Vp-p
2/16(V)
VARO
tST
1/16(V)
No.A0122-18/25
LC8740C8A/B2A/96A
Current Drain Characteristics at Ta = -10°C to +70°C, VSS1 = VSS2 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
current drain
Pin/
VDD1
=VDD2
(Note 7-1)
Specification
Conditions
Remarks
VDD[V]
min
typ
Max
unit
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to main clock VCO
• OSD VCO active
• Internal RC oscillator inactive
4.5 to 5.5
38
56
• 1/1 frequency division ratio
• OSD is analog mode
• DSL active
IDDOP(2)
mA
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to main clock VCO
• OSD VCO active
• Internal RC oscillator inactive
4.5 to 5.5
30
48
4.5 to 5.5
81
300
µA
4.5 to 5.5
4
8
mA
4.5 to 5.5
400
1400
4.5 to 5.5
73
200
4.5 to 5.5
0.05
20
• 1/1 frequency division ratio
• OSD is digital mode
• DSL active
IDDOP(3)
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz
• Main clock and OSD VCOs inactive
• Internal RC oscillator inactive
• 1/2 frequency division ratio
HALT mode
IDDHALT(1)
HALT mode
current drain
• FmX'tal=32.768kHz crystal oscillation mode
(Note 7-1)
• System clock set to main clock VCO
• OSD VCO active
• Internal RC oscillator inactive
• 1/1 frequency division ratio
IDDHALT(2)
HALT mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillator
• 1/1 frequency division ratio
IDDHALT(3)
HALT mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz
• Main and OSD VCOs inactive
µA
• Internal RC oscillator inactive
• 1/2 frequency division ratio
HOLD mode
current drain
IDDHOLD
VDD1
HOLD mode
• All oscillators inactive
Note 7-1: The current drain value includes none of the currents that flow into the output transistors and internal pull-up
resistors.
No.A0122-19/25
LC8740C8A/B2A/96A
UART (Full Duplex) Operating Conditions at Ta=-10°C to +70°C, VSS1=VSS2=0V
Parameter
Symbol
Transfer rate
UBR
Data length:
Stop bits:
Parity bits:
Pin/
Remarks
P24, P25
Specification
Conditions
VDD[V]
4.5 to 5.5
min
16/3
typ
max
8192/3
unit
tCYC
7/8/9 bits (LSB first)
1 bit
None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start bit
Start of transmission
Stop bit
Transmit data (LSB first)
End of transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Stop bit
Start bit
Start of reception
Receive data (LSB first)
End of reception
UBR
No.A0122-20/25
LC8740C8A/B2A/96A
Recommended Oscillation Circuit and Sample Characteristics
The sample oscillation circuit characteristics in the table below is based on the following conditions:
• Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation
evaluation board.
• Sample characteristics are the result of the evaluation with the recommended circuit parameters connected
externally.
Table 1. Recommended oscillation circuit and sample characteristics (Ta = -10°C to +70°C)
Frequency
32.768kHz
Manufacturer
Seiko Epson
Recommended circuit
Operating
parameters
supply voltage
Oscillator
C-002RX
C1
C2
Rf
Rd
[pF]
[pF]
[Ω]
[Ω]
18
18
OPEN
620k
range
[V]
4.5 to 5.5
Oscillation
stabilizing
time
typ
Remarks
max
[s]
[s]
1.00
1.50
Notes: The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes
stable after the following conditions. (See Figure 3.)
1. The VDD becomes higher than the minimum operating voltage after the power is supplied.
2. The HOLD mode is released.
The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with
oscillator manufacturer with the following notes in your mind.
• Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the
oscillation frequency on the production board.
• The above oscillation frequency and the operating supply voltage range are based on the operating temperature of
-10°C to +70°C. For the use with the temperature outside of the range herein, or in the application requiring high
reliability such as car products, please consult with oscillator manufacturer.
• When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with
Sanyo sales personnel.
Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed
with low gain in order to reduce the power dissipation, refer to the following notices.
• The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as
possible.
• The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND.
• The signal lines with rapid state change or with large current should be allocated away from the oscillation circuit.
XT1
XT2
Rf
Rd
C1
C2
X’tal
Figure 1 Recommended Oscillation Circuit
0.5VDD
Figure 2 AC Timing Measurement Point
No.A0122-21/25
LC8740C8A/B2A/96A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Interna RC
oscillation
tmsVCO
VCO1
tmsX’tal
XT1, XT2
Operating
mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
No HOLD reset signal
HOLD reset signal valid
Internal RC
oscillation
tmsVCO
VCO1
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 3 Oscillation Stabilization Timing
No.A0122-22/25
LC8740C8A/B2A/96A
VDD
RRES
Note:
Determine the value of CRES and RRES so that the
reset signal is present for a period of 200µs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
CRES
Figure 4 Reset Circuit
SIOCLK :
DATAIN :
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT :
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK :
tsDI
thDI
DATAIN :
tdDO
DATAOUT :
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK :
tsDI
thDI
DATAIN :
tdDO
DATAOUT :
Figure 5 Serial I/O Output Waveforms
tPIL
tPIH
Figure 6 Pulse Input Timing Signal Waveform 1
No.A0122-23/25
LC8740C8A/B2A/96A
tPIL(6)
HS
0.75VDD
0.25VDD
tTHL
VS
tPIL(6)
more than ±1tCYC
Figure 7 Pulse Input Timing Signal Waveform 2
HS
OSDCKI
tOSCKI
tOSCKI
Note: Last transition of the t0SCKI must be saving constant.
Figure 8 Pulse Input Timing Signal Waveform 3
Noise filter
1µF
C-Video
CVIN
200Ω
1000pF
Coupling capacitor
Note: The output impedance of the C-Video side as viewed from the input of the noise filter must be 100Ω or less.
Figure 9 Recommended CVIN Circuit
100Ω
FILT
1MΩ
+ 2.2µF
-
33000pF
Note: Place the components to be connected to the FILT pin so that their trace length is minimum.
Figure 10 Recommended Filter Circuit
No.A0122-24/25
LC8740C8A/B2A/96A
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
products must not be exported without obtaining the export license from the authorities concerned in
accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or
otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and
reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
property rights or other rights of third parties.
This catalog provides information as of November, 2006. Specifications and information herein are subject
to change without notice.
PS No.A0122-25/25