LMU217 LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier 16 x 16-bit Parallel multiplier DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 25 ns Worst-Case Multiply Time ❑ Low Power CMOS Technology ❑ Replaces Cypress CY7C517, IDT 7217L, and AMD Am29517 ❑ Single Clock Architecture with Register Enables ❑ Two’s Complement, Unsigned, or Mixed Operands ❑ Three-State Outputs ❑ 68-pin PLCC, J-Lead LMU217 BLOCK DIAGRAM TCA The LMU217 is a high-speed, low RND is loaded on the rising edge of power 16-bit parallel multiplier. CLK, provided either ENA or ENB are LOW. RND, when HIGH, adds ‘1’ to The LMU217 produces the 32-bit prodthe most significant bit position of the uct of two 16-bit numbers. Data present least significant half of the product. at the A inputs, along with the TCA Subsequent truncation of the 16 least control bit, is loaded into the A register significant bits produces a result on the rising edge of CLK. B data and correctly rounded to 16-bit precision. the TCB control bit are similarly loaded. Loading of the A and B At the output, the Right Shift control registers is controlled by the ENA and (RS) selects either of two output formats. ENB controls. When HIGH, these con- RS LOW produces a 31-bit product trols prevent application of the clock to with a copy of the sign bit inserted in the the respective register. The TCA and MSB postion of the least significant half. TCB controls specify the operands as RS HIGH gives a full 32-bit product. Two two’s complement when HIGH, or 16-bit output registers are provided to unsigned magnitude when LOW. hold the most and least significant halves of the result (MSP and LSP) as defined by RS. These registers are loaded on the rising edge of CLK, subject to the ENR control. When ENR is B 15-0/ HIGH, clocking of the result registers is R 15-0 prevented. A 15-0 TCB 16 16 CLK ENA A REGISTER B REGISTER ENB The two halves of the product may be routed to a single 16-bit three-state output port (MSP) via a multiplexer. MSPSEL LOW causes the MSP outputs to be driven by the most significant half of the result. MSPSEL HIGH routes the least significant half of the result to the MSP pins. In addition, the LSP is available via the B port through a separate three-state buffer. REGISTER RND 32 RS FORMAT ADJUST 16 For asynchronous output, these registers may be made transparent by setting the feed through control (FT) HIGH and ENR LOW. 16 FT ENR RESULT REGISTER MSPSEL OEM 16 OEL 16 R 31-16 Multipliers 1 08/16/2000–LDS.217-H LMU217 DEVICES INCORPORATED FIGURE 1A. 16 x 16-bit Parallel Multiplier INPUT FORMATS AIN BIN Fractional Two’s Complement (TCA, TCB = 1) 15 14 13 –20 2–1 2–2 2 1 0 2–13 2–14 2–15 15 14 13 –20 2–1 2–2 (Sign) 2 1 0 2–13 2–14 2–15 (Sign) Integer Two’s Complement (TCA, TCB = 1) 15 14 13 –215 214 213 2 1 0 22 21 20 15 14 13 –215 214 213 (Sign) 2 1 0 22 21 20 (Sign) Unsigned Fractional (TCA, TCB = 0) 15 14 13 2–1 2–2 2–3 2 1 0 2–14 2–15 2–16 15 14 13 2–1 2–2 2–3 2 1 0 2–14 2–15 2–16 Unsigned Integer (TCA, TCB = 0) 15 14 13 215 214 213 FIGURE 1B. 2 1 0 22 21 20 15 14 13 215 214 213 2 1 0 22 21 20 OUTPUT FORMATS MSP LSP Fractional Two’s Complement (RS = 0) 31 30 29 –20 2–1 2–2 18 17 16 2–13 2–14 2–15 15 14 13 –20 2–16 2–17 (Sign) 2 1 0 2–28 2–29 2–30 (Sign) Fractional Two’s Complement (RS = 1) 31 30 29 –21 20 2–1 18 17 16 2–12 2–13 2–14 15 14 13 2–15 2–16 2–17 2 1 0 2–28 2–29 2–30 (Sign) Integer Two’s Complement (RS = 1) 31 30 29 –231 230 229 18 17 16 218 217 216 15 14 13 215 214 213 2 1 0 22 21 20 (Sign) Unsigned Fractional (RS = 1) 31 30 29 2–1 2–2 2–3 18 17 16 2–14 2–15 2–16 15 14 13 2–17 2–18 2–19 2 1 0 2–30 2–31 2–32 Unsigned Integer (RS = 1) 31 30 29 231 230 229 18 17 16 218 217 216 15 14 13 215 214 213 2 1 0 22 21 20 Multipliers 2 08/16/2000–LDS.217-H LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial Active Operation, Military Supply Voltage 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 VOL Output Low Voltage VCC = Min., IOL = 8.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max Unit V 0.5 V 2.0 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±20 µA Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 25 mA ICC2 VCC Current, Quiescent (Note 7) 1.0 mA 12 Multipliers 3 08/16/2000–LDS.217-H LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) Symbol Parameter tMC Clocked Multiply Time tMUC Unclocked Multiply Time tPW Clock Pulse Width tS Input Setup Time tH Input Hold Time tD Output Delay tSEL Output Select Delay tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) LMU217– 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 12345678901234567890123456789 * * 65 55 45* 35 25 12345678901 20* 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 12345678901234567890123456789 Min Max Min Max Min Max Min Max Min Max12345678901 Min Max 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 65 55 45 35 25 12345678901 20 12345678901234567890123456789 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 85 75 65 55 38 12345678901 30 12345678901234567890123456789 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 15 15 15 10 10 9 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 15 15 15 12 12 11 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 3 3 3 1 1 1 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 12345678901234567890123456789 30 30 30 25 20 12345678901 18 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 12345678901234567890123456789 25 25 25 25 20 12345678901 18 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 25 25 25 25 20 12345678901 18 12345678901234567890123456789 12345678901234567890123456789 12345678901 12345678901234567890123456789 12345678901 25 25 25 25 20 12345678901 18 12345678901234567890123456789 12345678901 MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) Symbol Parameter tMC Clocked Multiply Time tMUC Unclocked Multiply Time tPW Clock Pulse Width tS Input Setup Time tH Input Hold Time tD Output Delay tSEL Output Select Delay tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) 123456789012345678901234567890121234567890123456789012345 LMU217– 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 * * 75 65 55* 40* 30* 25* 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 Min Max Min Max Min Max Min Max Min Max Min Max 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 75 65 55 40 30 25 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 95 85 75 60 43 38 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 20 15 15 15 10 10 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 15 15 15 15 12 12 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 3 3 3 2 2 2 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 35 30 30 25 20 20 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 30 30 30 25 20 20 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 25 25 25 25 20 20 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 123456789012345678901234567890121234567890123456789012345 25 25 25 25 20 20 123456789012345678901234567890121234567890123456789012345 SWITCHING WAVEFORMS tS tH INPUT ENA, ENB tS tH ENR tPW tPW tPW CLK tD tMC tMUC MSPSEL tSEL OEM OEL tDIS R31-0 tENA HIGH IMPEDANCE 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE Multipliers 4 08/16/2000–LDS.217-H LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a min- 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 DUT IOL VTH CL IOH FIGURE B. THRESHOLD LEVELS tENA OE Z tDIS 1.5 V 1.5 V 3.5V Vth 0 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency Multipliers 5 08/16/2000–LDS.217-H LMU217 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier ORDERING INFORMATION 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 64-pin 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 48 R31 A12 1 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 47 R30 A11 2 1234567890123456789012345678901212345678901234567 46 R29 A10 3 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 45 R28 A9 4 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 44 5 R27 A8 1234567890123456789012345678901212345678901234567 43 6 R26 A7 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 42 7 R25 A6 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 41 8 R24 A5 1234567890123456789012345678901212345678901234567 40 9 R23 A4 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 39 10 R22 A3 1234567890123456789012345678901212345678901234567 38 11 R21 A2 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 37 12 R20 A1 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 36 13 R19 A0 1234567890123456789012345678901212345678901234567 35 14 R18 OEL 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 34 15 CLK R17 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 33 16 ENB R16 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 Discontinued Package 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 11 59 12 58 13 57 14 56 15 55 16 54 17 Top View 18 19 53 52 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OEL CLK ENB Top View 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 10 Speed R15, B15 R14, B14 R13, B13 R12, B12 R11, B11 R10, B10 R9, B9 R8, B8 R7, B7 R6, B6 R5, B5 R4, B4 R3, B3 R2, B2 R1, B1 R0, B0 R15, B15 R14, B14 R13, B13 R12, B12 R11, B11 R10, B10 R9, B9 R8, B8 R7, B7 R6, B6 R5, B5 R4, B4 R3, B3 R2, B2 R1, B1 R0, B0 NC R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC ENR OEM RS FT MSPSEL GND GND VCC VCC TCB TCA RND ENA A15 A14 A13 ENR OEM RS FT MSPSEL GND GND VCC VCC TCB TCA RND ENA A15 A14 A13 68-pin Plastic J-Lead Chip Carrier (J2) Ceramic Flatpack (F4) 0°C to +70°C — COMMERCIAL SCREENING 35 ns 25 ns LMU217JC35 LMU217JC25 –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT Multipliers 6 08/16/2000–LDS.217-H