LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 10A SIMPLE SWITCHER® Power Module with 2.95V-17V Input and Current Sharing in QFN Package Check for Samples: LMZ31710 FEATURES DESCRIPTION • The LMZ31710 SIMPLE SWITCHER power module is an easy-to-use integrated power solution that combines a 10-A DC/DC converter with power MOSFETs, a shielded inductor, and passives into a low profile, QFN package. This total power solution allows as few as three external components and eliminates the loop compensation and magnetics part selection process. 1 2 • • • • • • • • • • • • • • • • • • Complete Integrated Power Solution Allows Small Footprint, Low-Profile Design 10mm x 10mm x 4.3mm Package - Pin Compatible with LMZ31707 & LMZ31704 Efficiencies Up to 95% Eco-Mode / Light Load Efficiency (LLE) Wide-Output Voltage Adjust 0.6 V to 5.5 V, with 1% Reference Accuracy Supports Parallel Operation for Higher Current Optional Split Power Rail allows Input Voltage Down to 2.95 V Adjustable Switching Frequency (200 kHz to 1.2 MHz) Synchronizes to an External Clock Provides 180° Out-of-Phase Clock Signal Adjustable Slow-Start Output Voltage Sequencing / Tracking Power Good Output Programmable Undervoltage Lockout (UVLO) Over-Current & Over-Temperature Protection Pre-bias Output Start-up Operating Temperature Range: –40°C to 85°C Enhanced Thermal Performance: 13.3°C/W Meets EN55022 Class B Emissions - Integrated Shielded Inductor APPLICATIONS • • • • The 10x10x4.3 mm QFN package is easy to solder onto a printed circuit board and allows a compact point-of-load design. Achieves greater than 95% efficiency and excellent power dissipation capability with a thermal impedance of 13.3°C/W. The LMZ31710 offers the flexibility and the feature-set of a discrete point-of-load design and is ideal for powering a wide range of ICs and systems. Advanced packaging technology affords a robust and reliable power solution compatible with standard QFN mounting and testing techniques. Figure 1. SIMPLIFIED APPLICATION VIN CIN PVIN VIN ISHARE VOUT VOUT SENSE+ COUT LMZ31710 SYNC_OUT PWRGD INH/UVLO Broadband & Communications Infrastructure Automated Test and Medical Equipment Compact PCI / PCI Express / PXI Express DSP and FPGA Point-of-Load Applications VADJ SS/TR RT/CLK STSEL AGND PGND RSET RRT 100 95 90 Efficiency (%) 85 80 75 Vout = 2.5 V Fsw = 750 kHz 70 65 PVIN = 3.3 V, VIN = 5 V 60 PVIN = VIN = 5 V 55 PVIN = VIN = 12 V 50 0 1 2 3 4 5 6 7 8 9 Output Current (A) 10 C001 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) over operating temperature range (unless otherwise noted) Input Voltage Output Voltage MIN MAX VIN, PVIN –0.3 20 V INH/UVLO, PWRGD, RT/CLK, SENSE+ –0.3 6 V ILIM, VADJ, SS/TR, STSEL, SYNC_OUT, ISHARE, OCP_SEL –0.3 3 V PH –1.0 20 V PH 10ns Transient –3.0 20 V VOUT –0.3 6 V ±100 µA PH current limit A PH current limit A PVIN current limit A RT/CLK, INH/UVLO Source Current Sink Current PWRGD UNIT –0.1 2 mA Operating Junction Temperature –40 125 (2) °C Storage Temperature –65 150 °C 1500 G Mechanical Shock Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted Mechanical Vibration Mil-STD-883D, Method 2007.2, 20-2000Hz (1) 20 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. See the temperature derating curves in the Typical Characteristics section for thermal information. (2) RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT PVIN Input Switching Voltage 2.95 17 V VIN Input Bias Voltage 4.5 17 V VOUT Output Voltage 0.6 5.5 V fSW Switching Frequency 200 1200 kHz PACKAGE SPECIFICATIONS LMZ31710 Weight Flammability MTBF Calculated reliability UNIT 1.45 grams Meets UL 94 V-O Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign 37.4 MHrs Table 1. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com. 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 ELECTRICAL CHARACTERISTICS Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 10 A, CIN = 0.1 µF + 2 x 22 µF ceramic + 100 µF bulk, COUT = 4 x 47 µF ceramic (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOUT Output current TA = 85°C, natural convection 0 (1) 10 A VIN Input bias voltage range Over output current range 4.5 17 V PVIN Input switching voltage range Over output current range 2.95 (2) 17 (3) V UVLO VIN Undervoltage lockout VOUT(adj) VOUT VIN Increasing VIN Decreasing 3.5 Output voltage adjust range Over output current range 0.6 Set-point voltage tolerance TA = 25°C, IOUT = 0 A Temperature variation –40°C ≤ TA ≤ +85°C, IOUT = 0 A ±0.2% Line regulation Over input voltage range ±0.1% Load regulation Over output current range ±0.2% Total output voltage variation Includes set-point, line, load, and temperature variation PVIN = VIN = 12 V IO = 5 A η Efficiency PVIN = VIN = 5 V IO = 5 A Output voltage ripple ILIM Current limit threshold Transient response VINH Inhibit threshold voltage IINH II(stby) 4.0 V ±1.5% (4) VOUT = 5.0 V, fSW = 1 MHz 93 % VOUT = 3.3 V, fSW = 750 kHz 92 % VOUT = 2.5 V, fSW = 750 kHz 90 % VOUT = 1.8 V, fSW = 500 kHz 89 % VOUT = 1.2 V, fSW = 300 kHz 86 % VOUT = 0.9 V, fSW = 250 kHz 84 % VOUT = 0.6 V, fSW = 200 kHz 81 % VOUT = 3.3 V, fSW = 750 kHz 94 % VOUT = 2.5 V, fSW = 750 kHz 93 % VOUT = 1.8 V, fSW = 500 kHz 92 % VOUT = 1.2 V, fSW = 300 kHz 89 % VOUT = 0.9 V, fSW = 250 kHz 87 % VOUT = 0.6 V, fSW = 200 kHz 83 % 14 mVP-P ILIM pin open 15 A ILIM pin to AGND 12 A 100 µs 1.0 A/µs load step from 25 to 75% IOUT(max) Recovery time VOUT over/undershoot 80 mV Inhibit High Voltage 1.3 open (5) Inhibit Low Voltage -0.3 1.1 INH Input current VINH < 1.1 V -1.15 INH Hysteresis current VINH > 1.3 V -3.3 Input standby current INH pin to AGND PWRGD Thresholds VOUT falling PWRGD Low Voltage I(PWRGD) = 0.5 mA Switching frequency RRT = 169 kΩ fCLK Synchronization frequency VCLK-H CLK High-Level VCLK-L CLK Low-Level DCLK CLK Duty Cycle (5) 5.5 V 20 MHz bandwith fSW (1) (2) (3) (4) 3.85 ±1% (4) VOUT rising Power Good 4.5 2 Good 95% Fault 108% Fault 91% Good 104% μA μA 10 µA 0.3 V 600 kHz 200 1200 kHz 2.0 5.5 400 CLK Control V 20 500 50 V 0.5 V 80 % See Light Load Efficiency (LLE) section for more information for output voltages < 1.5 V. The minimum PVIN is 2.95 V or (VOUT + 0.7 V), whichever is greater. See Table 9 for more details. The maximum PVIN voltage is 17 V or (22 x VOUT), whichever is less. See Table 9 for more details. The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor. Value when no voltage divider is present at the INH/UVLO pin. This pin has an internal pull-up. If it is left open, the device operates when input power is applied. A small, low-leakage MOSFET is recommended for control. Do not tie this pin to VIN. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 3 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 10 A, CIN = 0.1 µF + 2 x 22 µF ceramic + 100 µF bulk, COUT = 4 x 47 µF ceramic (unless otherwise noted) PARAMETER TEST CONDITIONS Thermal Shutdown CIN MIN Ceramic °C °C External output capacitance Non-ceramic 200 1500 220 (7) 5000 (8) Equivalent series resistance (ESR) (6) (7) (8) µF 100 (6) 47 (7) UNIT 10 44 (6) Non-ceramic Ceramic MAX 175 Thermal shutdown hysteresis External input capacitance COUT TYP Thermal shutdown 35 µF mΩ A minimum of 44 µF of external ceramic capacitance is required across the input (VIN and PVIN connected) for proper operation. An additional 100 µF of bulk capacitance is recommended. It is also recommended to place a 0.1 µF ceramic capacitor directly across the PVIN and PGND pins of the device. Locate the input capacitance close to the device. When operating with split VIN and PVIN rails, place 4.7µF of ceramic capacitance directly at the VIN pin. See Table 6 for more details. The amount of required output capacitance varies depending on the output voltage (see Table 5 ). The amount of required capacitance must include at least 1x 47µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 5 and Table 6 more details. The maximum output capacitance of 5000 µF includes the combination of both ceramic and non-ceramic capacitors. It may be necessary to increase the slow start time when turning on into the maximum capacitance. See the Slow Start (SS/TR) section for information on adjusting the slow start time. THERMAL INFORMATION LMZ31710 THERMAL METRIC (1) RVQ42 UNIT 42 PINS θJA Junction-to-ambient thermal resistance (2) 13.3 (3) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (4) (1) (2) (3) (4) 4 1.6 °C/W 5.3 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm double-sided PCB with 2 oz. copper and natural convection cooling. Additional airflow reduces θJA. The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM OCP_SEL ILIM OCP INH/UVLO Shutdown Logic PWRGD VIN Thermal Shutdown SENSE+ VIN UVLO PWRGD Logic PVIN + + PH VADJ SS/TR VREF Comp STSEL Current Share ISHARE SYNC_OUT RT/CLK Power Stage and Control Logic VOUT Oscillator with PLL PGND AGND LMZ31710 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 5 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com Table 2. PIN DESCRIPTIONS TERMINAL NAME DESCRIPTION NO. 2 AGND 23 Zero volt reference for the analog control circuit. These pins are not connected together internal to the device and must be connected to one another using an AGND plane of the PCB. These pins are associated with the internal analog ground (AGND) of the device. See Layout Recommendations. 20 21 PGND 31 This is the return current path for the power stage of the device. Connect these pins to the load and to the bypass capacitors associated with PVIN and VOUT. 32 33 VIN 3 Input bias voltage pin. Supplies the control circuitry of the power converter. Connect this pin to the input bias supply. Connect bypass capacitors between this pin and PGND. 1 11 PVIN 12 Input switching voltage. Supplies voltage to the power switches of the converter. Connect these pins to the input supply. Connect bypass capacitors between these pins and PGND. 39 40 34 35 36 VOUT 37 Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external bypass capacitors between these pins and PGND. 38 41 10 13 14 15 PH 16 17 Phase switch node. These pins must be connected to one another using a small copper island under the device for thermal relief. Do not place any external component on these pins or tie them to a pin of another function. 18 19 42 5 DNC 9 Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad. 24 ISHARE 25 Current share pin. Connect this pin to other LMZ31710 device's ISHARE pin when paralleling multple LMZ31710 devices. When unused, treat this pin as a Do Not Connect (DNC) and leave it isolated from all other signals or ground. OCP_SEL 4 Over current protection select pin. Leave this pin open for hiccup mode operation. Connect this pin to AGND for cycle-by-cycle operation. See Overcurrent Protection for more details. ILIM 6 Current limit pin. Leave this pin open for full current limit threshold. Connect this pin to AGND to reduce the current limit threshold by appoximately 3 A. SYNC_OUT 7 Synchronization output pin. Provides a 180° out-of-phase clock signal. PWRGD 8 Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately ±6% out of regulation. A pull-up resistor is required. RT/CLK 22 This pin is connected to an internal frequency setting resistor which sets the default switching frequency. An external resistor can be connected from this pin to AGND to increase the frequency. This pin can also be used to synchronize to an external clock. VADJ 26 Connecting a resistor between this pin and AGND sets the output voltage. SENSE+ 27 Remote sense connection. This pin must be connected to VOUT at the load or at the device pins. Connect this pin to VOUT at the load for improved regulation. 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 Table 2. PIN DESCRIPTIONS (continued) TERMINAL DESCRIPTION NAME NO. SS/TR 28 Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time. A voltage applied to this pin allows for tracking and sequencing control. STSEL 29 Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave this pin open to enable the TR feature. INH/UVLO 30 Inhibit and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to control the INH function. A resistor divider between this pin, AGND, and PVIN/VIN sets the UVLO voltage. PVIN 1 AGND 2 VIN 40 39 PGND PGND VOUT VOUT VOUT VOUT VOUT PVIN PVIN RVQ PACKAGE (TOP VIEW) 38 37 36 35 34 33 32 31 PGND 30 INH/UVLO 3 29 STSEL OCP_SEL 4 28 SS/TR DNC 5 27 SENSE+ ILIM 6 26 VADJ SYNC_OUT 7 25 ISHARE PWRGD 8 24 DNC DNC 9 23 AGND 22 RT/CLK 21 PGND PGND PH PH PH 14 15 16 17 18 19 20 PH 12 13 PH 11 PH PH PVIN 42 PH 10 PVIN PH 41 VOUT Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 7 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (PVIN = VIN = 12 V) 100 30 Output Ripple Voltage (mV) 90 70 Vo = 5.0V, fsw = 1MHz Vo = 3.3V, fsw = 750kHz Vo = 2.5V, fsw = 750kHz Vo = 1.8V, fsw = 500kHz Vo = 1.2V, fsw = 300kHz Vo = 0.9V, fsw = 250kHz 60 50 40 0 1 2 3 4 5 6 7 8 9 Output Current (A) Vo = 5.0V, fsw = 1MHz Vo = 3.3V, fsw = 750kHz Vo = 2.5V, fsw = 750kHz Vo = 1.8V, fsw = 500kHz Vo = 1.2V, fsw = 300kHz Vo = 0.9V, fsw = 250kHz 25 20 15 10 5 0 10 3.5 3.0 Gain (dB) Power Dissipation (W) 4.0 2.5 2.0 1.5 40 120 30 90 20 60 10 30 0 0 ±30 ±10 ±60 ±90 Phase ±40 1000 0 2 4 6 8 Output Current (A) Frequency (Hz) 80 Ambient Temperature (C) 80 70 60 Airflow = 0 LFM 9R9IVZ N+] Vo = 2.5V, fsw = 750kHz Vo = 3.3V, fsw = 750kHz Vo = 5.0V, fsw = 1MHz 30 20 0 2 4 6 Output Current (A) C006 Figure 5. VOUT= 1.8 V, IOUT= 10 A, COUT1= 200 µF ceramic, fSW= 500 kHz 90 40 ±120 400k 100k C004 90 50 10k 10 Figure 4. Power Dissipation vs. Output Current Ambient Temperature (C) C004 ±30 0.0 8 70 60 50 Airflow = 200 LFM 40 9R9IVZ N+] Vo = 2.5V, fsw = 750kHz Vo = 3.3V, fsw = 750kHz Vo = 5.0V, fsw = 1MHz 30 20 10 0 C001 Figure 6. Safe Operating Area 8 10 Gain 0.5 (2) 8 ±20 1.0 (1) 6 Figure 3. Voltage Ripple vs. Output Current Vo = 5.0V, fsw = 1MHz Vo = 3.3V, fsw = 750kHz Vo = 2.5V, fsw = 750kHz Vo = 1.8V, fsw = 500kHz Vo = 1.2V, fsw = 300kHz Vo = 0.9V, fsw = 250kHz 4.5 4 Output Current (A) Figure 2. Efficiency vs. Output Current 5.0 2 C001 Phase () Efficiency (%) 80 (1) (2) 2 4 6 Output Current (A) 8 10 C001 Figure 7. Safe Operating Area The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 2, Figure 3, and Figure 4. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 2 oz. copper. Applies to Figure 6 and Figure 7. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 TYPICAL CHARACTERISTICS (PVIN = VIN = 5 V) 100 30 Output Voltage Ripple (mV) 80 70 Vo = 3.3V, fsw = 750kHz Vo = 2.5V, fsw = 750kHz Vo = 1.8V, fsw = 500kHz Vo = 1.2V, fsw = 300kHz Vo = 0.9V, fsw = 250kHz Vo = 0.6V, fsw = 200kHz 60 50 40 0 1 2 3 4 5 6 7 8 9 Output Current (A) 25 20 15 10 5 10 0 3.5 3.0 6 8 10 C004 Figure 9. Voltage Ripple vs. Output Current Gain (dB) Power Dissipation (W) 4.0 4 Output Current (A) Vo = 3.3V, fsw = 750kHz Vo = 2.5V, fsw = 750kHz Vo = 1.8V, fsw = 500kHz Vo = 1.2V, fsw = 300kHz Vo = 0.9V, fsw = 250kHz Vo = 0.6V, fsw = 200kHz 4.5 2 C001 Figure 8. Efficiency vs. Output Current 5.0 Vo = 3.3V, fsw = 750kHz Vo = 2.5V, fsw = 750kHz Vo = 1.8V, fsw = 500kHz Vo = 1.2V, fsw = 300kHz Vo = 0.9V, fsw = 250kHz Vo = 0.6V, fsw = 200kHz 2.5 2.0 1.5 40 120 30 90 20 60 10 30 0 0 ±30 ±10 Phase () Efficiency (%) 90 (1) (2) ±60 ±20 Gain 1.0 ±90 ±30 Phase 0.5 ±40 1000 0.0 0 2 4 6 8 10k 10 Output Current (A) 100k ±120 400k Frequency (Hz) C006 C004 Figure 10. Power Dissipation vs. Output Current Figure 11. VOUT= 1.8 V, IOUT= 10 A, COUT1= 200 µF ceramic, fSW= 500 kHz 90 Ambient Temperature (C) 80 70 60 50 Airflow = 0 LFM 40 All Output Voltages 30 20 0 2 4 6 8 Output Current (A) 10 C001 Figure 12. Safe Operating Area (1) (2) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 8, Figure 9, and Figure 10. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 2 oz. copper. Applies to Figure 12. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 9 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (PVIN = 3.3 V, VIN = 5 V) 100 30 Output Ripple Voltage (mV) 80 70 Vo = 2.5V, fsw = 750kHz Vo = 1.8V, fsw = 500kHz 60 Vo = 1.2V, fsw = 300kHz 50 Vo = 0.9V, fsw = 250kHz 25 20 15 10 Vo = 0.6V, fsw = 200kHz 40 0 1 2 3 4 5 6 7 8 9 Output Current (A) 5 10 0 3.5 3.0 6 8 10 C004 Figure 14. Voltage Ripple vs. Output Current Gain (dB) Power Dissipation (W) 4.0 4 Output Current (A) Vo = 2.5V, fsw = 750kHz Vo = 1.8V, fsw = 500kHz Vo = 1.2V, fsw = 300kHz Vo = 0.9V, fsw = 250kHz Vo = 0.6V, fsw = 200kHz 4.5 2 C001 Figure 13. Efficiency vs. Output Current 5.0 Vo = 2.5V, fsw = 750kHz Vo = 1.8V, fsw = 500kHz Vo = 1.2V, fsw = 300kHz Vo = 0.9V, fsw = 250kHz Vo = 0.6V, fsw = 200kHz 2.5 2.0 1.5 40 120 30 90 20 60 10 30 0 0 ±30 ±10 Phase () Efficiency (%) 90 (1) (2) ±60 ±20 Gain 1.0 ±90 ±30 Phase 0.5 ±40 1000 0.0 0 2 4 6 8 10k 10 Output Current (A) Frequency (Hz) 100k ±120 400k C006 C004 Figure 15. Power Dissipation vs. Output Current Figure 16. VOUT= 1.8 V, IOUT= 10 A, COUT1= 200 µF ceramic, fSW= 500 kHz 90 Ambient Temperature (C) 80 70 60 50 Airflow = 0 LFM 40 All Output Voltages 30 20 0 2 4 6 8 Output Current (A) 10 C001 Figure 17. Safe Operating Area (1) (2) 10 The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 13, Figure 14, and Figure 15. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 2 oz. copper. Applies to Figure 17. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 APPLICATION INFORMATION Adjusting the Output Voltage The VADJ control sets the output voltage of the LMZ31710. The output voltage adjustment range is from 0.6V to 5.5V. The adjustment method requires the addition of RSET, which sets the output voltage, the connection of SENSE+ to VOUT, and in some cases RRT which sets the switching frequency. The RSET resistor must be connected directly between the VADJ (pin 26) and AGND (pin 23). The SENSE+ pin (pin 27) must be connected to VOUT either at the load for improved regulation or at VOUT of the device. The RRT resistor must be connected directly between the RT/CLK (pin 22) and AGND (pin 23). Table 3 gives the standard external RSET resistor for a number of common bus voltages, along with the recommended RRT resistor for that output voltage. Table 3. Standard RSET Resistor Values for Common Output Voltages RESISTORS OUTPUT VOLTAGE VOUT (V) 0.9 1.0 1.2 1.8 2.5 3.3 5.0 RSET (kΩ) 2.87 2.15 1.43 0.715 0.453 0.316 0.196 RRT (kΩ) 1000 1000 487 169 90.9 90.9 63.4 For other output voltages, the value of the required resistor can either be calculated using the following formula, or simply selected from the range of values given in Table 4. 1.43 RSET = (kW ) æ æ VOUT ö ö çç ÷ - 1÷ è è 0.6 ø ø (1) Table 4. Standard RSET Resistor Values VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz) VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz) 0.6 open OPEN 200 3.1 0.348 90.9 750 0.7 8.66 OPEN 200 3.2 0.332 90.9 750 0.8 4.32 OPEN 200 3.3 0.316 90.9 750 0.9 2.87 1000 250 3.4 0.309 90.9 750 1.0 2.15 1000 250 3.5 0.294 90.9 750 1.1 1.74 1000 250 3.6 0.287 90.9 750 1.2 1.43 487 300 3.7 0.280 90.9 750 1.3 1.24 487 300 3.8 0.267 90.9 750 1.4 1.07 487 300 3.9 0.261 90.9 750 1.5 0.953 487 300 4.0 0.255 90.9 750 1.6 0.866 487 300 4.1 0.243 63.4 1000 1.7 0.787 487 300 4.2 0.237 63.4 1000 1.8 0.715 169 500 4.3 0.232 63.4 1000 1.9 0.665 169 500 4.4 0.226 63.4 1000 2.0 0.619 169 500 4.5 0.221 63.4 1000 2.1 0.576 169 500 4.6 0.215 63.4 1000 2.2 0.536 169 500 4.7 0.210 63.4 1000 2.3 0.511 169 500 4.8 0.205 63.4 1000 2.4 0.475 169 500 4.9 0.200 63.4 1000 2.5 0.453 90.9 750 5.0 0.196 63.4 1000 2.6 0.432 90.9 750 5.1 0.191 63.4 1000 2.7 0.412 90.9 750 5.2 0.187 63.4 1000 2.8 0.392 90.9 750 5.3 0.182 63.4 1000 2.9 0.374 90.9 750 5.4 0.178 63.4 1000 3.0 0.357 90.9 750 5.5 0.174 63.4 1000 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 11 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com Capacitor Recommendations for the LMZ31710 Power Supply Capacitor Technologies Electrolytic, Polymer-Electrolytic Capacitors When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended. Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures are above 0°C. Ceramic Capacitors The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz. Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient response of the output. Tantalum, Polymer-Tantalum Capacitors Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended for power applications. Input Capacitor The LMZ31710 requires a minimum input capacitance of 44 μF of ceramic type. An additional 100 µF of nonceramic capacitance is recommended for applications with transient load requirements. The voltage rating of input capacitors must be greater than the maximum input voltage. At worst case, when operating at 50% duty cycle and maximum load, the combined ripple current rating of the input capacitors must be at least 5 Arms. Table 6 includes a preferred list of capacitors by vendor. It is also recommended to place a 0.1 µF ceramic capacitor directly across the PVIN and PGND pins of the device. When operating with split VIN and PVIN rails, place 4.7µF of ceramic capacitance directly at the VIN pin. Output Capacitor The required output capacitance is determined by the output voltage of the LMZ31710. See Table 5 for the amount of required capacitance. The effects of temperature and capacitor voltage rating must be considered when selecting capacitors to meet the minimum required capacitance. The required output capacitance can be comprised of all ceramic capacitors, or a combination of ceramic and bulk capacitors. The required capacitance must include at least one 47 µF ceramic. When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones recommended in Table 6 are required. The required capacitance above the minimum is determined by actual transient deviation requirements. See Table 7 for typical transient response values for several output voltage, input voltage and capacitance combinations. Table 6 includes a preferred list of capacitors by vendor. Table 5. Required Output Capacitance VOUT RANGE (V) (1) 12 MINIMUM REQUIRED COUT (µF) MIN MAX 0.6 < 0.8 500 µF (1) 0.8 < 1.2 300 µF (1) 1.2 < 3.0 200 µF (1) 3.0 < 4.0 100 µF (1) 4.0 5.5 47 µF ceramic Minimum required must include at least one 47 µF ceramic capacitor. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 Table 6. Recommended Input/Output Capacitors (1) CAPACITOR CHARACTERISTICS VENDOR SERIES PART NUMBER WORKING VOLTAGE (V) CAPACITANCE (µF) ESR (2) (mΩ) Murata X5R GRM32ER61E226K 25 22 2 TDK X5R C3225X5R0J107M 6.3 100 2 TDK X5R C3225X5R0J476K 6.3 47 2 Murata X5R GRM32ER60J107M 6.3 100 2 Murata X5R GRM32ER60J476M 6.3 47 2 100 30 Panasonic EEH-ZA EEH-ZA1E101XP 25 Sanyo POSCAP 16TQC68M 16 68 50 Kemet T520 T520V107M010ASE025 10 100 25 Sanyo POSCAP 10TPE220ML 10 220 25 Sanyo POSCAP 6TPE100MI 6.3 100 25 Sanyo POSCAP 2R5TPE220M7 2.5 220 7 Kemet T530 T530D227M006ATE006 6.3 220 6 Kemet T530 T530D337M006ATE010 6.3 330 10 Sanyo POSCAP 2TPF330M6 2.0 330 6 Sanyo POSCAP 6TPE330MFL 6.3 330 15 (1) (2) Capacitor Supplier Verification, RoHS, Lead-free and Material Details Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table. Maximum ESR @ 100kHz, 25°C. Transient Response Table 7. Output Voltage Transient Response CIN1 = 3x 47 µF CERAMIC, CIN2 = 100 µF POLYMER-TANTALUM VOLTAGE DEVIATION (mV) VOUT (V) 0.6 COUT1 Ceramic COUT2 BULK 2.5 A LOAD STEP, (1 A/µs) 5 A LOAD STEP, (1 A/µs) 5 500 µF 220 µF 25 60 100 12 500 µF 220 µF 30 65 100 300 µF 220 µF 40 85 100 300 µF 470 µF 35 70 110 300 µF 220 µF 45 90 100 300 µF 470 µF 35 75 110 200 µF 220 µF 55 110 110 200 µF 470 µF 45 90 110 200 µF 220 µF 55 110 110 200 µF 470 µF 45 90 110 200 µF 220 µF 70 140 130 200 µF 470 µF 60 120 140 200 µF 220 µF 70 145 140 200 µF 470 µF 55 120 150 5 100 µF 220 µF 115 230 200 12 100 µF 220 µF 120 240 200 5 0.9 12 5 1.2 12 5 1.8 12 3.3 RECOVERY TIME (µs) VIN (V) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 13 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com Transient Waveforms 14 Figure 18. PVIN = 12V, VOUT = 0.9V, 2.5A Load Step Figure 19. PVIN = 5V, VOUT = 0.9V, 2.5A Load Step Figure 20. PVIN = 12V, VOUT = 1.2V, 2.5A Load Step Figure 21. PVIN = 5V, VOUT = 1.2V, 2.5A Load Step Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 Figure 22. PVIN = 12V, VOUT = 1.8V, 2.5A Load Step Figure 23. PVIN = 5V, VOUT = 1.8V, 2.5A Load Step Application Schematics LMZ31710 VIN VIN / PVIN 4.5 V to 17 V PVIN VOUT 1.2 V SENSE+ VOUT + + CIN1 CIN2 100 µF 47 µF CIN3 0.1 µF ISHARE SYNC_OUT COUT1 2x 100 µF COUT2 220 µF PWRGD INH/UVLO RT/CLK SS/TR VADJ STSEL AGND PGND RSET 1.43 k RRT 487 k Figure 24. Typical Schematic PVIN = VIN = 4.5 V to 17 V, VOUT = 1.2 V Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 15 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com LMZ31710 VIN VIN / PVIN 4.5 V to 17 V PVIN VOUT 3.3 V SENSE+ VOUT + + CIN1 CIN2 100 µF 47 µF CIN3 0.1 µF COUT1 100 µF ISHARE SYNC_OUT COUT2 220 µF PWRGD INH/UVLO RT/CLK SS/TR RRT 90.9 k VADJ STSEL AGND PGND RSET 316 Figure 25. Typical Schematic PVIN = VIN = 4.5 V to 17 V, VOUT = 3.3 V VIN 4.5 V to 17 V CIN3 4.7 µF VIN LMZ31710 VOUT 1.0 V SENSE+ PVIN 3.3 V PVIN VOUT + + CIN1 CIN2 100 µF 47 µF CIN3 0.1 µF ISHARE SYNC_OUT COUT1 3x 100 µF COUT2 220 µF PWRGD INH/UVLO RT/CLK SS/TR VADJ STSEL AGND PGND RSET 2.15 k RRT 1M Figure 26. Typical Schematic PVIN = 3.3 V, VIN = 4.5 V to 17 V, VOUT = 1.0 V 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 VIN and PVIN Input Voltage The LMZ31710 allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the power converter system. If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 17 V. If using the VIN pin separately from the PVIN pin, the VIN pin must be greater than 4.5 V, and the PVIN pin can range from as low as 2.95 V to 17 V. When operating from a split rail, it is recommended to supply VIN from 5 V to 12 V, for best performance. A voltage divider connected to the INH/UVLO pin can adjust either input voltage UVLO appropriately. See the Programmable Undervoltage Lockout (UVLO) section of this datasheet for more information. 3.3 V PVIN Operation Applications operating from a PVIN of 3.3 V must provide at least 4.5 V for VIN. It is recommended to supply VIN from 5 V to 12 V, for best performance. See application note, SNVA692 for help creating 5 V from 3.3 V using a small, simple charge pump device. Power Good (PWRGD) The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 95% and 104% of the set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the voltage on SENSE+ is lower than 91% or greater than 108% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V. Light Load Efficiency (LLE) The LMZ31710 operates in pulse skip mode at light load currents to improve efficiency and decrease power dissipation by reducing switching and gate drive losses. These pulses may cause the output voltage to rise when there is no load to discharge the energy. For output voltages < 1.5 V, a minimum load is required. The amount of required load can be determined by Equation 2. In most cases the minimum current drawn by the load circuit will be enough to satisfy this load. Applications requiring a load resistor to meet the minimum load, the added power dissipation will be ≤ 3.6 mW. A single 0402 size resistor across VOUT and PGND can be used. (2) When VOUT = 0.6 V and RSET = OPEN, the minimum load current is 600 µA. SYNC_OUT The LMZ31710 provides a 180° out-of-phase clock signal for applications requiring synchronization. The SYNC_OUT pin produces a 50% duty cycle clock signal that is the same frequency as the device's switching frequency, but is 180° out of phase. Operating two devices 180° out of phase reduces input and output voltage ripple. The SYNC_OUT clock signal is compatible with other LMZ3 devices that have a CLK input. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 17 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com Parallel Operation Up to six LMZ31710 devices can be paralleled for increased output current. Multiple connections must be made between the paralleled devices and the component selection is slightly different than for a stand-alone LMZ31710 device. A typical LMZ31710 parallel schematic is shown in Figure 27. Refer to application note, SNVA695 for information and design help when paralleling multiple LMZ31710 devices. VIN = 12V PWRGD VIN PVIN SENSE+ 220µF 22µF 0.1µF LMZ31710 22µF 100µF 100µF VADJ SS/TR PGND RSET 715 Ω 0.1µF LMZ31710 PWRGD SENSE+ VOUT SYNC_OUT RT/CLK 330µF VADJ VIN PVIN 100µF AGND CSS SS/TR Voltage Supervisor CSH INH Control ISHARE 5V 100µF STSEL ISHARE RRT 169kΩ INH/UVLO Sync Freq 500KHz INH/UVLO SYNC_OUT RT/CLK VO = 1.8V VOUT STSEL AGND RRT 169kΩ PGND Figure 27. Typical LMZ31710 Parallel Schematic 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 Power-Up Characteristics When configured as shown in the front page schematic, the LMZ31710 produces a regulated output voltage following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input source. Figure 28 shows the start-up waveforms for a LMZ31710, operating from a 5-V input (PVIN=VIN) and with the output voltage adjusted to 1.8 V. Figure 29 shows the start-up waveforms for a LMZ31710 starting up into a pre-biased output voltage. The waveforms were measured with a 5-A constant current load. Figure 28. Start-Up Waveforms Figure 29. Start-up into Pre-bias Pre-Biased Start-Up The LMZ31710 has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During pre-biased startup, the low-side MOSFET does not turn on until the high-side MOSFET has started switching. The high-side MOSFET does not start switching until the slow start voltage exceeds the voltage on the VADJ pin. Refer to Figure 29. Remote Sense The SENSE+ pin must be connected to VOUT at the load, or at the device pins. Connecting the SENSE+ pin to VOUT at the load improves the load regulation performance of the device by allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by the high output current flowing through the small amount of pin and trace resistance. This should be limited to a maximum of 300 mV. NOTE The remote sense feature is not designed to compensate for the forward drop of nonlinear or frequency dependent components that may be placed in series with the converter output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When these components are enclosed by the SENSE+ connection, they are effectively placed inside the regulation control loop, which can adversely affect the stability of the regulator. Thermal Shutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C typically. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 19 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com Output On/Off Inhibit (INH) The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low quiescent current state. The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device. If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to interface with the pin. Using a voltage superviser to control the INH pin allows control of the turn-on and turn-off of the device as opposed to relying on the ramp up or down if the input voltage source. Figure 30 shows the typical application of the inhibit function. Turning Q1 on applies a low voltage to the inhibit control (INH) pin and disables the output of the supply, shown in Figure 31. If Q1 is turned off, the supply executes a soft-start power-up sequence, as shown in Figure 32. A regulated output voltage is produced within 2 ms. The waveforms were measured with a 5-A constant current load. INH/UVLO Q1 INH Control AGND STSEL SS/TR Figure 30. Typical Inhibit Control Figure 31. Inhibit Turn-Off 20 Figure 32. Inhibit Turn-On Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 Slow Start (SS/TR) Connecting the STSEL pin to AGND and leaving SS/TR pin open enables the internal SS capacitor with a slow start interval of approximately 1.2 ms. Adding additional capacitance between the SS pin and AGND increases the slow start time. Increasing the slow start time will reduce inrush current seen by the input source and reduce the current seen by the device when charging the output capacitors. To avoid the activation of current limit and ensure proper start-up, the SS capacitor may need to be increased when operating near the maximum output capacitance limit. Table 8 shows an additional SS capacitor connected to the SS/TR pin and the STSEL pin connected to AGND. See Table 8 below for SS capacitor values and timing interval. SS/TR CSS (Optional) AGND STSEL Figure 33. Slow-Start Capacitor (CSS) and STSEL Connection Table 8. Slow-Start Capacitor Values and Slow-Start Time CSS (nF) open 3.3 4.7 10 15 22 33 SS Time (msec) 1.2 2.1 2.5 3.8 5.1 7.0 9.8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 21 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com Overcurrent Protection For protection against load faults, the LMZ31710 incorporates output overcurrent protection. The overcurrent protection mode can be selected using the OCP_SEL pin. Leaving the OCP_SEL pin open selects hiccup mode and connecting it to AGND selects cycle-by-cycle mode. In hiccup mode, applying a load that exceeds the regulator's overcurrent threshold causes the regulated output to shut down. Following shutdown, the module periodically attempts to recover by initiating a soft-start power-up as shown in Figure 34. This is described as a hiccup mode of operation, whereby the module continues in a cycle of successive shutdown and power up until the load fault is removed. During this period, the average current flowing into the fault is significantly reduced which reduces power dissipation. Once the fault is removed, the module automatically recovers and returns to normal operation as shown in Figure 35. In cycle-by-cycle mode, applying a load that exceeds the regulator's overcurrent threshold limits the output current and reduces the output voltage as shown in Figure 36. During this period, the current flowing into the fault remains high causing the power dissipation to stay high as well. Once the overcurrent condition is removed, the output voltage returns to the set-point voltage as shown in Figure 37. 22 Figure 34. Overcurrent Limiting (Hiccup) Figure 35. Removal of Overcurrent (Hiccup) Figure 36. Overcurrent Limiting (Cycle-by-Cycle) Figure 37. Removal of Overcurrent (Cycle-byCycle) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 Synchronization (CLK) An internal phase locked loop (PLL) has been implemented to allow synchronization between 200 kHz and 1200 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.5 V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 38. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by the RT resistor (RRT). External Clock 200 kHz to 1200 kHz RT/CLK RRT AGND Figure 38. RT/CLK Configuration The synchronization frequency must be selected based on the output voltages of the devices being synchronized. Table 9 shows the allowable frequencies for a given range of output voltages. For the most efficient solution, always synchronize to the lowest allowable frequency. For example, an application requires synchronizing three LMZ31710 devices with output voltages of 1.0 V, 1.2 V and 1.8 V, all powered from PVIN = 12 V. Table 9 shows that all three output voltages should be synchronized to 300 kHz. Table 9. Synchronization Frequency vs Output Voltage PVIN = 12 V SYNCHRONIZATION FREQUENCY (kHz) PVIN = 5 V VOUT RANGE (V) VOUT RANGE (V) MIN MAX MIN MAX 200 0.6 1.3 0.6 1.5 300 0.8 2.0 0.6 4.3 400 1.1 2.5 0.6 4.3 500 1.4 3.4 0.6 4.3 600 1.6 5.0 0.7 4.3 700 1.9 5.5 0.8 4.3 800 2.1 5.5 0.9 4.3 900 2.4 5.5 1.0 4.3 1000 2.7 5.5 1.1 4.3 1100 2.9 5.5 1.3 4.3 1200 3.2 5.5 1.4 4.3 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 23 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com Sequencing (SS/TR) Many of the common power supply sequencing methods can be implemented using the SS/TR, INH and PWRGD pins. The sequential method is illustrated in Figure 39 using two LMZ31710 devices. The PWRGD pin of the first device is coupled to the INH pin of the second device which enables the second power supply once the primary supply reaches regulation. Figure 40 shows sequential turn-on waveforms of two LMZ31710 devices. INH/UVLO VOUT1 VOUT STSEL PWRGD INH/UVLO VOUT2 VOUT STSEL PWRGD Figure 39. Sequencing Schematic Figure 40. Sequencing Waveforms Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 41 to the output of the power supply that needs to be tracked or to another voltage reference source. The tracking voltage must exceed 750mV before VOUT2 reaches its set-point voltage. The PWRGD output of the VOUT2 device may remain low if the tracking voltage does not exceed 1.4V. Figure 42 shows simultaneous turn-on waveforms of two LMZ31710 devices. Use Equation 3 and Equation 4 to calculate the values of R1 and R2. R1 = (VOUT2 ´ 12.6 ) 0.6 R2 = (kW ) (3) 0.6 ´ R1 (kW ) V ( OUT2 - 0.6 ) (4) VOUT1 VOUT INH/UVLO STSEL SS/TR VOUT2 VOUT INH/UVLO R1 STSEL SS/TR R2 Figure 41. Simultaneous Tracking Schematic 24 Figure 42. Simultaneous Tracking Waveforms Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 Programmable Undervoltage Lockout (UVLO) The LMZ31710 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 4.5 V(max) with a typical hysteresis of 150 mV. If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a combined VIN and PVIN, then the UVLO pin can be configured as shown in Figure 43 or Figure 44. Table 10 lists standard values for RUVLO1 and RUVLO2 to adjust the VIN UVLO voltage up. PVIN PVIN VIN VIN RUVLO1 RUVLO1 INH/UVLO INH/UVLO RUVLO2 RUVLO2 Figure 43. Adjustable VIN UVLO Figure 44. Adjustable VIN and PVIN Undervoltage Lockout Table 10. Standard Resistor values for Adjusting VIN UVLO VIN UVLO (V) 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 RUVLO1 (kΩ) 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 RUVLO2 (kΩ) 21.5 18.7 16.9 15.4 14.0 13.0 12.1 11.3 10.5 9.76 9.31 Hysteresis (mV) 400 415 430 450 465 480 500 515 530 550 565 For a split rail application, if a secondary UVLO on PVIN is required, VIN must be ≥ 4.5V. Figure 45 shows the PVIN UVLO configuration. Use Table 11 to select RUVLO1 and RUVLO2 for PVIN. If PVIN UVLO is set for less than 3.0 V, a 5.1-V zener diode should be added to clamp the voltage on the UVLO pin below 6 V. > 4.5 V VIN PVIN RUVLO1 INH/UVLO RUVLO2 Figure 45. Adjustable PVIN Undervoltage Lockout, (VIN ≥4.5 V) Table 11. Standard Resistor Values for Adjusting PVIN UVLO, (VIN ≥4.5 V) PVIN UVLO (V) 2.9 3.0 3.5 4.0 4.5 RUVLO1 (kΩ) 68.1 68.1 68.1 68.1 68.1 RUVLO2 (kΩ) 47.5 44.2 34.8 28.7 24.3 Hysteresis (mV) 330 335 350 365 385 For higher PVIN UVLO voltages see Table 10 for resistor values Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 25 LMZ31710 SNVS987A – JULY 2013 – REVISED JULY 2013 www.ti.com Layout Considerations To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 46 thru Figure 49, shows a typical PCB layout. Some considerations for an optimized layout are: • Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal stress. • Place ceramic input and output capacitors close to the device pins to minimize high frequency noise. • Locate additional output capacitors between the ceramic capacitor and the load. • Keep AGND and PGND separate from one another. • Place RSET, RRT, and CSS as close as possible to their respective pins. • Use multiple vias to connect the power planes to internal layers. 26 Figure 46. Typical Top-Layer Layout Figure 47. Typical Layer-2 Layout Figure 48. Typical Layer 3 Layout Figure 49. Typical Bottom-Layer Layout Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 LMZ31710 www.ti.com SNVS987A – JULY 2013 – REVISED JULY 2013 EMI The LMZ31710 is compliant with EN55022 Class B radiated emissions. Figure 50 and Figure 51 show typical examples of radiated emissions plots for the LMZ31710 operating from 5V and 12V respectively. Both graphs include the plots of the antenna in the horizontal and vertical positions. Figure 50. Radiated Emissions 5-V Input, 1.8-V Output, 10-A Load (EN55022 Class B) Figure 51. Radiated Emissions 12-V Input, 1.8-V Output, 10-A Load (EN55022 Class B) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LMZ31710 27 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMZ31710RVQR ACTIVE BQFN RVQ 42 500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 LMZ31710 LMZ31710RVQT ACTIVE BQFN RVQ 42 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 LMZ31710 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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