PRODUCT SPECIFICATIONS ® Integrated Circuits Group LRS1805A Stacked Chip 64M (x16) Flash Memory + 16M (x16) Smartcombo RAM (Model No.: LRS1805A) Spec No.: EL139030 Issue Date: September 18, 2001 sharp LRS1805A • Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. • When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). • • • • • • Office electronics Instrumentation and measuring equipment Machine tools Audiovisual equipment Home appliance Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. • Control and safety devices for airplanes, trains, automobiles, and other transportation equipment • Mainframe computers • Traffic control systems • Gas leak detectors and automatic cutoff devices • Rescue and security equipment • Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. • • • • Aerospace equipment Communications equipment for trunk lines Control equipment for the nuclear power industry Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. • Please direct all queries regarding the products covered herein to a sales representative of the company. sharp LRS1805A 1 Contents 1. Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Simultaneous Operation Modes Allowed with Four Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. Command Definitions for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Identifier Codes for Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Functions of Block Lock and Block Lock-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.4 Block Locking State Transitions upon Command Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Block Locking State Transitions upon F-WP Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. Status Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. Memory Map for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10. Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12. AC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Write Cycle (F-WE / F-CE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Block Erase, Full Chip Erase, (Page Buffer) Program Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 21 22 23 26 13. AC Electrical Characteristics for Smartcombo RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 Sleep Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6 Address Skew Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7 Data Retention Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8 Smartcombo RAM AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 28 29 29 29 29 30 14. Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 15. Flash Memory Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 16. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 17. Related Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 18. Package and Packing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 sharp LRS1805A 2 1. Description The LRS1805A is a combination memory organized as 4,194,304 x16 bit flash memory and 1,048,576 x16 bit Smartcombo RAM in one package. Features - Power supply - Operating temperature • • • • • • • • 2.7V to 3.3V(Flash) 2.7V to 3.1V(Smartcombo RAM) • • • • -25°C to +85°C - Not designed or rated as radiation hardened - 72pin CSP (LCSP072-P-0811) plastic package - Flash memory has P-type bulk silicon, and Smartcombo RAM has P-type bulk silicon Flash Memory - Access Time • • • • 85 ns (Max.) - Power supply current (The current for F-VCC pin and F-VPP pin) Read • • • • 25 mA (Max. tCYCLE = 200ns, CMOS Input) Word write Block erase Reset Power-Down • • • • • • • • • • • • 60 mA 30 mA 25 µA (Max.) (Max.) (Max. F-RST = GND ± 0.2V, IOUT (F-RY/BY) = 0mA) Standby • • • • 25 µA (Max. F-CE = F-RST = F-VCC ± 0.2V) - Optimized Array Blocking Architecture Eight 4K-word Parameter Blocks One-hundred and twenty-seven 32K-word Main Blocks Top Parameter Location - Extended Cycling Capability 100,000 Block Erase Cycles (F-VPP = 1.65V to 3.3V) 1,000 Block Erase Cycles and total 80 hours (F-VPP = 11.7V to 12.3V) - Enhanced Automated Suspend Options Word Write Suspend to Read Block Erase Suspend to Word Write Block Erase Suspend to Read Smartcombo RAM - Access Time • • • • 85 ns - Cycle time • • • • 85 to 32,000 ns - Power Supply current Operating current • • • • 20 mA (Max. tRC, tWC = Min.) • • • • • • • • 80 µA 15 µA (Max.) (Max.) Standby current (Data retention current) Sleep Mode (Data non-retention current) (Max.) sharp LRS1805A 3 2. Pin Configuration !" # $%&' ()%' *(+ )( ,$-. /*% -%%0%0 )( 1% (,%-23 &( ,$-. /) )4% 5(*-%* /*% 5(--%5)%02 ( -() 67(/) /-8 ,$-.2 sharp LRS1805A Pin Description A0 to A16, A18, A19 Address Inputs (Common) F-A17, F-A20, F-A21 4 Type Input Address Inputs (Flash) Input S-A17 Address Input (Smartcombo RAM) Input F-CE Chip Enable Input (Flash) Input S-CE1 Chip Enable Input (Smartcombo RAM) Input S-CE2 Sleep State Input (Smartcombo RAM) Input F-WE Write Enable Input (Flash) Input S-WE Write Enable Input (Smartcombo RAM) Input F-OE Output Enable Input (Flash) Input S-OE Output Enable Input (Smartcombo RAM) Input S-LB Smartcombo RAM Byte Enable Input (DQ0 to DQ7) Input S-UB Smartcombo RAM Byte Enable Input (DQ8 to DQ15) Input F-RST Reset Power Down Input (Flash) Block erase and Write : VIH Read : VIH Reset Power Down : VIL Input F-WP Write Protect Input (Flash) When F-WP is VIL, locked-down blocks cannot be unlocked. Erase or program operation can be executed to the blocks which are not locked and locked-down. When F-WP is VIH, lock-down is disabled. Input F-RY/BY DQ0 to DQ15 Ready/Busy Output (Flash) During an Erase or Write operation : VOL Block Erase and Write Suspend : High-Z (High impedance) Data Inputs and Outputs (Common) Open Drain Output Input / Output F-VCC Power Supply (Flash) Power S-VCC Power Supply (Smartcombo RAM) Power F-VPP Monitoring Power Supply Voltage (Flash) Block Erase and Write : F-VPP = VPPH1/2 All Blocks Locked : F-VPP < VPPLK Input GND GND (Common) Power NC Non Connection - Test pins (Should be all open) - T1 to T4 sharp LRS1805A 5 3. Truth Table 3.1 Bus Operation(1) Smart combo RAM Flash Read Notes F-CE F-RST F-OE F-WE S-CE1 S-CE2 S-OE S-WE S-LB S-UB DQ0 to DQ15 3,5 Output Disable Standby L 5 L Write 2,3,4,5 Read 3,5 Output Disable Sleep H H Read Standby Write 5,6 Read 5,6 Standby Reset Power Standby Down Standby Reset Power Sleep Down 5,6 X X High - Z X DIN L H (7) H H X L X X High - Z X DIN L 5,6 5,6 Write H L 5 Output Disable Reset Power Output Down Disable H L 2,3,4,5 Write (7) H H H X L X X X X L L H H 5,6 5 H H 5,6 X L 5 H H 5,6 X L L H X H H H (8) H H X X X L High - Z (8) L H X H H H (8) H H X X X L High - Z (8) X X H H X X X High - Z X X X L X X X High - Z Notes: 1. L = VIL, H = VIH, X = H or L, High-Z = High impedance. Refer to the DC Characteristics. 2. Command writes involving block erase (page buffer) program are reliably executed when F-VPP = VPPH1/2 and F-VCC = 2.7V to 3.3V. Command writes involving full chip erase is reliably executed when F-VPP = VPPH1 and F-VCC = 2.7V to 3.3V. Block erase, full chip erase, (page buffer) program with F-VPP < VPPH1/2 (Min.) produce spurious results and should not be attempted. 3. Never hold F-OE low and F-WE low at the same timing. 4. Refer Section 5. Command Definitions for Flash Memory valid DIN during a write operation. 5. F-WP set to VIL or VIH. 6. Electricity consumption of Flash Memory is lowest when F-RST = GND ±0.2V. 7. Flash Read Mode Mode Read Array Read Identifier Codes Read Query 8. S-UB, S-LB Control Mode Address DQ0 to DQ15 X DOUT L L DOUT/DIN DOUT/DIN See 5.2 See 5.2 L H DOUT/DIN High - Z H L High - Z DOUT/DIN Refer to the Appendix Refer to the Appendix S-LB S-UB DQ0 to DQ7 DQ8 to DQ15 sharp LRS1805A 6 3.2 Simultaneous Operation Modes Allowed with Four Planes(1, 2) THEN THE MODES ALLOWED IN THE OTHER PARTITION IS: IF ONE PARTITION IS: Read Array Read ID Read Status Read Query Word Program Page Buffer Program Block Erase Read Array X X X X X X X X X Read ID X X X X X X X X X Full Chip Program Erase Suspend Read Status X X X X X X X Read Query X X X X X X X Word Program X X X X X Page Buffer Program X X X X X Block Erase X X X X Full Chip Erase X Block Erase Suspend X X X X X Program Suspend X X X X Block Erase Suspend X X X X X X X X Notes: 1. “X” denotes the operation available. 2. Configurative Partition Dual Work Restrictions: Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition. Only one partition can be erased or programmed at a time - no command queuing. Commands must be written to an address within the block targeted by that command. sharp LRS1805A 7 4. Block Diagram F-VCC F-A17, F-A20, F-A21 A0 to A16, A18, A19 F-CE F-OE F-WE F-WP F-RST S-A17 S-CE1 S-CE2 S-OE S-WE S-LB S-UB F-VPP 64M (x16) bit Flash memory F-RY/BY DQ0 to DQ15 16M (x16) bit Smartcombo RAM S-VCC GND sharp LRS1805A 8 5. Command Definitions for Flash Memory(11) 5.1 Command Definitions Bus Cycles Req’d Notes 1 Read Identifier Codes Read Query Command Read Array First Bus Cycle Second Bus Cycle Oper(1) Address(2) Data(3) Oper(1) Address(2) Data(3) 2 Write PA FFH ≥2 2,3,4 Write PA 90H Read IA ID ≥2 2,3,4 Write PA 98H Read QA QD Read Status Register 2 2,3 Write PA 70H Read PA SRD Clear Status Register 1 2 Write PA 50H Block Erase 2 2,3,5 Write BA 20H Write BA D0H Full Chip Erase 2 2,5,9 Write X 30H Write X D0H Write WA WD Write WA N-1 2 2,3,5,6 Write WA 40H or 10H ≥4 2,3,5,7 Write WA E8H Block Erase and (Page Buffer) Program Suspend 1 2,8,9 Write PA B0H Block Erase and (Page Buffer) Program Resume 1 2,8,9 Write PA D0H Set Block Lock Bit 2 2 Write BA 60H Write BA 01H Clear Block Lock Bit 2 2,10 Write BA 60H Write BA D0H Set Block Lock-down Bit 2 2 Write BA 60H Write BA 2FH Set Partition Configuration Register 2 2,3 Write PCRC 60H Write PCRC 04H Program Page Buffer Program Notes: 1. Bus operations are defined in 3.1 Bus Operation. 2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle. X=Any valid address within the device. PA=Address within the selected partition. IA=Identifier codes address (See 5.2 Identifier Codes for Read Operation). QA=Query codes address. Refer to the LH28F320BF, LH28F640BF series Appendix for details. BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA=Address of memory location for the Program command or the first address for the Page Buffer Program command. PCRC=Partition configuration register code presented on the address A0-A15. 3. ID=Data read from identifier codes (See 5.2 Identifier Codes for Read Operation). QD=Data read from query database. Refer to the LH28F320BF, LH28F640BF series Appendix for details. SRD=Data read from status register. See 6. Status Register Definition for a description of the status register bits. WD=Data to be programmed at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first). N-1=N is the number of the words to be loaded into a page buffer. 4. Following the Read Identifier Codes command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code (See 5.2 Identifier Codes for Read Operation). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when F-RST is VIH. 6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. 7. Following the third bus cycle, inputs the program sequential address and write data of “N” times. Finally, input the any valid address within the target partition to be programmed and the confirm command (D0H). Refer to the LH28F320BF, LH28F640BF series Appendix for details. sharp LRS1805A 8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. Full chip erase operation can not be suspended. 10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when F-WP is VIL. When F-WP is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. 9 sharp LRS1805A 10 5.2 Identifier Codes for Read Operation Code Address [A15-A0](4) Data [DQ15-DQ0] Notes Manufacturer Code Manufacturer Code 0000H 00B0H Device Code 64M Top Parameter Device Code 0001H 00B0H 1 DQ0 = 0 2 DQ0 = 1 2 DQ1 = 0 2 DQ1 = 1 2 PCRC 3 Block is Unlocked Block Lock Configuration Code Block Address +2 Block is Locked Block is not Locked-Down Block is Locked-Down Device Configuration Code Partition Configuration Register 0006H Notes: 1. Top parameter device has its parameter blocks in the plane 3 (The highest address). 2. DQ15-DQ2 is reserved for future implementation. 3. PCRC=Partition Configuration Register Code. 4. The address A21-A16 are shown in below table for reading the manufacturer, device, lock configuration, device configuration code. The address to read the identifier codes is dependent on the partition which is selected when writing the Read Identifier Codes command (90H). See Chapter 6. Partition Configuration Register Definition (P.15) for the partition configuration register. Identifier Codes for Read Operation on Partition Configuration (64M-bit device) Partition Configuration Register Address (64M-bit device) [A21-A16] PCR.10 PCR.9 PCR.8 0 0 0 00H 0 0 1 00H or 10H 0 1 0 00H or 20H 1 0 0 00H or 30H 0 1 1 00H or 10H or 20H 1 1 0 00H or 20H or 30H 1 0 1 00H or 10H or 30H 1 1 1 00H or 10H or 20H or 30H sharp LRS1805A 11 5.3 Functions of Block Lock and Block Lock-Down Current State State (1) F-WP DQ1 DQ0(1) Erase/Program Allowed (2) State Name [000] 0 0 0 Unlocked Yes [001](3) 0 0 1 Locked No [011] 0 1 1 Locked-down No [100] 1 0 0 Unlocked Yes [101](3) 1 0 1 Locked No [110](4) 1 1 0 Lock-down Disable Yes [111] 1 1 1 Lock-down Disable No Notes: 1. DQ0 = 1: a block is locked; DQ0 = 0: a block is unlocked. DQ1 = 1: a block is locked-down; DQ1 = 0: a block is not locked-down. 2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (F-WP = 0) or [101] (F-WP = 1), regardless of the states before power-off or reset operation. 4. When F-WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 5.4 Block Locking State Transitions upon Command Write(4) Current State Result after Lock Command Written (Next State) State F-WP DQ1 DQ0 Set Lock(1) Clear Lock(1) [000] 0 0 0 [001] No Change [001] 0 0 1 No Change(3) [000] [011] [011] 0 1 1 No Change No Change No Change [100] 1 0 0 [101] No Change [111](2) [101] 1 0 1 No Change [100] [111] [110] 1 1 0 [111] No Change [111](2) [111] 1 1 1 No Change [110] No Change Set Lock-down(1) [011](2) Notes: 1. “Set Lock” means Set Block Lock Bit command, “Clear Lock” means Clear Block Lock Bit command and “Set Lockdown” means Set Block Lock-Down Bit command. 2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0 = 0), the corresponding block is locked-down and automatically locked at the same time. 3. “No Change” means that the state remains unchanged after the command written. 4. In this state transitions table, assumes that F-WP is not changed and fixed VIL or VIH. sharp LRS1805A 12 5.5 Block Locking State Transitions upon F-WP Transition(4) Current State Previous State [110] Result after F-WP Transition (Next State) State F-WP DQ1 DQ0 F-WP = 0→1(1) F-WP = 1→0(1) [000] 0 0 0 [100] - [001] 0 0 1 [101] - [110] - [111] - (2) [011] 0 1 1 - [100] 1 0 0 - [000] - [101] 1 0 1 - [001] - [110] 1 1 0 - [011](3) - [111] 1 1 1 - [011] Other than [110](2) Notes: 1. “F-WP = 0→1” means that F-WP is driven to VIH and “F-WP = 1→0” means that F-WP is driven to VIL. 2. State transition from the current state [011] to the next state depends on the previous state. 3. When F-WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked. 4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. sharp LRS1805A 13 6. Status Register Definition Status Register Definition R R R R R R R R 15 14 13 12 11 10 9 8 WSMS BESS BEFCES PBPS VPPS PBPSS DPS R 7 6 5 4 3 2 1 0 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS (BEFCES) 1 = Error in Block Erase or Full Chip Erase 0 = Successful Block Erase or Full Chip Erase SR.4 = (PAGE BUFFER) PROGRAM STATUS (PBPS) 1 = Error in (Page Buffer) Program 0 = Successful (Page Buffer) Program SR.3 = F-VPP STATUS (VPPS) 1 = F-VPP LOW Detect, Operation Abort 0 = F-VPP OK SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) 1 = (Page Buffer) Program Suspended 0 = (Page Buffer) Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) Notes: Status Register indicates the status of the partition, not WSM (Write State Machine). Even if the SR.7 is “1”, the WSM may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. Check SR.7 or F-RY/BY to determine block erase, full chip erase, (page buffer) program completion. SR.6 - SR.1 are invalid while SR.7= “0”. If both SR.5 and SR.4 are “1”s after a block erase, full chip erase, page buffer program, set/clear block lock bit, set block lock-down bit or set partition configuration register attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of F-VPP level. The WSM interrogates and indicates the F-VPP level only after Block Erase, Full Chip Erase, (Page Buffer) Program command sequences. SR.3 is not guaranteed to report accurate feedback when F-VPP≠VPPH1/2 or VPPLK. SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, Full Chip Erase, (Page Buffer) Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes command indicates block lock bit status. SR.15 - SR.8 and SR.0 are reserved for future use and should be masked out when polling the status register. sharp LRS1805A Extended Status Register Definition R R 14 R R R R R R 15 14 13 12 11 10 9 8 SMS R R R R R R R 7 6 5 4 3 2 1 0 Notes: XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS) 1 = Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) After issue a Page Buffer Program command (E8H), XSR.7=“1” indicates that the entered command is accepted. If XSR.7 is “0”, the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not. XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status register. sharp LRS1805A 15 Partition Configuration Register Definition R R PC2 R R R 15 14 13 12 11 R R R R 7 6 5 4 PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = Plane 0-1 and Plane2-3 are merged into one partition respectively. 100 = Plane 0-2 are merged into one partition. (default in a top parameter device) 011 = Plane 2-3 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 110 = Plane 0-1 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. 101 = Plane 1-2 are merged into one partition. There are three partitions in this configuration. Dual work operation is available between any two partitions. PC1 PC0 10 9 8 R R R R 3 2 1 0 111 = There are four partitions in this configuration. Each plane corresponds to each partition respectively. Dual work operation is available between any two partitions. PCR.7-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) Notes: After power-up or device reset, PCR10-8 (PC2-0) is set to “001” in a bottom parameter device and “100” in a top parameter device. See the table below for more details. PCR.15-11 and PCR.7-0 are reserved for future use and should be masked out when polling the partition configuration register. Partition Configuration PLANE0 PLANE1 PLANE3 PLANE2 PLANE0 PLANE1 PLANE2 1 1 0 PLANE3 PARTITION2 PARTITION1 PARTITION0 PLANE0 PLANE1 1 0 1 PLANE2 PARTITION2 PARTITION1 PARTITION0 PLANE3 PLANE0 PLANE0 PARTITIONING FOR DUAL WORK PARTITION2 PARTITION1 PARTITION0 PLANE0 PLANE1 PLANE2 1 1 1 PLANE3 PARTITION3 PARTITION2 PARTITION1 PARTITION0 PLANE0 PLANE1 PLANE2 PLANE3 0 1 1 PARTITION0 PARTITION1 1 0 0 PLANE1 PARTITION0 PLANE1 PLANE2 PARTITION1 PLANE2 0 1 0 PC2 PC1PC0 PARTITION0 PLANE3 0 0 1 PLANE3 PARTITION1 PLANE0 PLANE1 PLANE2 0 0 0 PARTITIONING FOR DUAL WORK PARTITION0 PLANE3 PC2 PC1PC0 sharp LRS1805A 16 7. Memory Map for Flash Memory Top Parameter 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 4K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 3FF000H - 3FFFFFH 3FE000H - 3FEFFFH 3FD000H - 3FDFFFH 3FC000H - 3FCFFFH 3FB000H - 3FBFFFH 3FA000H - 3FAFFFH 3F9000H - 3F9FFFH 3F8000H - 3F8FFFH 3F0000H - 3F7FFFH 3E8000H - 3EFFFFH 3E0000H - 3E7FFFH 3D8000H - 3DFFFFH 3D0000H - 3D7FFFH 3C8000H - 3CFFFFH 3C0000H - 3C7FFFH 3B8000H - 3BFFFFH 3B0000H - 3B7FFFH 3A8000H - 3AFFFFH 3A0000H - 3A7FFFH 398000H - 39FFFFH 390000H - 397FFFH 388000H - 38FFFFH 380000H - 387FFFH 378000H - 37FFFFH 370000H - 377FFFH 368000H - 36FFFFH 360000H - 367FFFH 358000H - 35FFFFH 350000H - 357FFFH 348000H - 34FFFFH 340000H - 347FFFH 338000H - 33FFFFH 330000H - 337FFFH 328000H - 32FFFFH 320000H - 327FFFH 318000H - 31FFFFH 310000H - 317FFFH 308000H - 30FFFFH 300000H - 307FFFH 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 2F8000H - 2FFFFFH 2F0000H - 2F7FFFH 2E8000H - 2EFFFFH 2E0000H - 2E7FFFH 2D8000H - 2DFFFFH 2D0000H - 2D7FFFH 2C8000H - 2CFFFFH 2C0000H - 2C7FFFH 2B8000H - 2BFFFFH 2B0000H - 2B7FFFH 2A8000H - 2AFFFFH 2A0000H - 2A7FFFH 298000H - 29FFFFH 290000H - 297FFFH 288000H - 28FFFFH 280000H - 287FFFH 278000H - 27FFFFH 270000H - 277FFFH 268000H - 26FFFFH 260000H - 267FFFH 258000H - 25FFFFH 250000H - 257FFFH 248000H - 24FFFFH 240000H - 247FFFH 238000H - 23FFFFH 230000H - 237FFFH 228000H - 22FFFFH 220000H - 227FFFH 218000H - 21FFFFH 210000H - 217FFFH 208000H - 20FFFFH 200000H - 207FFFH BLOCK NUMBER ADDRESS RANGE PLANE1 (UNIFORM PLANE) 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 PLANE0 (UNIFORM PLANE) PLANE2 (UNIFORM PLANE) PLANE3 (PARAMETER PLANE) BLOCK NUMBER ADDRESS RANGE 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 1F8000H - 1FFFFFH 1F0000H - 1F7FFFH 1E8000H - 1EFFFFH 1E0000H - 1E7FFFH 1D8000H - 1DFFFFH 1D0000H - 1D7FFFH 1C8000H - 1CFFFFH 1C0000H - 1C7FFFH 1B8000H - 1BFFFFH 1B0000H - 1B7FFFH 1A8000H - 1AFFFFH 1A0000H - 1A7FFFH 198000H - 19FFFFH 190000H - 197FFFH 188000H - 18FFFFH 180000H - 187FFFH 178000H - 17FFFFH 170000H - 177FFFH 168000H - 16FFFFH 160000H - 167FFFH 158000H - 15FFFFH 150000H - 157FFFH 148000H - 14FFFFH 140000H - 147FFFH 138000H - 13FFFFH 130000H - 137FFFH 128000H - 12FFFFH 120000H - 127FFFH 118000H - 11FFFFH 110000H - 117FFFH 108000H - 10FFFFH 100000H - 107FFFH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 32K-WORD 0F8000H - 0FFFFFH 0F0000H - 0F7FFFH 0E8000H - 0EFFFFH 0E0000H - 0E7FFFH 0D8000H - 0DFFFFH 0D0000H - 0D7FFFH 0C8000H - 0CFFFFH 0C0000H - 0C7FFFH 0B8000H - 0BFFFFH 0B0000H - 0B7FFFH 0A8000H - 0AFFFFH 0A0000H - 0A7FFFH 098000H - 09FFFFH 090000H - 097FFFH 088000H - 08FFFFH 080000H - 087FFFH 078000H - 07FFFFH 070000H - 077FFFH 068000H - 06FFFFH 060000H - 067FFFH 058000H - 05FFFFH 050000H - 057FFFH 048000H - 04FFFFH 040000H - 047FFFH 038000H - 03FFFFH 030000H - 037FFFH 028000H - 02FFFFH 020000H - 027FFFH 018000H - 01FFFFH 010000H - 017FFFH 008000H - 00FFFFH 000000H - 007FFFH sharp LRS1805A 17 8. Absolute Maximum Ratings Symbol Parameter VCC Supply voltage VIN Input voltage TA Notes Ratings Unit 1,2 -0.2 to +3.6 V 1,2,3,4 -0.5 to VCC +0.3 V Operating temperature -25 to +85 °C TSTG Storage temperature -65 to +125 °C F-VPP F-VPP voltage -0.2 to +12.6 V 1,3,5 Notes: 1. The maximum applicable voltage on any pins with respect to GND. 2. Except F-VPP. 3. -1.0V undershoot is allowed when the pulse width is less than 5 nsec. 4. VIN should not be over VCC +0.3V. 5. Applying 12V ±0.3V to F-VPP during erase/write can only be done for a maximum of 1000 cycles on each block. F-VPP may be connected to 12V ±0.3V for total of 80 hours maximum. +13.0V overshoot is allowed when the pulse width is less than 20 nsec. 9. Recommended DC Operating Conditions (TA = -25°C to +85°C) Symbol Parameter Notes Min. Typ. Max. Unit 3.0 3.3 V F-VCC Supply Voltage 2.7 S-VCC Supply Voltage 2.7 3.1 V VIH Input Voltage VCC -0.3 (2) VCC +0.3 (1) V VIL Input Voltage -0.3 0.3 V Notes: 1. VCC is the lower of F-VCC or S-VCC. 2. VCC is the higher of F-VCC or S-VCC. 10. Pin Capacitance(1) (TA = 25°C, f = 1MHz) Symbol Parameter Notes Min. Typ. Max. Unit Condition CIN Input capacitance 15 pF VIN = 0V CI/O I/O capacitance 25 pF VI/O = 0V Note: 1. Sampled but not 100% tested. sharp LRS1805A 18 11. DC Electrical Characteristics(1) DC Electrical Characteristics (TA = -25°C to +85°C, F-VCC = 2.7V to 3.3V, S-VCC = 2.7V to 3.1V) Symbol Parameter Notes Min. Typ. Max. Unit Test Conditions ILI Input Load Current ±1.5 µA VIN = VCC or GND ILO Output Leakage Current ±1.5 µA VOUT = VCC or GND ICCS F-VCC Standby Current ICCAS F-VCC Automatic Power Savings Current ICCD F-VCC Reset Power-Down Current ICCR 2 4 20 µA F-VCC = F-VCC Max., F-CE = F-RST = F-VCC ±0.2V, F-WP = F-VCC or GND 2,5 4 20 µA F-VCC = F-VCC Max., F-CE = GND ±0.2V, F-WP = F-VCC or GND 2 4 20 µA F-RST = GND ±0.2V IOUT (F-RY/BY) = 0mA Average F-VCC Read Current Normal Mode 2,10 15 25 mA Average F-VCC 8 Word Read Read Current Page Mode 2,10 5 10 mA 2,6,10 20 60 mA F-VPP = VPPH1 2,6,10 10 20 mA F-VPP = VPPH2 2,6,10 10 30 mA F-VPP = VPPH1 2,6,10 10 30 mA F-VPP = VPPH2 F-VCC = F-VCC Max., F-CE = VIL, F-OE = VIH, f = 5MHz IOUT = 0mA ICCW F-VCC (Page Buffer) Program Current ICCE F-VCC Block Erase, Full Chip Erase Current ICCWS ICCES F-VCC (Page Buffer) Program or Block Erase Suspend Current 2,3,10 10 200 µA F-CE = VIH IPPS IPPR F-VPP Standby or Read Current 2,7,10 2 5 µA F-VPP ≤ F-VCC IPPW F-VPP (Page Buffer) Program Current 2,6,7,10 2 5 µA F-VPP = VPPH1 2,6,7,10 10 30 mA F-VPP = VPPH2 IPPE F-VPP Block Erase, Full Chip Erase Current 2,6,7,10 2 5 µA F-VPP = VPPH1 2,6,7,10 5 15 mA F-VPP = VPPH2 IPPWS F-VPP (Page Buffer) Program Suspend Current 2,7,10 2 5 µA F-VPP = VPPH1 2,7,10 10 200 µA F-VPP = VPPH2 IPPES F-VPP Block Erase Suspend Current 2,7,10 2 5 µA F-VPP = VPPH1 2,7,10 10 200 µA F-VPP = VPPH2 sharp LRS1805A 19 DC Electrical Characteristics (Continue) (TA = -25°C to +85°C, F-VCC = 2.7V to 3.3V, S-VCC = 2.7V to 3.1V) Symbol Parameter Notes Min. Typ. Max. Unit Conditions ISB S-VCC Standby Current 8 80 µA S-CE1 ≥ S-VCC - 0.2V ISLP S-VCC Sleep Mode Current 9 15 µA S-CE2 ≤ 0.2V ICC1 S-VCC Operation Current 20 mA tCYCLE = Min., II/O = 0mA ICC2 S-VCC Operation Current 3 mA tCYCLE = 1µs, II/O = 0mA VIL Input Low Voltage 6 -0.3 0.3 V VCC -0.3 VCC +0.3 V 0.3 V IOL = 0.5mA V IOH = -0.5mA VIH Input High Voltage 6 VOL Output Low Voltage 6 VOH Output High Voltage 6 VCC -0.3 VPPLK F-VPP Lockout during Normal Operations VPPH1 F-VPP during Block Erase, Full Chip Erase,(PageBuffer) Program 7 1.65 VPPH2 F-VPP during Block Erase, (PageBuffer) Program 7 11.7 VLKO F-VCC Lockout Voltage 4,6,7 1.5 0.4 V 3 3.3 V 12 12.3 V V Notes: 1. VCC includes both F-VCC and S-VCC. 2. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC = 3.0V and TA = +25°C unless VCC is specified. 3. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend mode, the device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. 4. Block erase, full chip erase, (page buffer) program are inhibited when F-VPP ≤ VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.) , between VPPH1 (max.) and VPPH2 (min.) and above VPPH2 (max.). 5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (tAVQV) provide new data when addresses are changed. 6. Sampled, not 100% tested. 7. F-VPP is not used for power supply pin. With F-VPP ≤ VPPLK, block erase, full chip erase, (page buffer) program cannot be executed and should not be attempted. Applying 12V ±0.3V to F-VPP provides fast erasing or fast programming mode. In this mode, F-VPP is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and layout considerations given to the VCC power bus. Applying 12V ±0.3V to F-VPP during erase/program can only be done for a maximum of 1000 cycles on each block. F-VPP may be connected to 12V ±0.3V for a total of 80 hours maximum. 8. Memory cell data is held. (S-CE2 = “VIH”) 9. Memory cell data is not held. (S-CE2 = “VIL”) 10. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane. sharp LRS1805A 20 12. AC Electrical Characteristics for Flash Memory 12.1 AC Test Conditions Input pulse level 0 V to 2.7 V Input rise and fall time 5 ns Input and Output timing Ref. level 1.35 V 1TTL + CL (50pF) Output load 12.2 Read Cycle (TA = -25°C to +85°C, F-VCC = 2.7V to 3.3V) Symbol Parameter Notes Min. Max. Unit tAVAV Read Cycle Time tAVQV Address to Output Delay tELQV F-CE to Output Delay tAPA Page Address Access Time tGLQV F-OE to Output Delay tPHQV F-RST High to Output Delay tEHQZ, tGHQZ F-CE or F-OE to Output in High-Z, Whichever Occurs First 1 tELQX F-CE to Output in Low-Z 1 0 ns tGLQX F-OE to Output in Low-Z 1 0 ns tOH Output Hold from First Occurring Address, F-CE or F-OE change 1 0 ns 85 2 2 Notes: 1. Sampled, not 100% tested. 2. F-OE may be delayed up to tELQV − tGLQV after the falling edge of F-CE without impact to tELQV. ns 85 ns 85 ns 35 ns 20 ns 150 ns 20 ns sharp LRS1805A 21 12.3 Write Cycle (F-WE / F-CE Controlled)(1,2) (TA = -25°C to +85°C, F-VCC = 2.7V to 3.3V) Symbol tAVAV Parameter Notes Write Cycle Time Min. Max. Unit 85 ns tPHWL (tPHEL) F-RST High Recovery to F-WE (F-CE) Going Low 3 150 ns tELWL (tWLEL) F-CE (F-WE) Setup to F-WE (F-CE) Going Low 4 0 ns tWLWH (tELEH) F-WE (F-CE) Pulse Width 4 60 ns tDVWH (tDVEH) Data Setup to F-WE (F-CE) Going High 8 40 ns tAVWH (tAVEH) Address Setup to F-WE (F-CE) Going High 8 50 ns tWHEH (tEHWH) F-CE (F-WE) Hold from F-WE (F-CE) High 0 ns tWHDX (tEHDX) Data Hold from F-WE (F-CE) High 0 ns tWHAX (tEHAX) Address Hold from F-WE (F-CE) High 0 ns tWHWL (tEHEL) F-WE (F-CE) Pulse Width High 5 30 ns tSHWH (tSHEH) F-WP High Setup to F-WE (F-CE) Going High 3 0 ns tVVWH (tVVEH) F-VPP Setup to F-WE (F-CE) Going High 3 200 ns 30 ns tWHGL (tEHGL) Write Recovery before Read tQVSL F-WP High Hold from Valid SRD, F-RY/BY High-Z 3, 6 0 ns tQVVL F-VPP Hold from Valid SRD, F-RY/BY High-Z 3, 6 0 ns F-WE (F-CE) High to SR.7 Going “0” 3, 7 tAVQV+40 ns 3 100 ns tWHR0 (tEHR0) tWHRL (tEHRL) F-WE (F-CE) High to F-RY/BY Going Low Notes: 1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program operations are the same as during read-only operations. See the AC Characteristics for read cycle. 2. A write operation can be initiated and terminated with either F-CE or F-WE. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from the falling edge of F-CE or F-WE (whichever goes low last) to the rising edge of F-CE or F-WE (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH. 5. Write pulse width high (tWPH) is defined from the rising edge of F-CE or F-WE (whichever goes high first) to the falling edge of F-CE or F-WE (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL. 6. F-VPP should be held at F-VPP=VPPH1/2 until determination of block erase, (page buffer) program success (SR.1/3/4/5=0) and held at F-VPP=VPPH1 until determination of full chip erase success (SR.1/3/5=0). 7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes command=tAVQV+100ns. 8. See 5.1 Command Definitions for valid address and data for block erase, full chip erase, (page buffer) program or lock bit configuration. sharp LRS1805A 22 12.4 Block Erase, Full Chip Erase, (Page Buffer) Program Performance(3) (TA = -25°C to +85°C, F-VCC = 2.7V to 3.3V) Symbol tWPB tWMB Parameter Page Buffer Command Notes is Used or not Used 4K-Word Parameter Block Program Time 2 2 32K-Word Main Block Program Time 2 2 tWHQV1/ Word Program Time tEHQV1 F-VPP=VPPH1 (In System) Min. Not Used Typ. (1) F-VPP=VPPH2 (In Manufacturing) Max. (2) 0.05 0.3 Used 0.03 Not Used 0.38 Used 2 Min. Typ.(1) Unit (2) Max. 0.04 0.12 s 0.12 0.02 0.06 s 2.4 0.31 1 s 0.24 1 0.17 0.5 s Not Used 11 200 9 185 µs 2 Used 7 100 5 90 µs tWHQV2/ 4K-Word Parameter Block tEHQV2 Erase Time 2 - 0.3 4 0.2 4 s tWHQV3/ 32K-Word Main Block tEHQV3 Erase Time 2 - 0.6 5 0.5 5 s 80 700 Full Chip Erase Time 2 tWHRH1/ (Page Buffer) Program Suspend tEHRH1 Latency Time to Read 4 - 5 10 5 10 µs tWHRH2/ Block Erase Suspend tEHRH2 Latency Time to Read 4 - 5 20 5 20 µs 5 - tERES Latency Time from Block Erase Resume Command to Block Erase Suspend Command 500 s 500 µs Notes: 1. Typical values measured at F-VCC =3.0V, F-VPP =3.0V or 12V, and TA=+25°C. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. 4. A latency time is required from writing suspend command (F-WE or F-CE going high) until SR.7 going “1”or F-RY/BY going High-Z. 5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished. sharp LRS1805A 23 12.5 Flash Memory AC Characteristics Timing Chart AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes or Query Code VIH A21-0 (A) VALID ADDRESS VIL tAVQV tEHQZ tGHQZ VIH F-CE (E) VIL tELQV VIH F-OE (G) VIL VIH F-WE (W) VIL tGLQV tGLQX tELQX VOH DQ15-0 (D/Q) High-Z VALID OUTPUT VOL tPHQV VIH F-RST (P) VIL tOH sharp LRS1805A 24 AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks A21-3 (A) VIH VALID ADDRESS VIL tAVQV A2-0 (A) VIH VIL VALID VALID VALID VALID ADDRESS ADDRESS ADDRESS ADDRESS VIH F-CE (E) VIL tELQV tEHQZ tGHQZ VIH F-OE (G) VIL VIH F-WE (W) tGLQV VIL tGLQX tAPA tELQX DQ15-0 (D/Q) VOH High-Z VOL tPHQV VIH F-RST (P) VIL tOH VALID VALID VALID VALID OUTPUT OUTPUT OUTPUT OUTPUT sharp LRS1805A 25 AC Waveform for Write Operations(F-WE / F-CE Controlled) NOTE 1 A21-0 (A) VIH VIL NOTE 2 NOTE 3 VALID ADDRESS VALID ADDRESS tAVAV NOTE 4 NOTE 5 VALID ADDRESS tAVWH (tAVEH) tWHAX (tEHAX) VIH F-CE (E) NOTES 5, 6 VIL tELWL (tWLEL) tWHEH (tEHWH) tWHGL (tEHGL) NOTES 5, 6 VIH F-OE (G) VIL tPHWL (tPHEL) tWHWL (tEHEL) VIH F-WE (W) VIL tWLWH (tELEH ) DQ15-0 (D/Q) tWHQV1,2,3 (tEHQV1,2,3) tWHDX (tEHDX) tDVWH (tDVEH) VIH VIL DATA IN tWHR0 (tEHR0) High-Z F-RY/BY (R) VALID SRD DATA IN tWHRL (tEHRL) ( 1 ) VOL (SR.7) ( 0 ) F-RST (P) VIH VIL tSHWH (tSHEH) tQVSL tVVWH (tVVEH) tQVVL VIH F-WP (S) VIL VPPH1,2 F-VPP (V) VPPLK VIL Notes: 1. F-VCC power-up and standby. 2. Write each first cycle command. 3. Write each second cycle command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operation, F-OE and F-CE must be driven active, and F-WE de-asserted. sharp LRS1805A 26 12.6 Reset Operations (TA = -25°C to +85°C, F-VCC = 2.7V to 3.3V) Symbol Parameter Notes Min. 100 tPLPH F-RST Low to Reset during Read (F-RST should be low during power-up.) 1, 2, 3 tPLRH F-RST Low to Reset during Erase or Program 1, 3, 4 tVPH F-VCC 2.7V to F-RST High 1, 3, 5 tVHQV F-VCC 2.7V to Output Delay 3 Max. Unit ns µs 22 100 ns 1 ms Notes: 1. A reset time, tPHQV, is required from the later of SR.7 (F-RY/BY) going “1” (High-Z) or F-RST going high until outputs are valid. See the AC Characteristics - read cycle for tPHQV. 2. tPLPH is <100ns the device may still reset but this is not guaranteed. 3. Sampled, not 100% tested. 4. If F-RST asserted while a block erase, full chip erase or (page buffer) program operation is not executing, the reset will complete within 100ns. 5. When the device power-up, holding F-RST low minimum 100ns is required after F-VCC has been in predefined range and also has been in stable there. AC Waveform for Reset Operation F-RST(P) tPHQV VIH VIL DQ15-0 (D/Q) VOH VOL VIH VIL DQ15-0 (D/Q) VOH VOL tPLPH High-Z (A) Reset during Read Array Mode tPLRH F-RST (P) F-VCC ABORT SR.7=1 COMPLETE tPHQV tPLPH High-Z VALID OUTPUT (B) Reset during Erase or Program Mode 2.7V GND tVHQV tVPH F-RST(P) VALID OUTPUT tPHQV VIH VIL DQ15-0 (D/Q) VOH VOL High-Z (C) F-RST rising timing VALID OUTPUT sharp LRS1805A 27 13. AC Electrical Characteristic for Smartcombo RAM 13.1 AC Test Conditions 0.3 V to VCC - 0.3 V Input pulse level Input rise and fall time 3 ns 1/2 VCC Input and Output timing Ref. level 1TTL +CL (50pF)(1) Output load Note: 1. Including scope and socket capacitance. 13.2 Read Cycle (1,2,3) (TA = -25°C to +85°C, S-VCC = 2.7V to 3.1V) Symbol Parameter Notes Min. Max. Unit 85 32,000 ns tRC Read Cycle Time tAA Address Access Time 85 ns tACE Chip Enable Access Time 85 ns tOE Output Enable to Output Valid 40 ns tBE Byte Enable Access Time 40 ns tASC Address Setup to S-CE1Low 0 ns tAHC Address Hold to S-CE1 High 0 ns tC1H S-CE1 High Pulse Width 30 ns tCLZ S-CE1 Low to Output Active 0 ns tCHZ S-CE1 High to Output in High-Z tBLZ S-UB or S-LB Low to Output Active tBHZ S-UB or S-LB High to Output in High-Z tOLZ S-OE Low to Output Active tOHZ S-OE High to Output in High-Z tOH Output Hold from Address Change 30 0 ns ns 30 0 ns ns 30 5 ns ns Notes: It is possible to control data width by S-LB and S-UB pins. 1. Reading data from lower byte Data can be read when the address is set while holding S-CE1 = Low, S-CE2 = High, S-OE = Low, S-WE = High and S-LB = Low. 2. Reading data from upper byte Data can be read when the address is set while holding S-CE1 = Low, S-CE2 = High, S-OE = Low, S-WE = High and S-UB = Low. 3. Reading data from both bytes Data can be read when the address is set while holding S-CE1 = Low, S-CE2 = High, S-OE = Low, S-WE = High, S-LB = Low and S-UB = Low. sharp LRS1805A 28 13.3 Write Cycle (1,2,3,4,5,6,7,8) (TA = -25°C to +85°C, S-VCC = 2.7V to 3.1V) Symbol Parameter Notes Min. Max. Unit 32,000 ns tWC Write Cycle Time 85 tCW Chip Enable to End of Write 70 ns tASC Address Setup to S-CE1 Low 0 ns tAHC Address Hold to S-CE1 High 0 ns tC1H S-CE1 High Pulse Width 30 ns tAW Address Valid to End of Write 70 ns tAS Address Setup Time 0 ns tWP Write Pulse Width 40 ns tBW Byte Select Time 70 ns tWR Write Recovery Time 0 ns tDW Input Data Setup Time 35 ns tDH Input Data Hold Time 0 ns tOW S-WE High to Output Active 5 ns tWHZ S-WE Low to Output in High-Z 30 ns Notes: 1. Writing data into lower byte (S-WE controlled) 1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE1 = Low, S-CE2 = High, S-LB = Low and S-UB = High. 2) The data on lower byte are latched up into the memory cell during S-WE = Low and S-LB = Low. 2. Witing data into lower byte (S-LB controlled) 1) Data can be written by adding Low pulse into S-LB when the address is set while holding S-CE1 = Low, S-CE2 = High, S-UB = High and S-WE = Low. 2) The data on lower byte are latched up into memory cell during S-WE = Low and S-LB = Low. 3. Writing data into upper byte (S-WE controlled) 1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE1 = Low, S-CE2 = High, S-LB = High and S-UB = Low. 2) The data on upper byte are latched up into the memory cell during S-WE = Low and S-UB = Low. 4. Writing data into upper byte (S-UB controlled) 1) Data can be written by adding Low pulse S-UB when the address is set while holding S-CE1 = Low, S-CE2 = High, S-LB = High and S-WE = Low. 2) The data on upper byte are latched up into the memory cell during S-WE = Low and S-UB = Low. 5. Writing data into both byte (S-WE controlled) 1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE1 = Low, S-CE2 = High, S-LB = Low and S-UB = Low. 2) The data are latched up into the memory cell during S-WE = Low, S-LB = Low and S-UB = Low. 6. Writing data into both byte (S-LB, S-UB controlled) 1) Data can be written by adding Low pulse into S-LB and S-UB when the address is set while holding S-CE1 = Low, S-CE2 = High and S-WE = Low. 2) The data are latched up into the memory cell during S-WE = Low, S-LB = Low and S-UB = Low 7. Read or write with using both S-LB and S-UB, the timing edge of S-LB and S-UB must be same. 8. While DQ pins are in the output state, the data that is opposite to the output data should not be given. sharp LRS1805A 29 13.4 Power Up Timing (TA = -25°C to +85°C, S-VCC = 2.7V to 3.1V) Symbol Parameter tSHU S-CE1, S-CE2 Setup Time after Power Up tHPU Standby Hold Time after Power Up Notes Min. Max. Unit 0 ns 300 µs 13.5 Sleep Mode Timing(1) (TA = -25°C to +85°C, S-VCC = 2.7V to 3.1V) Symbol Parameter Notes Min. Max. Unit tSSP S-CE1 High Setup Time for Sleep Mode Entry 0 ns tSHP S-CE1 High Hold Time before Sleep Mode Exit 0 ns tC2LP S-CE2 Low Pulse Width 30 ns tHPD S-CE1 High Hold Time after Sleep Mode Exit 300 µs Note: 1. When S-CE2 is low, the device will be in the Sleep Mode. In this case, an internal refresh stops and the data might be lost. 13.6 Address Skew Timing (TA = -25°C to +85°C, S-VCC = 2.7V to 3.1V) Symbol tSKEW Parameter Notes Min. Maximum Address Skew Max. Unit 10 ns 13.7 Data Retention Timing(1) (TA = -25°C to +85°C, S-VCC = 2.7V to 3.1V) Symbol Parameter Notes Min. Max. Unit tBAH Address Hold Time during Active 85 32,000 ns tCSH S-CE1 Low Hold Time for Address Fix 85 32,000 ns Note: 1. Either tBAH or tCSH required for data retention. sharp LRS1805A 30 13.8 Smartcombo RAM AC Characteristics Timing Chart Read Cycle Timing Chart #$% ! " #$% &'& ( # )*)& + #$% sharp LRS1805A 31 Write Cycle Timing Chart (S-WE Controlled) Address S-CE1 S-UB S-LB S-WE DOUT DIN tWC VIH ADDRESS STABLE VIL tAW VIH VIL tASC VIH VIL tCW tAHC tBW tAS tWP tWR VIH VIL VOH Data Undefined VOL VIH tOW tWHZ tDW High-Z VIL Notes: 1. If S-OE = High, DOUT will be a High-Z state. 2. S-CE2 and S-WE must be High level for entire write cycle. tDH VALID INPUT High-Z sharp LRS1805A 32 Write Cycle Timing Chart (S-UB, S-LB Controlled) ((, ! "## $ % % & & %'( )* $ #+# , ', ", -.-# sharp LRS1805A 33 Standby Mode Timing Address S-CE1 VIH VIL tC1H VIH VIL tAHC tASC Standby Active Active Note: 1. When S-CE1= High, the device will be in the standby cycle. In this case data DQ pins are High-Z and all input pins are inhibited. Power Up Timing VIH S-CE1 S-CE2 VIL tSHU VIH VIL S-VCC VIH VIL VCC (min.) tHPU sharp LRS1805A 34 Sleep Mode Timing VIH S-CE1 VIL tSHP tC2LP S-CE2 VIH VIL tSSP Address Skew Timing 1 VIH Address VIL tSKEW VIH S-CE1 VIL Note: 1. tSKEW is from first address change to last address change. tRC / tWC tHPD sharp LRS1805A 35 Address Skew Timing 2 VIH Address VIL tSKEW tRC / tWC VIH S-CE1 VIL Note: 1. tSKEW is from activate to last address change. Address Skew Timing 3 VIH Address VIL tSKEW VIH S-CE1 VIL Note: 1. tSKEW is from first address change to standby. sharp LRS1805A Data Retention Timing 1 VIH Address tBAH VIL S-CE1 VIH VIL Notes: 1. This applies for both read and write. Data Retention Timing 2 tCSH VIH Address No Change VIL VIH S-CE1 VIL Notes: 1. This applies for both read and write. 36 sharp LRS1805A 37 14. Notes This product is a stacked CSP package that a 64M (x16) bit Flash Memory and a 16M (x16) bit Smartcombo RAM are assembled into. - Supply Power Maximum difference (between F-VCC and S-VCC) of the voltage is less than 0.3V. - Power Supply and Chip Enable of Flash Memory and Smartcombo RAM (F-CE, S-CE1, S-CE2) S-CE1 should not be low and S-CE2 should not be high when F-CE is low simultaneously. If the two memories are active together, possibly they may not operate normally by interference noises or data collision on DQ bus. Both F-VCC and S-VCC are needed to be applied by the recommended supply voltage at the same time expect Smartcombo RAM data retention mode. - Power Up Sequence When turning on Flash memory power supply, keep F-RST low. After F-VCC reaches over 2.7V, keep F-RST low for more than 100 nsec. - Device Decoupling The power supply is needed to be designed carefully because one of the Smartcombo RAM and the Flash Memory is in standby mode when the other is active. A careful decoupling of power supplies is necessary between Smartcombo RAM and Flash Memory. Note peak current caused by transition of control signals (F-CE, S-CE1, S-CE2). sharp LRS1805A 38 15. Flash Memory Data Protection Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted as false commands and causes undesired memory updating. To protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate: The below describes data protection method. 1. Protection of data in each block • Αny locked block by setting its block lock bit is protected against the data alternation. When F-WP is low, any lockeddown block by setting its block lock-down bit is protected from lock status changes. By using this function, areas can be defined, for example, program area (locked blocks), and data area (unlocked blocks). • For detailed block locking scheme, see Chapter 5.Command Definitions for Flash Memory. 2. Protection of data with F-VPP control • When the level of F-VPP is lower than VPPLK (F-VPP lockout voltage), write functions to all blocks are disabled. All blocks are locked and the data in the blocks are completely protected. 3. Protection of data with F-RST • Especially during power transitions such as power-up and power-down, the flash memory enters reset mode by bringing F-RST to low, which inhibits write operation to all blocks. • For detailed description on F-RST control, see Chapter 12.6 AC Electrical Characteristics for Flash Memory, Reset Operations. Protection against noises on F-WE signal To prevent the recognition of false commands as write commands, system designer should consider the method for reducing noises on F-WE signal. sharp LRS1805A 39 16. Design Considerations 1. Power Supply Decoupling To avoid a bad effect to the system by flash memory and Smartcombo RAM power switching characteristics, each device should have a 0.1µF ceramic capacitor connected between F-VCC and GND, between F-VPP and GND and between S-VCC and GND. Low inductance capacitors should be placed as close as possible to package leads. 2. F-VPP Trace on Printed Circuit Boards Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the F-VPP Power Supply trace. Use similar trace widths and layout considerations given to the FVCC power bus. 3. The Inhibition of Overwrite Operation Please do not execute reprograming “0” for the bit which has already been programed “0”. Overwrite operation may generate unerasable bit. In case of reprograming “0” to the data which has been programed “1”. • Program “0” for the bit in which you want to change data from “1” to “0”. • Program “1” for the bit which has already been programed “0”. For example, changing data from “1011110110111101” to “1010110110111100” requires “1110111111111110” programing. 4. Power Supply Block erase, full chip erase, word write with an invalid F-VPP (See Chapter 11. DC Electrical Characteristics) produce spurious results and should not be attempted. Device operations at invalid F-VCC voltage (See Chapter 11. DC Electrical Characteristics) produce spurious results and should not be attempted. 17. Related Document Information(1) Document No. FUM00701 Document Name LH28F320BF, LH28F640BF Series Appendix Note: 1. International customers should contact their local SHARP or distribution sales offices. LRS1805A sharp i A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) F-VCC GND tVR tVPH tPHQV VIH F-RP (P) VIL (F-RST) F-VCCW *1 VCCWH1/2 (VPPH1/2) (V) GND (F-VPP) tR or tF tR or tF tAVQV VIH Valid ADDRESS (A) Address VIL tF tR tELQV VIH F-CE (E) (F-BE) VIL VIH F-WE (W) VIL tF tR tGLQV VIH F-OE (G) VIL VIH F-WP (S) VIL VOH DATA (D/Q) High-Z Valid Output VOL *1 To prevent the unwanted writes, system designers should consider the design, which applies F-V CCW (F-VPP) to 0V during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations. See the application note AP-007-SW-E for details. Figure A-1. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “AC Electrical Characteristics for Flash Memory” described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page. Rev. 1.10 LRS1805A sharp ii A-1.1.1 Rise and Fall Time Symbol Parameter Notes Min. Max. Unit 1 0.5 30000 µs/V tVR F-VCC Rise Time tR Input Signal Rise Time 1, 2 1 µs/V tF Input Signal Fall Time 1, 2 1 µs/V NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. Rev. 1.10 sharp LRS1805A iii A-1.2 Glitch Noises Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal Input Signal VIH (Min.) VIH (Min.) VIL (Max.) VIL (Max.) Input Signal Input Signal (a) Acceptable Glitch Noises (b) NOT Acceptable Glitch Noises Figure A-2. Waveform for Glitch Noises See the “DC Electrical Characteristics” described in specifications for VIH (Min.) and VIL (Max.). Rev. 1.10 sharp LRS1805A iv A-2 RELATED DOCUMENT INFORMATION(1) Document No. Document Name AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory AP-007-SW-E RP#, VPP Electric Potential Switching Circuit NOTE: 1. International customers should contact their local SHARP or distribution sales office. Rev. 1.10 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. 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