LHF64P01
• Handle this document carefully for it contains material protected by international copyright law. Any reproduction,
full or in part, of this material is prohibited without the express written permission of the company.
• When using the products covered herein, please observe the conditions written herein and the precautions outlined in
the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly
adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas. When using the
products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure
to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph
(3).
• Office electronics
• Instrumentation and measuring equipment
• Machine tools
• Audiovisual equipment
• Home appliance
• Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which demands high
reliability, should first contact a sales representative of the company and then accept responsibility for
incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring
reliability and safety of the equipment and the overall system.
• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
• Mainframe computers
• Traffic control systems
• Gas leak detectors and automatic cutoff devices
• Rescue and security equipment
• Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely high performance
in terms of functionality, reliability, or accuracy.
• Aerospace equipment
• Communications equipment for trunk lines
• Control equipment for the nuclear power industry
• Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales
representative of the company.
• Please direct all queries regarding the products covered herein to a sales representative of the company.
Rev. 0.06
LHF64P01
1
CONTENTS
PAGE
PAGE
56-Lead TSOP (Normal Bend) Pinout ....................... 3
1 Electrical Specifications ........................................ 16
Pin Descriptions.......................................................... 4
1.1 Absolute Maximum Ratings........................... 16
CE0, CE1, CE2 Truth Table ....................................... 5
1.2 Operating Conditions ..................................... 16
Memory Map .............................................................. 6
1.2.1 Capacitance.............................................. 17
Identifier Codes Address ............................................ 7
1.2.2 AC Input/Output Test Conditions............ 17
OTP Block Address Map............................................ 8
1.2.3 DC Characteristics................................... 18
Bus Operation............................................................. 9
1.2.4 AC Characteristics Read-Only Operations .............................. 20
Command Definitions .............................................. 10
1.2.5 AC Characteristics - Write Operations.... 24
Functions of Block Lock .......................................... 12
1.2.6 Reset Operations...................................... 26
Status Register Definition......................................... 13
Extended Status Register Definition ........................ 14
1.2.7 Block Erase, (Page Buffer) Program
and Block Lock Configuration
Performance.............................................. 27
STS Configuration Definition .................................. 15
2 Related Document Information ............................. 28
3 Package and packing specification........................ 29
Rev. 0.06
LHF64P01
2
LH28F640SPHT-PTL12
64Mbit (4Mbit×16/8Mbit×8)
Page Mode Flash MEMORY
64-Mbit Density
• Bit Organization ×8/×16
High Performance Page Mode Reads
for Memory Array
• 120/25ns 4-Word/ 8-Byte Page Mode
VCC=2.7V-3.6V Operation
• VCCQ for Input/Output Power Supply Isolation
• Automatic Power Savings Mode reduces ICCR
in Static Mode
OTP (One Time Program) Block
• 4-Word/ 8-Byte Factory-Programmed Area
• 3963-Word/ 7926-Byte User-Programmable Area
High Performance Program with Page Buffer
• 16-Word/ 32-Byte Page Buffer
• Page Buffer Program Time 12.5µs/byte (Typ.)
Operating Temperature -40°C to +85°C
Symmetrically-Blocked Architecture
• Sixty-four 64-KWord/ 128-KByte Blocks
Enhanced Data Protection Features
• Individual Block Lock
• Absolute Protection with VPEN≤VPENLK
• Block Erase, (Page Buffer) Program Lockout during
Power Transitions
Automated Erase/Program Algorithms
• Program Time 210µs (Typ.)
• Block Erase Time 1s (Typ.)
Cross-Compatible Command Support
• Basic Command Set
• Common Flash Interface (CFI)
Extended Cycling Capability
• Minimum 100,000 Block Erase Cycles
56-Lead TSOP (Normal Bend)
CMOS Process (P-type silicon substrate)
ETOXTM* Flash Technology
Not designed or rated as radiation hardened
The product, which is Page Mode Flash memory, is a high density, low cost, nonvolatile read/write storage solution for a
wide range of applications. The product can operate at VCC=2.7V-3.6V and VPEN=2.7V-3.6V
The product supports high performance page mode. It allows code execution directly from Flash, thus eliminating time
consuming wait states.
Fast program capability is provided through the use of high speed Page Buffer Program.
The block locking scheme is available for memory array and this scheme provides maximum flexibility for safe nonvolatile
code and data storage.
OTP (One Time Program) block provides an area to store security code and to protect its code.
* ETOX is a trademark of Intel Corporation.
Rev. 0.06
LHF64P01
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-LEAD TSOP
STANDARD PINOUT
14mm x 20mm
TOP VIEW
3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
WE#
OE#
STS
DQ15
DQ7
DQ14
DQ6
GND
DQ13
DQ5
DQ12
DQ4
VCCQ
GND
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
NC
CE2
Figure 1. 56-Lead TSOP (Normal Bend) Pinout
Rev. 0.06
LHF64P01
4
Table 1. Pin Descriptions
Symbol
Type
Name and Function
A0
INPUT
ADDRESS INPUTS: Lowest address input in byte mode (BYTE#=VIL : ×8 bit).
Address is internally latched during an erase or a program cycle. This pin is not used in
word mode (BYTE#=VIH : ×16 bit)
A22-A1
INPUT
ADDRESS INPUTS: Inputs for addresses during read, erase and program operations.
Addresses are internally latched during an erase or a program cycle.
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code,
identifier code reads. Data pins float to high-impedance (High Z) when the chip or
outputs are deselected. Data is internally latched during an erase or program cycle.
DQ15-DQ8 pins are not used in byte mode (BYTE#=VIL : ×8 bit).
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. When the device is de-selected, power consumption reduces to standby
levels. Refer to Table 2 to determine whether the device is selected or de-selected
depending on the state of CE0, CE1 and CE2.
RP#
INPUT
RESET: When low (VIL), RP# resets internal automation and inhibits erase and program
operations, which provides data protection. RP#-high (VIH) enables normal operation.
After power-up or reset mode, the device is automatically set to read array mode.
RP# must be low during power-up/down.
OE#
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE#
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the first edge of CE0, CE1 or CE2 that disables the device or the rising edge of
WE# (whichever occurs first).
DQ15-DQ0
CE0,
CE1,
CE2
STS
STATUS: Indicates the status of the internal WSM (Write State Machine). When
configured in level mode (default mode), STS acts as a RY/BY# pin (STS is VOL when
OPEN DRAIN
the WSM is executing internal erase or program algorithms). When configured in one of
OUTPUT
its pulse modes, STS can pulse to indicate erase/program completion. Refer to Table 9
for STS configuration.
BYTE#
INPUT
BYTE ENABLE: BYTE# VIL places the device in byte mode (×8). In this mode, DQ15DQ8 is floated (High Z) and A0 is the lowest address input. BYTE# VIH places the
device in word mode (×16) and A1 is the lowest address input.
VPEN
INPUT
MONITORING POWER SUPPLY VOLTAGE: VPEN is not used for power supply pin.
With VPEN≤VPENLK, block erase, (page buffer) program, block lock configuration and
OTP program cannot be executed and should not be attempted.
VCC
SUPPLY
DEVICE POWER SUPPLY (2.7V-3.6V): With VCC≤VLKO, all write attempts to the
flash memory are inhibited. Device operations at invalid VCC voltage (refer to DC
Characteristics) produce spurious results and should not be attempted.
VCCQ
SUPPLY
INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output
pins.
GND
SUPPLY
NC
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
Rev. 0.06
LHF64P01
5
Table 2. CE0, CE1, CE2 Truth Table (1)
CE2
CE1
CE0
Device
VIL
VIL
VIL
Enabled
VIL
VIL
VIH
Disabled
VIL
VIH
VIL
Disabled
VIL
VIH
VIH
Disabled
VIH
VIL
VIL
Enabled
VIH
VIL
VIH
Enabled
VIH
VIH
VIL
Enabled
VIH
VIH
VIH
Disabled
NOTE:
1. For single-chip applications, CE1 and CE2 can be connected to GND.
Rev. 0.06
LHF64P01
6
[A22-A1]
[A22-A0]
[A22-A1]
3FFFFF
3F0000
3EFFFF
3E0000
3DFFFF
3D0000
3CFFFF
3C0000
3BFFFF
3B0000
3AFFFF
3A0000
39FFFF
390000
38FFFF
380000
37FFFF
370000
36FFFF
360000
35FFFF
350000
34FFFF
340000
33FFFF
330000
32FFFF
320000
31FFFF
310000
30FFFF
300000
2FFFFF
2F0000
2EFFFF
2E0000
2DFFFF
2D0000
2CFFFF
2C0000
2BFFFF
2B0000
2AFFFF
2A0000
29FFFF
290000
28FFFF
280000
27FFFF
270000
26FFFF
260000
25FFFF
250000
24FFFF
240000
23FFFF
230000
22FFFF
220000
21FFFF
210000
20FFFF
200000
7FFFFF
7E0000
7DFFFF
7C0000
7BFFFF
7A0000
79FFFF
780000
77FFFF
760000
75FFFF
740000
73FFFF
720000
71FFFF
700000
6FFFFF
6E0000
6DFFFF
6C0000
6BFFFF
6A0000
69FFFF
680000
67FFFF
660000
65FFFF
640000
63FFFF
620000
61FFFF
600000
5FFFFF
5E0000
5DFFFF
5C0000
5BFFFF
5A0000
59FFFF
580000
57FFFF
560000
55FFFF
540000
53FFFF
520000
51FFFF
500000
4FFFFF
4E0000
4DFFFF
4C0000
4BFFFF
4A0000
49FFFF
480000
47FFFF
460000
45FFFF
440000
43FFFF
420000
41FFFF
400000
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
64-Kword/128-Kbyte Block 63
64-Kword/128-Kbyte Block 62
64-Kword/128-Kbyte Block 61
64-Kword/128-Kbyte Block 60
64-Kword/128-Kbyte Block 59
64-Kword/128-Kbyte Block 58
64-Kword/128-Kbyte Block 57
64-Kword/128-Kbyte Block 56
64-Kword/128-Kbyte Block 55
64-Kword/128-Kbyte Block 54
64-Kword/128-Kbyte Block 53
64-Kword/128-Kbyte Block 52
64-Kword/128-Kbyte Block 51
64-Kword/128-Kbyte Block 50
64-Kword/128-Kbyte Block 49
64-Kword/128-Kbyte Block 48
64-Kword/128-Kbyte Block 47
64-Kword/128-Kbyte Block 46
64-Kword/128-Kbyte Block 45
64-Kword/128-Kbyte Block 44
64-Kword/128-Kbyte Block 43
64-Kword/128-Kbyte Block 42
64-Kword/128-Kbyte Block 41
64-Kword/128-Kbyte Block 40
64-Kword/128-Kbyte Block 39
64-Kword/128-Kbyte Block 38
64-Kword/128-Kbyte Block 37
64-Kword/128-Kbyte Block 36
64-Kword/128-Kbyte Block 35
64-Kword/128-Kbyte Block 34
64-Kword/128-Kbyte Block 33
64-Kword/128-Kbyte Block 32
[A22-A0]
64-Kword/128-Kbyte Block 31
64-Kword/128-Kbyte Block 30
64-Kword/128-Kbyte Block 29
64-Kword/128-Kbyte Block 28
64-Kword/128-Kbyte Block 27
64-Kword/128-Kbyte Block 26
64-Kword/128-Kbyte Block 25
64-Kword/128-Kbyte Block 24
64-Kword/128-Kbyte Block 23
64-Kword/128-Kbyte Block 22
64-Kword/128-Kbyte Block 21
64-Kword/128-Kbyte Block 20
64-Kword/128-Kbyte Block 19
64-Kword/128-Kbyte Block 18
64-Kword/128-Kbyte Block 17
64-Kword/128-Kbyte Block 16
64-Kword/128-Kbyte Block 15
64-Kword/128-Kbyte Block 14
64-Kword/128-Kbyte Block 13
64-Kword/128-Kbyte Block 12
64-Kword/128-Kbyte Block 11
64-Kword/128-Kbyte Block 10
64-Kword/128-Kbyte Block 9
64-Kword/128-Kbyte Block 8
64-Kword/128-Kbyte Block 7
64-Kword/128-Kbyte Block 6
64-Kword/128-Kbyte Block 5
64-Kword/128-Kbyte Block 4
64-Kword/128-Kbyte Block 3
64-Kword/128-Kbyte Block 2
64-Kword/128-Kbyte Block 1
64-Kword/128-Kbyte Block 0
3FFFFF
3E0000
3DFFFF
3C0000
3BFFFF
3A0000
39FFFF
380000
37FFFF
360000
35FFFF
340000
33FFFF
320000
31FFFF
300000
2FFFFF
2E0000
2DFFFF
2C0000
2BFFFF
2A0000
29FFFF
280000
27FFFF
260000
25FFFF
240000
23FFFF
220000
21FFFF
200000
1FFFFF
1E0000
1DFFFF
1C0000
1BFFFF
1A0000
19FFFF
180000
17FFFF
160000
15FFFF
140000
13FFFF
120000
11FFFF
100000
0FFFFF
0E0000
0DFFFF
0C0000
0BFFFF
0A0000
09FFFF
080000
07FFFF
060000
05FFFF
040000
03FFFF
020000
01FFFF
000000
Figure 2. Memory Map
Rev. 0.06
LHF64P01
7
Table 3. Identifier Codes Address
Code
Address
[A22-A1] (1)
Data
[DQ7-DQ0]
Notes
Manufacturer Code
Manufacturer Code
000000H
B0H
2
Device Code
Device Code
000001H
17H
2
Block Lock Configuration
Code
Block is Unlocked
Block
Address
+2
DQ0 = 0
3
DQ0 = 1
3
Block is Locked
NOTES:
1. The address A0 don't care.
2. "00H" is presented on DQ15-DQ8 in word mode (BYTE#=VIH : ×16 bit).
3. Block Address = The beginning location of a block address. DQ15-DQ1 are reserved for future implementation.
Rev. 0.06
LHF64P01
8
[A22-A1]
[A22-A0]
000FFFH
001FFFH
Customer Programmable Area
000085H
00010AH
000084H
000081H
000080H
Factory Programmed Area
Reserved for Future Implementation
(DQ15-DQ2)
000109H
000102H
000100H
Customer Programmable Area Lock Bit (DQ1)
Factory Programmed Area Lock Bit (DQ0)
Figure 3. OTP Block Address Map
(The area not specified in the above figure cannot be used.)
Rev. 0.06
LHF64P01
9
Table 4. Bus Operation(1, 2)
Notes
RP#
CE0,1,2 (3)
OE#
WE#
Address
VPEN
DQ (4)
STS (10)
8
VIH
Enabled
VIL
VIH
X
X
DOUT
X
Output Disable
VIH
Enabled
VIH
VIH
X
X
High Z
X
Standby
VIH
Disabled
X
X
X
X
High Z
X
Mode
Read Array
Reset
5
VIL
X
X
X
X
X
High Z
High Z
Read Identifier
Codes/OTP
8
VIH
Enabled
VIL
VIH
Refer to
Table 3
X
Refer to
Table 3
X
8,9
VIH
Enabled
VIL
VIH
See
Appendix
X
See
Appendix
X
6,7,8
VIH
Enabled
VIH
VIL
X
X
DIN
X
Read Query
Write
NOTES:
1. Refer to DC Characteristics. When VPEN≤VPENLK, memory contents can be read, but cannot be altered.
2. X can be VIL or VIH for control pins and addresses, and VPENLK or VPENH for VPEN.
Refer to DC Characteristics for VPENLK and VPENH voltages.
3. Refer to Table 2 to determine whether the device is selected or de-selected depending on the state of CE0, CE1 and CE2.
4. DQ refers to DQ15-DQ0 in word mode (BYTE#=VIH : ×16 bit) and DQ7-DQ0 in byte mode (BYTE#=VIL : ×8 bit).
5. RP# at GND±0.2V ensures the lowest power consumption.
6. Command writes involving block erase, (page buffer) program, block lock configuration or OTP program are reliably
executed when VPEN=VPENH and VCC=2.7V-3.6V.
7. Refer to Table 5 for valid DIN during a write operation.
8. Never hold OE# low and WE# low at the same timing.
9. Refer to Appendix of LH28F640SP series for more information about query code.
10. STS is VOL when the WSM (Write State Machine) is executing internal block erase, (page buffer) program or OTP
program algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with program and page
buffer program inactive), (page buffer) program suspend mode, or reset mode.
Rev. 0.06
LHF64P01
10
Table 5. Command Definitions (10)
Command
Read Array
Bus
Cycles
Req’d
First Bus Cycle
Notes
1
Second Bus Cycle
Oper(1)
Addr(2)
Data(3)
Write
X
FFH
Oper(1)
Addr(2)
Data(3)
Read Identifier Codes/OTP
≥2
4
Write
X
90H
Read
IA or OA
ID or OD
Read Query
≥2
4
Write
X
98H
Read
QA
QD
Read
X
SRD
Read Status Register
2
Write
X
70H
Clear Status Register
1
Write
X
50H
Block Erase
2
5
Write
BA
20H
Write
BA
D0H
2
5,6
Write
X
40H or
10H
Write
WA
WD
≥4
5,7
Write
BA
E8H
Write
BA
N-1
Block Erase and (Page Buffer)
Program Suspend
1
8
Write
X
B0H
Block Erase and (Page Buffer)
Program Resume
1
8
Write
X
D0H
STS Configuration
2
Write
X
B8H
Write
X
CC
Set Block Lock Bit
2
Write
X
60H
Write
BA
01H
Clear Block Lock Bits
2
Write
X
60H
Write
X
D0H
OTP Program
2
Write
X
C0H
Write
OA
OD
Program
Page Buffer Program
9
NOTES:
1. Bus operations are defined in Table 4.
2. X=Any valid address within the device.
IA=Identifier codes address (Refer to Table 3).
QA=Query codes address. Refer to Appendix of LH28F640SP series for details.
BA=Address within the block for block erase, page buffer program or set block lock bit.
WA=Address of memory location for the Program command.
OA=Address of OTP block to be read or programmed (Refer to Figure 3).
3. The upper byte of the data bus (DQ15-DQ8) during command writes is ignored in word mode (BYTE#=VIH : ×16 bit).
ID=Data to be read from identifier codes. (Refer to Table 3).
QD=Data to be read from query database. Refer to Appendix of LH28F640SP series for details.
SRD=Data to be read from status register. Refer to Table 7 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the first edge of CE0, CE1 or CE2 that disables
the device or the rising edge of WE# (whichever occurs first) during command write cycles.
N-1=N is the number of the words /bytes to be loaded into a page buffer.
OD=Data within OTP block. Data is latched on the first edge of CE0, CE1 or CE2 that disables
the device or the rising edge of WE# (whichever occurs first) during command write cycles.
CC= STS configuration code (Refer to Table 9).
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code and the data within OTP block (Refer to Table 3).
The Read Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased
or programmed when RP# is VIH.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, write the program sequential address and data of "N" times. Finally, write the any valid
address within the block to be programmed and the confirm command (D0H).
Rev. 0.06
LHF64P01
11
Refer to Appendix of LH28F640SP series for details.
8. If both block erase operation and (page buffer) program operation are suspended, the suspended (page buffer) program
operation is resumed when writing the Block Erase and (Page Buffer) Program Resume (D0H) command.
9. Following the Clear Block Lock Bits command, all the blocks are unlocked at a time.
10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
Rev. 0.06
LHF64P01
12
Table 6. Functions of Block Lock (1), (2)
DQ0(3)
State Name
Erase/Program Allowed (4)
0
Unlocked
Yes
1
Locked
No
NOTES:
1. Selected block is locked by the Set Block Lock Bit command. Following the Clear Block
Lock Bits command, all the blocks are unlocked at a time.
2. Locked and unlocked states remain unchanged even after power-up/down and device reset.
3. After writing the Read Identifier Codes/OTP command, read operation outputs the block lock bit
status on DQ0 (refer to Table 3).
4. Erase and program are general terms, respectively, to express: block erase and
(page buffer) program operations.
Rev. 0.06
LHF64P01
13
Table 7. Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
WSMS
BESS
BECBLS
PBPOPSBLS
VPENS
PBPSS
DPS
R
7
6
5
4
3
2
1
0
SR.15 - SR.8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
NOTES:
Check SR.7 or STS to determine block erase, (page buffer)
program, block lock configuration or OTP program
completion. SR.6 - SR.1 are invalid while SR.7="0".
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = BLOCK ERASE AND CLEAR BLOCK LOCK If both SR.5 and SR.4 are "1"s after a block erase, page
buffer program, block lock configuration, STS configuration
BITS STATUS (BECBLS)
attempt, an improper command sequence was entered.
1 = Error in Block Erase or Clear Block Lock Bits
0 = Successful Block Erase or Clear Block Lock Bits
SR.4 = (PAGE BUFFER) PROGRAM, OTP PROGRAM
AND SET BLOCK LOCK BIT STATUS (PBPOPSBLS)
1 = Error in (Page Buffer) Program, OTP Program or Set
Block Lock Bit
0 = Successful (Page Buffer) Program, OTP Program or
Set Block Lock Bit
SR.3 = VPEN STATUS (VPENS)
1 = VPEN LOW Detect, Operation Abort
0 = VPEN OK
SR.3 does not provide a continuous indication of VPEN level.
The WSM interrogates and indicates the VPEN level only
after Block Erase, (Page Buffer) Program, Set Block Lock
Bit, Clear Block Lock Bits or OTP Program command
sequences. SR.3 is not guaranteed to report accurate feedback
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS
when VPEN≠VPENH or VPENLK.
(PBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, (Page Buffer) Program or OTP Program command
SR.1 = DEVICE PROTECT STATUS (DPS)
sequences. It informs the system, depending on the attempted
operation, if the block lock bit is set. Reading the block lock
1 = Erase or Program Attempted on a
configuration codes after writing the Read Identifier Codes/
Locked Block, Operation Abort
OTP command indicates block lock bit status.
0 = Unlocked
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.15 - SR.8 and SR.0 are reserved for future use and should
be masked out when polling the status register.
Rev. 0.06
LHF64P01
14
Table 8. Extended Status Register Definition
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
SMS
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
XSR.15-8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Page Buffer Program available
0 = Page Buffer Program not available
NOTES:
After issue a Page Buffer Program command (E8H),
XSR.7="1" indicates that the entered command is accepted.
If XSR.7 is "0", the command is not accepted and a next Page
Buffer Program command (E8H) should be issued again to
check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and
should be masked out when polling the extended status
XSR.6-0 =RESERVED FOR FUTURE ENHANCEMENTS (R) register.
Rev. 0.06
LHF64P01
15
Table 9. STS Configuration Definition (1)
R
R
R
R
R
R
R
R
15
14
13
12
11
10
9
8
R
R
R
R
R
R
CC
CC
7
6
5
4
3
2
1
0
DQ15-DQ2 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
NOTES:
After power-up or device reset, STS configuration is set to
"00".
DQ1-DQ0 = STS CONFIGURATION CODE (CC)
00 = level mode: RY/BY# indication. (Default)
01 = pulse mode on erase complete.
10 = pulse mode on program complete.
11 = pulse mode on erase or program complete.
STS configuration 00
The output of the STS pin is the control signal to prevent
accessing a flash memory while the internal WSM is busy
(SR.7="0").
In STS configuration = "00", STS is VOL when the WSM is STS configuration 01
The output of the STS pin is the control signal to indicate
executing internal erase or program algorithms.
that the erase operation is completed and the flash memory
is available for the next operation.
STS configuration codes "01", "10" and "11" are all pulse
modes such that the STS pin pulses low then high when the
operation indicated by the configuration code is completed. STS configuration 10
The output of the STS pin is the control signal to indicate
that the program operation is completed and the flash
memory is available for the next operation.
STS configuration 11
The output of the STS pin is the control signal to indicate
that the erase or program operation is completed and the
flash memory is available for the next operation.
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250ns.
Rev. 0.06
LHF64P01
1 Electrical Specifications
16
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent
damage. These are stress ratings only. Operation
beyond the "Operating Conditions" is not
recommended and extended exposure beyond the
"Operating Conditions" may affect device
reliability.
1.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Erase and Program ...-40°C to +85°C (1)
NOTES:
1. Operating temperature is for extended temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins and
-0.2V on VCC, VCCQ and VPEN pins. During
transitions, this level may undershoot to -2.0V for
periods <20ns. Maximum DC voltage on input/output
pins is VCC+0.5V which, during transitions, may
overshoot to VCC+2.0V for periods <20ns.
3. Output shorted for no more than one second. No more
than one output shorted at a time.
Storage Temperature
During under Bias............................... -40°C to +85°C
During non Bias................................ -65°C to +125°C
Voltage On Any Pin (except VCC, VCCQ and VPEN)
................................................... -0.5V to VCCQ+0.5V (2)
VCC and VCCQ Supply Voltage .......... -0.2V to +3.9V (2)
VPEN Supply Voltage.......................... -0.2V to +3.9V (2)
Output Short Circuit Current ........................... 100mA (3)
1.2 Operating Conditions
Symbol
TA
Parameter
Notes
Operating Temperature
Min.
Typ.
Max.
Unit
Test Conditions
-40
+25
+85
°C
Ambient
Temperature
VCC
VCC Supply Voltage
1, 2
2.7
3.0
3.6
V
VCCQ
I/O Supply Voltage
1, 2
2.7
3.0
3.6
V
VPENH
VPEN Voltage
1
2.7
3.0
3.6
V
Block Erase Cycling: VPEN=VPENH
100,000
Cycles
NOTES:
1. Refer to DC Characteristics tables for voltage range-specific specification.
2. VCC and VCCQ should be the same voltage.
Rev. 0.06
LHF64P01
17
1.2.1 Capacitance (1) (TA=+25°C, f=1MHz)
Symbol
Parameter
CIN
COUT
Min.
Typ.
Max.
Unit
Condition
Input Capacitance
6
8
pF
VIN=0.0V
Output Capacitance
8
12
pF
VOUT=0.0V
NOTE:
1. Sampled, not 100% tested.
1.2.2 AC Input/Output Test Conditions
VCCQ
INPUT
VCCQ/2
TEST POINTS
VCCQ/2 OUTPUT
0.0
AC test inputs are driven at VCCQ(min) for a Logic "1" and 0.0V for a Logic "0".
Input timing begins, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Worst case speed conditions are when VCC=VCC(min).
Figure 4. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V
Table 10. Configuration Capacitance Loading Value
VCCQ(min)/2
1N914
Test Configuration
CL (pF)
VCC=2.7V-3.6V
30
RL=3.3kΩ
DEVICE
UNDER
TEST
CL Includes Jig
Capacitances.
OUT
CL
Figure 5. Transient Equivalent Testing Load Circuit
Rev. 0.06
LHF64P01
18
1.2.3 DC Characteristics
VCC=2.7V-3.6V
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Test Conditions
VCC=VCCMax.,
VCCQ=VCCQMax.,
VIN/VOUT=VCCQ or
GND
ILI
Input Load Current
1
-1
+1
µA
ILO
Output Leakage Current
1
-10
+10
µA
50
ICCS
VCC Standby Current
120
µA
CMOS Inputs,
VCC=VCCMax.,
VCCQ=VCCQMax.,
Device is disabled
(refer to Table 2),
RP#=VCCQ±0.2V
mA
TTL Inputs,
VCC=VCCMax.,
VCCQ=VCCQMax.,
Device is disabled
(refer to Table 2),
RP#=VIH
1, 2, 8
0.71
2
ICCAS
VCC Automatic Power Savings Current 1, 2, 5
50
120
µA
CMOS Inputs,
VCC=VCCMax.,
VCCQ=VCCQMax.,
Device is enabled
(refer to Table 2)
ICCD
VCC Reset Current
50
120
µA
RP#=GND±0.2V
IOUT (STS)=0mA
mA
CMOS Inputs,
VCC=VCCMax.,
VCCQ=VCCQMax.,
Device is enabled
(refer to Table 2),
f=5MHz, IOUT=0mA
mA
CMOS Inputs,
VCC=VCCMax.,
VCCQ=VCCQMax.,
Device is enabled
(refer to Table 2),
f=33MHz, IOUT=0mA
1
1, 2
15
20
Average VCC Page 4 word/ 8 byte
Mode Read Current read
ICCR
1, 2
Average VCC Read 1 word/ 1 byte
read
Current
ICCW
VCC (Page Buffer) Program, Set Block
Lock Bit Current
24
29
1, 2
40
50
mA
CMOS Inputs,
VCC=VCCMax.,
VCCQ=VCCQMax.,
Device is enabled
(refer to Table 2),
f=5MHz, IOUT=0mA
1, 2, 6
35
60
mA
CMOS Inputs,
VPEN=VPENH
1, 2, 6
40
70
mA
TTL Inputs,
VPEN=VPENH
Rev. 0.06
LHF64P01
19
DC Characteristics (Continued)
VCC=2.7V-3.6V
Symbol
ICCE
Parameter
VCC Block Erase, Clear Block Lock
Bits Current
Notes
Min.
Typ.
Max.
Unit
1, 2, 6
35
70
mA
CMOS Inputs,
VPEN=VPENH
1, 2, 6
40
80
mA
TTL Inputs,
VPEN=VPENH
10
mA
Device is disabled
(refer to Table 2).
ICCWS
ICCES
VCC (Page Buffer) Program or
Block Erase Suspend Current
VIL
Input Low Voltage
6
-0.5
0.8
V
VIH
Input High Voltage
6
2.0
VCCQ
+ 0.5
V
VOL
Output Low Voltage
1, 3
0.4
V
VCC=VCCMin.,
VCCQ=VCCQMin.,
IOL=2mA
0.2
V
VCC=VCCMin.,
VCCQ=VCCQMin.,
IOL=100µA
V
VCC=VCCMin.,
VCCQ=VCCQMin.,
IOH=-1.5mA
V
VCC=VCCMin.,
VCCQ=VCCQMin.,
IOH=-100µA
6, 8
0.85×
VCCQ
VOH
Output High Voltage
6, 8
VCCQ
-0.2
VPENLK
VPEN Lockout Voltage during Normal
Operations
VPENH
VPEN Voltage during Block Erase,
(Page Buffer) Program, Set Block Lock
Bit, Clear Block Lock Bits or OTP
Program Operations
VLKO
VCC Lockout Voltage
4, 6, 7
4, 7
2.7
4
2.0
3.0
Test Conditions
1.0
V
3.6
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V, VCCQ=3.0V and
TA=+25°C unless VCC is specified.
2. CMOS inputs are either VCCQ±0.2V or GND±0.2V. TTL inputs are either VIL or VIH.
3. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program is executed while in block
erase suspend mode, the device’s current draw is the sum of ICCES and ICCR or ICCW. If read is executed while in (page
buffer) program suspend mode, the device’s current draw is the sum of ICCWS and ICCR.
4. Block erase, (page buffer) program, block lock configuration and OTP program operations are inhibited when
VPEN≤VPENLK or VCC≤VLKO. These operations are not guaranteed outside the specified voltage (VCC=2.7V-3.6V and
VPEN=2.7V-3.6V).
5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
completion. Standard address access timings (tAVQV) provide new data when addresses are changed.
6. Sampled, not 100% tested.
7. VPEN is not used for power supply pin. With VPEN≤VPENLK, block erase, (page buffer) program, block lock configuration
and OTP program operations are inhibited.
8. Includes STS.
Rev. 0.06
LHF64P01
20
1.2.4 AC Characteristics - Read-Only Operations (1)
TA=-40°C to +85°C
Symbol
Parameter
VCC
3.0V-3.6V
2.7V-3.6V
VCCQ
3.0V-3.6V
2.7V-3.6V
Notes
Min.
Max.
Min.
Max.
Unit
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CEX to Output Delay
tAPA
Page Address Access Time
tGLQV
OE# to Output Delay
tPHQV
RP# High to Output Delay
tELQX
CEX to Output in Low Z
2, 4
0
0
ns
tGLQX
OE# to Output in Low Z
2
0
0
ns
tEHQZ
CEX to Output in High Z
2, 5
35
35
ns
tGHQZ
OE# to Output in High Z
2
15
15
ns
tOH
Output Hold from First Occurring Address, CEX or OE#
change
2, 5
tELFL/tELFH
CEx Setup to BYTE# Going Low or High
2, 4
tFLQV/tFHQV
BYTE# to Output Delay
tFLQZ/tFHQZ
BYTE# to Output in High Z
120
3, 4
3
2
120
ns
120
120
ns
120
120
ns
25
30
ns
25
30
ns
180
180
ns
0
0
ns
10
10
ns
1000
1000
ns
1000
1000
ns
NOTES:
1. Refer to AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. OE# may be delayed up to tELQV tGLQV after the first edge of CE0, CE1 or CE2 that enables the device
(refer to Table 2) without impact to tELQV.
4. The timing is defined from the first edge of CE0, CE1 or CE2 that enables the device.
5. The timing is defined from the first edge of CE0, CE1 or CE2 that disables the device.
Rev. 0.06
LHF64P01
VIH
A22-0 (A)
21
VALID
ADDRESS
VIL
tAVAV
tAVQV
Disabled (VIH)
CEX (E)
Enabled (VIL)
tELQV
tEHQZ
tGHQZ
VIH
OE# (G)
VIL
VIH
WE# (W)
VIL
tGLQV
tGLQX
tELQX
VOH
DQ15-0 (D/Q)
tOH
High Z
VALID
OUTPUT
VOL
tPHQV
RP# (P)
VIH
VIL
tELFL/tELFH
tFLQV/tFHQV
tFLQZ/tFHQZ
BYTE# (F)
VIH
VIL
Figure 6. AC Waveform for 1-Word/ 1-Byte Read Operations
(Status Register, Identifier Codes, OTP Block or Query Code)
NOTE:
1. Status register, identifier codes, OTP block and query code can only be read in 1-word/ 1-byte
read operations.
Rev. 0.06
LHF64P01
A22-3 (A)
VIH
22
VALID
ADDRESS
VIL
tAVQV
A2-1 (A)
VIH
VALID
ADDRESS
VIL
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
Disabled (VIH)
CEX (E)
Enabled (VIL)
OE# (G)
WE# (W)
tELQV
tEHQZ
tGHQZ
VIH
VIL
VIH
tGLQV
VIL
tGLQX
tAPA
tELQX
DQ15-0 (D/Q)
VOH
High Z
VALID
OUTPUT
VOL
tOH
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tPHQV
RP# (P)
VIH
VIL
tELFH
tFHQV
tFHQZ
BYTE# (F)
VIH
VIL
Figure 7. AC Waveform for 4-Word Page Mode Read Operations
(Memory Array)
NOTE:
1. Memory array supports page mode read operations.
Rev. 0.06
LHF64P01
A22-3 (A)
VIH
23
VALID
ADDRESS
VIL
tAVQV
A2-0 (A)
VIH
VIL
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
Disabled (VIH)
CEX (E)
Enabled (VIL)
OE# (G)
WE# (W)
tEHQZ
tGHQZ
tELQV
VIH
VIL
VIH
tGLQV
VIL
tGLQX
tAPA
tELQX
DQ7-0 (D/Q)
VOH
High Z
VOL
VALID
OUTPUT
VALID
OUTPUT
tOH
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tPHQV
RP# (P)
VIH
VIL
tELFL
tFLQV
tFLQZ
BYTE# (F)
VIH
VIL
Figure 8. AC Waveform for 8-Byte Page Mode Read Operations
(Memory Array)
NOTE:
1. Memory array supports page mode read operations.
Rev. 0.06
LHF64P01
24
1.2.5 AC Characteristics - Write Operations (1), (2)
VCC=2.7V-3.6V, TA=-40°C to +85°C
Symbol
Parameter
tAVAV
Write Cycle Time
tPHWL (tPHEL)
RP# High Recovery to WE# (CEX) Going Low
tELWL (tWLEL)
CEX (WE#) Setup to WE# (CEX) Going Low
tWLWH (tELEH)
WE# (CEX) Pulse Width Low
tDVWH (tDVEH)
Notes
Min.
Max.
Unit
120
ns
3, 9
1
µs
9
0
ns
4, 9, 10
70
ns
Data Setup to WE# (CEX) Going High
7, 10
50
ns
tAVWH (tAVEH)
Address Setup to WE# (CEX) Going High
7, 10
55
ns
tWHEH (tEHWH)
CEX (WE#) Hold from WE# (CEX) High
10
0
ns
tWHDX (tEHDX)
Data Hold from WE# (CEX) High
10
0
ns
tWHAX (tEHAX)
Address Hold from WE# (CEX) High
10
0
ns
tWHWL (tEHEL)
WE# (CEX) Pulse Width High
5, 9, 10
30
ns
tVVWH (tVVEH)
VPEN Setup to WE# (CEX) Going High
3, 10
0
ns
tWHGL (tEHGL)
Write Recovery before Read
8
35
ns
tWHR0 (tEHR0)
tWHRL (tEHRL)
WE# (CEX) High to SR.7 Going "0", STS Going Low
10, 11
tQVVL
VPEN Hold from Valid SRD, STS High Z
3, 6, 11
0
ns
tFLWH/tFHWH
(tFLEH/tFHEH)
BYTE# Setup to WE# (CEX) Going High
10
50
ns
tWHFL/tWHFH
(tEHFL/tEHFH)
BYTE# Hold from WE# (CEX) High
10
90
ns
500
ns
NOTES:
1. The timing characteristics for reading the status register during block erase, (page buffer) program, block lock
configuration and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for
read-only operations.
2. A write operation can be initiated and terminated with either CE0, CE1, CE2 or WE#.
3. Sampled, not 100% tested.
4. Write pulse width low (tWP) is defined from the first edge of CE0, CE1 or CE2 that enables the device or the falling edge
of WE# (whichever occurs last) to the first edge of CE0, CE1 or CE2 that disables the device or the rising edge of WE#
(whichever occurs first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH.
5. Write pulse width high (tWPH) is defined from the first edge of CE0, CE1 or CE2 that disables the device or the rising edge
of WE# (whichever occurs first) to the first edge of CE0, CE1 or CE2 that enables the device or the falling edge of WE#
(whichever occurs last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.
6. VPEN should be held at VPEN=VPENH until determination of block erase, (page buffer) program, block lock configuration
or OTP program success (SR.1/3/4/5=0).
7. Refer to Table 5 for valid address and data for block erase, (page buffer) program, block lock configuration and OTP
program.
8. The output delay time tAVQV or tELQV is required in addition to tWHGL (tEHGL) for read operations after command writes.
9. The timing is defined from the first edge of CE0, CE1 or CE2 that enables the device.
10. The timing is defined from the first edge of CE0, CE1 or CE2 that disables the device.
11. STS timings depend on STS configuration.
Rev. 0.06
LHF64P01
NOTE 1
A22-0 (A)
VIH
VIL
25
NOTE 2
NOTE 3
VALID
ADDRESS
VALID
ADDRESS
tAVAV
VALID
ADDRESS
tAVWH (tAVEH)
tWHAX
(tEHAX)
Disabled (VIH)
CEX (E)
NOTES 5, 6
Enabled (VIL)
OE# (G)
tELWL (tWLEL)
tWHEH (tEHWH)
NOTES 5, 6
VIH
VIL
tPHWL (tPHEL)
WE# (W)
tWHWL (tEHEL)
VIH
VIL
tWLWH
(tELEH )
DQ15-0 (D/Q)
tWHGL (tEHGL)
tWHQV1,2,3,4,5,6
(tEHQV1,2,3,4,5,6)
tWHDX (tEHDX)
tDVWH (tDVEH)
VIH
VIL
DATA IN
VALID
SRD
DATA IN
tWHRL (tEHRL)
(tWHR0 (tEHR0))
High Z
STS
("1")
(R)
(SR.7)
VOL
NOTE 4
("0")
RP# (P)
BYTE# (F)
VIH
VIL
tFLWH/tFHWH
(tFLEH/tFHEH)
tWHFL/tWHFH
(tEHFL/tEHFH)
VIH
VIL
tVVWH (tVVEH)
tQVVL
VPENH
VPEN (V)
VPENLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write each first cycle command.
3. Write each second cycle command or valid address and data.
4. Automated erase or program delay. This waveform illustrates the case when STS is in level mode (RY/BY#).
5. Read status register data.
6. For read operation, OE# and CEX must be driven active, and WE# de-asserted.
Figure 9. AC Waveform for Write Operations
Rev. 0.06
LHF64P01
26
1.2.6 Reset Operations
tPHQV
RP#
VIH
(P)
VIL
DQ15-0 (D/Q)
VOH
VOL
tPLPH
High Z
VALID
OUTPUT
(A) Reset during Read Array Mode
SR.7="1"
tPLRH
RP#
ABORT
COMPLETE
tPHQV
VIH
(P)
VIL
DQ15-0 (D/Q)
VOH
VOL
tPLPH
High Z
VALID
OUTPUT
(B) Reset during Erase or Program Mode
VCC(min)
VCC
tVHQV
GND
t2VPH
RP#
(P)
tPHQV
VIH
VIL
DQ15-0 (D/Q)
VOH
High Z
VALID
OUTPUT
VOL
(C) RP# rising timing
Figure 10. AC Waveform for Reset Operations
Reset AC Specifications (VCC=2.7V-3.6V, TA=-40°C to +85°C)
Symbol
Parameter
Notes
Min.
100
tPLPH
RP# Low to Reset during Read
(RP# must be low during power-up.)
1, 2, 3
tPLRH
RP# Low to Reset during Erase or Program
1, 3, 4
t2VPH
VCC 2.7V to RP# High
1, 3, 5
tVHQV
VCC 2.7V to Output Delay
3
Max.
Unit
ns
30
100
µs
ns
1
ms
NOTES:
1. A reset time, tPHQV, is required from the later of SR.7 (STS) going "1" (High Z) or RP# going high until outputs are valid.
Refer to AC Characteristics - Read-Only Operations for tPHQV.
2. The device may reset if tPLPH is <100ns, but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RP# asserted while a block erase, (page buffer) program, block lock configuration or OTP program operation is not
executing, the reset will complete within 100ns.
5. When the device power-up, holding RP# low minimum 100ns is required after VCC has been in predefined range and also
has been in stable there.
Rev. 0.06
LHF64P01
27
1.2.7 Block Erase, (Page Buffer) Program and Block Lock Configuration Performance(3)
VCC=2.7V-3.6V, TA=-40°C to +85°C
Symbol
Parameter
Notes
VPEN=VPENH
Unit
Typ.(1)
Max.
2, 6,
7
400
1200
µs
Program Time
2
210
630
µs
Block Program Time
(Using Page Buffer Program Command)
2
1.6
4.8
s
tWHQV4/
tEHQV4
Block Erase Time
2
1
5
s
tWHQV5/
tEHQV5
Set Block Lock Bit Time
2
64
85
µs
tWHQV6/
tEHQV6
Clear Block Lock Bits Time
2
0.5
0.7
s
tWHRH1/
tEHRH1
(Page Buffer) Program Suspend
Latency Time to Read
4
25
90
µs
tWHRH2/
tEHRH2
Block Erase Suspend
Latency Time to Read
4
26
40
µs
tERES
Latency Time from Block Erase
Resume Command to Block
Erase Suspend Command
5
Page Buffer Program Time
(Time to Program 16 words/ 32 bytes)
tWHQV3/
tEHQV3
Min.
600
µs
NOTES:
1. Typical values measured at VCC=3.0V, VPEN=3.0V and TA=+25°C. Assumes corresponding lock bits
are not set. Subject to change based on device characterization.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
4. A latency time is required from writing suspend command (the first edge of CE0, CE1 or CE2 that disables
the device or the rising edge of WE#) until SR.7 going "1" or STS going High Z.
5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter
than tERES and its sequence is repeated, the block erase operation may not be finished.
6. These values are valid when the page buffer is full, and the start address is aligned on a 16-word/ 32-byte boundary.
7. Program time per byte (tWHQV1/ tEHQV1) is 12.5µs/byte (typical).
Program time per word (tWHQV2/ tEHQV2) is 25.0µs/word (typical).
Rev. 0.06
LHF64P01
28
2 Related Document Information(1)
Document No.
FUM03201
Document Name
LH28F640SP series Appendix
NOTE:
1. International customers should contact their local SHARP or distribution sales offices.
Rev. 0.06
i
LH28F640SPXX-XXXXX Flash MEMORY ERRATA
1. Table 5. Command Definitions
PROBLEM
While block erase or (page buffer) program is being suspended by issuing Block Erase and (Page
Buffer) Program Suspend command, memory array data can not be normally read by issuing read
array command.
WORKAROUND
Block Erase and (Page Buffer) Program Suspend command should not be issued.
STATUS
This is intended to be fixed in future devices.
031002
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
VCCQ
GND
tVR
t2VPH
tPHQV
VIH
RP# (P)
(RST#)
VPEN *1 (V)
VIL
VPENH
(VPPH)
GND
(VPP)
tR or tF
tR or tF
tAVQV
VIH
Valid
Address
ADDRESS (A)
VIL
tF
tR
tELQV
Disabled (VIH)
CEX
(E)
Enabled (VIL)
VIH
WE# (W)
VIL
tF
tR
tGLQV
VIH
OE#
(G)
VIL
DATA
(D/Q)
VOH
VOL
High Z
Valid
Output
*1 To prevent the unwanted writes, system designers should consider the design, which applies VPEN (VPP)
to 0V during read operations and VPENH (VPPH) during write or erase operations.
See the application note AP-007-SW-E for details.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
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ii
A-1.1.1 Rise and Fall Time
Symbol
Parameter
Notes
Min.
Max.
Unit
1
0.5
30000
µs/V
tVR
VCC Rise Time
tR
Input Signal Rise Time
1, 2
1
µs/V
tF
Input Signal Fall Time
1, 2
1
µs/V
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
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iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal
Input Signal
VIH (Min.)
VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for VIH (Min.) and VIL (Max.).
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iv
A-2 RELATED DOCUMENT INFORMATION(1)
Document No.
Document Name
AP-001-SD-E
Flash Memory Family Software Drivers
AP-006-PT-E
Data Protection Method of SHARP Flash Memory
AP-007-SW-E
RP#, VPP Electric Potential Switching Circuit
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
030313