LTC4252-1/LTC4252-2 Negative Voltage Hot Swap Controllers U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®4252 negative voltage Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. Allows Safe Board Insertion and Removal from a Live – 48V Backplane Floating Topology Permits Very High Voltage Operation Programmable Analog Current Limit With Circuit Breaker Timer Fast Response Time Limits Peak Fault Current Programmable Soft-Start Current Limit Programmable Timer with Drain Voltage Accelerated Response Programmable Undervoltage/Overvoltage Protection LTC4252-1: Latch Off After Fault LTC4252-2: Automatic Retry After Fault Programmable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. The LTC4252’s supply input is shunt regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial startup and controls the circuit breaker’s response time. The circuit breaker’s response time is accelerated by sensing excessive MOSFET drain voltage, keeping the MOSFET within its safe operating area (SOA). A programmable soft-start circuit controls MOSFET inrush current at startup. A power good status output can enable a power module at start-up or disable it if the circuit breaker trips. U APPLICATIO S ■ ■ ■ ■ ■ ■ ■ ■ Hot Board Insertion Electronic Circuit Breaker – 48V Distributed Power Systems Negative Power Supply Control Central Office Switching Programmable Current Limiting Circuit High Availability Servers Disk Arrays The LTC4252-1 latches off after a circuit breaker fault times out. The LTC4252-2 provides automatic retry after a fault. The LTC4252 is available in either an 8-pin or 10-pin MSOP. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO – 48V/2.5A Hot Swap Controller Start-Up Behavior GND RIN 3× 1.8k IN SERIES 1/4W EACH GND (SHORT PIN) CIN 1µF 1 VIN R1 402k 1% + 9 R2 32.4k 1% EN OV PWRGD UV DRAIN 10 TIMER 3 CT SS 0.33µF C1 10nF CSS 68nF GATE VEE 5 SENSE * 2 7 VOUT * M0C207 SENSE 2.5A/DIV RD 1M 6 Q1 IRF530S 4 RC 10Ω CC 18nF VOUT 20V/DIV RS 0.02Ω 4252-1/2 TA01 –48V GATE 5V/DIV LOAD R3 5.1k LTC4252-1 8 CL 100µF PWRGD 10V/DIV 1ms/DIV 4252-1/2 TA01a 425212f 1 LTC4252-1/LTC4252-2 U W W W ABSOLUTE AXI U RATI GS All Voltages Referred to VEE (Note 1) Current into VIN (100µs Pulse) ........................... 100mA VIN, DRAIN Pin Minimum Voltage ....................... – 0.3V Input/Output Pins (Except SENSE and DRAIN) Voltage ..........– 0.3V to 16V SENSE Pin Voltage ................................... – 0.6V to 16V Current Out of SENSE Pin (20µs Pulse) ........... – 200mA Current into DRAIN Pin (100µs Pulse) ................. 20mA Maximum Junction Temperature .......................... 125°C Operating Temperature Range LTC4252-1C/LTC4252-2C ....................... 0°C to 70°C LTC4252-1I/LTC4252-2I ................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U W U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER LTC4252-1CMS8 LTC4252-2CMS8 LTC4252-1IMS8 LTC4252-2IMS8 TOP VIEW VIN SS SENSE VEE 1 2 3 4 8 7 6 5 TIMER UV/OV DRAIN GATE MS8 PACKAGE 8-LEAD PLASTIC MSOP ORDER PART NUMBER LTC4252-1CMS LTC4252-2CMS LTC4252-1IMS LTC4252-2IMS TOP VIEW VIN PWRGD SS SENSE VEE 1 2 3 4 5 10 9 8 7 6 TIMER UV OV DRAIN GATE MS8 PART MARKING MS PACKAGE 10-LEAD PLASTIC MSOP MS PART MARKING LTWM LTWP LTRQ LTRR TJMAX = 125°C, θJA = 160°C/W LTWN LTWQ LTRS LTRT TJMAX = 125°C, θJA = 160°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) SYMBOL PARAMETER CONDITIONS VZ VIN – VEE Zener Voltage IIN = 2mA rZ VIN – VEE Zener Dynamic Impedance IIN = 2mA to 30mA IIN VIN Supply Current UV = OV = 4V, VIN = (VZ – 0.3V) ● 0.8 2 mA VLKO VIN Undervoltage Lockout Coming Out of UVLO (Rising VIN) ● 9.2 12 V VLKH VIN Undervoltage Lockout Hysteresis VCB Circuit Breaker Current Limit Voltage VCB = (VSENSE – VEE) ● 40 50 60 mV VACL Analog Current Limit Voltage VACL = (VSENSE – VEE), SS = Open or 2.2V ● 80 100 120 mV VFCL Fast Current Limit Voltage VFCL = (VSENSE – VEE) ● 150 200 300 mV VSS SS Voltage After End of SS Timing Cycle RSS SS Output Impedance ISS SS Pin Current VOS Analog Current Limit Offset Voltage VACL+VOS Ratio (VACL + VOS) to SS Voltage VSS ● MIN TYP MAX UNITS 12 13 14.5 V Ω 5 1 UV = OV = 4V, VSENSE = VEE, VSS = 0V (Sourcing) UV = OV = 0V, VSENSE = VEE, VSS = 2V (Sinking) V 2.2 V 100 kΩ 22 28 µA mA 10 mV 0.05 V/V 425212f 2 LTC4252-1/LTC4252-2 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) SYMBOL IGATE PARAMETER GATE Pin Output Current CONDITIONS UV = OV = 4V, VSENSE = VEE, VGATE = 0V (Sourcing) ● MIN TYP MAX 40 58 80 UNITS µA UV = OV = 4V, VSENSE – VEE = 0.15V, VGATE = 3V (Sinking) 17 mA UV = OV = 4V, VSENSE – VEE = 0.3V, VGATE = 1V (Sinking) 190 mA VGATE External MOSFET Gate Drive VGATE – VEE, IIN = 2mA VGATEH Gate High Threshold VGATEH = VIN – VGATE, IIN = 2mA, for PWRGD Status (MS Only) 2.8 V VGATEL Gate Low Threshold (Before Gate Ramp-Up) 0.5 V VUVHI UV Pin Threshold HIGH ● 3.075 3.225 3.375 V VUVLO UV Pin Threshold LOW ● 2.775 2.925 3.075 V VUVHST UV Pin Hysteresis VOVHI OV Pin Threshold HIGH ● 5.85 6.15 6.45 V VOVLO OV Pin Threshold LOW ● 5.25 5.55 5.85 V VOVHST OV Pin Hysteresis 0.6 V ISENSE SENSE Pin Input Current UV = OV = 4V, VSENSE = 50mV ● –30 –15 µA IINP UV, OV Pin Input Current UV = OV = 4V ● VTMRH TIMER Pin Voltage High Threshold 4 V VTMRL TIMER Pin Voltage Low Threshold 1 V ITMR TIMER Pin Current Timer On (Initial Cycle/Latchoff/ Shutdown Cooling, Sourcing), VTMR = 2V 5.8 µA Timer Off (Initial Cycle, Sinking), VTMR = 2V 28 mA Timer On (Circuit Breaker, Sourcing, IDRN = 0µA), VTMR = 2V 230 µA Timer On (Circuit Breaker, Sourcing, IDRN = 50µA), VTMR = 2V 630 µA Timer Off (Circuit Breaker/ Shutdown Cooling, Sinking), VTMR = 2V 5.8 µA ● 10 12 VZ V 0.3 ±0.1 ∆ITMRACC [(ITMR at IDRN = 50µA) – (ITMR at IDRN = 0µA)] ∆IDRN 50µA Timer On (Circuit Breaker with IDRN = 50µA) VDRNL DRAIN Pin Voltage Low Threshold For PWRGD Status (MS Only) 2.385 IDRNL DRAIN Leakage Current VDRAIN = 5V ±0.1 VDRNCL DRAIN Pin Clamp Voltage IDRN = 50µA 7 VPGL PWRGD Output Low Voltage IPG = 1.6mA (MS Only) IPG = 5mA (MS Only) ● ● IPGH PWRGD Pull-Up Current VPWRGD = 0V (Sourcing) (MS Only) ● tSS SS Default Ramp Period SS pin floating, VSS ramps from 0.2V to 2V tPLLUG tPHLOG V ±10 µA/µA 8 40 µA V ±1 µA V 0.2 0.4 1.1 V V 58 80 µA 180 µs UV Low to Gate Low 0.4 µs OV High to Gate Low 0.4 µs Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified. 425212f 3 LTC4252-1/LTC4252-2 U W TYPICAL PERFOR A CE CHARACTERISTICS rZ vs Temperature VZ vs Temperature 14.5 10 IIN = 2mA IIN vs Temperature 2000 IIN = 2mA 1800 9 VIN = (VZ – 0.3V) 1600 14.0 8 1400 7 13.0 1200 IIN (µA) VZ (V) rZ (Ω) 13.5 1000 6 5 800 600 4 400 12.5 3 12.0 –55 –35 –15 200 2 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G01 4252-1/2 G03 4252-1/2 G04 Undervoltage Lockout VLKO vs Temperature IIN vs VIN Undervoltage Lockout Hysteresis VLKH vs Temperature 12.0 1000 5 25 45 65 85 105 125 TEMPERATURE (°C) 1.5 11.5 TA = –40°C VLKH (V) TA = 85°C 10.5 VLKO (V) IIN (mA) TA = 25°C 10 1.3 11.0 100 10.0 9.5 TA = 125°C 1 1.1 0.9 9.0 0.7 8.5 0.1 0 2 4 6 8.0 –55 –35 –15 8 10 12 14 16 18 20 22 VIN (V) 0.5 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G05 4252-1/2 G02 4252-1/2 G06 Analog Current Limit Voltage VACL vs Temperature Circuit Breaker Current Limit Voltage VCB vs Temperature 60 120 58 115 56 Fast Current Limit Voltage VFCL vs Temperature 300 275 110 50 48 46 250 105 VFCL (mV) 52 VACL (mV) VCB (mV) 54 100 95 225 200 90 44 175 85 42 40 –55 –35 –15 5 25 45 65 95 105 125 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G07 80 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G08 150 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G09 425212f 4 LTC4252-1/LTC4252-2 U W TYPICAL PERFOR A CE CHARACTERISTICS VSS vs Temperature 2.35 2.30 RSS (kΩ) 2.25 2.20 2.15 110 45 108 40 106 35 104 30 102 ISS (mA) 2.40 VSS (V) ISS (Sinking) vs Temperature RSS vs Temperature 100 98 5 92 2.00 –55 –35 –15 90 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 20 10 94 2.05 25 15 96 2.10 UV = OV = VSENSE = VEE IIN = 2mA VSS = 2V 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G28 4252-1/2 G26 VOS vs Temperature 4252-1/2 G39 (VACL + VOS)/VSS vs Temperature IGATE (Sourcing) vs Temperature 70 0.058 10.6 0.056 UV/0V = 4V TIMER = 0V 65 VSENSE = VEE VGATE = 0V 0.054 60 10.4 VOS (mV) 10.2 10.0 9.8 9.6 0.052 0.050 0.048 0.044 9.2 0.042 5 25 45 65 85 105 125 TEMPERATURE (°C) 45 0.040 –55 –35 –15 400 350 300 IGATE (mA) IGATE (mA) 10 VGATE vs Temperature UV/0V = 4V TIMER = 0V VSENSE – VEE = 0.3V VGATE = 1V 200 150 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G11 12.5 12.0 11.5 11.0 50 0 –55 –35 –15 UV/0V = 4V 14.0 TIMER = 0V VSENSE = VEE 13.5 13.0 250 100 5 14.5 VGATE (V) UV/0V = 4V TIMER = 0V VSENSE – VEE = 0.15V VGATE = 3V 20 0 –55 –35 –15 4252-1/2 G10 IGATE (FCL, Sinking) vs Temperature 15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G30 IGATE (ACL, Sinking) vs Temperature 25 40 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G29 30 55 50 0.046 9.4 9.0 –55 –35 –15 IGATE (µA) 0.060 10.8 (VACL + VOS) / VSS (V/V) 11.0 10.5 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G12 10.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G13 425212f 5 LTC4252-1/LTC4252-2 U W TYPICAL PERFOR A CE CHARACTERISTICS VGATEH vs Temperature 3.6 UV Threshold vs Temperature 3.0 0.5 VGATEL (V) VGATEH = VIN – VGATE, IIN = 2mA (MS ONLY) 2.8 0.3 2.4 0.2 2.2 0.1 VUVH 3.175 3.075 2.975 VUVL 2.875 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 3.275 0.4 2.6 2.0 –55 –35 –15 3.375 UV THRESHOLD (V) 3.2 UV/0V = 4V 0.7 TIMER = 0V GATE THRESHOLD 0.6 BEFORE RAMP-UP 3.4 VGATEH (V) VGATEL vs Temperature 0.8 5 25 45 65 85 105 125 TEMPERATURE (°C) 2.775 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G14 4252-1/2 G31 4252-1/2 G15 ISENSE vs Temperature OV Threshold vs Temperature 6.45 ISENSE vs (VSENSE – VEE) –10 0.01 –12 VOVH –14 0.1 6.05 5.85 VOVL –18 –20 –22 –26 5.45 –28 5.25 –55 –35 –15 UV/0V = 4V TIMER = 0V GATE = HIGH VSENSE – VEE = 50mV –30 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G16 7 3.0 6 2.0 1.0 VTMRL 1.5 2.0 4252-1/2 G18 ITMR (Initial Cycle, Sinking) vs Temperature 50 TIMER = 2V TIMER = 2V 45 40 5 4 3 35 30 25 20 2 0.5 0 –55 –35 –15 1000 –1.5 –1.0 –0.5 0 0.5 1.0 (VSENSE – VEE) (V) 8 3.5 1.5 5 25 45 65 85 105 125 TEMPERATURE (°C) 9 VTMRH ITMR (µA) TIMER THRESHOLD (V) 10 2.5 UV/0V = 4V TIMER = 0V GATE = HIGH TA = 25°C 100 ITMR (Initial Cycle, Sourcing) vs Temperature 5.0 4.0 10 4252-1/2 G17 TIMER Threshold vs Temperature 4.5 1.0 –24 ITMR (mA) 5.65 –ISENSE (mA) –16 ISENSE (µA) OV THRESHOLD (V) 6.25 15 1 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G19 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G20 10 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G21 425212f 6 LTC4252-1/LTC4252-2 U W TYPICAL PERFOR A CE CHARACTERISTICS ITMR (Circuit Breaker, Sourcing) vs Temperature ITMR (Circuit Breaker, IDRN = 50µA, Sourcing) vs Temperature 690 280 TIMER = 2V IDRN = 0µA 670 ITMR (Cooling Cycle, Sinking) vs Temperature 10 TIMER = 2V IDRN = 50µA 8 220 650 7 630 6 ITMR (µA) 240 ITMR (µA) ITMR (µA) 260 610 5 4 3 590 200 2 570 180 –55 –35 –15 1 550 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G23 IDRN vs VDRAIN ∆ITMRACC/∆IDRN vs Temperature ITMR vs IDRN 9.0 ∆ITMRACC/∆IDRN (µA/µA) 8.8 8.6 100 TIMER ON (CIRCUIT BREAKING, IDRN = 50µA) IIN = 2mA 10 1 8.4 IDRN (mA) 10 1 8.2 8.0 7.8 0.1 TA = 125°C 0.01 TA = 85°C 7.6 0.001 7.4 0.0001 TA = 25°C 7.2 0.1 0.001 0.01 0.1 IDRN (mA) 1 7.0 –55 –35 –15 10 0.00001 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G33 VDRNL vs Temperature FOR PWRGD STATUS (MS ONLY) IDRN = 50µA VPGL (V) VDRNCL (V) VDRNL (V) 2.0 7.2 7.0 6.8 0.5 6.2 4252-1/2 G35 6.0 –55 –35 –15 14 16 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G36 IPG = 10mA 1.5 1.0 6.6 5 25 45 65 85 105 125 TEMPERATURE (°C) 12 (MS ONLY) 6.4 2.20 –55 –35 –15 8 10 VDRAIN (V) 2.5 7.4 2.25 6 VPGL vs Temperature 7.6 2.50 2.30 4 3.0 7.8 2.55 2.35 2 4252-1/2 G25 VDRNCL vs Temperature 8.0 2.40 0 TA = –40°C 4252-1/2 G34 2.60 2.45 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G32 4252-1/2 G22 ITMR (mA) TIMER = 2V 9 0 –55 –35 –15 IPG = 5mA IPG = 1.6mA 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G37 425212f 7 LTC4252-1/LTC4252-2 U W TYPICAL PERFOR A CE CHARACTERISTICS 210 60 200 59 190 tSS (µs) IPGH (µA) 220 VPWRGD = 0V (MS ONLY) 58 170 56 160 5 25 45 65 85 105 125 TEMPERATURE °(C) 4252-1/2 G38 0.7 0.6 180 57 55 –55 –35 –15 0.8 SS PIN FLOATING, VSS RAMPS FROM 0.2V TO 2V DELAY (µs) 62 61 tPLLUG and tPHLOG vs Temperature tSS vs Temperature IPGH vs Temperature 150 –55 –35 –15 0.4 0.3 tPLLUG tPHLOG 0.2 0.1 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G27 U U U PI FU CTIO S 0.5 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4252-1/2 G24 (MS/MS8) VIN (Pin 1/Pin 1): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor. A shunt regulator clamps VIN at 13V. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO (9.2V), overriding UV and OV. If UV is high, OV is low and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating a GATE ramp-up. If VIN drops below approximately 8.2V, GATE pulls low immediately. low until SS exceeds 20 • VOS = 0.2V. SS is internally shunted by a 100k resistor (RSS) which limits the SS pin voltage to 2.2V. This corresponds to an analog current limit SENSE voltage of 100mV. If the SS capacitor is omitted, the SS pin ramps from 0V to 2.2V in about 220µs. The SS pin is pulled low under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. PWRGD (Pin 2/Not Available): Power Good Status Output (MS only). At start-up, PWRGD latches low if DRAIN is below 2.385V and GATE is within 2.8V of VIN. PWRGD status is reset by UV, VIN (UVLO) or a circuit breaker fault timeout. This pin is internally pulled high by a 58µA current source. SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense Pin. Load current is monitored by a sense resistor RS connected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (230µA+8•IDRN) TIMER pull-up current. If SENSE exceeds VACL (100mV), the analog current limit amplifier pulls GATE down to regulate the MOSFET current at VACL/RS. In the event of a catastrophic short-circuit, SENSE may overshoot 100mV. If SENSE reaches VFCL (200mV), the fast current limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE. SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp inrush current during start up, thereby effecting control over di/dt. A 20x attenuated version of the SS pin voltage is presented to the current limit amplifier. This attenuated voltage limits the MOSFET’s drain current through the sense resistor during the soft-start current limiting. At the beginning of a start-up cycle, the SS capacitor (CSS) is ramped by a 22µA current source. The GATE pin is held 425212f 8 LTC4252-1/LTC4252-2 U U U PI FU CTIO S (MS/MS8) VEE (Pin 5/Pin 4): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. GATE (Pin 6/Pin 5): N-Channel MOSFET Gate Drive Output. This pin is pulled high by a 58µA current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV, OV, or a circuit breaker fault timeout. GATE is actively servoed to control the fault current as measured at SENSE. A compensation capacitor at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, GATE ramp-up after an overvoltage event or restart after a current limit fault. During GATE start-up, a second comparator detects if GATE is within 2.8V of VIN before PWRGD is set (MS package only). DRAIN (Pin7/Pin 6): Drain Sense Input. Connecting an external resistor, RD, between this pin and the MOSFET’s drain (VOUT) allows voltage sensing below 6.15V and current feedback to TIMER. A comparator detects if DRAIN is below 2.385V and together with the GATE high comparator sets the PWRGD flag. If VOUT is above VDRNCL, DRAIN clamps at approximately VDRNCL. The current through RD is internally multiplied by 8 and added to TIMER’s 230µA pullup current during a circuit breaker fault cycle. This reduces the fault time and MOSFET heating. OV (Pin 8/Pin7): Overvoltage Input. The active high threshold at the OV pin is set at 6.15V with 0.6V hysteresis. If OV > 6.15V, GATE pulls low. When OV returns below 5.55V, GATE start-up begins without an initial timing cycle. If an overvoltage condition occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after the overvoltage condition goes away. An overvoltage condition does not reset the PWRGD flag. The internal UVLO at VIN always overrides OV. A 1nF to 10nF capacitor at OV prevents transients and switching noise from affecting the OV thresholds and prevents glitches at the GATE pin. UV (Pin 9/Pin 7): Undervoltage Input. The active low threshold at the UV pin is set at 2.925V with 0.3V hysteresis. If UV < 2.925V, PWRGD pulls high, both GATE and TIMER pull low. If UV rises above 3.225V, this initiates an initial timing cycle followed by GATE start-up. The internal UVLO at VIN always overrides UV. A low at UV resets an internal fault latch. A 1nF to 10nF capacitor at UV prevents transients and switching noise from affecting the UV thresholds and prevents glitches at the GATE pin. TIMER (Pin 10/Pin 8): Timer Input. TIMER is used to generate an initial timing delay at start-up and to delay shutdown in the event of an output overload (circuit breaker fault). TIMER starts an initial timing cycle when the following conditions are met: UV is high, OV is low, VIN clears UVLO, TIMER pin is low, GATE is lower than VGATEL, SS < 0.2V, and VSENSE – VEE < VCB. A pull-up current of 5.8µA then charges CT, generating a time delay. If CT charges to VTMRH (4V), the timing cycle terminates, TIMER quickly pulls low and GATE is activated. If SENSE exceeds 50mV while GATE is high, a circuit breaker cycle begins with a 230µA pull-up current charging CT. If DRAIN is approximately 7V during this cycle, the timer pull-up has an additional current of 8 • IDRN. If SENSE drops below 50mV before TIMER reaches 4V, a 5.8µA pull-down current slowly discharges the CT. In the event that CT eventually integrates up to the VTMRH threshold, the circuit breaker trips, GATE quickly pulls low and PWRGD pulls high. The LTC4252-1 TIMER pin latches high with a 5.8µA pull-up source. This latched fault is cleared by either pulling TIMER low with an external device or by pulling UV below 2.925V. The LTC4252-2 the starts a shutdown cooling cycle following an overcurrent fault. This cycle consists of 4 discharging ramps and 3 charging ramps. The charging and discharging currents are 5.8µA and TIMER ramps between its 1V and 4V thresholds. At the completion of a shutdown cooling cycle, the LTC4252-2 attempts a start-up cycle. 425212f 9 LTC4252-1/LTC4252-2 W BLOCK DIAGRA VIN – DRAIN VIN + 2.385V 8× VEE 6.15V 1× 1× 1× VIN 58µA VEE PWRGD ** VIN 6.15V – 58µA VEE GATE + OV * 2.8V – VEE – UV * –+ VIN + 2.925V + VIN LOGIC – + 4V 5.8µA – 230µA VIN + 0.5V TIMER + – VIN 1V 200mV – VEE 5.8µA FCL + +– VEE VEE 22µA + SS VOS = 10mV 95k 5k VEE ACL – VEE + RSS –+ CB VEE SENSE 50mV +– VEE – 4252-1/2 BD VEE *OV AND UV ARE TIED TOGETHER ON THE MS8 PACKAGE. OV AND UV ARE SEPARATE PINS ON THE MS PACKAGE ** ONLY AVAILABLE IN THE MS PACKAGE 425212f 10 LTC4252-1/LTC4252-2 U OPERATIO Hot Circuit Insertion Interlock Conditions When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4252 is designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. A start-up sequence commences once these “interlock” conditions are met. The LTC4252 resides on a removable circuit board and controls the path between the connector and load or power conversion circuitry with an external MOSFET switch (see Figure 1). Both inrush control and short-circuit protection are provided by the MOSFET. A detailed schematic is shown in Figure 2. – 48V and – 48RTN receive power through the longest connector pins and are the first to connect when the board is inserted. The GATE pin holds the MOSFET off during this time. UV/ OV determines whether or not the MOSFET should be turned on based upon internal high accuracy thresholds and an external divider. UV/OV does double duty by also monitoring whether or not the connector is seated. The top of the divider detects – 48RTN by way of a short connector pin that is the last to mate during the insertion sequence. PLUG-IN BOARD + –48RTN LTC4252 + CLOAD LONG 3. The voltage at OV < 5.55V. 4. The (SENSE – VEE) voltage is < 50mV (VCB). 6. The voltage on the TIMER capacitor (CT) is < 1V (VTMRL). 7. The voltage at GATE is < 0.5V (VGATEL). The first three conditions are continuously monitored and the latter four are checked prior to initial timing or GATE ramp-up. Upon exiting an OV condition, the TIMER pin voltage requirement is inhibited. Details are described in the Applications Information, Timing Waveforms section. TIMER begins the start-up sequence by sourcing 5.8µA into CT. If VIN, UV or OV falls out of range, the start-up cycle stops and TIMER discharges CT to less than 1V, then waits until the aforementioned conditions are once again met. If CT successfully charges to 4V, TIMER pulls low and both SS and GATE pins are released. GATE sources 58µA (IGATE), charging the MOSFET gate and associated capacitance. The SS voltage ramp limits VSENSE to control the inrush current. PWRGD pulls active low when GATE is within 2.8V of VIN and DRAIN is lower than VDRNL. + ISOLATED DC/DC CONVERTER MODULE – –48V 2. The voltage at UV > 3.225V. 5. The voltage at SS is < 0.2V (20 • VOS). Initial Start-Up LONG 1. The input voltage VIN exceeds 9.2V (UVLO). LONG LOW VOLTAGE CIRCUITRY –48RTN – SHORT BACKPLANE R1 402k 1% RIN 10k 1/2W 1 CIN 1µF UV/OV LTC4252-1 8 TIMER 2 6 SS DRAIN C1 10nF SENSE VEE R2 32.4k 1% + VIN 7 4252-1/2 F01 Figure 1. Basic LTC4252 Hot Swap Topology CLOAD 100µF TYP CSS 68nF CT 0.33µF 4 GATE 3 CC 18nF 5 RD 1M RC 10Ω LONG –48V RS 0.02Ω Q1 IRF530S 4252-1/2 F02 Figure 2. –48V, 2.5A Hot Swap Controller 425212f 11 LTC4252-1/LTC4252-2 U OPERATIO Two modes of operation are possible during the time the MOSFET is first turning on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp to –48V and the LTC4252 will fully enhance the MOSFET. A second possibility is that the load current exceeds the softstart current limit threshold of [VSS(t)/20 – VOS]/RS. In this case the LTC4252 will ramp the output by sourcing softstart limited current into the load capacitance. If the softstart voltage is below 1.2V, the circuit breaker TIMER is held low. Above 1.2V, TIMER ramps up. It is important to set the timer delay so that, regardless of which start-up mode is used, the TIMER ramp is less than one circuit breaker delay time. If this condition is not met, the LTC4252-1 may shut down after one circuit breaker delay time whereas the LTC4252-2 may continue to autoretry. Board Removal If the board is withdrawn from the card cage, the UV/OV divider is the first to lose connection. This shuts off the MOSFET and commutates the flow of current in the connector. When the power pins subsequently separate, there is no arcing. Current Control Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and resistor RS. There are three distinct thresholds at SENSE: 50mV for a timed circuit breaker function; 100mV for an analog current limit loop; and 200mV for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. If, owing to an output overload, the voltage drop across RS exceeds 50mV, TIMER sources 230µA into CT. CT eventually charges to a 4V threshold and the LTC4252 shuts off. If the overload goes away before CT reaches 4V and SENSE measures less than 50mV, CT slowly discharges (5.8µA). In this way the LTC4252’s circuit breaker function responds to low duty cycle overloads and accounts for fast heating and slow cooling characteristics of the MOSFET. Higher overloads are handled by an analog current limit loop. If the drop across RS reaches 100mV, the current limiting loop servos the MOSFET gate and maintains a constant output current of 100mV/RS. In current limit mode, VOUT typically rises and this increases MOSFET heating. If VOUT > VDRNCL (7V), connecting an external resistor, RD, between VOUT and DRAIN allows the fault timing cycle to be shortened by accelerating the charging of the TIMER capacitor. The TIMER pull-up current is increased by 8 • IDRN. Note that because SENSE > 50mV, TIMER charges CT during this time and the LTC4252 will eventually shut down. Low impedance failures on the load side of the LTC4252 coupled with 48V or more driving potential can produce current slew rates well in excess of 50A/µs. Under these conditions, overshoot is inevitable. A fast SENSE comparator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than the weaker current limit loop. The 100mV/RS current limit loop then takes over and servos the current as previously described. As before, TIMER runs and shuts down the LTC4252 when CT reaches 4V. If CT reaches 4V, the LTC4252-1 latches off with a 5.8µA pull-up current source whereas the LTC4252-2 starts a shutdown cooling cycle. The LTC4252-1 circuit breaker latch is reset by either pulling UV momentarily low or dropping the input voltage VIN below the internal UVLO threshold of 8.2V or pulling TIMER momentarily low with a switch. The LTC4252-2 retries after its shutdown cooling cycle. Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the insertion of non-hot-swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and CT rejects these events allowing the LTC4252 to “ride out” temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse. 425212f 12 LTC4252-1/LTC4252-2 U U W U APPLICATIO S I FOR ATIO SHUNT REGULATOR UV low-to-high (VUVHI) = 3.225V A fast responding regulator shunts the LTC4252 VIN pin. Power is derived from – 48RTN by an external current limiting resistor. The shunt regulator clamps VIN to 13V (VZ). A 1µF decoupling capacitor at VIN filters supply transients and contributes a short delay at start-up. RIN should be chosen to accommodate both VIN supply current and the drive required for an optocoupler if the PWRGD function on the 10-pin MS package is used. Higher current through RIN results in higher dissipation for RIN and the LTC4252. An alternative is a separate NPN buffer driving the optocoupler as shown in Figure 3. Multiple 1/4W resistors can replace a single higher power RIN resistor. UV high-to-low (VUVLO) = 2.925V An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds: OV low-to-high (VOVHI) = 6.150V OV high-to-low (VOVLO) = 5.550V The UV and OV trip point ratio is designed to match the standard telecom operating range of 43V to 75V when connected together as in Figure 2. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 402k and R2 = 32.4k gives a typical operating range of 43.2V to 74.4V. The under- and overvoltage shutdown thresholds are then 39.2V and 82.5V. 1% divider resistors are recommended to preserve threshold accuracy. INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) The R1-R2 divider values shown in the Typical Application set a standing current of slightly more than 100µA and define an impedance at UV/OV of 30kΩ. In most applications, 30kΩ impedance coupled with 300mV UV hysteresis makes the LTC4252 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. A hysteretic comparator, UVLO, monitors VIN for undervoltage. The thresholds are defined by VLKO and its hysteresis, VLKH. When VIN rises above 9.2V (VLKO) the chip is enabled; below 8.2V (VLKO – VLKH) it is disabled and GATE is pulled low. The UVLO function at VIN should not be confused with the UV/OV pin(s). These are completely separate functions. Separate UV and OV pins are available in the 10-pin MS package and can be used for a wider operating range such as 35.5V to 76V as shown in Figure 3. Other combinations are possible with different resistor arrangements. UV/OV COMPARATORS An UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds: GND RIN 10k 1/2W CL 100µF R4 22k + Q2 GND (SHORT PIN) CIN 1µF 1 VIN R1 432k 1% R3 32.4k 1% EN LTC4252-1 9 R2 14k 1% 8 UV PWRGD OV DRAIN 10 TIMER 3 CT SS 330nF C2 10nF CSS 68nF GATE VEE 5 LOAD R5 2.2k SENSE * 2 7 RD 1M 6 Q1 IRF530S 4 RC 10Ω CC 18nF RS 0.02Ω 4252-1/2 F03 –48V * M0C207 Q2: MMBT5551LT1 Figure 3. – 48V/2.5A Application with Wider Input Operating Range 425212f 13 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO UV/OV OPERATION A low input to the UV comparator will reset the chip and pull the GATE and TIMER pins low. A low-to-high UV transition will initiate an initial timing sequence if the other interlock conditions are met. A high-to-low transition in the UV comparator immediately shuts down the LTC4252, pulls the MOSFET gate low and resets the latched PWRGD high. Overvoltage conditions detected by the OV comparator will also pull GATE low, thereby shutting down the load. However, it will not reset the circuit breaker TIMER, PWRGD flag or shutdown cooling timer. Returning the supply voltage to an acceptable range restarts the GATE pin if all the interlock conditions except TIMER are met. Only during the initial timing cycle does an OV condition reset the TIMER. 1) A 5.8µA slow charge; initial timing and shutdown cooling delay. 2) A (230µA + 8 • IDRN) fast charge; circuit breaker delay. 3) A 5.8µA slow discharge; circuit breaker "cool off" and shutdown cooling. 4) Low impedance switch; resets the TIMER capacitor after an initial timing delay, in UVLO, in UV and in OV during initial timing. For initial start-up, the 5.8µA pull-up is used. The low impedance switch is turned off and the 5.8µA current source is enabled when the interlock conditions are met. CT charges to 4V in a time period given by: t= DRAIN Connecting an external resistor, RD, to the dual function DRAIN pin allows VOUT sensing without it being damaged by large voltage transients. Below 6.15V, negligible pin leakage allows a DRAIN low comparator to detect VOUT less than 2.385V (VDRNL). This condition, together with the GATE low comparator, sets the PWRGD flag. If VOUT > VDRNCL (7V), the DRAIN pin is clamped at about 7V and the current flowing in RD is given by: IDRN ≈ TIMER to provide timing for the LTC4252. Four different charging and discharging modes are available at TIMER: VOUT − VDRNCL RD (1) This current is scaled up 8 times during a circuit breaker fault and is added to the nominal 230µA TIMER current. This accelerates the fault TIMER pull-up when the MOSFET’s drain-source voltage exceeds 7V and effectively shortens the MOSFET heating duration. TIMER The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor CT is used at 4V • C T 5.8µA (2) When CT reaches 4V (VTMRH), the low impedance switch turns on and discharges CT. A GATE start-up cycle begins and both SS and GATE are released. CIRCUIT BREAKER TIMER OPERATION If the SENSE pin detects more than a 50mV drop across RS, the TIMER pin charges CT with (230µA + 8 • IDRN). If CT charges to 4V, the GATE pin pulls low and the LTC4252-1 latches off while the LTC4252-2 starts a shutdown cooling cycle. The LTC4252-1 remains latched off until the UV pin is momentarily pulsed low or TIMER is momentarily discharged low by an external switch or VIN dips below UVLO and is then restored. The circuit breaker timeout period is given by: t= 4V • C T 230µA + 8 • IDRN (3) If VOUT < 6.15V, an internal PMOS device isolates any DRAIN pin leakage current, making IDRN = 0µA in Equation (3). If VOUT > 7V (VDRNCL) during the circuit breaker fault 425212f 14 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO period, the charging of CT accelerates by 8 • IDRN of Equation (1). Intermittent overloads may exceed the 50mV threshold at SENSE, but, if their duration is sufficiently short, TIMER will not reach 4V and the LTC4252 will not shut the external MOSFET off. To handle this situation, the TIMER discharges CT slowly with a 5.8µA pull-down whenever the SENSE voltage is less than 50mV. Therefore, any intermittent overload with VOUT < 6.15V and an aggregate duty cycle of 2.5% or more will eventually trip the circuit breaker and shut down the LTC4252. Figure 4 shows the circuit breaker response time in seconds normalized to 1µF for IDRN = 0µA. The asymmetric charging and discharging of CT is a fair gauge of MOSFET heating. The normalized circuit response time is estimated by t 4 = C T (µF ) (235.8 + 8 • IDRN ) • D − 5.8 [ ] (4) 10 NORMALIZED RESPONSE TIME (s/µF) IDRN = 0µA 1 t 4 = CT(µF) [(235.8 + 8 • IDRN) • D – 5.8] a shutdown cooling cycle begins if TIMER reaches the 4V threshold. TIMER starts with a 5.8µA pull-down until it reaches the 1V threshold. Then, the 5.8µA pull-up turns back on until TIMER reaches the 4V threshold. Four 5.8µA pull-down cycles and three 5.8µA pull-up cycles occur between the 1V and 4V thresholds, creating a time interval given by: tSHUTDOWN = 7 • 3V • C T 5.8µA (5) At the 1V threshold of the last pull-down cycle, a GATE ramp-up is attempted. SOFT-START Soft-start limits the inrush current profile during GATE start-up. Unduly long soft-start intervals can exceed the MOSFET’s SOA rating if powering up into an active load. If SS floats, an internal current source ramps SS from 0V to 2.2V in about 220µs. Connecting an external capacitor CSS from SS to ground modifies the ramp to approximate an RC response of: t − R •C VSS (t) ≈ VSS • 1 − e SS SS (6) 0.1 An internal resistor divider (95k/5k) scales VSS(t) down by 20 times to give the analog current limit threshold: 0.01 0 20 40 60 80 FAULT DUTY CYCLE (%) 100 4252-1/2 F04 Figure 4. Circuit-Breaker Response Time SHUTDOWN COOLING CYCLE For the LTC4252-1 (latchoff version), TIMER latches high with a 5.8µA pull-up after the circuit breaker fault TIMER reaches 4V. For the LTC4252-2 (automatic retry version), VACL (t) = VSS (t) − VOS 20 (7) This allows the inrush current to be limited to VACL(t)/RS. The offset voltage, VOS (10mV), ensures CSS is sufficiently discharged and the ACL amplifier is in current limit before GATE start-up. SS is pulled low under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. 425212f 15 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO GATE GATE is pulled low to VEE under any of the following conditions: in UVLO, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. When GATE turns on, a 58µA current source charges the MOSFET gate and any associated external capacitance. VIN limits the gate drive to no more than 14.5V. Gate-drain capacitance (CGD) feedthrough at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit pulls GATE low with practically no usable voltage at VIN and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating CGD. Instead, a smaller value (≥ 10nF) capacitor CC is adequate. CC also provides compensation for the analog current limit loop. GATE has two comparators: the GATE low comparator looks for < 0.5V threshold prior to initial timing or a GATE start-up cycle; the GATE high comparator looks for < 2.8V relative to VIN and, together with the DRAIN low comparator, sets PWRGD status during GATE startup. needs time to discharge GATE to the threshold of the MOSFET. For a mild overload the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV the FCL comparator takes over, quickly discharging the GATE pin to near VEE potential. FCL then releases and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is to add a nonlinear response to the control loop in favor of reducing MOSFET current. Owing to inductive effects in the system, FCL typically overcorrects the current limit loop and GATE undershoots. A zero in the loop (resistor RC in series with the gate capacitor) helps the ACL amplifier to recover. SHORT-CIRCUIT OPERATION Circuit behavior arising from a load side low impedance short is shown in Figure 5 for the LTC4252. Initially, the current overshoots the fast current limit level of VSENSE = 200mV (Trace 2) as the GATE pin works to bring VGS under control (Trace 3). The overshoot glitches the backplane in the negative direction and when the current is reduced to 100mV/RS, the backplane responds by glitching in the positive direction. SENSE The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to VEE. When SENSE exceeds 50mV, the CB comparator activates the 230µA TIMER pull-up. At 100mV, the ACL amplifier servos the MOSFET current and, at 200mV, the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control. If any of these conditions persists long enough for TIMER to charge CT to 4V (see Equation␣ 3), the LTC4252 shuts down and pulls GATE low. If the SENSE pin encounters a voltage greater than 100mV, the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the MOSFET in normal operation, the ACL amplifier SUPPLY RING OWING TO CURRENT OVERSHOOT SUPPLY RING OWING TO MOSFET TURN OFF –48RTN 50V/DIV ONSET OF OUTPUT SHORT-CIRCUIT SENSE 200mV/DIV GATE 10V/DIV TIMER 5V/DIV FAST CURRENT LIMIT ANALOG CURRENT LIMIT CTIMER RAMP LATCH OFF 0.5ms/DIV 4252-1/2 F05 Figure 5. Output Short-Circuit Behavior of LTC4252 425212f 16 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO TIMER commences charging CT (Trace 4) while the analog current limit loop maintains the fault current at 100mV/RS, which in this case is 5A (Trace 2). Note that the backplane voltage (Trace 1) sags under load. Timer pull-up is accelerated by VOUT. When CT reaches 4V, GATE turns off, PWRGD pulls high, the load current drops to zero and the backplane rings up to over 100V. The positive peak is usually limited by avalanche breakdown in the MOSFET and can be further limited by adding a zener diode across the input from – 48V to – 48RTN, such as Diodes Inc. SMAT70A. A low impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 5 Trace 1, can rob charge from output capacitors on adjacent cards. When the faulty card shuts down, current flows in to refresh the capacitors. If LTC4252s are used by the other cards, they respond by limiting the inrush current to a value of 100mV/RS. If CT is sized correctly, the capacitors will recharge long before CT times out. POWER GOOD, PWRGD PWRGD latches low if GATE charges up to within 2.8V of VIN and DRAIN pulls below VDRNL during start-up. PWRGD is reset in UVLO, in a UV condition or if CT charges up to 4V. An overvoltage condition has no effect on PWRGD status. A 58µA current pulls this pin high during reset. Due to voltage transients between the power module and PWRGD, optoisolation is recommended. This pin provides sufficent drive for an optocoupler. MOSFET SELECTION The external MOSFET switch must have adequate safe operating area (SOA) to handle short-circuit conditions until TIMER times out. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current, but the opposite may not be true. Consult the manufacturer’s MOSFET data sheet for safe operating area and effective transient thermal impedance curves. MOSFET selection is a 3-step process by assuming the absense of a soft-start capacitor. First, RS is calculated and then the time required to charge the load capacitance is determined. This timing, along with the maximum shortcircuit current and maximum input voltage defines an operating point that is checked against the MOSFET’s SOA curve. To begin a design, first specify the required load current and Ioad capacitance, IL and CL. The circuit breaker current trip point (VCB/RS) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at VSUPPLY(MIN). RS is given by: RS = VCB(MIN) IL(MAX) (8) where VCB(MIN) = 40mV represents the guaranteed minimum circuit breaker threshold. During the initial charging process, the LTC4252 may operate the MOSFET in current limit, forcing (VACL) between 80mV to 120mV across RS. The minimum inrush current is given by: IINRUSH(MIN)= 80mV RS (9) Maximum short-circuit current limit is calculated using the maximum VSENSE. This gives ISHORTCIRCUIT(MAX)= 120mV RS (10) The TIMER capacitor CT must be selected based on the slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for CT is calculated based on the maximum time it takes the load capacitor to charge. That time is given by: tCL(CHARGE) = C • V C L• V SUPPLY(MAX) = I IINRUSH(MIN) (11) 425212f 17 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO The maximum current flowing in the DRAIN pin is given by: IDRN(MAX) V −V = SUPPLY(MAX) DRNCL RD (12) Approximating a linear charging rate as IDRN drops from IDRN(MAX) to zero, the IDRN component in Equation (3) can be approximated with 0.5 • IDRN(MAX). Rearranging equation, TIMER capacitor CT is given by: CT = tCL(CHARGE) • (230µA + 4 • IDRN(MAX) ) 4V (13) Returning to Equation (3), the TIMER period is calculated and used in conjunction with V SUPPLY(MAX) and ISHORTCIRCUIT(MAX) to check the SOA curves of a prospective MOSFET. From the SOA curves of a prospective MOSFET, determine the time allowed, tSOA(MAX). CSS is given by: tSOA(MAX) (15) 0.916 • RSS In the above example, 60mV/40mΩ gives 1.5A. tSOA(MAX) for the IRF530S is 40ms. From Equation (15), CSS = 437nF. Actual board evaluation showed that CSS = 100nF was appropriate. The ratio (RSS • CSS) to tCL(CHARGE) is a good gauge as a large ratio may result in the time-out period expiring. This gauge is determined empirically with board level evaluation. C SS = SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 2. It was designed for 50W. Calculate the maximum load current: 50W/36V = 1.4A; allowing for 83% converter efficiency, IIN(MAX) = 1.7A. As a numerical design example, consider a 30W load, which requires 1A input current at 36V. If VSUPPLY(MAX) = 72V and CL = 100µF, RD = 1MΩ, Equation (8) gives RS = 40mΩ; Equation (13) gives CT = 441nF. To account for errors in RS, CT, TIMER current (230µA), TIMER threshold (4V), RD, DRAIN current multiplier and DRAIN voltage clamp (VDRNCL), the calculated value should be multiplied by 1.5, giving the nearest standard value of CT = 680nF. Calculate I SHORTCIRCUIT(MAX) : from Equation (9) ISHORTCIRCUIT(MAX) = 6A. If a short-circuit occurs, a current of up to 120mV/ 40mΩ␣ =␣ 3A will flow in the MOSFET for 3.6ms as dictated by CT␣ =␣ 680nF in Equation (3). The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 3A for 10ms and is safe to use in this application. Consult MOSFET SOA curves: the IRF530S can handle 6A at 72V for 5ms, so it is safe to use in this application. Computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear MOSFET’s SOA characteristics and the RSSCSS response. An overly conservative but simple approach begins with the maximum circuit breaker current, given by: ICB(MAX)= 60mV RS (14) Calculate RS: from Equation (8) RS = 20mΩ. Select a MOSFET that can handle 6A at 72V: IRF530S. Calculate CT: from Equation (13) CT = 220nF. Select CT␣ =␣ 330nF, which gives the circuit breaker time-out period tMAX␣ = 1.76ms. Calculate CSS: using Equations (14) and (15) select CSS␣ =␣ 68nF. FREQUENCY COMPENSATION The LTC4252 typical frequency compensation network for the analog current limit loop is a series RC (10Ω) and CC connected to VEE. Figure 6 depicts the relationship between the compensation capacitor CC and the MOSFET’s CISS. The line in Figure 6 is used to select a starting value 425212f 18 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO COMPENSATION CAPACITANCE CC (nF) 60 CURRENT FLOW FROM LOAD CURRENT FLOW TO –48V BACKPLANE NTY100N10 50 SENSE RESISTOR 40 TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER IRF3710 W 30 IRF540 IRF530 20 4252-1/2 F07 IRF740 10 TO SENSE TO VEE 0 0 2000 8000 4000 6000 MOSFET CISS (pF) Figure 7. Making PCB Connections to the Sense Resistor 4252-1/2 F06 Figure 6. Recommended Compensation Capacitor CC vs MOSFET CISS for CC based upon the MOSFET’s CISS specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing. As seen in Figure 5 previously, at the onset of a shortcircuit event, the input supply voltage can ring dramatically owing to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output. The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche. SENSE RESISTOR CONSIDERATIONS For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4252’s VEE and SENSE pins are strongly recommended. The drawing in Figure 7 illustrates the correct way of making connections between the LTC4252 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. TIMING WAVEFORMS System Power-Up Figure 8 details the timing waveforms for a typical powerup sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At time point 1, the supply ramps up, together with UV/OV, VOUT and DRAIN. VIN and PWRGD follow at a slower rate as set by the VIN bypass capacitor. At time point 2, VIN exceeds VLKO and the internal logic checks for UV > VUVHI, OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS and TIMER < VTMRL. If all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8µA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < V GATEL , SENSE < V CB and SS␣ <␣ 20␣ •␣ VOS must be satisfied before a GATE ramp-up cycle begins. SS ramps up as dictated by RSS • CSS (as in Equation 6); GATE is held low by the analog current limit (ACL) amplifier until SS crosses 20 • VOS. Upon releasing GATE, 58µA sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor at time point 5. At time point 6, load current reaches the SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed, the SENSE voltage is regulated at 425212f 19 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 3 4 56 7 8 9 10 11 GND – VEE OR (–48RTN) – (–48V) UV/OV VIN VLKO VTMRH 230µA + 8 • IDRN 5.8µA TIMER 5.8µA VTMRL 58µA GATE 5.8µA VIN – VGATEH 58µA VGATEL 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS SS VACL SENSE VCB VOUT VDRNCL DRAIN VDRNL PWRGD INITIAL TIMING GATE START-UP 4252-1/2 F08 Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE) VACL(t) (Equation 7) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE – VEE) reaches the VCB threshold at time point 7, the circuit breaker TIMER activates. The TIMER capacitor, CT, is charged by a (230µA + 8 • IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At time point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB, the fault TIMER cycle ends, followed by a 5.8µA discharge cycle (cool off). The duration between time points 7 and 9 must be shorter than one circuit breaker delay to avoid a fault time out during GATE ramp-up. When GATE ramps past the VGATEH threshold at time point 10, PWRGD pulls low. At time point␣ 11, GATE reaches its maximum voltage as determined by VIN. Live Insertion with Short Pin Control of UV/OV In the example shown in Figure 9, power is delivered through long connector pins whereas the UV/OV divider makes contact through a short pin. This ensures the power connections are firmly established before the LTC4252 is activated. At time point 1, the power pins make contact and 425212f 20 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO UV CLEARS VUVHI, CHECK OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 3 4 56 7 8 9 1011 GND – VEE OR (–48RTN) – (–48V) UV/OV VIN VUVHI VLKO VTMRH 230µA + 8 • IDRN 5.8µA TIMER 5.8µA VTMRL 58µA GATE VIN – VGATEH 58µA VGATEL SS 5.8µA 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL VCB SENSE VOUT VDRNCL DRAIN VDRNL PWRGD INITIAL TIMING GATE START-UP 4252-1/2 F09 Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE) VIN ramps through VLKO. At time point 2, the UV/OV divider makes contact and its voltage exceeds VUVHI. In addition, the internal logic checks for OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS and TIMER < VTMRL. If all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8µA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL, SENSE < VCB and SS < 20 • VOS must be satisfied before a GATE start-up cycle begins. SS ramps up as dictated by RSS␣ •␣ CSS; GATE is held low by the analog current limit amplifier until SS crosses 20 • VOS. Upon releasing GATE, 58µA sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor at time point 5. At time point 6, load current reaches the SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed, the SENSE voltage is regulated at VACL(t) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE – VEE) reaches the VCB threshold at time point 7, the circuit breaker TIMER 425212f 21 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO activates. The TIMER capacitor, CT, is charged by a (230µA + 8 • IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB and the fault TIMER cycle ends, followed by a 5.8µA discharge cycle (cool off). When GATE ramps past VGATEH threshold at time point 10, PWRGD pulls low. At time point 11, GATE reaches its maximum voltage as determined by VIN. When UV recovers and clears VUVHI (time point 2), an initial timer cycle begins followed by a start-up cycle. VIN Undervoltage Lockout Timing The VIN undervoltage lockout comparator, UVLO, has a similar timing behavior as the UV pin timing except it looks for VIN < (VLKO – VLKH) to shut down and VIN > VLKO to start. In an undervoltage lockout condition, both UV and OV comparators are held off. When VIN exits undervoltage lockout, the UV and OV comparators are enabled. Undervoltage Timing with Overvoltage Glitch Undervoltage Timing In Figure 11, both UV and OV pins are connected together. When UV clears VUVHI (time point 1), an initial timing cycle starts. If the system bus voltage overshoots VOVHI as shown at time point 2, TIMER discharges. At time point 3, the supply voltage recovers and drops below the VOVLO In Figure 10 when UV pin drops below VUVLO (time point␣ 1), the LTC4252 shuts down with TIMER, SS and GATE all pulling low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses. UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES UV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 UV 2 3 4 56 7 8 9 10 11 VUVHI VUVLO VTMRH 5.8µA TIMER 230µA + 8 • IDRN 5.8µA VTMRL 5.8µA 58µA GATE SS VIN – VGATEH 58µA VGATEL 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL SENSE VCB VDRNCL DRAIN VDRNL PWRGD INITIAL TIMING GATE START-UP 4252-1/2 F10 Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE) 425212f 22 LTC4252-1/LTC4252-2 U U W U APPLICATIO S I FOR ATIO UV/OV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE UV/OV DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 VOVHI UV/OV 3 4 5 67 8 10 12 9 11 VOVLO VUVHI VTMRH 230µA + 8 • IDRN 5.8µA TIMER 5.8µA VTMRL 58µA GATE 58µA VGATEL 5.8µA VIN – VGATEH 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS SS VACL VCB SENSE VDRNCL DRAIN VDRNL PWRGD INITIAL TIMING GATE START-UP 4252-1/2 F11 Figure 11. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE) threshold. The initial timing cycle restarts, followed by a GATE start-up cycle. Overvoltage Timing During normal operation, if the OV pin exceeds VOVHI as shown at time point 1 of Figure 12, the TIMER and PWRGD status are unaffected. Nevertheless, SS and GATE pull down and the load is disconnected. At time point 2, OV recovers and drops below the VOVLO threshold. A GATE start-up cycle begins. If the overvoltage glitch is long enough to deplete the load capacitor, a full start-up cycle as shown between time points 4 through 7 may occur. Circuit Breaker Timing In Figure 13a, the TIMER capacitor charges at 230µA if the SENSE pin exceeds VCB but VDRN is less than 6.15V. If the SENSE pin drops below VCB before TIMER reaches the VTMRH threshold, TIMER is discharged by 5.8µA. In Figure 13b, when TIMER exceeds VTMRH, GATE pulls down immediately and the LTC4252 shuts down. In Figure 13c, multiple momentary faults cause the TIMER capacitor to integrate and reach VTMRH. GATE pull down follows and the LTC4252 shuts down. During shutdown, the LTC4252-1 latches TIMER high with a 5.8µA pull-up current source; the LTC4252-2 activates a shutdown cooling cycle. 425212f 23 LTC4252-1/LTC4252-2 U U W U APPLICATIO S I FOR ATIO OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD AND TIMER ARE UNAFFECTED OV DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS 1 2 34 VOVHI OV 5 67 8 9 VOVLO VTMRH 5.8µA 230µA + 8 • IDRN TIMER 58µA GATE VGATEL 5.8µA VIN – VGATEH 58µA 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL SS VCB SENSE GATE START-UP 4252-1/2 F12 Figure 12. Overvoltage Timing (All Waveforms are Referenced to VEE) CB TIMES OUT 1 2 1 VTMRH 2 1 VTMRH 5.8µA TIMER CB TIMES OUT VTMRH TIMER 230µA + 8 • IDRN 230µA + 8 • IDRN GATE GATE SS SS SS VACL VCB 3 230µA + 8 • IDRN 230µA + 8 • IDRN VACL VCB SENSE VACL VCB SENSE VOUT VOUT DRAIN DRAIN VOUT DRAIN PWRGD PWRGD PWRGD VDRNCL CB FAULT CB FAULT 4 5.8µA TIMER GATE SENSE 2 VDRNCL CB FAULT CB FAULT 4252-1/2 F13 (13a) Momentary Circuit-Breaker Fault (13b) Circuit-Breaker Time Out (13c) Multiple Circuit-Breaker Fault Figure 13. Circuit-Breaker Timing Behavior (All Waveforms are Referenced to VEE) 425212f 24 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO Resetting a Fault Latch (LTC4252-1) The duration of the TIMER reset pulse should be smaller than the time taken to reach 0.2V at SS pin. With a single pole mechanical pushbutton switch, this may not be feasible. A double pole, single throw pushbutton switch removes this restriction by connecting the second switch to the SS pin. With this method, both the SS and TIMER pins are released at the same time (see Figure 19). The latched circuit breaker fault of LTC4252-1 benefits from long cooling time. It is reset by pulling the UV pin below VUVLO with a switch. Reset is also accomplished by pulling the VIN pin momentarily below (VLKO – VLKH). A third reset method involves pulling the TIMER pin below VTMRL as shown in Figure 14. An initial timing cycle is skipped if TIMER is used for reset. An initial timing cycle is generated if reset by the UV pin or the VIN pin. SWITCH RESETS LATCHED TIMER SWITCH RELEASES SS 1 5.8µA TIMER 2 34 5 67 8 9 VTMRH 230µA + 8 • IDRN VTMRL 58µA GATE VGATEL SS 58µA 5.8µA 5.8µA VIN – VGATEH 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS VACL VCB SENSE VDRNCL DRAIN VDRNL PWRGD GATE START-UP MOMENTARY DPST SWITCH RESET 4252-1/2 F14 Figure 14. Pushbutton Reset of LTC4252-1’s Latched Fault (All Waveforms are Referenced to VEE) 425212f 25 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO Shutdown Cooling Cycle (LTC4252-2) Figure 15 shows the timer behavior of the LTC4252-2. At time point 2, TIMER exceeds VTMRH, GATE pulls down immediately and the LTC4252 shuts down. TIMER starts a shutdown cooling cycle by discharging TIMER with 5.8µA to the VTMRL threshold. TIMER then charges with 5.8µA to the VTMRH threshold. There are four 5.8µA discharge phases and three 5.8µA charge phases in this shutdown cooling cycle spanning time points 2 and 3. At time point 3, the LTC4252 automatic retry occurs with a start-up cycle. Good thermal management techniques are highly recommended; power and thermal dissipation must be carefully evaluated when implementing the automatic retry scheme. RETRY CIRCUIT BREAKER TIMES OUT 1 2 230µA + 8 • IDRN TIMER 5.8µA 5.8µA VTMRL 3 45 5.8µA 5.8µA 5.8µA 5.8µA 6 78 9 10 VTMRH 230µA + 8 • IDRN 5.8µA 58µA 58µA GATE 5.8µA 5.8µA VIN – VGATEH VGATEL 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS SS VACL VCB SENSE VOUT VDRNCL DRAIN VDRNL PWRGD CB SHUTDOWN COOLING GATE START-UP 4252-1/2 F15 Figure 15. Shutdown Cooling Timing Behavior of LTC4252-2 (All Waveforms are Referenced to VEE) 425212f 26 LTC4252-1/LTC4252-2 U U W U APPLICATIO S I FOR ATIO Analog Current Limit and Fast Current Limit In Figure 16a, when SENSE exceeds VACL, GATE is regulated by the analog current limit amplifier loop. When SENSE drops below VACL, GATE is allowed to pull up. In Figure 16b, when a severe fault occurs, SENSE exceeds VFCL and GATE immediately pulls down until the analog current amplifier can establish control. If the severe fault causes VOUT to exceed VDRNCL, the DRAIN pin is clamped at VDRNCL. IDRN flows into the DRAIN pin and is multiplied by 8. This extra current is added to the TIMER pull-up current of 230µA. This accelerated TIMER current of [230µA+8 • IDRN] produces a shorter circuit breaker fault delay. Careful selection of CT, RD and MOSFET can help prevent SOA damage in a low impedance fault condition. CB TIMES OUT 12 34 230µA + 8 • IDRN TIMER VTMRH 5.8µA 5.8µA 1 VTMRH 230µA + 8 • IDRN TIMER GATE GATE SS SS VACL SENSE VCB VOUT SENSE 2 VFCL VACL VCB VOUT VDRNCL DRAIN DRAIN PWRGD PWRGD 4252-1/2 F16 (16a) Analog Current Limit Fault (16b) Fast Current Limit Fault Figure 16. Current Limit Behavior (All Waveforms are Referenced to VEE) 425212f 27 LTC4252-1/LTC4252-2 U U W U APPLICATIO S I FOR ATIO Soft-Start If the SS pin is not connected, this pin defaults to a linear voltage ramp, from 0V to 2.2V in about 220µs at GATE start-up, as shown in Figure 17a. If a soft-start capacitor, CSS, is connected to this SS pin, the soft-start response is modified from a linear ramp to an RC response (Equation␣ 6), as shown in Figure 17b. This feature allows load current to slowly ramp-up at GATE start-up. Soft-start is initiated at time point 3 by a TIMER transition from VTMRH to VTMRL (time points 1 to 2) or by the OV pin falling below the VOVLO threshold after an OV condition. When the SS pin is below 0.2V, the analog current limit amplifier holds GATE low. Above 0.2V, GATE is released and 58µA ramps up the compensation network and GATE capacitance at time point 4. Meanwhile, the SS pin voltage continues to ramp up. When GATE reaches the MOSFET’s threshold, the MOSFET begins to conduct. Due to the MOSFET’s high gm, the MOSFET current quickly reaches the soft-start control value of VACL(t) (Equation 7). At time point 6, the GATE voltage is controlled by the current limit amplifier. The soft-start control voltage reaches the circuit breaker voltage, VCB, at time point 7 and the circuit breaker TIMER activates. As the load capacitor nears full charge, load current begins to decline below VACL(t). The current limit loop shuts off and GATE releases at time point 8. At time point␣ 9, the SENSE voltage falls below VCB and TIMER deactivates. Large values of CSS can cause premature circuit breaker time out as VACL(t) may exceed the VCB potential during the circuit breaker delay. The load capacitor is unable to achieve full charge in one GATE start-up cycle. A more serious side effect of large CSS values is SOA duration may be exceeded during soft-start into a low impedance load. A soft-start voltage below VCB will not activate the circuit breaker TIMER. END OF INTIAL TIMING CYCLE 12 34 567 VTMRH TIMER 7a END OF INTIAL TIMING CYCLE 8 9 10 11 5.8µA 230µA + 8 • IDRN VTMRL 58µA GATE VIN – VGATEH 12 3 4 5 6 VTMRH TIMER VIN – VGATEH 58µA 20 • (VACL + VOS) 20 • (VCB + VOS) SS 20 • VOS 11 5.8µA 230µA + 8 • IDRN 58µA 58µA 20 • (VACL + VOS) 20 • VOS VACL SENSE 10 VTMRL VGS(th) 20 • (VCB + VOS) 8 9 GATE VGS(th) SS 7 VCB VACL SENSE VCB VDRNCL VDRNL DRAIN PWRGD VDRNCL VDRNL DRAIN PWRGD 4252-1/2 F17 (17a) Without External CSS (17b) With External CSS Figure 17. Soft-Start Timing (All Waveforms are Referenced to VEE) 425212f 28 LTC4252-1/LTC4252-2 U W U U APPLICATIO S I FOR ATIO Power Limit Circuit Breaker when Figure 18 shows the LTC4252-2 in a power limit circuit breaking application. The SENSE pin is modulated by the board supply voltage, VSUPPLY. The zener voltage, VZ is set to be the same as the low supply operating voltage, VSUPPLY(MIN) = 36V. If the goal is to have the high supply operating voltage, VSUPPLY(MAX) = 72V give the same power at VSUPPLY(MIN), then resistors R4 and R6 are selected using the ratio: R6 VCB = R4 VSUPPLY(MAX) VSUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX)) = 54V. The peak power at the fault current limit occurs at the supply overvoltage threshold. The fault current limited power is: POWERFAULT = VSUPPLY R6 • VACL – (VSUPPLY – VZ ) • RS R4 (18) (16) If R6 is 22Ω, R4 is 31.6k. The peak circuit breaker power limit is: POWERMAX 2 VSUPPLY(MIN) + VSUPPLY(MAX) ) ( = 4 • VSUPPLY(MIN) • VSUPPLY(MAX) (17) •POWERSUPPLY(MIN) = 1.125 • POWERSUPPLY(MIN) GND RIN 3× 1.8k 1/4W EACH GND (SHORT PIN) CIN 1µF 1 VIN R1 432k 1% 8 R2 14k 1% R3 32.4k 1% 10 CSS 0.33µF C1 10nF 3 UV PWRGD OV DRAIN TIMER SS CT 68nF GATE VEE 5 SENSE 2 LOAD EN * VOUT RD 1M 7 6 4 CL 100µF R5 5.6k D1 BZX84C36 LTC4252-1 9 + R4 31.6k R6 22Ω RC 10Ω CC 18nF Q1 IRF530S RS 0.02Ω 4252-1/2 F18 –48V * M0C207 Figure 18. Power Limit Circuit Breaking Application 425212f 29 LTC4252-1/LTC4252-2 U PACKAGE DESCRIPTIO MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 0.42 ± 0.04 (.0165 ± .0015) TYP 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.65 (.0256) BSC 8 7 6 5 0.52 (.206) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.88 ± 0.1 (.192 ± .004) DETAIL “A” 0° – 6° TYP GAUGE PLANE 0.53 ± 0.015 (.021 ± .006) DETAIL “A” 1 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.077) SEATING PLANE 0.22 – 0.38 (.009 – .015) 0.65 (.0256) BCS 0.13 ± 0.05 (.005 ± .002) MSOP (MS8) 1001 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 425212f 30 LTC4252-1/LTC4252-2 U PACKAGE DESCRIPTIO MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.497 ± 0.076 (.0196 ± .003) REF 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.88 ± 0.10 (.192 ± .004) DETAIL “A” 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.01 (.021 ± .006) DETAIL “A” 0.86 (.034) REF 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) 0.50 (.0197) TYP 0.13 ± 0.05 (.005 ± .002) MSOP (MS) 0402 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 425212f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC4252-1/LTC4252-2 U TYPICAL APPLICATIO GND RIN 2× 5.1k IN SERIES 1/4W EACH GND (SHORT PIN) 1 CIN 1µF VIN R1 402k 1% CL 100µF R2 32.4k 1% 8 2 CT 150nF C1 10nF UV/OV DRAIN TIMER GATE SS CSS 27nF PUSH RESET VEE SENSE 6 VOUT 5 Q1 IRF540S 3 4 LOAD RD 1M LTC4252-1 7 + R3 22Ω RC 10Ω CC 22nF RS 0.01Ω 4252-1/2 F19 –48V Figure 19. – 48V/5A Application RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8 Negative High Voltage Supplies from –10V to – 80V LT1641-1/LT1641-2 Positive High Voltage Hot Swap Controllers in SO-8 Supplies from 9V to 80V, Latched Off/Autoretry LTC1642 Fault Protected Hot Swap Controller 3V to 16.5V, Overvoltage Protection up to 33V LT4250 – 48V Hot Swap Controller in SO-8 Active Current Limiting, Supplies from – 20V to – 80V LTC4251/LTC4251-1 – 48V Hot Swap Controllers in SOT-23 Fast Active Current Limiting, Supplies from –15V LTC4253 –48V Hot Swap Controller with Sequencer Fast Current Limiting with Three Sequenced Power Good Outputs, Supplies from –15V 425212f 32 Linear Technology Corporation LT/TP 0702 2K PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001