M41T94
512 Bit (64 bit x8) SERIAL RTC (SPI) SRAM
FEATURES SUMMARY
■ 2.7 TO 5.5V OPERATING VOLTAGE
■
SERIAL PERIPHERAL INTERFACE (SPI)
■
2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE
■
AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
■
CHOICE OF POWER-FAIL DESELECT
VOLTAGES (VCC = 2.7 to 5.5V):
– THS = VSS; 2.55V ≤ VPFD ≤ 2.70V
– THS = VCC; 4.20V ≤ VPFD ≤ 4.50V
■
COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY
■
44 BYTES OF GENERAL PURPOSE RAM
■
PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (VALID EVEN DURING BATTERY
BACK-UP MODE)
■
WATCHDOG TIMER
■
MICROPROCESSOR POWER-ON RESET
■
BATTERY LOW FLAG
■
LOW OPERATING CURRENT OF 2.0mA
■
ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (MAX)
■
PACKAGING INCLUDES A 28-LEAD SOIC and
SNAPHAT® TOP (to be ordered separately) or
16-LEAD SOIC
■
28-LEAD SOIC PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY and
CRYSTAL
June 2003
Rev. 2.0
Figure 1. 16-pin SOIC Package
16
1
SO16 (MQ)
Figure 2. 28-pin SOIC Package
SNAPHAT (SH)
Battery & Crystal
28
1
SOH28 (MH)
1/31
M41T94
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. 16-pin SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. 28-pin SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. AC Testing Input/Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Crystal Electrical Characteristics (Externally Supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Output Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
READ and WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. WRITE Mode Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Alarm Repeat Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Alarm Interrupt Reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Back-up Mode Alarm Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/31
M41T94
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. RSTIN1 and RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
tREC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. tREC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
M41T94
SUMMARY DESCRIPTION
The M41T94 Serial TIMEKEEPER® SRAM is a
low power, 512-bit static CMOS SRAM organized
as 64 words by 8 bits. A built-in 32,768 Hz oscillator (external crystal controlled) and 8 bytes of the
SRAM (see Table 10, page 17) are used for the
clock/calendar function and are configured in binary coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/control of Alarm, Watchdog and Square Wave functions. Addresses and data are transferred serially
via a serial SPI interface. The built-in address register is incremented automatically after each
WRITE or READ data byte. The M41T94 has a
built-in power sense circuit which detects power
failures and automatically switches to the battery
supply when a power failure occurs. The energy
needed to sustain the SRAM and clock operations
can be supplied by a small lithium button-cell supply when a power failure occurs. Functions available to the user include a non-volatile, time-of-day
clock/calendar, Alarm interrupts, Watchdog Timer
and programmable Square Wave output. Other
features include a Power-On Reset as well as two
additional debounced inputs (RSTIN1 and
RSTIN2) which can also generate an output Reset
(RST). The eight clock address locations contain
the century, year, month, date, day, hour, minute,
second and tenths/hundredths of a second in 24
hour BCD format. Corrections for 28, 29 (leap year
- valid until year 2100), 30 and 31 day months are
4/31
made automatically. The ninth clock address location controls user access to the clock information
and also stores the clock software calibration setting.
The M41T94 is supplied in either a 16-lead plastic
SOIC (requiring user supplied crystal and battery)
or a 28-lead SOIC SNAPHAT® package (which integrates both crystal and battery in a single
SNAPHAT top). The 28-pin, 330mil SOIC provides
sockets with gold plated contacts at both ends for
direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique
design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device surface-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4TXX-BR12SH” (see Table 21, page 29).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
M41T94
Figure 3. Logic Diagram
Table 1. Signal Names
E
Chip Enable
IRQ/FT/OUT
Interrupt/Frequency Test/Out
Output (Open Drain)
RST
Reset Output (Open Drain)
(1)
RSTIN1
Reset 1 Input
(1)
RSTIN2
Reset 2 Input
SCL
Serial Clock Input
SDI
Serial Data Input
SQW
SDO
Serial Data Output
SDO
SQW
Square Wave Output
RSTIN2
THS
Threshold Select Pin
WDI
WDI
Watchdog Input
THS
XI (1)
Oscillator Input
XO (1)
Oscillator Output
VBAT (1)
Battery Supply Voltage
VCC
Supply Voltage
VSS
Ground
VCC VBAT
XI
XO
(1)
SCL
RST
SDI
IRQ/FT/OUT
M41T94
E
RSTIN1
VSS
AI03683
Note: 1. For SO16 package only.
Note: 1. For SO16 package only.
Figure 4. 16-pin SOIC Connections
Figure 5. 28-pin SOIC Connections
XI
XO
RST
WDI
RSTIN1
RSTIN2
VBAT
VSS
1
2
3
4
5
6
7
8
M41T94
16
15
14
13
12
11
10
9
AI03684
VCC
E
IRQ/FT/OUT
THS
SDI
SQW
SCL
SDO
SQW
NC
NC
NC
NC
NC
NC
WDI
RSTIN1
RSTIN2
NC
NC
NC
VSS
1
2
3
4
5
6
7
M41T94
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
E
IRQ/FT/OUT
NC
NC
THS
NC
NC
SCL
NC
RST
SDI
SDO
NC
AI03685
5/31
M41T94
Figure 6. Block Diagram
REAL TIME CLOCK
CALENDAR
E
44 BYTES
USER RAM
SDO
SPI
INTERFACE
SDI
IRQ/FT/OUT
WDF
WATCHDOG
32KHz
OSCILLATOR
Crystal
AF
RTC w/ALARM
& CALIBRATION
SCL
SQUARE WAVE
(1)
SQW
WDI
VCC
VBAT
VBL= 2.5V
COMPARE
VSO = 2.5V
COMPARE
VPFD = 4.4V
COMPARE
BL
POR
(2.65V if THS = VSS)
RSTIN1
RST(1)
RSTIN2
AI04785
Note: 1. Open drain output
Figure 7. Hardware Hookup
SPI Interface with
(CPOL, CPHA)(1) =
('0','0') or ('1','1')
Master
(ST6, ST7, ST9,
ST10, Others)
D
Q
C
C
Q
D
C
M41T94
CS3
CS2
CS1
E
Q
D
C
XXXXX
E
Q
D
XXXXX
E
AI03686
Note: 1. CPOL (Clock Polarity) and CPHA (Clock Phase) are bits that may be set in the SPI Control Register of the MCU.
6/31
M41T94
Table 2. Function Table
Mode
E
SCL
SDI
SDO
Disable Reset
H
Input Disabled
Input Disabled
High Z
WRITE
L
Data Bit latch
High Z
X
Next data bit shift (1)
AI04630
READ
L
AI04631
Note: 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 8. Data and Clock Timing
CPOL
CPHA
0
0
C
1
1
C
SDI
MSB
LSB
SDO
MSB
LSB
AI04632
Signal Description
Serial Data Output (SDO). The output pin is
used to transfer data serially out of the Memory.
Data is shifted out on the falling edge of the serial
clock.
Serial Data Input (SDI). The input pin is used to
transfer data serially into the device. Instructions,
addresses, and the data to be written, are each received this way. Input is latched on the rising edge
of the serial clock.
Serial Clock (SCL). The serial clock provides the
timing for the serial interface (as shown in Figure
10, page 12 and Figure 11, page 12). The W/R Bit,
addresses, or data are latched, from the input pin,
on the rising edge of the clock input. The output
data on the SDO pin changes state after the falling
edge of the clock input.
The M41T94 can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2, page 7 and Figure
8, page 7).
Chip Enable (E). When E is high, the memory
device is deselected, and the SDO output pin is
held in its high impedance state.
After power-on, a high-to-low transition on E is required prior to the start of any operation.
7/31
M41T94
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
TSTG
Storage Temperature (VCC Off, Oscillator Off)
VCC
Supply Voltage
TSLD(1)
VIO
Lead Solder Temperature for 10 seconds
Input or Output Voltage
IO
Output Current
PD
Power Dissipation
Value
Unit
SNAPHAT
–40 to 85
°C
SOIC
–55 to 125
°C
–0.3 to 7
V
260
°C
–0.3 to VCC+0.3
V
20
mA
1
W
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
8/31
M41T94
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 4. DC and AC Measurement Conditions
Parameter
M41T94
VCC Supply Voltage
2.7 to 5.5V
Ambient Operating Temperature
–40 to 85°C
Load Capacitance (CL)
100pF
Input Rise and Fall Times
≤ 50ns
Input Pulse Voltages
0.2 to 0.8VCC
Input and Output Timing Ref. Voltages
0.3 to 0.7VCC
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 9. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Table 5. Capacitance
Parameter(1,2)
Symbol
CIN
COUT(3)
tLP
Min
Max
Unit
Input Capacitance
7
pF
Output Capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs are deselected.
9/31
M41T94
Table 6. DC Characteristics
Symb.
Parameter
Battery Current OSC ON
IBAT
Battery Current OSC OFF
ICC1
Supply Current
ICC2
Supply Current (Standby)
ILI(2)
Input Leakage Current
ILO(3)
Output Leakage Current
Test Condition(1)
Min
TA = 25°C, VCC = 0V,
VBAT = 3V
Typ
Max
Unit
400
500
nA
50
nA
f = 2 MHz
2
mA
SCL, SDI = VCC – 0.3V
1.4
mA
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
VIH
Input High Voltage
0.7VCC
VCC + 0.3
V
VIL
Input Low Voltage
–0.3
0.3VCC
V
VBAT
Battery Voltage
2.5
3.5(6)
V
VOH
Output High Voltage(4)
IOH = –1.0mA
Output Low Voltage(4)
IOL = 3.0mA
0.4
Output Low Voltage (Open Drain)(5)
IOL = 10mA
0.4
VOL
2.4
V
V
VPFD
VSO
Power Fail Deselect (THS = VCC)
4.20
4.40
4.50
Power Fail Deselect (THS = VSS)
2.55
2.60
2.70
V
Battery Back-up Switchover
2.5
V
Note: 1.
2.
3.
4.
5.
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
RSTIN1 and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
Outputs Deselected.
For SQW pin (CMOS).
For IRQ/FT/OUT, RST pins (Open Drain): if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0V when
VCC = 0V (during battery back-up mode).
6. For rechargeable back-up, VBAT (max) may be considered VCC.
Table 7. Crystal Electrical Characteristics (Externally Supplied)
Symbol
Parameter(1,2)
f0
Resonant Frequency
RS
Series Resistance
CL
Load Capacitance
Typ
Min
Max
32.768
kHz
50
12.5
Unit
kΩ
pF
Note: 1. Load capacitors are integrated within the M41T94. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account. These characteristics are externally supplied.
2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S:
1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at [email protected] or http://www.kdsj.co.jp for further information on this crystal type.
10/31
M41T94
OPERATION
The M41T94 clock operates as a slave device on
the SPI serial bus. Each memory device is accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL, SDI and SDO
(see Table 1, page 5 and Figure 7, page 6). The
device is selected when the Chip Enable input (E)
is held low. All instructions, addresses and data
are shifted serially in and out of the chip. The most
significant bit is presented first, with the data input
(SDI) sampled on the first rising edge of the clock
(SCL) after the Chip Enable (E) goes low. The 64
bytes contained in the device can then be accessed sequentially in the following order:
1.
Tenths/Hundredths of a Second Register
2.
Seconds Register
3.
Minutes Register
4.
Century/Hours Register
5.
Day Register
6.
Date Register
7.
Month Register
8.
Year Register
9.
Control Register
10.
Watchdog Register
11 - 16.Alarm Registers
17 - 19.Reserved
20.
Square Wave Register
21 - 64.User RAM
The M41T94 clock continually monitors VCC for an
out-of tolerance condition. Should VCC fall below
VPFD, the device terminates an access in progress
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from a an out-of-tolerance system. When
VCC falls below VSO, the device automatically
switches over to the battery and powers down into
an ultra low current mode of operation to conserve
battery life. As system power returns and VCC rises above VSO, the battery is disconnected, and the
power supply is switched to external VCC. Write
protection continues until VCC reaches VPFD (min)
plus tREC (min). For more information on Battery
Storage Life refer to Application Note AN1012.
SPI Bus Characteristics
The Serial Peripheral interface (SPI) bus is intended for synchronous communication between different ICs. It consists of four signal lines: Serial
Data Input (SDI), Serial Data Output (SDO), Serial
Clock (SCL) and a Chip Enable (E).
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are called
“slaves.”
The E input is used to initiate and terminate a data
transfer. The SCL input is used to synchronize
data transfer between the master (micro) and the
slave (M41T94) devices.
The SCL input, which is generated by the microcontroller, is active only during address and data
transfer to any device on the SPI bus (see Figure
7, page 6).
The M41T94 can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and output data (SDO) is shifted out on the high-to-low
transition of SCL (see Table 2, page 7 and Figure
8, page 7).
There is one clock for each bit transferred. Address and data bits are transferred in groups of
eight bits. Due to memory size the second most
significant address bit is a Don’t Care (address bit
6).
11/31
M41T94
Figure 10. Input Timing Requirements
tEHEL
E
tELCH
tCHEH
tEHCH
SCL
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
SDI
HIGH IMPEDANCE
SDO
LSB IN
tDLDH
tDHDL
AI04633
Figure 11. Output Timing Requirements
E
tCH
SCL
tCLQV
tCL
tEHQZ
tCLQX
SDO
LSB OUT
MSB OUT
tQLQH
tQHQL
SDI
ADDR. LSB IN
AI04634
12/31
M41T94
Table 8. AC Characteristics
Parameter(1)
Symbol
Min
Max
Unit
2
MHz
fSCL
Serial Clock Input Frequency
DC
tCH(2)
Clock High
200
tCHCL(3)
Clock Transition (Fall Time)
ns
1
µs
tCHDX
Serial Clock Input High to Input Data Transition
50
ns
tCHEH
Serial Clock Input High to Chip Enable High
200
ns
tCL(2)
Clock Low
200
ns
tCLCH(3)
Clock Transition (Rise Time)
tCLQV
Serial Clock Input Low to Output Valid
tCLQX
Serial Clock Input Low to Output Data Transition
1
µs
150
ns
0
ns
tDHDL(3)
Input Data Transition (Fall Time)
1
µs
tDLDH(3)
Input Data Transition (Rise Time)
1
µs
tDVCH
Input Data to Serial Clock Input High
40
ns
tEHCH
Chip Enable High to Serial Clock Input High
200
ns
tEHEL
Chip Enable High to Chip Enable Low
200
ns
tEHQZ(3)
tELCH
Chip Enable High to Output High-Z
Chip Enable Low to Serial Clock Input High
250
200
ns
ns
tQHQL(3)
Output Data Transition (Fall Time)
100
ns
tQLQH(3)
Output Data Transition (Rise Time)
100
ns
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
2. tCH + tCL ≥ 1/fSCL
3. Value guaranteed by design, not 100% tested in production.
13/31
M41T94
READ and WRITE Cycles
Address and data are shifted MSB first into the Serial Data Input (SDI) and out of the Serial Data
Output (SDO). Any data transfer considers the first
bit to define whether a READ or WRITE will occur.
This is followed by seven bits defining the address
to be read or written. Data is transferred out of the
SDO for a READ operation and into the SDI for a
WRITE operation. The address is always the second through the eighth bit written after the Enable
(E) pin goes low. If the first bit is a '1,' one or more
WRITE cycles will occur. If the first bit is a '0,' one
or more READ cycles will occur (see Figure 12
and Figure 13, page 15).
Data transfers can occur one byte at a time or in
multiple byte burst mode, during which the address pointer will be automatically incremented.
For a single byte transfer, one byte is read or written and then E is driven high. For a multiple byte
transfer all that is required is that E continue to remain low. Under this condition, the address pointer
will continue to increment as stated previously. Incrementing will continue until the device is deselected by taking E high. The address will wrap to
00h after incrementing to 3Fh.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). Although the clock continues to maintain the correct time, this will prevent
updates of time and date during either a READ or
WRITE of these address locations by the user.
The update will resume either due to a deselect
condition or when the pointer increments to an
non-clock or RAM address (08h to 3Fh).
Note: This is true both in READ and WRITE mode.
Figure 12. READ Mode Sequence
E
0
1
3
2
5
4
7
6
8
9
12 13 14 15 16 17
22
SCL
7 BIT ADDRESS
W/R BIT
SDI
7
6
5
4
3
2
1
0
MSB
SDO
HIGH IMPEDANCE
DATA OUT
(BYTE 1)
7
MSB
6
5
4
3
2
DATA OUT
(BYTE 2)
1
0
7
6
5
4
3
2
1
0
MSB
AI04635
14/31
M41T94
Figure 13. WRITE Mode Sequence
E
0
1
3
2
4
5
6
7
8
9
15
10
SCL
DATA BYTE
7 BIT ADDR
W/R BIT
SDI
7
6
5
4
3
2
MSB
1
0
7
6
5
4
3
2
1
0
7
MSB
SDO
HIGH IMPEDANCE
AI04636
Data Retention Mode
With valid VCC applied, the M41T94 can be accessed as described above with READ or WRITE
cycles. Should the supply voltage decay, the
M41T94 will automatically deselect, write protecting itself when VCC falls between VPFD (max) and
VPFD (min) (see Figure 14, page 15). At this time,
the Reset pin (RST) is driven active and will remain active until VCC returns to nominal levels.
When VCC falls below the switch-over voltage
(VSO ), power input is switched from the VCC pin to
the SNAPHAT battery (or external battery for
SO16) at this time, and the clock registers are
maintained from the attached battery supply. All
outputs become high impedance. On power up,
when VCC returns to a nominal value, write protection continues for tREC by internally inhibiting E.
The RST signal also remains active during this
time (see Figure 14, page 15). Before the next active cycle, Chip Enable should be taken high for at
least tEHEL, then low.
For a further more detailed review of battery lifetime calculations, please see Application Note
AN1012.
Figure 14. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tRB
tDR
INPUTS
RECOGNIZED
tREC
DON'T CARE
RECOGNIZED
RST
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI03687
15/31
M41T94
Table 9. Power Down/Up AC Characteristics
Symbol
Parameter(1)
Min
Typ
Max
Unit
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
tFB(3)
VPFD (min) to VSS VCC Fall Time
10
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
Power up Deselect Time
40
tREC(5)
tDR
Expected Data Retention Time
200
10(4)
ms
YEARS
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until
200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. At 25°C, VCC = 0V (when using SOH28 + M4T28-BR12SH SNAPHAT top).
5. Programmable (see Table 14, page 23)
CLOCK OPERATIONS
The eight byte clock register (see Table 10, page
17) is used to both set the clock and to read the
date and time from the clock, in a binary coded
decimal format. Tenths/Hundredths of Seconds,
Seconds, Minutes, and Hours are contained within
the first four registers. Bits D6 and D7 of Clock
Register 03h (Century/Hours Register) contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle. Bits D0
through D2 of Register 04h contain the Day (day
of week). Registers 05h, 06h, and 07h contain the
Date (day of month), Month and Years. The ninth
clock register is the Control Register (this is described in the Clock Calibration section). Bit D7 of
Register 01h contains the STOP Bit (ST). Setting
this bit to a '1' will cause the oscillator to stop. If the
device is expected to spend a significant amount
of time on the shelf, the oscillator may be stopped
to reduce current drain. When reset to a '0' the oscillator restarts within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Register (Address location 08h) may be accessed independently. Provision has been made to assure
that a clock update does not occur while any of the
eight clock addresses are being read. If a clock address is being read, an update of the clock regis-
16/31
ters will be halted. This will prevent a transition of
data during the READ.
Note: When a power failure occurs, the Halt Update Bit (HT) will automatically be set to a '1.' This
will prevent the clock from updating the clock registers, and will allow the user to read the exact time
of the power-down event. Resetting the HT Bit to
a '0' will allow the clock to update the clock registers with the current time.
TIMEKEEPER ® Registers
The M41T94 offers 20 internal registers which
contain Clock, Alarm, Watchdog, Flag, Square
Wave and Control data (see Table 10, page 17).
These registers are memory locations which contain external (user accessible) and internal copies
of the data (usually referred to as BiPORT™ TIMEKEEPER cells). The external copies are independent of internal functions except that they are
updated periodically by the simultaneous transfer
of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address.
The system-to-user transfer of clock data will be
halted whenever the clock addresses (00h to 07h)
are being written. The update will resume either
due to a deselect condition or when the pointer increments to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Registers store data in Binary format.
M41T94
Table 10. TIMEKEEPER® Register Map
Addr
D7
00h
D6
D5
D4
D3
D2
0.1 Seconds
D1
D0
Function/Range
BCD Format
0.01 Seconds
Seconds
00-99
01h
ST
10 Seconds
Seconds
Seconds
00-59
02h
0
10 Minutes
Minutes
Minutes
00-59
03h
CEB
CB
Hours (24 Hour Format)
Century/Hours
0-1/00-23
04h
TR
0
Day
01-7
05h
0
0
Date: Day of Month
Date
01-31
06h
0
0
Month
Month
01-12
Year
Year
00-99
07h
10 Hours
0
0
0
10 Date
0
Day of Week
10M
10 Years
08h
OUT
FT
S
Calibration
09h
WDS
BMB4
BMB3
BMB2
0Ah
AFE
SQWE
ABE
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
HT
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
AF
0
BL
0
0
0
0
Flags
10h
0
0
0
0
0
0
0
0
Reserved
11h
0
0
0
0
0
0
0
0
Reserved
12h
0
0
0
0
0
0
0
0
Reserved
13h
RS3
RS2
RS1
RS0
0
0
0
0
SQW
BMB1
BMB0
Control
RB1
RB0
Watchdog
Alarm Month
Al Month
01-12
AI 10 Date
Alarm Date
Al Date
01-31
AI 10 Hour
Alarm Hour
Al Hour
00-23
Alarm 10 Minutes
Alarm Minutes
Al Min
00-59
Alarm 10 Seconds
Alarm Seconds
Al Sec
00-59
Keys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
OUT = Output level
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag (Read only)
AF = Alarm flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
TR = tREC Bit
17/31
M41T94
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. It can also be programmed to go off while the M41T94 is in the battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 11, page 18 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert
the user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT/OUT pin.
Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different ad-
dress. It should also be noted that if the last address written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
To disable the alarm, write '0' to the Alarm Date
Register and to RPT1–5. The IRQ/FT/OUT output
is cleared by a READ to the Flags Register. This
READ of the Flags Register will also reset the
Alarm Flag (D6; Register 0Fh). See Figure 15,
page 18.
The IRQ/FT/OUT pin can also be activated in the
battery back-up mode. The IRQ/FT/OUT will go
low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The
ABE and AFE Bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M41T94 was in the deselect
mode during power-up. Figure 16, page 19 illustrates the back-up mode alarm timing.
Table 11. Alarm Repeat Mode
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
1
1
1
1
1
Once per Second
1
1
1
1
0
Once per Minute
1
1
1
0
0
Once per Hour
1
1
0
0
0
Once per Day
1
0
0
0
0
Once per Month
0
0
0
0
0
Once per Year
Figure 15. Alarm Interrupt Reset Waveforms
0Eh
0Fh
10h
ACTIVE FLAG
IRQ/FT/OUT
HIGH-Z
AI03664
18/31
M41T94
Figure 16. Back-up Mode Alarm Waveforms
VCC
VPFD
VSO
tREC
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT
HIGH-Z
HIGH-Z
AI03920
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second,
10 = 1 second, and 11 = 4 seconds. The amount
of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M41T94 sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by
reading the Flags Register (0Fh).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0,' the watchdog will activate the IRQ/FT/OUT
pin when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for tREC. The Watchdog register and the AFE,
ABE, SQWE, and FT Bits will reset to a '0' at the
end of a Watchdog time-out when the WDS Bit is
set to a '1.'
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI), or
2. the microprocessor can perform a WRITE of the
Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to VSS if not used. In order to perform a software reset of the watchdog timer, the
original time-out period can be written into the
Watchdog Register, effectively restarting the
count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT pin. This will also
disable the watchdog function until it is again programmed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT/OUT pin and the Frequency Test (FT)
function is activated, the watchdog function prevails and the Frequency Test function is denied.
19/31
M41T94
Square Wave Output
The M41T94 offers the user a programmable
square wave function which is output on the SQW
pin. RS3-RS0 bits located in 13h establish the
square wave output frequency. These frequencies
are listed in Table 12. Once the selection of the
SQW frequency has been completed, the SQW
pin can be turned on and off under software control with the Square Wave Enable Bit (SQWE) located in Register 0Ah.
Table 12. Square Wave Output Frequency
Square Wave Bits
20/31
Square Wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
–
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
M41T94
Reset Inputs (RSTIN1 & RSTIN2)
The M41T94 provides two independent inputs
which can generate an output reset. The duration
and function of these resets is identical to a reset
generated by a power cycle. Table 13, page 21
and Figure 17, page 21 illustrate the AC reset
characteristics of this function. Pulses shorter than
tRLRH1 and tRLRH2 will not generate a reset condition. RSTIN1 and RSTIN2 are each internally
pulled up to VCC through a 100kΩ resistor.
Power-on Reset
The M41T94 continuously monitors VCC. When
VCC falls to the power fail detect trip point, the RST
pulls low (open drain) and remains low on powerup for tREC after VCC passes VPFD (max). The RST
pin is an open drain output and an appropriate
pull-up resistor should be chosen to control rise
time.
Figure 17. RSTIN1 and RSTIN2 Timing Waveforms
RSTIN1
tRLRH1
RSTIN2
tRLRH2
RST
(1)
tR1HRH
tR2HRH
AI03665
Table 13. Reset AC Characteristics
Symbol
Parameter(1)
Min
Max
Unit
tRLRH1(2)
RSTIN1 Low to RSTIN1 High
200
ns
tRLRH2(3)
RSTIN2 Low to RSTIN2 High
100
ms
tR1HRH(4)
RSTIN1 High to RST High
40
200
ms
tR2HRH(4)
RSTIN2 High to RST High
40
200
ms
Note: 1.
2.
3.
4.
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
Pulse width less than 50ns will result in no RESET (for noise immunity).
Pulse width less than 20ms will result in no RESET (for noise immunity).
Programmable (see Table 14, page 23).
21/31
M41T94
Calibrating the Clock
The M41T94 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. Uncalibrated clock accuracy will not exceed ±35 PPM
(parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month. When the Calibration circuit is properly employed, accuracy improves to better than +1/–2
PPM at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 18, page 24). Therefore, the
M41T94 design employs periodic counter correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 19, page 24.
The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into
the five Calibration Bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Control Register (8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibration step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M41T94 may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate reference and recording deviation over a fixed period
of time. Calibration values, including the number of
22/31
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
CALIBRATION. This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that accesses the Calibration Byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
IRQ/FT/OUT pin. The pin will toggle at 512 Hz,
when the Stop Bit (ST, D7 of 1h) is '0,' the Frequency Test Bit (FT, D6 of 8h) is '1,' the Alarm Flag
Enable Bit (AFE, D7 of Ah) is '0,' and the Watchdog Steering Bit (WDS, D7 of 9h) is '1' or the
Watchdog Register (9h = 0) is reset.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124 Hz would indicate a +20 PPM oscillator frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output frequency.
The IRQ/FT/OUT pin is an open drain output
which requires a pull-up resistor for proper operation. A 500 to 10kΩ resistor is recommended in order to control the rise time. The FT Bit is cleared
on power-down.
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle.
Output Driver Pin
When the FT Bit, AFE Bit and Watchdog Register
are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of the
Control Register. In other words, when D7 (OUT
Bit) and D6 (FT Bit) of address location 08h are a
'0,' then the IRQ/FT/OUT pin will be driven low.
Note: The IRQ/FT/OUT pin is an open drain which
requires an external pull-up resistor.
M41T94
Battery Low Warning
The M41T94 automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of battery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT top
may be replaced while VCC is applied to the device.
Note: This will cause the clock to lose time during
the interval the SNAPHAT battery/crystal top is
disconnected.
The M41T94 only monitors the battery when a
nominal VCC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
tREC Bit
Bit D7 of Clock Register 04h contains the tREC Bit
(TR). tREC refers to the automatic continuation of
the deselect time after VCC reaches VPFD. This allows for a voltage setting time before WRITEs may
again be performed to the device after a powerdown condition. The tREC Bit will allow the user to
set the length of this deselect time as defined by
Table 14.
Initial Power-on Defaults
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watchdog Register, TR, FT, AFE, ABE, and SQWE. The
following bits are set to a '1' state: ST, OUT, and
HT (see Table 15).
Table 14. t REC Definitions
tREC Bit (TR)
tREC Time
STOP Bit (ST)
Units
Min
Max
0
0
96
98
ms
0
1
40
200(1)
ms
1
X
50
2000
µs
Note: 1. Default Setting
Table 15. Default Values
Condition
TR
ST
HT
Out
FT
AFE
ABE
SQWE
WATCHDOG
Register(1)
Initial Power-up
(Battery Attach for SNAPHAT)(2)
0
1
1
1
0
0
0
0
0
UC
UC
1
UC
0
0
0
0
0
Subsequent Power-up (with
battery back-up)(3)
Note: 1. BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged
23/31
M41T94
Figure 18. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
∆F = -0.038 ppm (T - T )2 ± 10%
0
F
C2
–120
T0 = 25 °C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 19. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
24/31
M41T94
PACKAGE MECHANICAL INFORMATION
Figure 20. SO16 – 16-lead Plastic Small Outline Package Outline
A
A2
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 16. SO16 – 16-lead Plastic Small Outline Package Mechanical Data
millimeters
inches
Symbol
Typ.
Min.
Max.
Typ.
Min.
Max.
A
–
–
1.75
–
–
0.069
A1
–
0.10
0.25
–
0.004
0.010
A2
–
–
1.60
–
–
0.063
B
–
0.35
0.46
–
0.014
0.018
C
–
0.19
0.25
–
0.007
0.010
D
–
9.80
10.00
–
0.386
0.394
E
–
3.80
4.00
–
0.150
0.158
e
1.27
–
–
0.050
–
–
H
–
5.80
6.20
–
0.228
0.244
L
–
0.40
1.27
–
0.016
0.050
a
–
0°
8°
–
0°
8°
N
CP
16
–
–
16
0.10
–
–
0.004
25/31
M41T94
Figure 21. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 17. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
–
–
3.05
–
–
0.120
A1
–
0.05
0.36
–
0.002
0.014
A2
–
2.34
2.69
–
0.092
0.106
B
–
0.36
0.51
–
0.014
0.020
C
–
0.15
0.32
–
0.006
0.012
D
–
17.71
18.49
–
0.697
0.728
E
–
8.23
8.89
–
0.324
0.350
e
1.27
–
–
0.050
–
–
eB
–
3.20
3.61
–
0.126
0.142
H
–
11.51
12.70
–
0.453
0.500
L
–
0.41
1.27
–
0.016
0.050
α
–
0°
8°
–
0°
8°
N
CP
26/31
28
–
–
28
0.10
–
–
0.004
M41T94
Figure 22. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A1
A2
A
A3
eA
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 18. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
–
–
9.78
–
–
0.385
A1
–
6.73
7.24
–
0.265
0.285
A2
–
6.48
6.99
–
0.255
0.275
A3
–
–
0.38
–
–
0.015
B
–
0.46
0.56
–
0.018
0.022
D
–
21.21
21.84
–
0.835
0.8560
E
–
14.22
14.99
–
0.556
0.590
eA
–
15.55
15.95
–
0.612
0.628
eB
–
3.20
3.61
–
0.126
0.142
L
–
2.03
2.29
–
0.080
0.090
27/31
M41T94
Figure 23. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1
A2
A
A3
eA
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 19. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
millimeters
inches
Symbol
28/31
Typ
Min
Max
Typ
Min
Max
A
–
–
10.54
–
–
0.415
A1
–
8.00
8.51
–
0.315
0.335
A2
–
7.24
8.00
–
0.285
0.315
A3
–
–
0.38
–
–
0.015
B
–
0.46
0.56
–
0.018
0.022
D
–
21.21
21.84
–
0.835
0.860
E
–
17.27
18.03
–
0.680
0.710
eA
–
15.55
15.95
–
0.612
0.628
eB
–
3.20
3.61
–
0.126
0.142
L
–
2.03
2.29
–
0.080
0.090
M41T94
PART NUMBERING
Table 20. Ordering Information Scheme
Example:
M41T
94
MH
6
TR
Device Type
M41T
Supply Voltage and Write Protect Voltage
94 = VCC = 2.7 to 5.5V
THS = VCC; 4.20V ≤ VPFD ≤ 4.50V
THS = VSS; 2.55V ≤ VPFD ≤ 2.70V
Package
MQ = SO16
MH (1) = SOH28
Temperature Range
6 = –40 to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The 28-pin SOIC package (SOH28) requires the battery/crystal package (SNAPHAT®) which is ordered separately under the part
number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form.
Caution: Do NOT place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell
battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 21. SNAPHAT Battery Table
Part Number
Description
Package
M4T28-BR12SH
Lithium Battery (48mAh) and Crystal SNAPHAT
SH
M4T32-BR12SH
Lithium Battery (120mAh) and Crystal SNAPHAT
SH
29/31
M41T94
REVISION HISTORY
Table 22. Document Revision History
Date
Rev. #
April 2002
1.0
First edition
25-Apr-02
1.1
Adjust graphic (Figure 6); fix table text (Table 3, 20); adjust characteristics (Table 6. 7)
03-Jul-02
1.2
Modify DC, Crystal Electrical Characteristics footnotes, Default Value table (Tables 6,
7, 15)
06-Nov-02
1.3
Correct dimensions (Table 19)
26-Mar-03
1.4
Update test condition (Table 9)
28-Apr-03
2.0
New Si changes (Figure 6;Table 9, 13, 14, 15)
30/31
Revision Details
M41T94
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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