19-3054; Rev 1a; 2/04 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface The MAX1497/MAX1499 low-power, 3.5- and 4.5-digit, analog-to-digital converters (ADCs) with integrated lightemitting diode (LED) drivers operate from a single 2.7V to 5.25V power supply. They include an internal reference, a high-accuracy on-chip oscillator, and a multiplexed LED display driver. An internal charge pump generates the negative supply needed to power the integrated input buffers for single-supply operation. The ADC is configurable for either a ±2V or ±200mV input range and it outputs its conversion results to an LED and/or to a microcontroller (µC). Microcontroller communication is possible through an SPI™-/QSPI™/MICROWIRE™-compatible serial interface. The MAX1497 is a 3.5-digit (±1999 count) device and the MAX1499 is a 4.5-digit (±19,999 count) device. The MAX1497/MAX1499 do not require external precision integrating capacitors, autozero capacitors, crystal oscillators, charge pumps, or other circuitry required with dual-slope ADCs (commonly used in panel meter circuits). These devices also feature on-chip buffers for the differential signal and reference inputs, allowing direct interface with high-impedance signal sources. In addition, they use continuous internal offset-calibration and offer >100dB rejection of 50Hz and 60Hz line noise. Other features include data hold and peak detection, overrange and underrange detection, and a user-programmable low-battery monitor. The MAX1499 is available in a 32-pin, 7mm ✕ 7mm TQFP package and the MAX1497 is available in 28-pin SSOP and 28-pin PDIP packages. All devices in this family operate over the -40°C to +85°C extended temperature range. Features ♦ High Resolution MAX1499: 4.5 Digits (±19,999 Count) MAX1497: 3.5 Digits (±1999 Count) ♦ Sigma-Delta ADC Architecture No Integrating Capacitors Required No Autozeroing Capacitors Required >100dB of Simultaneous 50Hz and 60Hz Rejection ♦ Operate from a Single 2.7V or 5.25V Supply ♦ Selectable Input Range of ±200mV or ±2V ♦ Selectable Voltage Reference: Internal 2.048V or External ♦ Internal High-Accuracy Oscillator Needs No External Components ♦ Automatic Offset Calibration ♦ Low Power (Exclude LED Driver Current) Maximum 664µA Operating Current Maximum 268µA Shutdown Current ♦ Small 32-Pin, 7mm x 7mm TQFP Package (4.5 Digits), 28-Pin SSOP Package (3.5 Digits) ♦ Also Available in a PDIP Package (3.5 Digits) ♦ Multiplexed LED Drivers Resistor-Programmable Segment Current ♦ SPI-/QSPI-/MICROWIRE-Compatible Serial Interface ♦ Extended Temperature Range (-40°C to +85°C) Applications Ordering Information Digital Panel Meters Hand-Held Meters PART TEMP RANGE PINRESOLUTION PACKAGE (DIGITS) Digital Voltmeters MAX1497EAI* -40°C to +85°C 28 SSOP 3.5 Digital Multimeters MAX1497EPI -40°C to +85°C 28 PDIP 3.5 MAX1499ECJ -40°C to +85°C 32 TQFP 4.5 *Future product—contact factory for availability. Pin Configurations appear at end of data sheet. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1497/MAX1499 General Description MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface ABSOLUTE MAXIMUM RATINGS AVDD to GND (MAX1499).........................................-0.3V to +6V DVDD to GND (MAX1499) ........................................-0.3V to +6V AIN+, AIN- to GND (MAX1499) ...........VNEG to (AVDD to +0.3V) REF+, REF- to GND (MAX1499) ......... VNEG to (AVDD to +0.3V) LOWBATT to GND (MAX1499) ................-0.3V to (AVDD + 0.3V) CLK, EOC, CS, DIN, SCLK, DOUT to GND (MAX1499) .......................-0.3V to (DVDD + 0.3V) VNEG to GND (MAX1499) .......................-2.6V to (AVDD + 0.3V) LED_EN to GND (MAX1499)....................-0.3V to (DVDD + 0.3V) ISET to GND (MAX1499)..........................-0.3V to (AVDD + 0.3V) VDD to GND (MAX1497) ...........................................-0.3V to +6V AIN+, AIN- to GND (MAX1497)..............VNEG to (VDD to +0.3V) REF+, REF- to GND (MAX1497) ........... VNEG to (VDD to +0.3V) CLK, EOC, CS, DIN, SCLK, DOUT to GND (MAX1497)..........................-0.3V to (VDD + 0.3V) VNEG to GND (MAX1497)..........................-2.6V to (VDD + 0.3V) ISET to GND (MAX1497) ............................-0.3V to (VDD + 0.3V) VLED to GLED ..........................................................-0.3V to +6V GLED to GND ........................................................-0.3V to +0.3V SEG_ to GLED..........................................-0.3V to (VLED + 0.3V) DIG_ to GLED ..........................................-0.3V to (VLED + 0.3V) DIG_ Sink Current .............................................................300mA DIG_ Source Current...........................................................50mA SEG_ Sink Current ..............................................................50mA SEG_ Source Current..........................................................50mA Maximum Current Input into Any Other Pin ........................50mA Continuous Power Dissipation (TA = +70°C) 32-Pin TQFP (derate 20.7mW/°C above +70°C).....1652.9mW 28-Pin SSOP (derate 9.5mW/°C above +70°C) ...........762mW 28-Pin PDIP (derate 14.3mW/°C above +70°C)......1142.9mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference) CREF+ = CREF- = 0.1µF, CVNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Noise-Free Resolution Integral Nonlinearity (Note 1) INL MAX1499 -19,999 +19,999 MAX1497 -1999 +1999 2.000V range ±1 200mV range ±1 Range Change Ratio (VAIN+ - VAIN- = 0.100V) on 200mV range (VAIN+ - VAIN- = 0.100V) on 2.0V range Rollover Error VAIN+ - VAIN- = full scale VAIN- - VAIN+ = full scale Output Noise Offset Error (Zero Input Reading) Offset VIN = 0 (Note 2) Gain Error (Note 3) Offset Drift (Zero Reading Drift) VIN = 0 (Note 4) Count Count 10:1 Ratio ±1 Count 10 µVP-P -0 0 Reading -0.5 +0.5 %FSR Gain Drift 0.1 µV/°C ±1 ppm/°C INPUT CONVERSION RATE External-Clock Frequency 4.9152 External-Clock Duty Cycle Conversion Rate 2 40 MHz 60 Internal clock 5 External clock, fCLK = 4.9152MHz 5 _______________________________________________________________________________________ % Hz 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface (AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference) CREF+ = CREF- = 0.1µF, CVNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUTS (AIN+, AIN-) (bypass to GND with 0.1µF or greater capacitors) AIN Input Voltage Range (Note 5) RANGE bit = 0 -2.0 +2.0 RANGE bit = 1 -0.2 +0.2 -2.2 +2.2 AIN Absolute Input Voltage Range to GND Normal-Mode 50Hz and 60Hz Rejection (Simultaneously) Internal clock mode, 50Hz and 60Hz ±2% 100 External clock mode, 50Hz and 60Hz ±2%, fCLK = 4.9152MHz 120 V dB Common-Mode 50Hz and 60Hz Rejection (Simultaneously) CMR For 50Hz and 60Hz ±2%, RSOURCE < 10kΩ 150 dB Common-Mode Rejection CMR At DC 100 dB Input Leakage Current 10 nA Input Capacitance 10 pF Average Dynamic Input Current (Note 6) -20 +20 nA LOW-BATTERY VOLTAGE MONITOR (LOWBATT) (MAX1499 only) LOWBATT TripThreshold 2.048 V LOWBATT Leakage Current 10 pA Hysteresis 20 mV INTERNAL REFERENCE (REF- = GND, INTREF bit = 1) (bypass REF+ to GND with a 4.7µF capacitor) REF Output Voltage VREF AVDD = VDD = 5V 2.007 REF Output Short-Circuit Current REF Output Temperature Coefficient TCVREF Load Regulation AVDD = VDD = 5V ISOURCE = 0 to 300µA, ISINK = 0 to 30µA Line Regulation Noise Voltage 2.048 2.089 V 1 mA 40 ppm/°C 6 mV/µA 50 µV/V 0.1Hz to 10Hz 25 10Hz to 10kHz 400 µVP-P EXTERNAL REFERENCE (INTREF bit = 0) (bypass REF+ and REF- to GND with 0.1µF or greater capacitors) REF Input Voltage Differential (VREF+ - VREF-) Absolute REF+, REF- Input Voltage to GND 2.048 -2.2 Normal-Mode 50Hz and 60Hz Rejection (Simultaneously) +2.2 Internal clock mode, 50Hz and 60Hz ±2% 100 External clock mode, 50Hz and 60Hz ±2%, fCLK = 4.9152MHz 120 V dB Common-Mode 50Hz and 60Hz Rejection (Simultaneously) CMR For 50Hz and 60Hz ±2%, RSOURCE < 10kΩ 150 dB Common-Mode Rejection CMR At DC 100 dB 10 nA Input Leakage Current _______________________________________________________________________________________ 3 MAX1497/MAX1499 ELECTRICAL CHARACTERISTICS (continued) MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference) CREF+ = CREF- = 0.1µF, CVNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN Input Capacitance TYP MAX UNITS +20 nA -2.30 V +10 µA 10 Average Dynamic Input Current (Note 6) -20 pF CHARGE PUMP Output Voltage VNEG CVNEG = 0.1µF -2.60 -2.42 DIGITAL INPUTS (SCLK, DIN, CS, CLK) Input Current Input Low Voltage Input High Voltage Input Hysteresis IIN VIN = 0 or DVDD = VDD -10 MAX1499 0.3 x DVDD MAX1497 0.3 x VDD VINL MAX1499 0.7 x DVDD MAX1497 0.7 x VDD VINH VHYS DVDD = VDD = 3.0V VOL ISINK = 1mA V V 200 mV DIGITAL OUTPUTS (DOUT, EOC) Output Low Voltage Output High Voltage Tri-State Leakage Current 0.4 ISOURCE = 200µA, MAX1499 0.8 x DVDD ISOURCE = 200µA, MAX1497 0.8 x VDD VOH V V IL DOUT only COUT DOUT only VDD MAX1497 2.70 5.25 V AVDD Voltage AVDD MAX1499 2.70 5.25 V DVDD Voltage DVDD MAX1499 2.70 5.25 Power-Supply Rejection VDD PSRR (Note 7) Power-Supply Rejection AVDD PSRRA (Note 7) 80 dB Power-Supply Rejection DVDD PSRRD (Note 7) 100 dB VDD = 5.25V 664 744 VDD = 3.3V 618 663 Standby mode 268 325 Tri-State Output Capacitance -1 +1 15 µA pF POWER SUPPLY (Note 10) VDD Voltage VDD Current (Notes 8, 9) AVDD Current (Notes 8, 9) 4 IVDD IAVDD 80 AVDD = 5.25V 640 AVDD = 3.3V 600 Standby mode 305 _______________________________________________________________________________________ V dB µA µA 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface (AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference) CREF+ = CREF- = 0.1µF, CVNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER DVDD Current (Notes 8, 9) SYMBOL IDVDD LED Drivers Bias Current CONDITIONS MIN TYP MAX DVDD = 5V 320 DVDD = 3.3V 180 Standby mode 20 From AVDD or VDD 120 UNITS µA µA LED DRIVERS (Table 6) LED Supply Voltage VLED LED Shutdown Supply Current ISHDN LED Supply Current ILED Display Scan Rate fOSC Segment Current Slew Rate Seven segments and decimal point on, RISET = 25kΩ 176 MAX1499 512 MAX1497 640 ∆ISEG/∆t DIG_ Voltage Low VDIG Segment Drive Source Current Matching ∆ISEG Segment Drive Source Current ISEG Interdigit Blanking Time 2.70 LED driver shutdown mode 5.25 V 10 µA mA Hz 25 IDIG_ = 176mA VLED - VSEG = 0.6V, RISET = 25kΩ 16 mA/µs 0.178 0.300 V ±3 ±10 % 20 25.5 mA 4 µs _______________________________________________________________________________________ 5 MAX1497/MAX1499 ELECTRICAL CHARACTERISTICS (continued) MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface TIMING CHARACTERISTICS (Notes 11, 12, Figure 8) (AVDD = DVDD = VDD = +2.7V to +5.25V, GND = 0, GLED = 0, VLED = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference) CREF+ = CREF- = 0.1µF, CVNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SCLK Operating Frequency SYMBOL CONDITIONS MIN TYP MAX UNITS 4.2 MHz fSCLK 0 tCH 100 ns SCLK Pulse-Width Low tCL 100 ns DIN to SCLK Setup tDS 50 ns DIN to SCLK Hold tDH 0 ns CS Fall to SCLK Rise Setup tCSS 50 ns SCLK Rise to CS Rise Hold tCSH 0 ns SCLK Fall to DOUT Valid tDO CLOAD = 50pF, Figures 13, 14 120 ns CS Rise to DOUT Disable tTR CLOAD = 50pF, Figures 13, 14 120 ns CS Fall to DOUT Enable tDV CLOAD = 50pF, Figures 13, 14 120 ns SCLK Pulse-Width High Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and offset error. Note 2: Offset calibrated. See OFFSET_CAL1 and OFFSET_CAL2 (MAX1499 only) in the On-Chip Registers section. Note 3: Offset nulled. Note 4: Offset drift error is eliminated by recalibration at the new temperature. Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair. Note 6: VAIN+ or VAIN- = -2.2V to +2.2V. VREF+ or VREF- = -2.2V to +2.2V. All input structures are identical. Production tested on AIN+ and REF+ only. Note 7: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2). Note 8: CLK and SCLK are disabled. Note 9: LED drivers are disabled. Note 10: Power-supply currents are measured with all digital inputs at either GND, DVDD, or VDD and with the device in internal-clock mode. Note 11: All input signals are specified with tRISE = tFALL = 5ns (10% to 90% of DVDD) and are timed from a voltage level of 50% of DVDD, unless otherwise noted. Note 12: See the serial-interface timing diagrams. 6 _______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface 300 DIGITAL SUPPLY 550 500 450 100 0 3.25 3.75 4.25 4.75 5.25 200 0 2.70 3.21 3.72 4.23 4.74 5.25 0 10 20 30 40 50 SHUTDOWN CURRENT vs. TEMPERATURE (MAX1499) SHUTDOWN CURRENT vs. TEMPERATURE (MAX1497) 640 630 150 100 300 50 600 0 -15 10 35 60 85 10 20 30 40 50 60 70 -40 -15 150 100 50 0 250 200 150 100 5.25 85 0.14 0.09 0.04 -0.01 -0.06 -0.11 0 4.75 60 0.19 MAX1497/99 toc08 300 50 DIGITAL SUPPLY 35 MAX1499 OFFSET ERROR vs. SUPPLY VOLTAGE OFFSET ERROR (LSB) 200 10 TEMPERATURE (°C) 350 SHUTDOWN CURRENT (µA) ANALOG SUPPLY SUPPLY VOLTAGE (V) 100 SHUTDOWN CURRENT vs. SUPPLY VOLTAGE (MAX1497) MAX1497/99 toc07 300 4.25 150 TEMPERATURE (°C) SHUTDOWN CURRENT vs. SUPPLY VOLTAGE (MAX1499) 3.75 200 0 0 TEMPERATURE (°C) 3.25 250 50 DIGITAL SUPPLY 610 MAX1497/99 toc06 MAX1497/99 toc05 200 350 SHUTDOWN CURRENT (µA) 650 ANALOG SUPPLY 250 SHUTDOWN CURRENT (µA) MAX1497/99 toc04 670 660 300 70 60 SUPPLY CURRENT vs. TEMPERATURE (MAX1497) 620 SHUTDOWN CURRENT (µA) DIGITAL SUPPLY TEMPERATURE (°C) 680 2.75 300 SUPPLY VOLTAGE (V) 690 250 400 SUPPLY VOLTAGE (V) 700 -40 ANALOG SUPPLY 500 100 400 2.75 SUPPLY CURRENT (µA) 600 600 MAX1497/99 toc09 200 650 700 SUPPLY CURRENT (µA) 400 MAX1497/99 toc02 ANALOG SUPPLY SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 600 500 700 MAX1497/99 toc01 700 SUPPLY CURRENT vs. TEMPERATURE (MAX1499) SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX1497) MAX1497/99 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX1499) -0.16 2.70 3.21 3.72 4.23 SUPPLY VOLTAGE (V) 4.74 5.25 2.75 3.25 3.75 4.25 4.75 5.25 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 7 MAX1497/MAX1499 Typical Operating Characteristics (AVDD = DVDD = VDD = +2.7V to +5.25V, VLED = +2.7V to +5.25V, GND = 0, GLED = 0, external reference mode, REF+ = 2.048V, REF- = GND, CREF+ = CREF- = 0.1µF, RANGE bit = 1, internal clock mode, CVNEG = 0.1µF. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = DVDD = VDD = +2.7V to +5.25V, VLED = +2.7V to +5.25V, GND = 0, GLED = 0, external reference mode, REF+ = 2.048V, REF- = GND, CREF+ = CREF- = 0.1µF, RANGE bit = 1, internal clock mode, CVNEG = 0.1µF. TA = +25°C, unless otherwise noted.) 0 -0.02 -0.04 -0.06 -0.1 -0.08 -0.2 -0.10 0 10 20 30 40 50 60 3.25 3.75 4.25 4.75 MAX1499 (±200mV INPUT RANGE) INL vs. OUTPUT CODE MAX1499 (±2V INPUT RANGE) INL vs. OUTPUT CODE INL (COUNTS) 0.5 -0.5 MAX1497/99 toc12 -0.06 -0.07 -0.08 0 10 20 30 40 50 60 70 TEMPERATURE (°C) 1.0 MAX1497/99 toc13 0 -0.05 5.25 SUPPLY VOLTAGE (V) 0.5 -0.04 -0.10 2.75 70 -0.03 -0.09 TEMPERATURE (°C) 1.0 INL (COUNTS) 0 -0.02 0 -0.5 NOISE DISTRIBUTION 25 MAX1497/99 toc15 0.1 0.02 GAIN ERROR (% FULL SCALE) 0.2 0.04 0 -0.01 PERCENTAGE OF UNITS (%) 0.3 MAX1497/99 toc11 0.4 0.06 MAX1497/99 toc14 OFFSET ERROR (LSB) 0.5 0.08 GAIN ERROR (% FULL SCALE) MAX1497/99 toc10 0.6 MAX1499 GAIN ERROR vs. TEMPERATURE MAX1499 GAIN ERROR vs. SUPPLY VOLTAGE MAX1499 OFFSET ERROR vs. TEMPERATURE 20 15 10 5 -1.0 -20,000 -10,000 0 -1.0 -20,000 20,000 10,000 0 -10,000 0 10,000 20,000 OUTPUT CODE NOISE (LSB) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE DATA OUTPUT RATE vs. TEMPERATURE 2.050 2.049 2.048 2.047 2.046 2.048 2.047 2.046 MAX1497/99 toc18 2.049 5.10 5.08 DATA OUTPUT RATE (Hz) 2.051 MAX1497/99 toc17 2.052 2.050 REFERENCE VOLTAGE (V) MAX1497/99 toc16 2.053 5.06 5.04 5.02 5.00 4.98 4.96 4.94 2.045 4.92 2.045 2.044 4.90 2.044 0 10 20 30 40 50 TEMPERATURE (°C) 8 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 OUTPUT CODE 2.054 REFERENCE VOLTAGE (V) MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface 60 70 2.75 3.25 3.75 4.25 SUPPLY VOLTAGE (V) 4.75 5.25 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface OFFSET ERROR vs. COMMON-MODE VOLTAGE OFFSET ERROR (LSB) 5.005 5.000 4.995 MAX1497/99 toc20 5.010 0.15 0.10 VDD 2V/div 0.05 0 1V/div VNEG -0.05 4.990 -0.10 4.985 -0.15 -0.20 4.980 4.23 4.74 5.25 -2.0 -1.5 -1.0 -0.5 SUPPLY VOLTAGE (V) 0 0.5 1.0 2.0 1.5 20ms/div COMMON-MODE VOLTAGE (V) CHARGE-PUMP OUTPUT VOLTAGE vs. ANALOG SUPPLY VOLTAGE -2.40 SEGMENT CURRENT vs. SUPPLY VOLTAGE 30 -2.42 -2.44 -2.46 -2.48 MAX1497/99 toc23 3.72 RISET = 25kΩ 25 SEGMENT CURRENT (µA) 3.21 MAX1497/99 toc22 2.70 VNEG VOLTAGE (V) DATA OUTPUT RATE (Hz) 5.015 VNEG STARTUP SCOPE SHOT 0.20 MAX1497/99 toc19 5.020 MAX1497/99 toc21 DATA OUTPUT RATE vs. SUPPLY VOLTAGE 20 15 10 5 -2.50 0 2.75 3.25 3.75 4.25 SUPPLY VOLTAGE (V) 4.75 5.25 2.70 3.21 3.72 4.23 4.74 5.25 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 9 MAX1497/MAX1499 Typical Operating Characteristics (continued) (AVDD = DVDD = VDD = +2.7V to +5.25V, VLED = +2.7V to +5.25V, GND = 0, GLED = 0, external reference mode, REF+ = 2.048V, REF- = GND, CREF+ = CREF- = 0.1µF, RANGE bit = 1, internal clock mode, CVNEG = 0.1µF. TA = +25°C, unless otherwise noted.) MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Pin Description PIN NAME FUNCTION MAX1497 MAX1499 1 31 VNEG -2.5V Charge-Pump Voltage-Output. Connect a 0.1µF capacitor to GND. 2 32 REF- Negative Reference Voltage Input. For internal reference operation, connect REF- to GND. For external reference operation, bypass REF- to GND with a 0.1µF capacitor and set VREF- from -2.2V to +2.2V, provided VREF+ > VREF-. 3 1 REF+ Positive Reference Voltage Input. For internal reference operation, connect a 4.7µF capacitor from REF+ to GND. For external reference operation, bypass REF+ to GND with a 0.1µF capacitor and set VREF+ from -2.2V to +2.2V, provided VREF+ > VREF-. 4 2 AIN+ Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to GND with a 0.1µF or greater capacitor. 5 3 AIN- Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to GND with a 0.1µF or greater capacitor. 6 4 ISET Segment Current Controller. Connect to ground through a resistor to set the segment current. See Table 6 for segment current selection. 7 5 GND Ground 8 — VDD Analog and Digital Circuit Supply Voltage. Connect VDD to a +2.7V to +5.25V power supply. Bypass VDD to GND with a 0.1µF and a 4.7µF capacitor. 10 9 8 CLK External Clock Input. When the EXTCLK register bit is set to one, CLK is the master clock input (frequency = 4.9152MHz) for the modulator and the filter. When the EXTCLK register bit is reset to zero, the internal clock is used. Connect CLK to GND or DVDD (MAX1499) or VDD (MAX1497) when the internal oscillator is used. 10 9 EOC Active-Low End-of-Conversion Logic Output. A logic low at EOC indicates that a new ADC result is available in the ADC result register. 11 10 CS Active-Low Chip Select Input. Forcing CS low activates the serial interface. 12 11 DIN Serial Data Input. Data present at DIN is shifted into the internal registers in response to a rising edge at SCLK when CS is low. 13 12 SCLK Serial Clock Input. Apply an external clock to SCLK to facilitate communication through the serial bus. SCLK may idle high or low. 14 13 DOUT Serial Data Output. DOUT presets serial data in response to register queries. Data shifts out on the falling edge of SCLK. DOUT goes high impedance when CS is high. 15 14 DIG0 Digit 0 Driver 16 15 DIG1 Digit 1 Driver 17 16 GLED Ground for LED-Display Segment Driver 18 17 DIG2 Digit 2 Driver 19 18 DIG3 Digit 3 Driver 20 20 SEGA Segment A Driver 21 21 SEGB Segment B Driver 22 22 SEGC Segment C Driver 23 23 SEGD Segment D Driver 24 24 SEGE Segment E Driver ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface PIN MAX1497 MAX1499 25 25 26 27 28 NAME FUNCTION VLED LED-Display Segment-Driver Supply. Connect to a +2.7V to +5.25V supply. Bypass with a 0.1µF capacitor to GLED. 26 SEGF Segment F Driver 27 SEGG Segment G Driver 28 SEGDP Segment DP Driver — 6 AVDD Analog Positive Supply Voltage. Connect AVDD to a +2.7V to +5.25V power supply. Bypass AVDD to GND with a 0.1µF capacitor. — 7 DVDD Digital Positive Supply Voltage. Connect DVDD to a +2.7V to +5.25V power supply. Bypass DVDD to GND with a 0.1µF capacitor. — 19 DIG4 Digit 4 Driver — 29 LED_EN Active-High LED Enable. The MAX1499 LED display driver turns off when LED_EN is driven to logic low. The MAX1499 LED display driver turns on when LED_EN is driven to logic high. — 30 LOWBATT Low-Battery Voltage Monitor. When the LOWBATT input voltage is lower than 2.048V, the LOWBATT bit in the status register is set to one. Detailed Description The MAX1497/MAX1499 low-power, highly integrated ADCs with LED drivers convert a ±2V differential input voltage (one count is equal to 100µV for the MAX1499 and 1mV for the MAX1497) with a sigma-delta ADC and output the result to an LED or µC. An additional ±200mV input range (one count is equal to 10µV for the MAX1499 and 100µV for the MAX1497) is available to measure small signals with increased resolution. The devices operate from a single 2.7V to 5.25V power supply and offer 3.5-digit (MAX1497) or 4.5-digit (MAX1499) conversion results. An internal 2.048V reference, internal charge pump, and a high-accuracy onchip oscillator eliminate external components. The MAX1497/MAX1499 interface with a µC using an SPI-/QSPI-/MICROWIRE-compatible serial interface. Data can either be sent directly to the display or to the µC first for processing before being displayed. The devices also feature on-chip buffers for the differential input signal and external reference inputs, allowing direct interface with high-impedance signal sources. In addition, they use continuous internal offsetcalibration and offer >100dB of 50Hz and 60Hz line noise rejection. Other features include data hold and peak detection, overrange and underrange detection. The MAX1499 also provides a low-battery monitor. Analog Input Protection Internal protection diodes limit the analog input range from VNEG to (AVDD + 0.3V) for the MAX1499, and from VNEG to (VDD to 0.3V) for the MAX1497. If the analog input exceeds this range, limit the input current to 10mA. Internal Analog Input/Reference Buffers The MAX1497/MAX1499 analog input/reference buffers allow the use of high-impedance signal sources. The input buffers’ common-mode input range allows the analog inputs and the reference to range from -2.2V to +2.2V. Modulator The MAX1497/MAX1499 perform analog-to-digital conversions using a single-bit, 3rd-order, sigma-delta modulator. The sigma-delta modulator converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. The modulator quantizes the input signal at a much higher sample rate than the bandwidth of the input. The MAX1497/MAX1499 modulator provides 3rd-order frequency shaping of the quantization noise resulting from the single-bit quantizer. The modulator is fully differential for maximum signal-to-noise ratio and minimum susceptibility to power-supply noise. A single-bit data stream is then presented to the digital filter to remove the frequency-shaped quantization noise. ______________________________________________________________________________________ 11 MAX1497/MAX1499 Pin Description (continued) MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface AVDD DVDD SCLK MAX1499 DIN DOUT ISET VLED CS EOC SERIAL I/O AND CONTROL +2.5V SEG1 AIN+ BINARY-TOBCD CONVERTERS ADC AIN- LED DRIVER SEGF SEGDP DIG0 DIG4 INPUT BUFFERS LED_EN REF+ GLED OSCILLATOR CLOCK REF- -2.5V +2.5V -2.5V 2.048V BANDGAP REFERENCE A = 1.22 CLK TO CONTROL CHARGE PUMP 2.048V GND VNEG LOWBATT Figure 1. MAX1499 Functional Diagram Digital Filtering The MAX1497/MAX1499 contain an on-chip digital lowpass filter that processes the data stream from the modulator using a SINC4 response: sin(x) 4 x The SINC4 filter has a settling time of four output data periods (4 x 200ms). The MAX1497/MAX1499 have 25% overrange capability built into the modulator and digital filter. The digital filter is optimized for the fCLK equal to 4.9152MHz. Other clock frequencies can be used; however, 50Hz/60Hz noise rejection decreases. The frequency response of the SINC4 filter is calculated as follows: 1 (1 - Z -N ) 4 H(z) = N (1 - Z -1) 4 f sin Nπ fm 1 H(f) = N sin πf fm 12 where N is the oversampling ratio, and fm = N x output data rate = 5Hz. Filter Characteristics Figure 2 shows the filter frequency response. The SINC4 characteristic -3dB cutoff frequency is 0.228 times the first notch frequency (5Hz). The oversampling ratio (OSR) for the MAX1497 is 128 and the OSR for the MAX1499 is 1024. The output data rate for the digital filter corresponds to the positioning of the first notch of the filter’s frequency response. The notches of the SINC4 filter are repeated at multiples of the first notch frequency. The SINC4 filter provides an attenuation of better than 100dB at these notches. For example, 50Hz is equal to 10 times the first notch frequency and 60Hz is equal to 12 times the first notch frequency. For large step changes at the input, allow a settling time of 800ms before valid data is read. Clock Modes Configure the MAX1497/MAX1499 to use either the internal oscillator or an externally applied clock to drive the modulator and filter. Set the EXTCLK bit in the control register to zero to put the device in internal-clock mode. Set the EXTCLK bit to one to put the device in ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 0 A -40 A F -80 C E DP G DIGIT 4 A G F D GAIN (dB) B B F C E DP A G B F C E DP A G B F C E DP G B C DP D D D D DIGIT 3 DIGIT 2 DIGIT 1 DIGIT 0 -120 Figure 3. Segment Connection for the MAX1499 (4.5 Digits) -160 -200 0 10 20 30 40 50 A 60 A FREQUENCY (Hz) B F F C D Figure 2. Frequency Response of the SINC4 Filter (Notch at 60Hz) G DIGIT 3 external-clock mode. When using the internal oscillator, connect CLK to GND or DVDD for the MAX1499, or connect CLK to V DD for the MAX1497. The MAX1497/ MAX1499 ideally operate with a 4.9152MHz clock to achieve maximum rejection of 50Hz/60Hz commonmode, power-supply, and normal-mode noise. Internal-Clock Mode The MAX1497/MAX1499 contain an internal oscillator. The power-up condition for the MAX1497/MAX1499 is internal clock operation with the EXTCLK bit in the control register equal to zero. Using the internal oscillator saves board space by removing the need for an external clock source. External-Clock Mode For external clock operation, set the EXTCLK bit in the control register to one and drive CLK with a 4.9152MHz clock source for best 50Hz/60Hz rejection ratio. Other external clock frequencies allow for custom conversion rates. A 2.4576MHz clock signal reduces the conversion rate and the LED update rate by a factor of two while keeping good 50Hz/60Hz noise rejection. The MAX1497/MAX1499 operate with an external clock source of up to 5.05MHz. Charge Pump The MAX1497/MAX1499 contain an internal charge pump to provide the negative supply voltage for the internal analog input/reference buffers. The bipolar input range of the analog input/reference buffers allows this device to accept negative inputs with high source impedances. Connect a 0.1µF capacitor from VNEG to GND. G A B C E DP F A B F C E DP G E DP G B C DP D D D DIGIT 2 DIGIT 1 DIGIT 0 Figure 4. Segment Connection for the MAX1497 (3.5 Digits) Table 1. LED Priority Table SEG_SEL SPI/ADC HOLD PEAK DISPLAY VALUES FORM 1 X X X LED segment registers 0 1 X X LED display register (user written) 0 0 1 X LED display register 0 0 0 1 Peak register 0 0 0 0 ADC result register X = Don’t care. LED Driver The MAX1499 has a 4.5-digit common-cathode display driver and the MAX1497 has a 3.5-digit common-cathode display driver. Figures 3 and 4 show the connection schemes for a standard seven-segment LED display. The LED update rate is 2.5Hz. The MAX1497/ MAX1499 automatically display the results of the ADC, if desired (Table 1). The MAX1497/MAX1499 also allow independent control of the LED driver through the serial interface, allowing for data processing of the ADC result before showing the result on the LED. Additionally, each LED segment can be individually controlled (see the LED segment-display register sections). ______________________________________________________________________________________ 13 MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Table 2. Decimal-Point Control Table—MAX1499 DPON DPSET1 DPSET2 DISPLAY OUTPUT ZERO INPUT READING 0 0 0 18888 0 0 0 1 18888 0 0 1 0 18888 0 0 1 1 18888 0 1 0 0 1888.8 0.0 1 0 1 188.88 0.00 1 1 0 18.888 0.000 1 1 1 1.8888 0.0000 Table 3. Decimal-Point Control Table—MAX1497 DPON DPSET1 DPSET2 DISPLAY OUTPUT X 0 0 188.8 ZERO INPUT READING 0.0 X 0 1 18.88 0.00 X 1 0 1888 0 X 1 1 1.888 0.000 X = Don’t care. Figure 5 shows a typical common-cathode configuration for two digits. In common-cathode configuration, the cathodes of all LEDs in a digit are connected together. Each segment driver of the MAX1497/ MAX1499 connects to its corresponding LEDs anodes. For example, segment driver SEGA connects to all LED segments designated as A. Similar configurations are followed for other segment drivers. The MAX1497/MAX1499 use a multiplexing scheme to drive one digit at a time. The scan rate is fast enough to make the digits appear to be lit. Figures 6 and 7 show data timing diagrams for the MAX1497/MAX1499 where T is the display scan period typically around 1/512Hz or 1.9531ms for the MAX1499 and 1/640Hz or 1.5625ms for the MAX1497. TON in Figures 6 and 7 denotes the amount of time each digit is on and is calculated as follows: Table 4. LED During Overrange and Underrange Conditions CONDITION MAX1497 MAX1499 Overrange 1--- 1---- Underrange -1--- -1---- SEGDP SEGG SEGF SEGE SEGD SEGC SEGB SEGA A B C D E F G DP A B C DIGIT 1 G F G B C E DP D DP D Figure 5. Two-Digit Common-Cathode Configuration 14 G DP TON = T 1.95312ms = = 390.60µs (MAX1499) 5 5 TON = T 1.5625ms = = 390.60µs (MAX1497) 4 4 A F B C E E DIGIT 2 A F D The MAX1497/MAX1499 allow for full decimal-point control and feature leading-zero suppression. Use the DPON, DPSET1, and DPSET2 bits in the control register to set the value of the decimal point (Tables 2 and 3). The MAX1497/MAX1499 overrange and underrange display is shown in Table 4. ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 TON DIGIT 4 (MSD) DIGIT 3 DIGIT 2 DIGIT 1 DIGIT 0 (LSD) T DATA 4 MSD 3 2 1 0 LSD 4 3 2 1 0 4 1 0 LSD 3 2 1 0 3 2 1 Figure 6. LED Voltage Waveform—MAX1499 TON DIGIT 3 (MSD) DIGIT 2 DIGIT 1 DIGIT 0 (LSD) T DATA 3 MSD 2 Figure 7. LED Voltage Waveform—MAX1497 Leading-Zero Suppression The MAX1497/MAX1499 include a leading-zero suppression circuitry to turn off unnecessary zeros. For example, when DPSET1 and DPSET2 = [0,0], 0.0 is displayed instead of 000.0. This feature saves a substantial amount of power from being wasted. Interdigit Blanking The MAX1497/MAX1499 also include an interdigit blanking circuitry. Without this feature, it is possible to see a faint digit next to a digit that is completely on. The interdigit blanking circuitry prevents bleeding over into the next digit for a short period of time. The typical interdigit blanking time is 4µs. Reference The MAX1497/MAX1499 reference sets the full-scale range of the ADC transfer function. With a nominal 2.048V reference, the ADC full-scale range is ±2V with the RANGE bit equal to zero. With the RANGE bit set to one, the full-scale range is ±200mV. A decreased reference voltage decreases full-scale range (see the Transfer Functions section). The MAX1497/MAX1499 accept either an external reference or an internal reference. The INTREF bit selects the reference mode (see the Control Register (Read/Write) section). For internal reference operation, set the INTREF bit to one, connect REF- to GND, and bypass REF+ to GND with a 4.7µF capacitor. The internal reference provides a nominal 2.048V source between REF+ and GND. The internal reference temperature coefficient is typically 40ppm/°C. The default power-on state sets the MAX1497/ MAX1499 to use the external reference with the INTREF bit cleared to zero. The external reference inputs, REF+ and REF-, are fully differential. For a valid external reference input, VREF+ must be greater than VREF-. Bypass REF+ and REF- with a 0.1µF or greater capacitor to GND in external reference mode. Figure 16 shows the MAX1497/MAX1499 operating with an external single-ended reference. In this mode, REFis connected to GND and REF+ is driven with an external 2.048V reference. Bypass REF+ to GND with a 0.47µF capacitor. ______________________________________________________________________________________ 15 MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Figure 15 shows the MAX1497/MAX1499 operating with an external differential reference. In this mode, REF- is connected to the top of the strain gauge and REF+ is connected to the midpoint of the resistor-divider of the supply. Applications Information Serial Interface The SPI/QSPI/MICROWIRE serial interface consists of a chip select (CS), a serial clock (SCLK), a data in (DIN), a data out (DOUT), and an asynchronous EOC output. EOC provides an asynchronous end-of-conversion signal with a period of 200ms (fCLK = 4.9152MHz). The MAX1497 updates the data register when EOC goes high. Data is valid in the ADC result registers when EOC returns low. The serial interface provides access to 12 on-chip registers, allowing control to all the power modes and functional blocks. Table 5 lists the address and read/write accessibility of all the registers. A logic high on CS tri-states DOUT and causes the MAX1497/MAX1499 to ignore any signals on SCLK and DIN. To clock data in or out of the internal shift register, drive CS low. SCLK synchronizes the data transfer. The rising edge of SCLK clocks DIN into the shift register, and the falling edge of SCLK clocks DOUT out of the shift register. DIN and DOUT are transferred MSB first (data is left justified). Figures 8–12 show the detailed serial interface timing diagrams for the 8- and 16-bit read/write operations. All communication with the MAX1497/MAX1499 begins with a command byte on DIN, where the first logic one on DIN is recognized as the START bit (MSB) for the command byte. The following seven clock cycles load the command into a shift register. These 7 bits specify which of the registers are accessed next, and whether a read or write operation takes place. Transitions on the serial clock after the command byte transfer, cause a write or read from the device until the correct number of CS tCSH tCL tCSS tCSH tCH SCLK tDS tDH DIN tDV tDO tTR DOUT Figure 8. Detailed Timing Diagram CS SCLK DIN 1 0 RS4 RS3 RS2 RS1 RS0 x D15 D14 D13 D12 D11 D10 CONTROL BYTE D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE DOUT Figure 9. Serial-Interface, 16-Bit, Write Timing Diagram 16 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 CS SCLK 1 DIN 0 RS4 RS3 RS2 RS1 RS0 x D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE CONTROL BYTE DOUT Figure 10. Serial-Interface, 8-Bit, Write Timing Diagram CS SCLK 1 DIN 1 RS4 RS3 RS2 RS1 RS0 x DATA BYTE CONTROL BYTE D15 D14 D13 D12 D11 D10 D9 DOUT D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 11. Serial-Interface, 16-Bit, Read Timing Diagram CS SCLK DIN 1 1 RS4 RS3 RS2 RS1 RS0 x DATA BYTE CONTROL BYTE DOUT D7 D6 D5 D4 D3 D2 D1 D0 Figure 12. Serial-Interface, 8-Bit, Read Timing Diagram ______________________________________________________________________________________ 17 MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Table 5. Register Address Table REGISTER N0. ADDRESS RS [4:0] 1 00000 2 00001 3 NAME WIDTH ACCESS Status register 8 Read only Control register 16 R/W 00010 Overrange register 16 R/W 4 00011 Underrange register 16 R/W 5 00100 LED segment-display register 1 16 R/W 6 00101 LED segment-display register 2 16 R/W 7 00110 LED segment-display register 3 8 R/W 8 00111 ADC custom offset register 16 R/W 9 01000 ADC result register 1 (16 MSBs) 16 Read only 10 01001 LED data register 16 R/W 11 01010 Peak register 16 Read only 12 10100 ADC result register 2 (4 LSBs) 8 Read only — All other addresses Reserved — — DVDD DVDD 6kΩ DOUT 6kΩ CLOAD 50pF DOUT CLOAD 50pF GND GND A) VOH TO HIGH-Z 6kΩ DOUT B) VOL TO HIGH-Z 6kΩ CLOAD 50pF DOUT GND GND B) HIGH-Z TO VOH AND VOL TO VOH CLOAD 50pF B) HIGH-Z TO VOL AND VOH TO VOL Figure 13. Load Circuits for Disable Time Figure 14. Load Circuits for Enable Time bits have been transferred (8 or 16). Once this has occurred, the MAX1497/MAX1499 wait for the next command byte. CS must not go high between data transfers. If CS is toggled before the end of a write or read operation, the device mode may be unknown. Clock in 32 zeros to clear the device state and reset the interface so it is ready to receive a new command byte. The second register is the 16-bit control register. This register sets the LED display controls, range modes, power-down modes, offset calibration, and the reset register function (CLR). The third register is the 16-bit overrange register, which sets the overrange limit of the analog input. The fourth register is the 16-bit underrange register, which sets the underrange limit of the analog input. Registers 5 through 7 contain the display data for the individual segments of the LED. The eighth register contains the custom offset value. The ninth register contains the 16 MSBs of the ADC conversion result. The 10th register contains the LED data. The 11th register contains the peak analog input value. The last register contains the lower four LSBs of the 20-bit ADC conversion result. On-Chip Registers The MAX1497/MAX1499 contain 12 on-chip registers. These registers configure the various functions of the device and allow independent reading of the ADC results and writing to the LED display. Table 5 lists the address and size of each register. The first of these registers is the status register. The 8bit status register contains the status flags for the ADC. 18 ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Command Byte (Write Only) MSB LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 START(1) R/W RS4 RS3 RS2 RS1 RS0 X START: Start bit. The first 1 clocked into the MAX1497/ MAX1499 is the first bit of the command byte. (R/W): Read/Write. Set this bit to 1 to read from the specified register. Set this bit to zero to write to the selected register. Note that certain registers are read only. Write commands to a read-only register are ignored. (RS4–RS0): Register address bits. RS4 to RS0 specify which register is accessed. X: Don’t care. Status Register (Read Only) MSB SIGN LSB OVER UNDER LOW_BATT Default values: 00h This register contains the status of the conversion results. SIGN: Latched negative-polarity indicator. Latches high when the result is negative. Clears by reading the status register, unless the condition remains true. OVER: Overrange bit. Latches high if an overrange condition occurs (the ADC result is larger than the value in the overrange register). Clears by reading the status register, unless the condition remains true. DRDY 0 0 0 value in the underrange register). Clears by reading the status register, unless the condition remains true. LOW_BATT: Low-battery bit. Latches high if the voltage at the LOWBATT is lower than 2.048V (typ). Clears by reading the status register, unless the condition remains true. For the MAX1497, LOWBATT is not used and the LOWBATT bit always returns to zero. DRDY: Data ready bit. Latches high to indicate a completed conversion result with valid data. Read the ADC result register to clear this bit. UNDER: Underrange bit. Latches high if an underrange condition occurs (the ADC result is less than the Control Register (Read/Write) MSB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 SPI/ADC EXTCLK INTREF DPON DPSET2 DPSET1 PD_DIG PD_ANA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HOLD PEAK RANGE CLR SEG_SEL OFFSET_CAL1 OFFSET_ CAL2 ENABLE LSB Default values: 0001h This register is the primary control register for the MAX1497/MAX1499. It is a 16-bit read/write register. It is used to indicate the desired clock and reference source. It sets the LED display controls, range modes, power-down modes, offset calibration, and the reset register function (CLR). ENABLE: (default = 1) LED driver enable bit. When set to 1, the MAX1497/MAX1499 enables the LED display drivers. A 0 in this location disables the LED display drivers. OFFSET_CAL2: (default = 0) Enhanced offset-calibration start bit (MAX1499, RANGE = 1). To achieve the lowest possible offset in the ±200mV input range, perform an enhanced offset calibration by setting this bit to ______________________________________________________________________________________ 19 MAX1497/MAX1499 Control and Status Registers MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface 1. The calibration takes about nine cycles (1800ms). After the calibration completes, set this bit to zero to resume ADC conversions. OFFSET_CAL1: (default = 0) Automatic offset calibration enable bit. When set to 1, the MAX1497/ MAX1499 disable automatic offset calibration. When this bit is set to zero, automatic offset calibration is enabled. SEG_SEL: (default = 0) SEG_SEL segment selection bit. When set to 1, the LED segment drivers use the LED segment registers to display individual segments that can form letters or numbers or other information on the display. The LED data register is not displayed. Send the data first to the LED segment-display registers and then set this bit high. CLR: (default = 0) Clear all registers bit. When set to 1, all registers reset to their power-on reset states after CS makes a low-to-high transition. RANGE: (default = 0) Input range select bit. When set to zero, the input voltage range is ±2V. When set to 1, the input voltage range is ±200mV. PEAK: (default = 0) Peak bit. When set to 1 (and the HOLD bit is set to zero), the LED shows the result stored in the peak register (see Table 6). HOLD: (default = 0) Hold bit. When set to 1, the LED register does not update from the ADC conversion results and holds the last result on the LED. The MAX1497/MAX1499 continue to perform conversions during HOLD (Table 1). PD_ANA: (default = 0) Power-down analog select bit. When set to 1, the analog circuits (analog modulator and ADC input buffers) go into the power-down mode. When set to zero, the device is in full power-up mode. PD_DIG: (default = 0) Power-down digital select bit. When set to 1, the digital circuits (digital filter and LED drivers) go into power-down mode. This also resets the values of the internal SRAM in the digital filter to zeros. When set to zero, the device returns to full power-up mode. When powering down PD_DIG, power down the LED segment drivers by clearing the ENABLE bit to zero. DPSET[2:1]: (default = 00) Decimal-point selection bits (Table 2 and 3). DPON: (default = 0) Decimal-point enable bit (Tables 2 and 3). INTREF: (default = 0) Reference select bit. For internal reference operation, set INTREF to 1. For external reference operation, set INTREF to zero. EXTCLK: (default = 0) External clock select bit. The EXTCLK bit controls selection of the internal clock or an external clock source. A 1 in this location selects the signal at the CLK input as the clock source. A zero in this location selects and powers up the internal clock oscillator. SPI/ADC: (default = 0) Display select bit. The SPI/ADC bit controls selection of the data fed into LED data register. A 1 in this location selects SPI/QSPI/ MICROWIRE data (user writes this data to the LED data register). A zero in this location selects the ADC result register data, unless hold or peak functions are active (Table 1). Note: When changing any one of the following control bits: OFFSET_CAL1, RANGE, PD_ANA, PD_DIG, INTREF, and EXTCLK, wait 800ms before reading the ADC results. Overrange Register (Read/Write) MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 7CF0h (for 3.5-digit, +1999) 4E1Fh (for 4.5-digit, +19,999) The overrange register is a 16-bit read/write register (D15 is the MSB). When the conversion result exceeds the value in the overrange register, the OVER bit in the status register latches to 1. The LED shows a 1 followed D7 D6 D5 D4 D3 D2 D1 D0 Default values: 20 by four dashes for the MAX1499 or a 1 followed by three dashes for the MAX1497 (Table 4). The data is represented in two’s complement format. ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MSB D15 LSB D14 D13 D12 D11 D10 D9 D8 8300h (for 3.5-digit, -2000) B1E0h (for 4.5-digit, -20,000) The underrange data register is 16-bit read/write register (D15 is the MSB). When the conversion result falls below the value in the underrange register, the UNDR bit in the status register sets to 1. The LED shows a -1 D7 D6 D5 D4 D3 D2 D1 D0 Default values: followed by four dashes for the MAX1499 or a -1 followed by three dashes for the MAX1497 (Table 4). The data is represented in two’s complement format. Default values: 0000h LED Segment-Display Register 1 (Read/Write) MSB Bit 15 Bit 14 Bit 13 Bit 1 Bit 11 Bit 10 Bit 9 Bit 8 A1 G1 D1 F1 E1 DP2 X B0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C0 A0 G0 D0 F0 E0 DP1 0 LSB LED segment-display register 1 is a 16-bit read/write register. When the LED bit (in the control register) is set to 1, the MAX1497/MAX1499 provide direct access to individual LED segments. The bits in the LED segmentdisplay register determine if a segment is on or off. Write a zero to turn on a segment and a 1 to turn off a segment. DP1: Segment DP driver bit of digit 1. The default value turns on the LED segment. E0: Segment E driver bit of digit 0. The default value turns on the LED segment. F0: Segment F driver bit of digit 0. The default value turns on the LED segment. D0: Segment D driver bit of digit 0. The default value turns on the LED segment. G0: Segment G driver bit of digit 0. The default value turns on the LED segment. A0: Segment A driver bit of digit 0. The default value turns on the LED segment. C0: Segment C driver bit of digit 0. The default value turns on the LED segment. B0: Segment B driver bit of digit 0. The default value turns on the LED segment. X: Don’t care. DP2: Segment DP driver bit of digit 2. The default value turns on the LED segment. E1: Segment E driver bit of digit 1. The default value turns on the LED segment. F1: Segment F driver bit of digit 1. The default value turns on the LED segment. D1: Segment D driver bit of digit 1. The default value turns on the LED segment. G1: Segment G driver bit of digit 1. The default value turns on the LED segment. A1: Segment A driver bit of digit 1. The default value turns on the LED segment. ______________________________________________________________________________________ 21 MAX1497/MAX1499 Underrange Register (Read/Write) MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface LED Segment-Display Register 2 (Read/Write) MSB Bit 15 Bit 14 Bit 13 Bit 1 Bit 11 Bit 10 Bit 9 Bit 8 F3 E3 DP4 MINUS B2 C2 A2 G2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D2 F2 E2 DP3 X B1 C1 0 LSB Default values: 0000h LED segment-display register 2 is a 16-bit read/write register. When the SEG_SEL bit (in the control register) is set to 1, the MAX1497/MAX1499 provide direct access to individual LED segments. The bits in the LED segment-display register determine if a segment is on or off. Write a zero to turn on a segment and a 1 to turn off a segment. C1: Segment C driver bit of digit 1. The default value turns on the LED segment. B1: Segment B driver bit of digit 1. The default value turns on the LED segment. MINUS: Segment minus driver bit. The default value turns on the LED minus segment. Setting this bit to 1 enables the plus sign on the LED display. DP3: Segment DP driver bit of digit 3. The default value turns on the LED segment. E2: Segment E driver bit of digit 2. The default value turns on the LED segment. F2: Segment F driver bit of digit 2. The default value turns on the LED segment. D2: Segment D driver bit of digit 2. The default value turns on the LED segment. G2: Segment G driver bit of digit 2. The default value turns on the LED segment. A2: Segment A driver bit of digit 2. The default value turns on the LED segment. C2: Segment C driver bit of digit 2. The default value turns on the LED segment. B2: Segment B driver bit of digit 2. The default value turns on the LED segment. DP4: Segment DP driver bit of digit 4. The default value turns on the LED segment (MAX1499 only). E3: Segment E driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). F3: Segment F driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). LED Segment-Display Register 3 (Read/Write) MSB LSB X X BC_ B3 C3 A3 G3 D3 Default values: 00h LED segment-display register 3 is an 8-bit read/write register. When the SEG_SEL bit (in the control register) is set to 1, the MAX1497/MAX1499 provide direct access to individual LED segments. The bits in the LED segment-display register determine if a segment is on or off. Write a zero to turn on a segment and a 1 to turn off a segment. D3: Segment D driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). G3: Segment G driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). 22 A3: Segment A driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). C3: Segment C driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). B3: Segment B driver bit of digit 3. The default value turns on the LED segment (MAX1499 only). BC_: Segment B and C driver bit of digit 3 (3.5 digits) or Digit 4 (4.5 digits). The default value turns on the LED segment. X: Don’t care. ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 Default values: 0000h In addition to automatic offset calibration, the MAX1497/MAX1499 offer a user-defined custom offset 16-bit read/write register. The final result of the ADC conversion is the input after autocalibration minus D7 D6 D5 D4 D3 D2 D1 D0 the value in the custom offset. The custom offset value is stored in this register. D15 is the MSB. The data is represented in two’s complement format. ADC Result Register 1 (Read Only) LSB (MAX1497) MSB D15 D14 D13 D12 D11 D10 D9 D8 Default values: 0000h ADC result register 1 is a 16-bit read-only register. This register stores the 16 MSBs of the ADC result. The data is represented in two’s complement format. D7 D6 D5 D4 LSB (MAX1499) D3 D2 D1 D0 For the MAX1499, the data is 16-bit and D15 is the MSB. For the MAX1497, the data is 12-bit, D15 is the MSB, and D4 is the LSB. ADC Result Register 2 (Read Only) MSB LSB D3 D2 D1 D0 0 Default values: 00h ADC result register 2 is an 8-bit read-only register. This register stores the 4 LSBs of the ADC result. 0 0 0 Use this result with the result in ADC result-register 1 to form a 20-bit two’s complement conversion result. LED Data Register (Read/Write) LSB (MAX1497) MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 LSB (MAX1499) D3 D2 D1 D0 Default values: 0000h The LED data register is a 16-bit read/write register. This register updates from ADC result register 1 or from the serial interface by selecting the SPI/ADC bit in the control register. The data is represented in two’s complement format. For the MAX1499, the data is 16-bit and D15 is the MSB. For the MAX1497, the data is 12-bit, D15 is the MSB, and D4 is the LSB, followed by 4 trailing sub-bits. ______________________________________________________________________________________ 23 MAX1497/MAX1499 ADC Custom Offset-Calibration Register (Read/Write) MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface PEAK Register (Read Only) LSB (MAX1497) MSB D15 D14 D13 D12 D11 D10 D9 D8 Default values: B1E0h The peak data register is a 16-bit read only register. Set the PEAK bit to 1 to enable the PEAK function. This register stores the peak value of the ADC conversion result. First, the current ADC result is saved to the PEAK register, then the new ADC conversion result is compared to this value. If the new value is larger than the value in the peak register, the MAX1497/MAX1499 save the new value to the peak register. If the new 24 D7 D6 D5 D4 LSB (MAX1499) D3 D2 D1 D0 value is less than the value in the peak register, the value in the peak register remains unchanged. Set the PEAK bit to zero to clear the value in the PEAK register. The data is represented in two’s complement format. For the MAX1499, the data is 16-bit and D15 is the MSB. For the MAX1497, the data is 12-bit, D15 is the MSB, and D4 is the LSB followed by 4 trailing sub-bits. ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 ANALOG SUPPLY FERRITE BEAD 0.1µF TEMP SENSOR 4.7µF 0.1µF 4.7µF AVDD DVDD THERMOCOUPLE JUNCTION REF+ 0.1µF AIN+ RREF REF- +5V SCLK AIN+ DIN AIN- DUMMY GAUGE µC AIN- R 0.1µF SPI MAX1497 MAX1499 0.1µF ACTIVE GAUGE MAX1497 MAX1499 DOUT 0.1µF 0.1µF +2.048V REF+ MAX6062 REF- CS R GND EOC GND 0.47µF Figure 15. Strain-Gauge Application with the MAX1497/MAX1499 Power-On Reset At power-on, the serial interface, logic LED drivers, digital filter, and modulator circuits reset. The registers return to their default values. Allow time for the reference to settle before starting calibration. Offset Calibration The MAX1497/MAX1499 offer on-chip offset calibration. The device offset calibrates during every conversion when the OFFSET_CAL1 bit is zero in the control register. Enhanced offset calibration is only needed in the MAX1499 when the RANGE bit = 1. It is performed on demand by setting the OFFSET_CAL2 bit to 1. Enhanced Offset Calibration Enhanced offset calibration is a more accurate calibration method that is needed in the case of the ±200mV range and 4.5-digit resolution. The MAX1499 performs the enhanced calibration on demand by setting the OFFSET_CAL2 bit to 1. Power-Down Modes The MAX1497/MAX1499 feature independent powerdown control of the analog and digital LED drivers circuitry. Writing a 1 to the PD_DIG and PD_ANA bits in the control word, powers down the analog and digital circuitry, reducing the supply current to 268µA (typ). PD_DIG powers down the digital filter, while PD_ANA Figure 16. Thermocouple Application with the MAX1497/MAX1499 powers down the analog modulator and ADC input buffers. Writing a zero to the ENABLE bit in the control word, powers down the LED drivers. Peak The MAX1497/MAX1499 feature peak detection circuitry. When activated (PEAK bit = 1), the devices display only the highest voltage measured to the LED. Hold The MAX1497/MAX1499 feature data-hold circuitry. When activated (HOLD bit = 1), the device displays the current reading on the LED. Low Battery The MAX1499 features a low-battery detection input. When the voltage at LOWBATT drops below 2.048V (typ), the LOWBATT bit of the status register goes high. Strain-Gauge Measurement Connect the differential inputs of the MAX1497/MAX1499 to the bridge network of the strain gauge. In Figure 15, the analog supply voltage powers the bridge network and the MAX1497/MAX1499 along with the reference voltage. The MAX1497/MAX1499 handle an analog input voltage range of ±200mV and ±2V full scale. The analog/reference inputs of the parts allow the analog input range to have an absolute value of anywhere between -2.2V and +2.2V. ______________________________________________________________________________________ 25 MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface ADC RESULT LED ADC RESULT LED 1---- >4E1Fh 1---- 4E1Fh 19,999 4E1Fh 19,999 4E1Fh 2 1 0002h 0002h 0001h 2 1 0 0000h 0 0000h -0 FFFFh -0 FFFFh -1 FFFEh -1 FFFEh -2 FFFDh -2 FFFDh -19,999 B1E0h -19,999 B1E0h -1---- <B1E0h -1---- <B1E0h -2V -100µV 0 100µV 00001h -200mV +2V ADC RESULT LED ADC RESULT 1--- 7CFh 1--- >7CFh 1999 7CFh 1999 7CFh 2 1 002h 2 1 002h 001h 0 000h 0 000h -0 FFFh -0 FFFh -1 FFEh -1 FFEh -2 FFDh -2 FFDh -1999 830h -1999 830h -1--- <830h -1--- <830h -200mV -100µV 0 100µV +200mV Figure 18. MAX1499 Transfer Function, ±200mV Range Figure 17. MAX1499 Transfer Function, ±2V Range LED -10µV 0 10µV ANALOG INPUT VOLTAGE ANALOG INPUT VOLTAGE +200mV ANALOG INPUT VOLTAGE Figure 19. MAX1497 Transfer Function, ±200mV Range 001h -2V -1mV 0 1mV +2V ANALOG INPUT VOLTAGE Figure 20. MAX1497 Transfer Function, ±2V Range Thermocouple Measurement Transfer Functions Figure 16 shows a connection from a thermocouple to the MAX1497/MAX1499. In this application, the MAX1497/MAX1499 take advantage of the on-chip input buffers that allow large source impedances on the front end. The decoupling capacitors reduce noise pickup from the thermocouple leads. To place the differential voltage from the thermocouple at a suitable common-mode voltage, the AIN- input of the MAX1497/ MAX1499 is biased to GND. Use an external temperature sensor, such as the DS75, and a µC to perform cold-junction temperature compensation. Figures 17–20 show the transfer functions of the MAX1497/MAX1499. The output data is stored in the ADC data register in two’s complement. The transfer function for the MAX1499 with AIN+ - AIN≥ 0, RANGE = 0 is: 26 V −V COUNTS = 1.024 AIN+ AIN− × 20,000 VREF + − VREF − ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface V −V COUNTS = 1.024 AIN+ AIN− × 20,000 + 1 V V − REF + REF − The transfer function for the MAX1497 with AIN+ - AIN≥ 0, RANGE = 0 is: V −V COUNTS = 1.024 AIN+ AIN− × 2000 VREF+ − VREF− The transfer function for the MAX1497 with AIN+ - AIN< 0, RANGE = 0 is: V −V COUNTS = 1.024 AIN+ AIN− × 2000 + 1 VREF + − VREF − The transfer function for the MAX1499 with AIN+ - AIN≥ 0, RANGE = 1 is: V −V COUNTS = 1.024 AIN+ AIN− × 20,000 × 10 VREF + − VREF − The transfer function for the MAX1499 with AIN+ - AIN< 0, RANGE = 1 is: V −V COUNTS = 1.024 AIN+ AIN− × 20,000 × 10 + 1 VREF + − VREF − The transfer function for the MAX1497 with AIN+ - AIN≥ 0, RANGE = 1 is: V −V COUNTS = 1.024 AIN+ AIN− × 2000 × 10 VREF+ − VREF− The transfer function for the MAX1497 with AIN+ - AIN< 0, RANGE = 1 is: V −V COUNTS = 1.024 AIN+ AIN− × 2000 × 10 + 1 VREF + − VREF − Table 6. Segment Current Selection RISET (kΩ) ISEG (mA) 25 20 50 10 100 5 500 1 >2500 LED driver disabled Supplies, Layout, and Bypassing Power up AVDD and DVDD (MAX1499) and VDD (MAX1497) before applying an analog input and external reference voltage to the device. If this is not possible, limit the current into these inputs to 50mA. When the analog and digital supplies come from the same source, isolate the digital supply from the analog supply with a low-value resistor (10Ω) or ferrite bead. For best performance, ground the MAX1497/MAX1499 to the analog ground plane of the circuit board. Avoid running digital lines under the device, because they may couple noise onto the die. Run the analog ground plane under the MAX1497/MAX1499 to minimize coupling of digital noise. Make the power-supply lines to the MAX1497/MAX1499 as wide as possible to provide low-impedance paths and reduce the effects of glitches on the power-supply line. Shield fast-switching signals, such as clocks, with digital ground to avoid radiating noise to other sections of the board. Avoid running clock signals near the analog inputs. Avoid crossover of digital and analog signals. Running traces that are on opposite sides of the board at right angles to each other reduces feedthrough effects. A microstrip technique is best, but is not always possible with double-sided boards. With this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is important when using high-resolution ADCs. Decouple the supplies with 0.1µF ceramic capacitors to GND. Place these components as close to the device as possible to achieve the best decoupling. Segment-Current Selection A resistor from ISET to ground sets the current for each LED segment. See Table 6 for more detail. Use the following formula to set the segment current: 1.25V ISEG = × 400 RISET RISET values below 25kΩ increase the ISEG. However, the internal current-limit circuit limits the ISEG to less than 30mA. At higher ISEG values, the proper operation of the device is not guaranteed. In addition, the power dissipated may exceed the package power dissipation limit. ______________________________________________________________________________________ 27 MAX1497/MAX1499 The transfer function for the MAX1499 with AIN+ - AIN< 0, RANGE = 0 is: MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface Choosing Supply Voltage to Minimize Power Dissipation The MAX1497/MAX1499 drive a peak current of 25.5mA into LEDs with a 2.2V forward-voltage drop when operated from a supply voltage of at least 3.0V. Therefore, the minimum voltage drop across the internal LED drivers is (3.0V - 2.2V) = 0.8V. The MAX1497/ MAX1499 sink (8 x 25.5mA = 204mA) when the outputs are operating and LED segment drivers are at full current. For a 3.3V supply, the MAX1497/MAX1499 dissipate (3.3V - 2.2V) x 204 = 224.4mW. If a higher supply voltage is used, the driver absorbs a higher voltage, and the driver’s power dissipation increases accordingly. However, if the LEDs used have a higher forward voltage drop than 2.2V, the supply voltage must be raised accordingly to ensure that the driver always has at least 0.8V headroom. For a VLED supply voltage of 2.7V, the maximum LED forward voltage is 1.9V to ensure 0.8V driver headroom. The voltage drop across the drivers with a nominal +5V supply (5.0V - 2.2V = 2.8V) is almost three times the drop across the drivers with a nominal 3.3V supply (3.3V - 2.2V = 1.1V). Therefore, the driver’s power dissipation increases three times. The power dissipation in the part causes the junction temperature to rise accordingly. In the high ambient temperature case, the total junction temperature may be very high (>+125°C). At higher junction temperatures, the ADC performance degrades. To ensure the dissipation limit for the MAX1497/MAX1499 is not exceeded and the ADC performance is not degraded, a diode can be inserted between the power supply and VLED. Computing Power Dissipation The following can be used to compute power dissipation: PD = (VLED x IVLED ) + (VLED - VDIODE) (DUTY x ISEG x N) + VSUPPLY x ISUPPLY VLED = LED driver supply voltage IVLED = VLED bias current VDIODE = LED forward voltage DUTY = segment ON time during each digit ON time ISEG = segment current set by RISET N = number of segments driven (worst case is eight) VSUPPLY = supply voltage of the part ISUPPLY = supply current from VDD for the MAX1497 or AVDD + DVDD for the MAX1499 28 Dissipation Example For ISEG = 25.5mA, N = 8, DUTY = 127 / 128, VDIODE = 1.5V at 25.5mA, VLED = VSUPPLY = 5.25V: PD = (5.25 x 2mA) + (5.25V - 1.5) [(127 / 128) x 25.5mA x 8)] + 5.25 x 1.080mA PD = 0.7751W 28-Pin SSOP Package Example For the 28-pin SSOP package (TJA = 1 / 0.009496 = +105.3°C/W), the maximum allowed ambient temperature TA is given by: TJ (max) = TA + (PD x TJA) = +125°C = TA + (0.7751W x +105.3°C/W) TA = +43°C Thus, the device cannot operate safely at a maximum package temperature of +85°C. The power dissipates in the part need to be lowered. (PD x TJA) max = (+125°C) - (+85°C) = +40°C PD (max) = +40°C /+105.3°C/W = 380mW (VLED - VDIODE) = [380mW - (5.25V x 2mA) - 5.25V x 1.080mA] / [(127 / 128) x 25.5mA x 8] VLED - VDIODE = 1.854V VLED - VDIODE should have the following condition to ensure it operates safely: 0.8V < VLED - VDIODE < 2.08V 28-Pin PDIP Package Example PD x TJA (max) = (+125°C) - (+85°C) = +40°C PD (max) = +40°C /+70°C/W = 571mW VLED - VDIODE = [571mW - (5.25V x 2mA) - 5.25V x 1.080mA] / [(127 / 128) x 25.5mA x 8] VLED - VDIODE = 2.80V For a 28-pin PDIP package, VLED - V DIODE should have the following condition to ensure it operates safely: 0.8V < VLED - VDIODE < 3.18V 32-Pin TQFP Package The MAX1499 TQFP package can operate safely for all supply voltages provided VDIODE > 1.5V. ______________________________________________________________________________________ 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface INL Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line is either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1497/ MAX1499 is measured using the endpoint method. DNL Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of ±1 LSB. A DNL error specification of less than ±1 LSB guarantees no missing codes and a monotonic transfer function. Rollover Error Rollover error is defined as the absolute-value difference between a near positive full-scale reading and near negative full-scale reading. Rollover error is tested by applying a full-scale positive voltage, swapping AIN+ and AIN-, and adding the results. Zero Input Reading Ideally, with AIN+ connected to AIN-, the MAX1497/ MAX1499 digital ADC result is 0000h. Zero input reading is the measured deviation from the ideal 0x0000 and the actual measured point. Gain Error Gain error is the amount of deviation between the measured full-scale transition point and the ideal full-scale transition point. Common-Mode Rejection Common-mode rejection (CMR) is the ability of a device to reject a signal that is common to both input terminals. The common-mode signal can be either an AC or a DC signal or a combination of the two. CMR is often expressed in decibels. Normal-Mode 50Hz and 60Hz Rejection (Simultaneously) Normal-mode rejection is a measure of how much output changes when a 50Hz and a 60Hz signal is injected into only one of the differential inputs. The MAX1497/ MAX1499 sigma-delta converter uses its internal digital filter to provide normal-mode rejection to both 50Hz and 60Hz power-line frequencies simultaneously. Power-Supply Rejection Ratio Power-supply rejection ratio (PSRR) is the ratio of the input supply change (in volts) to the change in the converter output (in volts). It is typically measured in decibels. Pin Configurations ISET 6 MAX1497 23 SEGD GND 7 22 SEGC VDD 8 21 SEGB CLK 9 20 SEGA EOC 10 19 DIG3 CS 11 18 DIG2 DIN 12 17 GLED SCLK 13 16 DIG1 DOUT 14 15 DIG0 SSOP/PDIP LOWBATT LED_EN SEGDP SEGG SEGF VLED 27 26 25 REF+ 1 24 SEGE AIN+ 2 23 SEGD AIN- 3 22 SEGC ISET 4 GND 5 AVDD 6 19 DIG4 DVDD 7 18 DIG3 CLK 8 17 DIG2 21 SEGB MAX1499 9 10 11 20 SEGA 12 13 14 15 16 GLED 24 SEGE 28 DIG1 AIN- 5 29 DIG0 25 VLED 30 DOUT AIN+ 4 31 SCLK 26 SEGF VNEG REF+ 3 32 CS 27 SEGG DIN 28 SEGDP REF- 2 EOC VNEG 1 REF- TOP VIEW TOP VIEW TQFP Chip Information TRANSISTOR COUNT: 80,000 PROCESS: BiCMOS ______________________________________________________________________________________ 29 MAX1497/MAX1499 Definitions 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface MAX1497/MAX1499 Typical Operating Circuits VIN DIG0–DIG3 DIGIT CONNECTIONS SEGA–SEGDP SEGMENT CONNECTIONS AIN+ AIN- CLK SCLK 10µF CS MAX1497 VDD DIN 0.1µF µC DOUT VLED EOC 2.7V TO 5.25V ISET VNEG GND REF- REF+ 0.1µF GLED 4.7µF 25kΩ AIN+ VIN AINLOWBATT VLED DIG0–DIG4 DIGIT CONNECTIONS SEGA–SEGDP SEGMENT CONNECTIONS CLK SCLK CS MAX1499 DVDD DIN 0.1µF 10µF DOUT EOC AVDD 0.1µF ISET LISO VNEG GND 0.1µF REF- REF+ GLED 4.7µF 25kΩ 2.7V TO 5.25V 30 10µF ______________________________________________________________________________________ µC 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface 32L/48L,TQFP.EPS ______________________________________________________________________________________ 31 MAX1497/MAX1499 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 2 SSOP.EPS MAX1497/MAX1499 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface 1 INCHES E H MILLIMETERS DIM MIN MAX MIN MAX A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 B 0.010 0.015 0.25 0.38 C D 0.20 0.09 0.004 0.008 SEE VARIATIONS E 0.205 e 0.212 0.0256 BSC 5.20 MILLIMETERS INCHES D D D D D 5.38 MIN MAX MIN MAX 0.239 0.239 0.278 0.249 0.249 0.289 6.07 6.07 7.07 6.33 6.33 7.33 0.317 0.397 0.328 0.407 8.07 10.07 8.33 10.33 N 14L 16L 20L 24L 28L 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.025 0∞ 0.037 8∞ 0.63 0∞ 0.95 8∞ N A C B e A1 L D NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. 32 PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL DOCUMENT CONTROL NO. 21-0056 ______________________________________________________________________________________ REV. C 1 1 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and µC Interface DIM A A1 A2 A3 B B1 C D1 E E1 e eA eB L 1 TOP VIEW E D A E1 A3 A1 A2 e MILLIMETERS MAX MIN 5.08 0.39 3.18 4.45 2.03 1.40 0.51 0.41 1.65 1.14 0.21 0.30 0.13 0.22 15.24 15.87 13.34 14.61 2.54 BSC 15.24 BSC 3.05 17.78 3.81 VARIATIONS: INCHES 0∞-15∞ L INCHES MAX MIN 0.200 0.015 0.125 0.175 0.080 0.055 0.020 0.016 0.065 0.045 0.012 0.008 0.009 0.005 0.625 0.600 0.525 0.575 0.100 BSC 0.600 BSC 0.700 0.120 0.150 PDIPW.EPS D1 N C B1 B eA eB FRONT VIEW MILLIMETERS DIM D MIN 1.230 MAX 1.270 MIN 31.24 MAX 32.26 N MS011 24 AA D D 1.430 2.025 1.470 2.075 36.32 51.44 37.34 52.71 28 40 AB AC SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, .600" PDIP APPROVAL DOCUMENT CONTROL NO. 21-0044 REV. B 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1497/MAX1499 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)