19-2079; Rev 2; 4/09 Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers Features The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduced at five differential outputs. The differential inputs can be adapted to accept single-ended inputs by connecting the on-chip VBB supply to one input as a reference voltage. o +2.25V to +3.8V Differential HSTL/LVPECL Operation The MAX9312/MAX9314 feature low part-to-part skew (30ps) and output-to-output skew (12ps), making them ideal for clock and data distribution across a backplane or a board. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. The MAX9312 features an on-chip VBB reference output of 1.425V below the positive supply voltage. The MAX9314 offers an on-chip VBB reference output of 1.32V below the positive supply voltage. Both devices are offered in an industry-standard 32-pin 7mm x 7mm LQFP package. In addition, the MAX9312 is offered in a space-saving 32-pin 5mm x 5mm TQFN package. o 312ps (typ) Propagation Delay o -2.25V to -3.8V Differential LVECL Operation o 30ps (typ) Part-to-Part Skew o 12ps (typ) Output-to-Output Skew o ≥ 300mV Differential Output at 3GHz o On-Chip Reference for Single-Ended Inputs o Output Low with Open Input o Pin Compatible with MC100LVEP210 (MAX9312) and MC100EP210 (MAX9314) o Offered in Tiny QFN* Package (70% Smaller Footprint than LQFP) Ordering Information PART Applications TEMP RANGE PIN-PACKAGE MAX9312ECJ+ -40°C to +85°C 32 LQFP MAX9312ETJ+ -40°C to +85°C 32 TQFN-EP* MAX9314ECJ -40°C to +85°C 32 LQFP *Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package. Precision Clock Distribution Low-Jitter Data Repeater Functional Diagram QB0 QA0 VCC VCC QA1 75kΩ QA1 CLKA QA2 CLKA QA2 75kΩ 75kΩ QB1 75kΩ QB1 CLKB QB2 CLKB QB2 75kΩ 75kΩ QB3 QA3 VEE QB0 QA0 VEE VBB QA3 VEE VEE QB3 QA4 QB4 QA4 QB4 Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX9312/MAX9314 General Description MAX9312/MAX9314 Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers ABSOLUTE MAXIMUM RATINGS VCC - VEE...............................................................................4.1V Inputs (CLK_, CLK_) .............................VEE - 0.3V to VCC + 0.3V CLK_ to CLK_ ....................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................±0.65mA Continuous Power Dissipation (TA = +70°C) 32-Pin LQFP (derate 20.7mW/°C above +70°C) ....1652.9mW 32-Pin TQFN (derate 34.5mW/°C above +70°C)....2758.6mW Junction-to-Case Thermal Resistance (TJC) (Note A) 32-Pin LQFP ................................................................12°C/W 32-Pin TQFN ..................................................................2°C/W Junction-to-Ambient Thermal Resistance (TJA) (Note 1) 32-Pin LQFP .............................................................48.4°C/W 32-Pin TQFN ................................................................29°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Protection Human Body Model (CLK_, CLK_, Q_, Q_) ........................2kV Soldering Temperature (10s) ...........................................+300°C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC - VEE = +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC - 2V.) (Notes 2–5) PARAMETER SYMBOL CONDITIONS -40°C MIN +25°C MAX MIN +85°C MAX MIN MAX UNITS INPUTS (CLK_, CLK_) Single-Ended Input High Voltage Single-Ended Input Low Voltage VIH VIL VBB connected MAX9312 to CLK_ (VIL for VBB connected MAX9314 to CLK_) VBB connected MAX9312 to CLK_ (VIL for VBB connected MAX9314 to CLK_) VCC 1.23 VCC VCC 1.23 VCC VCC 1.23 VCC 1.165 VCC VCC 1.165 VCC VCC 1.165 VCC VEE VCC 1.62 VEE VCC 1.62 VEE VCC 1.62 VCC V V VEE VCC 1.475 VEE VCC 1.475 VEE VCC 1.475 High Voltage of Differential Input VIHD VEE + 1.2 VCC VEE + 1.2 VCC VEE + 1.2 VCC V Low Voltage of Differential Input VILD VEE VCC 0.095 VEE VCC 0.095 VEE VCC 0.095 V Differential Input Voltage VIHD VILD For VCC - VEE < 3.0V 0.095 VCC VEE 0.095 VCC VEE 0.095 VCC VEE For VCC - VEE ≥ 3.0V 0.095 3.0 0.095 3.0 0.095 3.0 Input High Current CLK_ Input Low Current 2 150 IIH IILCLK -10 +10 150 -10 +10 -10 _______________________________________________________________________________________ V 150 µA +10 µA Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9312/MAX9314 DC ELECTRICAL CHARACTERISTICS (continued) (VCC - VEE = +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC - 2V.) (Notes 2–5) PARAMETER CLK_ Input Low Current SYMBOL CONDITIONS IILCLK -40°C MIN +25°C MAX -150 MIN +85°C MAX -150 MIN MAX -150 UNITS µA OUTPUTS (Q__, Q__) Single-Ended Output High Voltage VOH Figure 1 VCC 1.025 VCC 0.900 VCC 1.025 VCC 0.900 VCC 1.025 VCC 0.900 V Single-Ended Output Low Voltage VOL Figure 1 VCC -1.930 VCC 1.695 VCC -1.930 VCC 1.695 VCC -1.930 VCC 1.695 V VOH VOL Figure 1 670 950 670 950 670 950 mV MAX9312 VCC 1.525 VCC 1.325 VCC 1.525 VCC 1.325 VCC 1.525 VCC 1.325 MAX9314 VCC 1.38 VCC 1.26 VCC 1.38 VCC 1.26 VCC 1.38 VCC 1.26 Differential Output Voltage REFERENCE (VBB) Reference Voltage Output (Note 6) POWER SUPPLY Supply Current (Note 7) VBB IEE IBB = ±0.5mA V 75 82 95 mA _______________________________________________________________________________________ 3 MAX9312/MAX9314 Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers AC ELECTRICAL CHARACTERISTICS (VCC - VEE = +2.25V to +3.8V, outputs loaded with 50Ω ±1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE, unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Note 8) PARAMETER SYMBOL CONDITIONS -40°C +25°C +85°C UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX 220 321 380 220 312 410 260 322 400 ps Differential Inputto-Output Delay tPLHD, tPHLD Output-to-Output Skew (Note 9) tSKOO 12 46 12 46 10 35 ps Part-to-Part Skew (Note 10) tSKPP 30 160 30 190 30 140 ps fIN = 1.5GHz clock pattern 1.2 2.5 1.2 2.5 1.2 2.5 fIN = 3.0GHz clock pattern 1.2 2.6 1.2 2.6 1.2 2.6 3Gbps, 223 -1 PRBS pattern 80 95 80 95 80 95 VOH - VOL ≥ 300mV, clock pattern, Figure 2 3.0 Added Random Jitter (Note 11) tRJ Added Deterministic Jitter (Note 11) tDJ Switching Frequency Output Rise/Fall Time (20% to 80%) fMAX tR, tF Figure 2 3.0 ps (RMS) ps (pk-pk) 3.0 GHz VOH - VOL ≥ 500mV, clock pattern, Figure 2 1.5 Figure 2 100 1.5 112 140 100 1.5 116 140 100 121 140 ps Note 2: Measurements are made with the device in thermal equilibrium. Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 4: Single-ended input operation using VBB is limited to VCC - VEE = 3.0V to 3.8V for the MAX9312 and VCC - VEE = 2.7V to 3.8V for the MAX9314. Note 5: DC parameters production tested at TA = +25°C. Guaranteed by design and characterization over the full operating temperature range. Note 6: Use VBB only for inputs that are on the same device as the VBB reference. Note 7: All pins open except VCC and VEE. Note 8: Guaranteed by design and characterization limits are set at ±6 sigma. Note 9: Measured between outputs on the same part at the signal crossing points for a same-edge transition. Note 10: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 11: Device jitter added to the input signal. 4 _______________________________________________________________________________________ Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY 60 MAX9312 toc02 0.7 tR 125 0.6 0.5 0.4 0.3 35 60 85 0 1000 TEMPERATURE (°C) 2000 35 60 85 PROPAGATION DELAY vs. TEMPERATURE 340 VIHD = VCC - 0.95V VILD = VCC - 1.1V PROPAGATION DELAY (ps) 302 10 TEMPERATURE (°C) MAX9312 toc04 VIHD -VILD = 150mV tPLHD 298 296 294 tPHLD 292 -15 FREQUENCY (MHz) 304 300 -40 3000 PROPAGATION DELAY vs. SINGLE-ENDED HIGH VOLTAGE OF DIFFERENTIAL INPUT (VIHD) 306 105 90 0 10 tF 110 95 0.1 -15 115 100 0.2 55 50 -40 120 MAX9312 toc05 65 130 TRANSITION TIME (ps) OUTPUT AMPLITUDE (V) 0.8 70 PROPAGATION DELAY (ps) SUPPLY CURRENT (mA) 75 TRANSITION TIME vs. TEMPERATURE 0.9 MAX9312 toc01 80 MAX9312 toc03 SUPPLY CURRENT, IEE vs. TEMPERATURE 320 tPLHD 300 tPHLD 290 280 288 1.0 1.4 1.8 2.2 2.6 VIHD (V) 3.0 3.4 3.8 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX9312/MAX9314 Typical Operating Characteristics (VCC = +3.3V, VEE = 0, VIHD = VCC - 0.95V, VILD = VCL - 1.25V, input transition time = 125ps (20% to 80%), fIN = 1.5GHz, outputs loaded with 50Ω to VCC - 2V, TA = +25°C, unless otherwise noted.) Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9312/MAX9314 Pin Description 6 PIN NAME FUNCTION 1, 9, 16, 25, 32 VCC Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 N.C. No Connection. Internally not connected. 3 CLKA Noninverting Differential Clock Input A 4 CLKA Inverting Differential Clock Input A 5 VBB 6 CLKB Noninverting Differential Clock Input B 7 CLKB Inverting Differential Clock Input B 8 VEE Negative Supply Voltage 10 QB4 Inverting QB4 Output. Typically terminate with 50Ω resistor to VCC - 2V. 11 QB4 Noninverting QB4 Output. Typically terminate with 50Ω resistor to VCC - 2V. 12 QB3 Inverting QB3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 13 QB3 Noninverting QB3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 14 QB2 Inverting QB2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 15 QB2 Noninverting QB2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 17 QB1 Inverting QB1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 18 QB1 Noninverting QB1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 19 QB0 Inverting QB0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 20 QB0 Noninverting QB0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 21 QA4 Inverting QA4 Output. Typically terminate with 50Ω resistor to VCC - 2V. 22 QA4 Noninverting QA4 Output. Typically terminate with 50Ω resistor to VCC - 2V. 23 QA3 Inverting QA3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 24 QA3 Noninverting QA3 Output. Typically terminate with 50Ω resistor to VCC - 2V. 26 QA2 Inverting QA2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 27 QA2 Noninverting QA2 Output. Typically terminate with 50Ω resistor to VCC - 2V. 28 QA1 Inverting QA1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 29 QA1 Noninverting QA1 Output. Typically terminate with 50Ω resistor to VCC - 2V. 30 QA0 Inverting QA0 Output. Typically terminate with 50Ω resistor to VCC - 2V. 31 QA0 Noninverting QA0 Output. Typically terminate with 50Ω resistor to VCC - 2V. — EP Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass to VCC with a 0.01µF ceramic capacitor. Exposed Pad (TQFN package only). Internally connected to VEE. Connect EP to the VEE pad on the PCB. _______________________________________________________________________________________ Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers The MAX9312/MAX9314 are low-skew, dual 1-to-5 differential drivers designed for clock and data distribution. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. The differential inputs can be configured to accept single-ended inputs when operating at approximately VCC VEE = 3.0V to 3.8V for the MAX9312 or VCC - VEE = 2.7V to 3.8V for the MAX9314. This is accomplished by connecting the on-chip reference voltage, VBB, to an input as a reference. For example, the differential CLKA, CLKA input is converted to a noninverting, single-ended input by connecting VBB to CLKA and connecting the singleended input to CLKA. Similarly, an inverting input is obtained by connecting VBB to CLKA and connecting the single-ended input to CLKA. With a differential input configured as single ended (using VBB), the singleended input can be driven to VCC and VEE or with a single-ended LVPECL/LVECL signal. When a differential input is configured as a single-ended input (using VBB), the approximate supply range is VCC VEE = 3.0V to 3.8V for the MAX9312 and VCC - VEE = 2.7V to 3.8V for the MAX9314. This is because one of the inputs must be VEE + 1.2V or higher for proper operation of the input stage. VBB must be at least VEE + 1.2V because it becomes the high-level input when the other (single-ended) input swings below it. Therefore, minimum VBB = VEE + 1.2V. The minimum V BB output for the MAX9312 is V CC 1.525V and the minimum VBB output for the MAX9314 is VCC - 1.38V. Substituting the minimum VBB output for each device into VBB = VEE + 1.2V results in a minimum supply of 2.725V for the MAX9312 and 2.58V for the MAX9314. Rounding up to standard supplies gives the single-ended operating supply ranges of VCC - VEE = 3.0V to 3.8V for the MAX9312 and VCC - VEE = 2.7V to 3.8V for the MAX9314. When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC. If the VBB reference is not used, it can be left open. The VBB reference can source or sink 0.5mA, which is sufficient to drive two inputs. Use VBB only for inputs that are on the same device as the VBB reference. The maximum magnitude of the differential input from CLK_ to CLK_ is 3.0V or VCC - VEE, whichever is less. This limit also applies to the difference between any reference voltage input and a single-ended input. The differential inputs have bias resistors that drive the outputs to a differential low when the inputs are open. The inverting inputs (CLKA and CLKB) are biased with a 75kΩ pullup to VCC and a 75kΩ pulldown to VEE. The noninverting inputs (CLKA and CLKB) are biased with a 75kΩ pulldown to VEE. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously (VILD cannot be higher than VIHD). Output levels are referenced to VCC and are considered LVPECL or LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to GND, the outputs are LVPECL. The outputs are LVECL when VCC is connected to GND and VEE is connected to a negative supply. A single-ended input of at least VBB ±95mV or a differential input of at least 95mV switches the outputs to the V OH and V OL levels specified in the DC Electrical Characteristics table. Applications Information Supply Bypassing Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF value capacitor closest to the device. Use multiple parallel vias for low inductance. When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC (if the VBB reference is not used, it can be left open). Traces Input and output trace characteristics affect the performance of the MAX9312/MAX9314. Connect each signal of a differential input or output to a 50Ω characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces. Output Termination Terminate outputs through 50Ω to VCC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if QA0 is used as a single-ended output, terminate both QA0 and QA0. _______________________________________________________________________________________ 7 MAX9312/MAX9314 Detailed Description MAX9312/MAX9314 Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers CLK_ VIH CLK_ VBB VIL (CONNECTED TO CLK_) VOH Q_ VOH - VOL VOL Q_ Figure 1. Switching with Single-Ended Input CLK_ VIHD VIHD - VILD VILD CLK_ tPLHD tPHLD Q_ VOH VOH - VOL VOL Q_ 80% 80% 0 (DIFFERENTIAL) (Q_) - (Q_) 0 (DIFFERENTIAL) 20% 20% tR tF Figure 2. Differential Transition Time and Propagation Delay Timing Diagram Chip Information Pin Configuration PROCESS: BIPOLAR TOP VIEW VCC QA0 QA0 QA1 QA1 QA2 QA2 VCC 32 VCC 31 30 29 28 27 26 25 1 Package Information 24 QA3 N.C. 2 23 QA3 CLKA 3 22 QA4 CLKA 4 VBB 5 CLKB 6 19 QB0 CLKB 7 18 QB1 VEE 8 17 QB1 21 QA4 MAX9312 MAX9314 9 10 11 12 13 20 QB0 14 15 For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 32 LQFP C32-1 21-0054 12 TQFN-EP T3255+4 21-0140 16 VCC QB4 QB4 QB3 QB3 QB2 QB2 VCC LQFP OR TDFN 8 _______________________________________________________________________________________ Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers REVISION NUMBER REVISION DATE 2 4/09 DESCRIPTION Added lead-free TQFN package for MAX9312, deleted future product packages for MAX9314, and updated Pin Description PAGES CHANGED 1, 6 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX9312/MAX9314 Revision History