FUJITSU SEMICONDUCTOR DATA SHEET DS07-12529-1E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89950 Series MB89951/953/P955/PV950 ■ OUTLINE The MB89950 series of single-chip compact microcontroller using the F2MC*-8L family core which can operate at high-speeds and low voltages. They contain peripherals such as timers, UART, serial interfaces, external interrupts and a 168-pixel LCD controller/driver. It is best suited for use in LCD panels. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES • Minimum instruction execution time: 0.8 µs at 5 MHz • F2MC-8L family CPU core Instruction system most suited to controllers Multiplication and division instructions 16-bit arithmetic operation Instruction test and branch instruction Bit manipulation instruction, etc. (Continued) ■ PACKAGE 64-pin Plastic QFP 64-pin Ceramic MQFP (FPT-64P-M09) (MQP-64C-P01) MB89950 Series (Continued) • LCD controller/driver Maximum 42 segment outputs x 4 common outputs Build-in LCD driver split resistor • Three-channel timer unit 8-bit PWM timer: (usable as both reload timer and PWM timer) 8-bit pulse width counter timer: (usable as both reload timer) 20-bit timebased counter • Two serial interfaces 8-bit synchronous serial interface UART (5, 7, and 8-bit transfers possible) • External-interrupt input: 2 channels 2 channels can be used to clear the low-power consumption modes An edge detection function is provided for each channel • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption) Sleep mode (CPU stops to reduce current consumption to about 30%) • Package: QFP-64 (0.65mm pitch) 2 MB89950 Series ■ PRODUCT LINEUP Part number Item Classification MB89951 MB89953 Mass-produced products (Mask ROM product) MB89P955 MB89PV950 One-time PROM products Piggyback/ evaluation and development ptoduct (internal mask ROM) 8 K × 8 bits (internal mask ROM) 16 K × 8 bits (internal PROM, to be programmed with general-purpose EPROM programmer) 32 K × 8 bits (external ROM) RAM size 128 × 8 bits 256 × 8 bits 512 × 8 bits 1024 × 8 bits CPU functions The number of basic instructions: Instruction bit length: Instruction length: Data bit length: Minimum imstruction execution time: Interrupt processing time: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.8 µs at 5 MHz (VCC =5.0 V) 7.2 µs at 5 MHz (VCC =5.0 V) Ports I/O port (N-ch open-drain): I/O port (N-ch open-drain): I/O port (CMOS): Total: 22 (also used as segment pin)*1 4 (two of them are also used as LCD bias pins) 7 (6 used as peripheral) 33 (max.) ROM size 8-bit PWM timer 4 K × 8 bits 8-bit reload timer operation (toggle output possible) 8-bit resolution PWM operation Operation clock (pulse-width count timer output: 0.8 µs, 12.8 µs, 51.2 µs/5 MHz) 8-bit pulse-width counter timer 8-bit reload timer operation 8-bit pulse width measurement (continuous measurement, High- and Low-width measurement, and one-cycle measurement) Operation clock (0.8 µs, 3.2 ms, 25.6 µs/5 MHz) 8-bit serial I/O 8-bit length, selectable from least significant bit (LSB) first or most significant bit (MSB) first, transfer clock (external, 1.6 µs, 6.4 ms, 25.6 µs/5 MHz) UART LCD controller/ driver External interrupt 5-, 7-, 8-bit transfers possible, internal baud-rate generator (Max. 78125 bps/5 MHz) Common output: 4 Segment output: 42 (max.) Operation mode: 1/2 bias and 1/2 duty, 1/3 bias and 1/3 duty, 1/3 bias and 1/4 duty LCD controller display RAM capacity: 42 × 4 bits LCD driver split resistor: built-in (external resistor selectable) 2 (edge selectable: one serving as pulse-width count timer input) Standby mode Power supply voltage*2 EPROM Sleep mode, stop mode 2.2 V to 6.0 V 2.7 V to 6.0 V — MBM27C256A-20TV (LCC package) *1: Mask Option. *2: Varies with conditions such as the operating frequency. (See “■ Electrical Characteristics”.) 3 MB89950 Series ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB89951 MB89953 MB89P955 × FPT-64P-M09 MQP-64C-P01 : Available × × × ×: Not available Note: For more information about each package, see section “■ Package Dimensions.” 4 MB89PV950 MB89950 Series ■ PIN ASSIGNMENT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P00/SEG20 P01/SEG21 P02/SEG22 P03/SEG23 P04/SEG24 P05/SEG25 P06/SEG26 P07/SEG27 P10/SEG28 P11/SEG29 P12/SEG30 P13/SEG31 P14/SEG32 P15/SEG33 P16/SEG34 P17/SEG35 P44/SO MODA X0 X1 VSS P45/SCK P46/INT0 P25/SEG41 P24/SEG40 P23/SEG39 P22/SEG38 P21/SEG37 P20/SEG36 RST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P42/INT1/PWC P43/SI SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 P33/V2 P32/V1 P31 P30 P40 P41/PWM 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 VCC SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 (Top view) (FPT-64P-M09) 5 MB89950 Series 64 63 62 61 60 59 58 57 56 55 54 53 52 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 Vcc SEG13 SEG14 SEG15 SEG16 SEG17 (Top view) SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 P33/V2 P32/V1 P31 P30 P40 P41/PWM P42/INT1/PWC P43/SI 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 84 83 82 81 80 79 78 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 85 86 87 88 89 90 91 92 93 RST P44/SO MODA X0 X1 Vss P45/SCK P46/INT0 P25/SEG41 P24/SEG40 P23/SEG39 P22/SEG38 P21/SEG37 20 21 22 23 24 25 26 27 28 29 30 31 32 94 95 96 65 66 67 68 77 76 75 74 73 72 71 70 69 SEG18 SEG19 P00/SEG20 P01/SEG21 P02/SEG22 P03/SEG23 P04/SEG24 P05/SEG25 P06/SEG26 P07/SEG27 P10/SEG28 P11/SEG29 P12/SEG30 P13/SEG31 P14/SEG32 P15/SEG33 P16/SEG34 P17/SEG35 P20/SEG36 (MQP-64C-P01) • Pin assignment on package top (MB89PV950 only) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 65 N.C. 73 A2 81 N.C. 89 OE 66 VPP 74 A1 82 O4 90 N.C. 67 A12 75 A0 83 O5 91 A11 68 A7 76 N.C. 84 O6 92 A9 69 A6 77 O1 85 O7 93 A8 70 A5 78 O2 86 O8 94 A13 71 A4 79 O3 87 CE 95 A14 72 A3 80 VSS 88 A10 96 VCC N.C.:Internally connected. Do not use. 6 MB89950 Series ■ PIN DESCRIPTION Pin no. QFP *1 MQFP Pin name *2 22 23 X0 23 24 X1 21 22 19 20 Circuit type Function A Clock oscillator pins MODA B Operation-mode select pin This pin is connected directly to VSS with pull down resistor. RST C Reset I/O pin This pin consists of an N-ch open-drain output with a pull-up resistor and hysteresis input. A Low level is put out from this pin. A “LOW” voltage on this port generates a RESET condition 48 to 41 49 to 42 P00/SEG20 to P07/SEG27 D N-channel open-drain type general-purpose I/O ports Also serve as LCDC controller segment outputs. Switching between port output and segment output is performed by the mask option every 8 bits. 40 to 33 41 to 34 P10/SEG28 to P17/SEG35 D N-channel open-drain type general-purpose I/O ports Also serve as LCDC controller segment outputs. Switching between port output and segment output is performed by the mask option. 32 to 27 33 to 28 P20/SEG36 to P25/SEG41 D N-channel open-drain type general-purpose I/O ports Also serve as LCDC controller segment outputs. Switching between port output and segment output is performed by the mask option. 14 to 11 15 to 12 P30 to P31 F N-channel open-drain type general-purpose I/O ports 12 to 11 13 to 12 P32/V1 to P33/V2 D N-channel open-drain type general-purpose I/O ports Also serve as LCDC controller power supply. 15 16 P40 E General-purpose I/O port A pull-up resistor option is provided. 16 17 P41/PWM E General-purpose I/O port Serves as PWM timer toggle output (PWM). A pull-up resistor option is provided. 17 18 P42/PWC/INT1 E General-purpose I/O port Also serves as pulse-width count timer input (PWC) and external interrupt input (INT1) The PWC and INT1 inputs are of a hysteresis type. A pull-up resistor option is provided. 18 19 P43/SI E General-purpose I/O port Also serves as serial I/O and UART data input (SI) The SI input is of a hysteresis type. A pull-up resistor option is provided. 20 21 P44/SO E General-purpose I/O port Also serves as serial I/O and UART data output (SO). A pull-up resistor option is provided. *1: FPT-64P-M09 *2: MQP-64C-P01 (Continued) 7 MB89950 Series (Continued) Pin no. QFP*1 MQFP*2 25 26 26 27 5 to 1, 64 to 57, 55 to 49 Function P45/SCK E General-purpose I/O port Also serves as serial I/O and UART clock input/output (SCK). The SCK input is of a hysteresis type. A pull-up resistor option is provided. P46/INT0 E General-purpose input port Also serves as external-interrupt input (INT0). The input is of a hysteresis type. A pull-up resistor option is provided. 6 to 1, SEG0 to SEG4, 64 to 58, SEG5 to SEG12, 56 to 50 SEG13 to SEG19 9 to 6 7 to 10 10 G For LCDC controller segment ouput COM0 to COM3 G For LCDC controller common output 11 V3 — For LCD driver power supply 56 57 VCC — Power supply Pin 24 25 VSS — Power supply (GND) Pin *1: FPT-64P-M09 *2: MQP-64C-P01 8 Circuit type Pin name MB89950 Series • External EPROM pins (MB89PV950 only) Pin no. Pin name I/O Function 66 VPP O “H” level output pin 67 68 69 70 71 72 73 74 75 A12 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins 77 78 79 O1 O2 O3 I Data input pins 80 VSS O Power supply (GND) pins 82 83 84 85 86 O4 O5 O6 O7 O8 I Data input pins 87 CE O ROM chip enable pin Outputs “H” during standby. 88 A10 O Address output pin 89 OE O ROM output enable pin Outputs “L” at all times. 91 92 93 94 95 A11 A9 A8 A13 A14 O Address output pins 96 VCC O EPROM power supply pin 65 76 81 90 N.C. — Internally connected pins Be sure to leave them open. 9 MB89950 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks A • Crystal oscillator • Feedback resistor: Approx. 1 MΩ/5.0 V (1 to 5 MHz) X1 N-ch P-ch P-ch X0 N-ch N-ch Standby control signal B • CMOS input • Pull-down resistor (N-ch) R • Output pull-up resistor (P-ch): Approx. 50 kΩ (5.0 V) • Hysteresis input C R P-ch N-ch D P-ch N-ch • N-ch open-drain output • CMOS input P-ch N-ch N-ch • The segment output is optional. E • CMOS output • CMOS input • Hysteresis input (peripheral input) R P-ch P-ch N-ch • The pull-up resistor is optional. (Continued) 10 MB89950 Series (Continued) Type Circuit F Remarks • N-ch open-drain output • CMOS input N-ch G • LCDC output 11 MB89950 Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down resistor. 3. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 4. Power Supply Voltage Fluctuations Although operation is assured within the rated, rapid of VCC power supply voltage, a rapid fluctuation of the voltage cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC rippli fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 5. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. 12 MB89950 Series ■ PROGRAMMING TO THE EPROM ON THE MB89P955 The MB89P955 is an OTPROM version of the MB89950 series. 1. Features • 16-Kbyte PROM on chip • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below. Address Single chip EPROM mode (Corresponding addresses on the EPROM programmer) 0000H I/O 0080H RAM 0280H Not available 8000H 0000H Vacancy (Read value FFH) Not available BFF0H 3FF0H Option area Option area BFF6H 3FF7H Vacancy (Read value FFH) Not available C000H 4000H PROM EPROM 16 KB 16 KB FFFFH 7FFFH 3. Programming to the EPPROM Functions equivalent to the MBM27C256A can be used in the MB89P955 EPROM mode. Accordingly, the user can write data with a general-purpose EPROM writer by using a dedicated adapter. Note that the electrical signature mode is not supported. • Programming procedure (1) Set the EPROM writer for the MBM27C256A. (2) Load program data from 4000H to 7FFFH of the EPROM writer (Note that 0C000H to 0FFFFH in the operation mode are equivalent to 4000H to 7FFFH in the EPROM mode). Load option data from 3FF0H to 3FF6H of the EPROM writer (See Bit Map on the next page for the correspondence to each option). (3) Write the data with the EPROM writer. 13 MB89950 Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 5. Programming Yield Due to its nature, bit programming test can’t be conducted as Fujitsu delivery test. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Part number Package Compatible socket adapter Sun Hayato Co., Ltd. Inquiry: Sun Hayato Co., Ltd.: TEL : (81)-3-3986-0403 FAX : (81)-3-5396-9106 14 MB89P955PFM QFP-64 ROM-64QF2-28DP-8L3 MB89950 Series 7. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • OTPROM option bit map Address Bit 7 Vacancy 3FF0H 3FF1H 3FF2H 3FF3H 3FF4H 3FF5H 3FF6H Bit 6 Vacancy Bit 5 Vacancy Bit 4 Bit 3 Oscillation Reset pin stabilization ouput time Readable Readable Readable 1: 218/fC and writable and writable and writable 0: 214/fC Vacancy P46 P45 P44 Pull-up Readable 1: Yes and writable 0: No Pull-up 1: Yes 0: No Pull-up 1: Yes 0: No 1: Yes 0: No P43 Pull-up 1: Yes 0: No Vacancy Vacancy Vacancy Vacancy Vacancy Bit 2 Power-on reset Bit 1 Vacancy Bit 0 Vacancy 1: Yes 0: No P42 Pull-up 1: Yes 0: No Readable Readable and writable and writable P41 Pull-up 1: Yes 0: No P40 Pull-up 1: Yes 0: No Vacancy Vacancy Vacancy Readable Readable Readable Readable Readable Readable Readable Readable and writable and writable and writable and writable and writable and writable and writable and writable Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Readable Readable Readable Readable Readable Readable Readable Readable and Writable and writable and writable and writable and writable and writable and writable and writable Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Readable Readable Readable Readable Readable Readable Readable Readable and writable and writable and writable and writable and writable and writable and writable and writable Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Readable Readable Readable Readable Readable Readable Readable Readable and writable and writable and writable and writable and writable and writable and writable and writable Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Readable Readable Readable Readable Readable Readable Readable Readable and writable and writable and writable and writable and writable and writable and writable and writable Note: Each bit is set to ‘1’ as the initialized value, therefore the pull-up option is not selected. 15 MB89950 Series ■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TV 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below: Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX : (81)-3-5396-9106 3. Memory Space Memory space in each mode such as 32-Kbyte PROM, is diagrammed below. Address Single chip Corresponding address on the EPROM programmer 0000 H I/O 0080 H RAM Not available 0000 H PROM 32 KB FFFFH EPROM 32 KB 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer for the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH. (3) Program with the EPROM programmer. 16 MB89950 Series ■ BLOCK DIAGRAM X0 X1 Oscillator 20-bit timebase timer Clock control 8-bit PWM timer P41/PWM P40 External interrupt P10/SEG28 to P17/SEG35 8 N-ch open-drain I/O port 20 SEG0 to SEG19 4 COM0 to COM3 LCD controller/driver P20/SEG36 to P25/SEG41 P33/V2 P32/V1 P30 P31 6 Port 2 and port 3 V3 Internal bus bus 8 Port 0 and port1 P00/SEG20 to P07/SEG27 8-bit pulse width counter timer Noise clear Port 4 Reset circuit (WDT) RST P42/PWC/ INT1 P45/SCK P44/SO P43/SI 8-bit serial I/O P46/INT0 UART CMOS I/O port N-ch open-drain I/O port R A M (256 × 8 bits) Other pins MODA VCC, VSS F2MC-8L CPU R O M (8 K × 8 bits) 17 MB89950 Series ■ CPU CORE 1. Memory Space F2MC-8L CPU has 64 Kbytes of memory. All I/O, data program areas are located in this space. The I/O area is near the lowest address and the data area is immediately above it. The data area can be divided into register, stack, and direct-address areas according to the applications. The program area is located near the highest address, and the tables of interrupt and reset vectors and vector-call instructions are at the highest address in this area. The following figure shows the structure of the memory space for the MB89950 series of microcontrollers. • Memory Space MB89951 0000H 0080H I/O MB89P955 MB89953 0000H 0080H I/O 0000H 0080H I/O MB89PV950 0000H 0080H I/O Reserved 00C0H RAM RAM RAM RAM 0100H Register 0100H 0100H 0140H 0180H 0100H Register Register 0200H Register 0200H 0280H 0480H Vacant Vacant Vacant Vacant 8000H C000H E000H F000H ROM FFFFH 18 ROM ROM FFFFH FFFFH ROM FFFFH MB89950 Series 2. Registers The F2MC-8L family has two types of registers; dedicated hardware registers in the CPU and general-purpose memory registers. The following registers are provided: Program counter (PC): A 16-bit register for indicating the instruction storage positions. Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which is used for arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit pointer for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code 16 bits Initial value FFFDH : Program counter PC A : Accumulator Indeterminate T : Temporary accumulator Indeterminate IX : Index register Indeterminate EP : Extra pointer Indeterminate SP : Stack pointer Indeterminate PS : Program status I-flag = 0, IL1, 0 = 11 The other bit values are Indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) • Structure of the Program Status Register 15 PS 14 13 12 RP 11 10 9 8 Vacancy Vacancy Vacancy RP 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR 19 MB89950 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for Conversion of Actual Addresses of the General-purpose Register Area Lower OP codes RP “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data, and bits for control of CPU operations at the time of an interrupt. H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared to ‘0’ at the reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is cleared to ‘0’. Z-flag: Set to ‘1’ when an arithmetic operation results in ‘0’. Cleared to ‘0’ otherwise. V-flag: Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the overflow does not occur. C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. Set to the shift-out value in the case of a shift instruction. 20 MB89950 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit resister for storing data The general-purpose registers are of 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 4 banks can be used on the MB89951 and a total of 8 banks can be used on the MB89953 and a total of 16 banks can be used on the MB89P955 and a total of 32 banks can be used on the MB89PV950. The bank currently in use is indicated by the register bank pointer (RP). • Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 4 banks (MB89951) 8 banks (MB89953) 16 banks (MB89P955) 32 banks (MB89PV950) Memory area 21 MB89950 Series ■ I/O MAP Address Read/write Register name 00H (R/W) PDR0 (R/W) PDR1 03H 04H Port 0 data register Vacancy 01H 02H Register description Port 1 data register Vacancy (R/W) PDR2 05H to 07H Port 2 data register Vacancy 08H (R/W) STBC Standby control register 09H (R/W) WDTC Watchdog timer control register 0AH (R/W) TBCR Timebase timer control register 0BH 0CH Vacancy (R/W) PDR3 Port 3 data register Vacancy 0DH 0EH (R/W) PDR4 Port 4 data register 0FH (W) DDR4 Port 4 data direction register 10H Vacancy 11H 12H (R/W) CNTR PWM control register 13H (W) COMR PWM compare register 14H (R/W) PCR1 PWC pulse width control register 1 15H (R/W) PCR2 PWC pulse width control register 2 16H (R/W) RLBR PWC reload buffer register 17H (R/W) NCCR PWC noise reduction control register 18H to 1BH Vacancy 1CH (R/W) SMR Serial mode register 1DH (R/W) SDR Serial data register 1EH Vacancy 1FH 20H (R/W) SMC1 UART serial mode control register 1 21H (R/W) SRC UART serial rate control register 22H (R/W) SSD UART serial status/data register 23H (R/W) SIDR/SODR 24H (R/W) SMC2 UART serial data register UART serial mode control register 2 (Continued) 22 MB89950 Series (Continued) Address Read/write Register name 25H to 2FH 30H Register description Vacancy (R/W) EIC1 31H to 63H External interrupt 1 control register 1 Vacancy 64H to 78H (R/W) VRAM Display data RAM 79H (R/W) LCDR LCD control register 7AH (R/W) SEGR Segment output select register 7BH Vacancy 7CH (W) ILR1 Interrupt level setting register 1 7DH (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH — ITR Interrupt test register Note: Do not use vacancies. 23 MB89950 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = 0.0 V) Parameter Symbol Value Min. Max. Unit Remarks Power supply voltage VCC VSS – 0.3 VSS + 7.0 V LCD power supply voltage V3 VSS – 0.3 VSS + 7.0 V VI1 VSS – 0.3 VCC + 0.3 V All the pins must not exceed VSS + 7.0 V, excluding P00 to P07, P10 to P17, P20 to P25,P32 to P33 in MB89P955/PV950 VI2 VSS – 0.3 VSS + 7.0 V Applicable to P00 to P07, P10 to P17, P20 to P25 (port select) in MB89951/953 VI3 VSS – 0.3 V *P00 to P07, P10 to P17, P20 to P25, P32 to P33 Input voltage V3 VO1 VSS – 0.3 VCC + 0.3 V All the pins must not exceed Vss + 7.0 V, excluding P00 to P07, P10 to P17, P20 to P25, P32 to P33 in MB89P955/PV950 VO2 VSS – 0.3 VSS + 7.0 V Applicable to P00 to P07, P10 to P17, P20 to P25 (port select) in MB89951/953 VO3 VSS – 0.3 V3 V P00 to P07, P10 to P17, P20 to P25, P32 to P33* 10 mA Output voltage “L” level output current IOL “L” level average output current IOLAV 4 mA Applicable to all pins except power supply pin. Applicable to all pins excluding power supply pin. Specified as the average value in 1 hour. “L” level total output current ∑IOL “H” level output current IOH “H” level average output current IOHAV 40 mA –5 mA –2 mA Applicable to all pins excluding power supply pin. Applicable to all pins excluding power supply pin. Specified as the average value in 1 hour. “H” level total output maximum current ∑IOH –10 mA Power consumption PD 300 mW Operating temperature TA –40 +85 °C Storage temperature –55 +150 °C Tstg * : It is only suitable to MB89P955/PV950. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 24 MB89950 Series 2. Recommended Operating Conditions (VSS = 0.0 V) Symbol Parameter Value Unit Remarks Min. Max. 2.2* 6.0 V Usual operation guarantee range 1.5 6.0 V RAM-data-holding guarantee range at stop mode V3 pins for MB89953 The voltage range supplied to LCD and its optimum value depend on the LCD Power supply voltage VCC LCD power supply voltage V3 VSS 6.0 V Operating temperature TA –40 +85 °C * : This value varies with the operating frequency and analog assurance range. See Figure 1. • Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MHz) 6 Operating voltage (V) 5 Operating assurance range 4 3 2 1 1 2 3 4 5 1.0 0.8 Operating frequency (MHz) 4.0 2.0 1.3 Minimum instruction cycle (µs) WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 25 MB89950 Series 3. DC Characteristics (VCC = V3 = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Parameter “H” level input voltage Symbol Pin name Condition Value Min. Typ. Max. Unit P00 to P07, P10 to P17, P20 to P25, P30 to P31, P40 to P46 — 0.7 VCC *1 — 0.3 VCC *1 V P32,P33 — 0.7 VCC *1 — V3 V VIHS RST, INT0, SCK, SI, PWC/INT1 — 0.8 VCC — VCC + 0.3 V VIL P00 to P07, P10 to P17, P20 to P25, P30 to P33, P40 to P46 — VSS – 0.3 — 0.3 VCC *1 V VILS RST, MODA, INT0, SCK, SI, PWC/INT1 — VSS – 0.3 — 0.2 VCC V VIH “L” level input voltage Open-drain output pin VD Applied voltage “H” level Output VOH voltage “L” level Output VOL1 voltage VOL2 Remarks P30 to P31, P20 to P25, P10 to P17, P00 to P07 — VSS – 0.3 — VSS + 6.0 V P00 to P07, P10 to P17, P20 to P25 (port select) in MB89951/953 P32, P33 — VSS – 0.3 — V3 V P32 to P33 (port select) P40 to P46 IOH = –2.0 mA 4.0 — — V P00 to P07, P10 to P17, P20 to P25, P30 to P33 IOL = 4.0 mA — — 0.4 V RST, P40 to P46 IOL = 4.0 mA — — 0.4 V — — ±5 When pull-up µA option is not selected — — ±5 When pull-up µA option is not selected MODA, P30, P31, P40 to P46 Input leakage current (Hi-z output leak current) ILI1 Pull-up resistance RPULL RST, P40 to P46 VI = 0.0 V 25 50 100 When pull-up kΩ option is selected Common Output impedance RVCOM COM0 to COM3 V1 to V3 = +5.0 V — — 2.5 kΩ P00 to P07, P10 to P17, P20 to P25, P32, P33 0.45 V < VI < VCC (Continued) 26 MB89950 Series (Continued) (VCC = V3 = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Segment Output impedance RVSEG LCD divided resistance RLCD LCD leak current ILCDL Pull-down resistance Power Supply voltage Input capacitance Pin name Symbol — Condition Value Unit Min. Typ. Max. V1 to V3 = +5.0 V — — 15 kΩ V1 to V3 30 60 120 kΩ V1 to V3, COM0 to COM3, SEG0 to SEG41 — — — ±10 µA MODA — TBD TBD TBD kΩ SEG0 to SEG41 — Remarks ICC VCC FC = 5 MHz tinst*3 = 0.8µs — 3.5 5.0 mA Main RUN mode ICCS VCC FC = 5 MHz tinst*3 = 0.8µs — 1.1 1.7 mA Main SLEEP mode ICCH VCC TA = +25°C — 0.1 1 µA STOP mode CIN Except VCC and VSS f = 1 MHz — 10 — pF *1: Port input voltage is smaller than V3 for MB89P955/PV950. *2: TBD = To be determined *3: For information on tinst, see “(4) Instruction Cycle” in “4.AC Characteristics.” Note: For pins for selection of segments (SEG8 to SEG31) and ports (P10 to P17, P40 to P47, P50 to P57), see the limits values of ports when port output is selected and those for segments when segment output is selected. 27 MB89950 Series 4. AC Characteristics (1) Reset Timing (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter RST “L” pulse width Value Condition tZLZH — Min. Max. 48 tXCYL* — Unit Remarks ns * : tXCYL is the oscillation cycle (1/FC) to input to the XO pin. tZLZH RST 0.2 VCC (2) Specifications for Power-on Reset (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Power supply rising time Power supply cut-off time Symbol Condition tR — tOFF Value Unit Remarks Min. Max. — 50 ms Power-on reset function only 1 — ms Min. interval time to the next power-on reset Note: If power-on reset provided is selected, an abrupt change in the power supply voltage could cause a poweron reset. When changing the power supply voltage during operation, voltage fluctuations should be two or less times for smooth start-up. tR tOFF 2.0 V VCC 28 0.2 V 0.2 V 0.2 V MB89950 Series (3) Clock Timing (VSS = 0.0 V, TA = –40°C to +85°C) Symbol Pin name Clock frequency FC Clock cycle time Parameter Value Unit Remarks Min. Typ. Max. X0, X1 1 — 5 MHz tHCYL X0, X1 400 — 2000 ns Input clock duty ratio* duty X0 30 — 70 % crystal & ceramic Input clock rising/falling time tCR tCF X0 — — 10 ns Applied when external clock used * : duty = PWH/tHCYL • Timing Conditions tHCYL X0 0.8 VCC 0.8 VCC 0.8 VCC 0.2 VCC PWH tCF 0.2 VCC PWL tCR • Clock Configurations When crystal or ceramic resonator is used X0 When external clock is used X1 X0 X1 fCH C0 Open FC C1 (4) Instruction Cycle (VSS = 0.0 V, TA = –40°C to +85°C) Parameter Instruction cycle (Minimum instruction executing time) Symbol tinst Value Unit 4/FC to 64/FC µs Remarks tinst = 0.8 µs when operating at FC = 5 MHz 29 MB89950 Series (5) Serial I/O & UART timing (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Serial clock cycle time tSCYC SCK SCK1 ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK SCK ↑ → valid SI hold time tSHIX SCK, SI Serial clock “H” pulse width tSHSL SCK Serial clock “L” pulse width tSLSH SCK SCK1 ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK SCK ↑ → valid SI hold time tSHIX SCK, SI * : For information on tinst, see “(4) Instruction Cycle.” 30 Condition Internal clock operation External clock operation Value Unit Remarks Min. Max. 2 tinst* — µs 200 200 ns 0.5 tinst* — µs 0.5 tinst* — µs 1 tinst* — µs 1 tinst — µs 0 200 ns 0.5 tinst* — µs 0.5 tinst* — µs MB89950 Series • Internal Shift Clock Mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV SO 2.4 V 0.8 V tIVSH SI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External Shift Clock Mode tSLSH tSHSL 0.7 VCC 0.7 VCC SCK 0.2 VCC 0.2 VCC tSLOV 2.4 V SO 0.8 V tIVSH SI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 31 MB89950 Series (6) Peripheral Input Timing (VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Value Pin name Min. Max. Peripheral input “H” level pulse width 1 tILIH1 PWC, INT1, INT0 2 tinst* — µs Peripheral input “L” level pulse width 1 tIHIL1 PWC, INT1, INT0 2 tinst* — µs * : For information on tinst, see “(4) Instruction Cycle.” tIHIL1 tILIH1 PWC, INT, INT0 0.8 VCC 0.2 VCC 32 Unit 0.2 VCC 0.8 VCC Remarks MB89950 Series ■ INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups: • Transfer • Arithmetic operation • Branch • Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri × (×) (( × )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH prior to the instruction executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 33 MB89950 Series Table 2 Mnemonic ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Note 34 Transfer Instructions (48 instructions) During byte transfer to A, T ← A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) MB89950 Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A (Continued) 35 MB89950 Series (Continued) Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ # Operation 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 36 ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 L MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel 9 A B C D E F A SUBC A XCH A, T XOR A AND A OR A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS R7 R6 R5 R4 R3 R2 R1 R0 DEC DEC DEC DEC DEC DEC DEC DEC R7 R6 R5 R4 R3 R2 R1 R0 rel rel rel rel CALLV BLT #7 rel CALLV BGE #6 rel CALLV BZ #5 CALLV BNZ #4 rel CALLV BN #3 CALLV BP #2 CALLV BC #1 CALLV BNC #0 rel CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP ADDC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP 8 A A SETC MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP CMPW CMP JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A 7 F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX E 6 D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP C 5 B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 A A DIVU SETI 9 4 8 RORC 7 3 6 ROLC A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89950 Series ■ INSTRUCTION MAP 37 MB89950 Series ■ MASK OPTIONS Model MB89951 MB89953 MB89P955 MB89PV950 Specification method Select when ordering mask Set by EPROM Fixed No. 1 Pull-up resistors P40 to P46 Can be selected for Can be selected for each pin each pin 2 Port/segment output P00 to P07, P10 to P17, P20 to P25 Can be selected for every 8 to 1 pins*2 Port/segment output*3 Port/segment output*3 3 Power-on reset Power-on reset available Power-on reset unavailable Selectable Selectable Power-on reset available 4 Selection of main clock oscillation stabilization time (at 5 MHz)*1 Approx. 218/FC (Approx. 52.4 ms) Approx. 214/FC (Approx. 3.28 ms) Selectable Selectable 218/FC 5 Reset pin output Reset output available Reset output unavailable Selectable Selectable Reset output available No pull-up resistor *1: The main clock oscillation stabilization time is generated by dividing the main clock oscillation. Since the oscillation cycle is unstable immedeately after oscillation starts, the time in this table is only a guide. *2: Port/segment output switching should be specified in the same manner as the port allocation set by the segment output select register in the LCD controller/driver. *3: When those pins are used as ports, applied voltage should never be jogjer than V3. ■ ORDERING INFORMATION Part Number 38 Package MB89951PFM MB89953PFM MB89P955PFM 64-pin Plastic QFP (FPT-64P-M09) MB89PV950CF 64-pin Ceramic MQFP (MQP-64C-M01) Remarks MB89950 Series ■ PACKAGE DIMENSIONS 64-pin Plastic QFP (FPT-64P-M09) 14.00±0.20(.551±.008)SQ 48 33 12.00±0.10(.472±.004)SQ 49 +0.20 1.50 –0.10 +.008 .059 –.004 (Mounting height) 32 9.75 (.384) REF 13.00 (.512) NOM 1 PIN INDEX 64 17 LEAD No. 1 Details of "A" part 16 0.65(.0256)TYP "A" 0.30±0.10 (.012±.004) 0.13(.005) M +0.05 0.127 –0.02 +.002 .005 –.001 0.10±0.10 (STAND OFF) (.004±.004) 0.10(.004) 0 C 1994 FUJITSU LIMITED F64018S-1C-2 10° 0.50±0.20 (.020±.008) Dimensions in mm (inches) 64-pin Ceramic MQFP (MQP-64C-P01) 18.70(.736)TYP INDEX AREA 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 12.00(.472)TYP +0.40 1.20 –0.20 +.016 .047 –.008 1.00±0.25 (.039±.010) 1.00±0.25 (.039±.010) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 1.27±0.13 (.050±.005) 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 0.30(.012)TYP 7.62(.300)TYP 0.40±0.10 (.016±.004) 18.00(.709) TYP 0.40±0.10 (.016±.004) +0.40 1.20 –0.20 +.016 .047 –.008 9.48(.373)TYP 11.68(.460)TYP 0.50(.020)TYP C 1994 FUJITSU LIMITED M64004SC-1-3 10.82(.426) 0.15±0.05 MAX (.006±.002) Dimensions in mm (inches) 39 MB89950 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, USA Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ F9609 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). 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