MC74HC4538A Dual Precision Monostable Multivibrator (Retriggerable, Resettable) The MC74HC4538A is identical in pinout to the MC14538B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This dual monostable multivibrator may be triggered by either the positive or the negative edge of an input pulse, and produces a precision output pulse over a wide range of pulse widths. Because the device has conditioned trigger inputs, there are no trigger–input rise and fall time restrictions. The output pulse width is determined by the external timing components, Rx and Cx. The device has a reset function which forces the Q output low and the Q output high, regardless of the state of the output pulse circuitry. http://onsemi.com MARKING DIAGRAMS 16 16 PDIP–16 N SUFFIX CASE 648 • Unlimited Rise and Fall Times Allowed on the Trigger Inputs • Output Pulse is Independent of the Trigger Pulse Width • ± 10% Guaranteed Pulse Width Variation from Part to Part (Using • • • • • • • the Same Test Jig) Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 145 FETs or 36 Equivalent Gates MC74HC4538AN AWLYYWW 1 1 16 16 HC4538A AWLYWW 1 SO–16 D SUFFIX CASE 751B 1 16 16 HC 4538A ALYW 1 GND 1 16 VCC CX1/RX1 2 15 GND RESET 1 3 14 CX2/RX2 A1 4 13 RESET 2 B1 5 12 A2 Q1 6 11 B2 Q1 7 10 Q2 GND 8 9 Q2 TSSOP–16 DT SUFFIX CASE 948F A L, WL Y, YY W, WW Device MC74HC4538AN April, 2001 – Rev. 8 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Figure 1. Pin Assignment Semiconductor Components Industries, LLC, 2001 1 1 Package Shipping PDIP–16 2000/Box MC74HC4538AD SOIC–16 48/Rail MC74HC4538ADR2 SOIC–16 2500/Reel MC74HC4538ADT TSSOP–16 96/Rail MC74HC4538ADTR2 TSSOP–16 2500/Reel Publication Order Number: MC74HC4538A/D MC74HC4538A CX 1 RX 1 VCC 1 TRIGGER INPUTS A1 B1 RESET 1 2 4 6 5 7 Q1 Q1 3 CX 2 RX 2 VCC 15 14 A2 TRIGGER INPUTS B2 12 10 11 9 13 PIN 16 = VCC RESET 2 PIN 8 = GND RX AND CX ARE EXTERNAL COMPONENTS PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND Figure 2. Logic Diagram FUNCTION TABLE Inputs Reset A Outputs B Q Q H H H L H H X H L X Not Triggered Not Triggered H H L,H, L H L,H, Not Triggered Not Triggered L X X X X L H Not Triggered http://onsemi.com 2 Q2 Q2 MC74HC4538A MAXIMUM RATINGS (Note 1) Symbol Parameter Value Unit 0.5 to 7.0 V 0.5 VI VCC 0.5 V 0.5 VO VCC 0.5 V 20 30 mA 25 mA VCC DC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Sink Current 25 mA ICC DC Supply Current per Supply Pin 100 mA IGND DC Ground Current per Ground Pin 100 mA TSTG Storage Temperature Range 65 to 150 C TL Lead temperature, 1 mm from Case for 10 Seconds 260 C TJ Junction temperature under Bias 150 C JA Thermal resistance PDIP SOIC TSSOP 78 112 148 C/W PD Power Dissipation in Still Air at 85C PDIP SOIC TSSOP 750 500 450 mW MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage Human Body Model (Note 3) Machine Model (Note 4) Charged Device Model (Note 5) >2000 >100 >500 V ILatch–Up Latch–Up Performance Above VCC and Below GND at 85C (Note 6) 300 mA (Note 2) A, B, Reset CX, RX Level 1 Oxygen Index: 30% – 35% UL–94–VO (0.125 in) 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. 2. IO absolute maximum rating must be observed. 3. Tested to EIA/JESD22–A114–A. 4. Tested to EIA/JESD22–A115–A. 5. Tested to JESD22–C101–A. 6. Tested to EIA/JESD78. 7. For high frequency or heavy load considerations, see the ON Semiconductor High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min VCC DC Supply Voltage (Referenced to GND) Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 7) Max Unit 3.0* 6.0 V 0 VCC V –55 +125 C VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 0 0 0 – 1000 500 400 No Limit ns VCC < 4.5 V VCC ≥ 4.5 V 1.0 2.0 † † k 0 † F A or B (Figure 5) Rx External Timing Resistor Cx External Timing Capacitor *The HC4538A will function at 2.0 V but for optimum pulse–width stability, VCC should be above 3.0 V. †The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage due to board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10 F/1.0 M. Values of Cx > 1.0 F may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may occur for Rx > 1.0 M. 8. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level. 9. Information on typical parametric values can be found in the ON Semiconductor High–Speed CMOS Data Book (DL129/D). http://onsemi.com 3 MC74HC4538A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ DC CHARACTERISTICS Guaranteed Limits Symbol Parameter Test Conditions –55 to 25C VCC Volts Min 1.5 3.15 4.2 Max 85C Min 125C Max Min VIH Minimum High–Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| 20 µA 2.0 4.5 6.0 VIL Maximum Low–Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| 20 µA 2.0 4.5 6.0 VOH Minimum High–Level Output Voltage Vin = VIH or VIL |Iout| 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 Vin = VIH or VIL |Iout| –4.0 mA |Iout| –5.2 mA VOL Maximum Low–Level Output Voltage Vin = VIH or VIL |Iout| 20 µA 1.5 3.15 4.2 Max 1.5 3.15 4.2 0.5 1.35 1.8 0.5 1.35 1.8 Unit V 0.5 1.35 1.8 V V 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 V Iin Maximum Input Leakage Current (A, B, Reset) Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA Iin Maximum Input Leakage Current (Rx, Cx) Vin = VCC or GND 6.0 ± 50 ± 500 ± 500 nA ICC Maximum Quiescent Supply Current (per package) Standby State Vin = VCC or GND Q1 and Q2 = Low Iout = 0 µA 6.0 130 220 350 µA ICC Maximum Supply Current (per package) Active State Vin = VCC or GND Q1 and Q2 = High Iout = 0 µA Pins 2 and 14 = 0.5 VCC 25C 6.0 http://onsemi.com 4 400 –45C to 85C 600 –55C to 125C 800 µA MC74HC4538A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limits Symbol VCC Volts Parameter –55 to 25C Min Max 85C Min Max 125C Min Max Unit tPLH Maximum Propagation Delay Input A or B to Q (Figures 6 and 8) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tPHL Maximum Propagation Delay Input A or B to NQ (Figures 6 and 8) 2.0 4.5 6.0 195 39 33 245 49 42 295 59 50 ns tPHL Maximum Propagation Delay Reset to Q (Figures 7 and 8) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tPLH Maximum Propagation Delay Reset to NQ (Figures 7 and 8) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 7 and 8) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Cin Maximum Input Capacitance — 10 25 10 25 10 25 pF (A. B, Reset) (Cx, Rx) 10. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD 150 Power Dissipation Capacitance (per Multivibrator)* *Used to determine the no–load dynamic power consumption: High–Speed CMOS Data Book (DL129/D). P D = CPD VCC2 f + ICC VCC . pF For load considerations, see the ON Semiconductor ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING CHARACTERISTICS (Input tr = tf = 6.0 ns) Guaranteed Limits Symbol VCC Volts Parameter –55 to 25C Min Max 85C Min Max 125C Min Max Unit trec Minimum Recovery Time, Inactive to A or B (Figure 7) 2.0 4.5 6.0 0 0 0 0 0 0 0 0 0 ns tw Minimum Pulse Width, Input A or B (Figure 6) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tw Minimum Pulse Width, Reset (Figure 7) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tr, tf Maximum Input Rise and Fall Times, Reset (Figure 7) 2.0 4.5 6.0 A or B (Figure 7) 2.0 4.5 6.0 http://onsemi.com 5 1000 500 400 1000 500 400 No Limit 1000 500 400 ns MC74HC4538A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ OUTPUT PULSE WIDTH CHARACTERISTICS (CL = 50 pF)t Conditions Symbol Parameter Guaranteed Limits Timing Components VCC Volts Rx = 10 kΩ, Cx = 0.1 µF 5.0 85C –55 to 25C 125C Min Max Min Max Min Max Unit 0.63 0.77 0.6 0.8 0.59 0.81 ms τ Output Pulse Width* (Figures 6 and 8) — Pulse Width Match Between Circuits in the same Package — — ± 5.0 % — Pulse Width Match Variation (Part to Part) — — ± 10 % 0.8 10 s TA = 25°C 1s OUTPUT PULSE WIDTH (τ) k, OUTPUT PULSE WIDTH CONSTANT (TYPICAL) *For output pulse widths greater than 100 µs, typically τ = kRxCx, where the value of k may be found in Figure 3. 0.7 0.6 0.5 0.4 0.3 1 2 3 4 5 6 VCC = 5 V, TA = 25°C 100 ms 10 ms 1 ms 100 µs 1 MΩ 10 µs 100 kΩ 1 µs 10 kΩ 1 kΩ 100 ns 0.00001 0.0001 0.001 7 VCC, POWER SUPPLY VOLTAGE (VOLTS) 0.01 OUTPUT PULSE WIDTH (τ) (NORMALIZED TO 5 V NUMBER) Rx = 100 kΩ Cx = 1000 pF TA = 25°C 0.9 0.8 Rx = 1 MΩ Cx = 0.1 µF 0.6 0.5 1 10 100 Figure 4. Output Pulse Width versus Timing Capacitance 1.1 0.7 1 CAPACITANCE (µF) Figure 3. Typical Output Pulse Width Constant, k, versus Supply Voltage (For output pulse widths > 100 µs: τ = kRxCx) 1 0.1 2 3 4 5 6 VCC, POWER SUPPLY VOLTAGE (VOLTS) 7 Figure 5. Normalized Output Pulse Width versus Power Supply Voltage http://onsemi.com 6 MC74HC4538A OUTPUT PULSE WIDTH (τ) (NORMALIZED TO 25C NUMBER) 1.1 1.05 1 VCC = 6 V Rx = 10 kΩ Cx = 0.1 µF 0.95 0.9 0.85 VCC = 3 V 0.8 –75 –50 –25 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (°C) Figure 6. Normalized Output Pulse Width versus Power Supply Voltage OUTPUT PULSE WIDTH (τ) (NORMALIZED TO 25C NUMBER) 1.03 1.02 Rx = 10 kΩ Cx = 0.1 µF 1.01 1 0.99 VCC = 5.5 V VCC = 5 V 0.98 VCC = 4.5 V 0.97 –75 –50 –25 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (°C) Figure 7. Normalized Output Pulse Width versus Power Supply Voltage tw(H) VCC 50% A GND tw(L) B VCC 50% GND τ tPLH tPLH τ 50% Q τ tPHL tPHL Q 50% Figure 8. Switching Waveform http://onsemi.com 7 τ MC74HC4538A tr tf VCC 90% 10% A GND trr VCC 50% GND B tf tf GND trec τ + trr tPHL 90% 50% 50% 10% Q tTHL Q 10% tw(L) tTLH VCC 90% 50% RESET tPLH 90% 10% 50% Figure 9. Switching Waveform TEST POINT OUTPUT DEVICE UNDER TEST CL * *Includes all probe and jig capacitance Figure 10. Test Circuit http://onsemi.com 8 (RETRIGGERED PULSE) MC74HC4538A PIN DESCRIPTIONS capacitors (see the Block Diagram). Polystyrene capacitors are recommended for optimum pulse width control. A1, A2 (Pins 4, 12) Electrolytic capacitors are not recommended due to high Positive–edge trigger inputs. A rising–edge signal on leakages associated with these type capacitors. either of these pins triggers the corresponding multivibrator GND (Pins 1 and 15) when there is a high level on the B1 or B2 input. External ground. The external timing capacitors discharge B1, B2 (Pins 5, 11) to ground through these pins. Negative–edge trigger inputs. A falling–edge signal on either of these pins triggers the corresponding multivibrator OUTPUTS when there is a low level on the A1 or A2 input. INPUTS Reset 1, Reset 2 (Pins 3, 13) Q1, Q2 (Pins 6, 10) Reset inputs (active low). When a low level is applied to one of these pins, the Q output of the corresponding multivibrator is reset to a low level and the Q output is set to a high level. Noninverted monostable outputs. These pins (normally low) pulse high when the multivibrator is triggered at either the A or the B input. The width of the pulse is determined by the external timing components, RX and CX. CX1/RX1 and CX2/RX2 (Pins 2 and 14) Q1, Q2 (Pins 7, 9) Inverted monostable outputs. These pins (normally high) pulse low when the multivibrator is triggered at either the A or the B input. These outputs are the inverse of Q1 and Q2. External timing components. These pins are tied to the common points of the external timing resistors and RxCx UPPER REFERENCE CIRCUIT – + Vre, UPPER VCC VCC OUTPUT LATCH LOWER REFERENCE CIRCUIT M1 2 kΩ – + M2 Q Vre, LOWER M3 Q TRIGGER CONTROL CIRCUIT A C CB B Q TRIGGER CONTROL RESET CIRCUIT R RESET POWER ON RESET RESET LATCH Figure 11. Logic Detail (1/2 the Device) http://onsemi.com 9 MC74HC4538A CIRCUIT OPERATION TRIGGER OPERATION Figure 12 shows the HC4538A configured in the retriggerable mode. Briefly, the device operates as follows (refer to Figure 10): In the quiescent state, the external timing capacitor, Cx, is charged to VCC. When a trigger occurs, the Q output goes high and Cx discharges quickly to the lower reference voltage (Vref Lower 1/3 VCC). Cx then charges, through Rx, back up to the upper reference voltage (Vref Upper 2/3 VCC), at which point the one–shot has timed out and the Q output goes low. The following, more detailed description of the circuit operation refers to both the logic detail (Figure 9) and the timing diagram (Figure 10). The HC4538A is triggered by either a rising–edge signal at input A (#7) or a falling–edge signal at input B (#8), with the unused trigger input and the Reset input held at the voltage levels shown in the Function Table. Either trigger signal will cause the output of the trigger–control circuit to go high (#9). The trigger–control circuit going high simultaneously initiates two events. First, the output latch goes low, thus taking the Q output of the HC4538A to a high state (#10). Second, transistor M3 is turned on, which allows the external timing capacitor, Cx, to rapidly discharge toward ground (#11). (Note that the voltage across Cx appears at the input of both the upper and lower reference circuit comparator). When Cx discharges to the reference voltage of the lower reference circuit (#12), the outputs of both reference circuits will be high (#13). The trigger–control reset circuit goes high, resetting the trigger–control circuit flip–flop to a low state (#14). This turns transistor M3 off again, allowing Cx to begin to charge back up toward VCC, with a time constant t = RxCx (#15). Once the voltage across Cx charges to above the lower reference voltage, the lower reference circuit will go low allowing the monostable multivibrator to be retriggered. QUIESCENT STATE In the quiescent state, before an input trigger appears, the output latch is high and the reset latch is high (#1 in Figure 10). Thus the Q output (pin 6 or 10) of the monostable multivibrator is low (#2, Figure 10). The output of the trigger–control circuit is low (#3), and transistors M1, M2, and M3 are turned off. The external timing capacitor, Cx, is charged to VCC (#4), and both the upper and lower reference circuit has a low output (#5). In addition, the output of the trigger–control reset circuit is low. QUIESCENT STATE TRIGGER CYCLE (A INPUT) TRIGGER CYCLE (B INPUT) RESET RETRIGGER trr 7 TRIGGER INPUT A (PIN 4 OR 12) TRIGGER INPUT B (PIN 5 OR 11) 8 24 9 TRIGGER-CONTROL CIRCUIT OUTPUT 3 14 11 4 RX/CX INPUT (PIN 2 OR 14) 15 21 17 23 12 Vref LOWER UPPER REFERENCE CIRCUIT 5 LOWER REFERENCE CIRCUIT 6 Vref UPPER 13 25 18 13 16 RESET INPUT (PIN 3 OR 13) 20 1 RESET LATCH 22 10 Q OUTPUT (PIN 6 OR 10) 2 19 τ τ Figure 12. Timing Diagram http://onsemi.com 10 τ + trr MC74HC4538A occurs, the output of the reset latch goes low (#22), turning on transistor M1. Thus Cx is allowed to quickly charge up to VCC (#23) to await the next trigger signal. On power up of the HC4538A the power–on reset circuit will be high causing a reset condition. This will prevent the trigger–control circuit from accepting a trigger input during this state. The HC4538A’s Q outputs are low and the Q not outputs are high. When Cx charges up to the reference voltage of the upper reference circuit (#17), the output of the upper reference circuit goes low (#18). This causes the output latch to toggle, taking the Q output of the HC4538A to a low state (#19), and completing the time–out cycle. POWER–DOWN CONSIDERATIONS Large values of Cx may cause problems when powering down the HC4538A because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge from VCC through the input protection diodes at pin 2 or pin 14. Current through the protection diodes must be limited to 30 mA; therefore, the turn–off time of the VCC power supply must not be faster than t = VCCCx /(30 mA). For example, if VCC = 5.0 V and Cx = 15 µF, the VCC supply must turn off no faster than t = (5.0 V)(15 µF)/30 mA = 2.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VCC to zero volts occurs, the HC4538A may sustain damage. To avoid this possibility, use an external damping diode, Dx, connected as shown in Figure 11. Best results can be achieved if diode Dx is chosen to be a germanium or Schottky type diode able to withstand large current surges. RETRIGGER OPERATION When used in the retriggerable mode (Figure 12), the HC4538A may be retriggered during timing out of the output pulse at any time after the trigger–control circuit flip–flop has been reset (#24), and the voltage across Cx is above the lower reference voltage. As long as the Cx voltage is below the lower reference voltage, the reset of the flip–flop is high, disabling any trigger pulse. This prevents M3 from turning on during this period resulting in an output pulse width that is predictable. The amount of undershoot voltage on RxCx during the trigger mode is a function of loop delay, M3 conductivity, and VDD. Minimum retrigger time, trr (Figure 7), is a function of 1) time to discharge Rx Cx from VDD to lower reference voltage (Tdischarge); 2) loop delay (Tdelay); 3) time to charge Rx Cx from the undershoot voltage back to the lower reference voltage (Tcharge). Figure 13 shows the device configured in the non–retriggerable mode. For additional information, please see Application Note (AN1558/D) titled Characterization of Retrigger Time in the HC4538A Dual Precision Monostable Multivibrator. RESET AND POWER ON RESET OPERATION A low voltage applied to the Reset pin always forces the Q output of the HC4538A to a low state. The timing diagram illustrates the case in which reset occurs (#20) while Cx is charging up toward the reference voltage of the upper reference circuit (#21). When a reset DX CX VCC RX Q A B Q RESET Figure 13. Discharge Protection During Power Down http://onsemi.com 11 MC74HC4538A TYPICAL APPLICATIONS CX RISING–EDGE TRIGGER RX CX RX RISING–EDGE TRIGGER VCC Q A B VCC Q A Q B Q B = VCC RESET = VCC RESET = VCC CX RX CX FALLING–EDGE TRIGGER VCC A = GND VCC Q Q B RX A B Q Q FALLING–EDGE TRIGGER RESET = VCC RESET = VCC Figure 14. Retriggerable Monostable Circuitry Figure 15. Non–retriggerable Monostable Circuitry GND N/C A = GND VCC RX CX Q N/C B Q RESET N/C Figure 16. Connection of Unused Section ONE–SHOT SELECTION GUIDE 100 ns MC14528B MC14536B MC14538B MC14541B HC4538A* 1 µs 10 µs 100 µs 1 ms 10 ms 100 ms 1 s 10 s 23 HR 5 MIN *Limited operating voltage (2–6 V) TOTAL OUTPUT PULSE WIDTH RANGE RECOMMENDED PULSE WIDTH RANGE http://onsemi.com 12 MC74HC4538A PACKAGE DIMENSIONS PDIP–16 N SUFFIX CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 13 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 MC74HC4538A PACKAGE DIMENSIONS SOIC–16 D SUFFIX CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 14 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 MC74HC4538A PACKAGE DIMENSIONS TSSOP–16 DT SUFFIX CASE 948F–01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉ ÇÇ ÇÇ ÉÉ K1 2X L/2 16 9 J1 B –U– L SECTION N–N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A –V– NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M N F DETAIL E http://onsemi.com 15 DIM A B C D F MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 MC74HC4538A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET) Email: ONlit–[email protected] French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET) Email: ONlit–[email protected] English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT) Email: [email protected] CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–[email protected] Toll–Free from Mexico: Dial 01–800–288–2872 for Access – then Dial 866–297–9322 ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone: 1–303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit–[email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, UK, Ireland For additional information, please contact your local Sales Representative. http://onsemi.com 16 MC74HC4538A/D