MAGNACHIP SEMICONDUCTOR LTD. 8-BIT SINGLE-CHIP MICROCONTROLLERS MC80F0424/0432/0448 MC80C0424/0432/0448 User’s Manual (Ver. 0.2) Version History Ver 0.2 (MAR, 2005) this book FLASH memory feature is included. Ver 0.1 (MAR, 2005) First release version. Version 0.2 Published by MCU Application Team 2005 MagnaChip Semiconductor Ltd. All right reserved. Additional information of this manual may be served by MagnaChip semiconductor offices in Korea or Distributors and Representatives. MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. Preliminary MC80F0424/0432/0448 CONTENTS 1. OVERVIEW .................................................................................................................................................... 1 1.1 Description .............................................................................................................................................. 1 1.2 Features .................................................................................................................................................. 1 1.3 Development Tools ................................................................................................................................. 2 1.4 Ordering Information ......................................................................................................................... 3 2. BLOCK DIAGRAM ........................................................................................................................................ 4 3. PIN ASSIGNMENT ........................................................................................................................................ 5 4. PACKAGE DIAGRAM ................................................................................................................................... 7 5. PIN FUNCTION .............................................................................................................................................. 9 5.1 MC80F0424/0432/0448 Pin Description ............................................................................................... 10 6. PORT STRUCTURES .................................................................................................................................. 13 7. ELECTRICAL CHARACTERISTICS ........................................................................................................... 17 7.1 Absolute Maximum Ratings .................................................................................................................. 17 7.2 Recommended Operating Conditions ................................................................................................... 17 7.3 A/D Converter Characteristics .............................................................................................................. 17 7.4 DC Electrical Characteristics ................................................................................................................ 18 7.5 AC Characteristics ................................................................................................................................ 19 7.6 Serial Interface Timing Characteristics ................................................................................................. 20 7.7 Typical Characteristic Curves ............................................................................................................... 21 8. MEMORY ORGANIZATION ........................................................................................................................ 24 8.1 Registers ............................................................................................................................................... 24 8.2 Program Memory .................................................................................................................................. 26 8.3 Data Memory ........................................................................................................................................ 30 8.4 Addressing Mode .................................................................................................................................. 36 9. I/O PORTS ................................................................................................................................................... 40 10. CLOCK GENERATOR .............................................................................................................................. 44 11. BASIC INTERVAL TIMER ......................................................................................................................... 46 12. WATCHDOG TIMER ................................................................................................................................. 48 13. WATCH TIMER .......................................................................................................................................... 51 14. TIMER/EVENT COUNTER ........................................................................................................................ 52 14.1 8-bit Timer / Counter Mode ................................................................................................................. 56 14.2 16-bit Timer / Counter Mode ............................................................................................................... 62 14.3 8-bit Compare Output (16-bit) ............................................................................................................. 63 14.4 8-bit Capture Mode ............................................................................................................................. 64 14.5 16-bit Capture Mode ........................................................................................................................... 68 14.6 PWM Mode ......................................................................................................................................... 71 15. ANALOG TO DIGITAL CONVERTER ....................................................................................................... 75 MAR. 2005 Ver 0.2 MC80F0424/0432/0448 Preliminary 16. SERIAL INPUT/OUTPUT (SIO) ................................................................................................................. 78 16.1 Transmission/Receiving Timing .......................................................................................................... 79 16.2 The method of Serial I/O ..................................................................................................................... 81 16.3 The Method to Test Correct Transmission .......................................................................................... 81 17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) ................................................... 82 17.1 UART Serial Interface Functions ........................................................................................................ 82 17.2 Serial Interface Configuration ............................................................................................................. 83 17.3 Communication operation ................................................................................................................... 85 17.4 Relationship between main clock and baud rate ................................................................................ 86 17.5 Communication operation ................................................................................................................... 87 18. BUZZER FUNCTION ................................................................................................................................. 88 19. INTERRUPTS ............................................................................................................................................ 90 19.1 Interrupt Sequence ............................................................................................................................. 92 19.2 BRK Interrupt ...................................................................................................................................... 94 19.3 Shared Interrupt Vector ....................................................................................................................... 94 19.4 Multi Interrupt ...................................................................................................................................... 95 19.5 External Interrupt ................................................................................................................................ 96 20. OPERATION MODE .................................................................................................................................. 98 20.1 Operation Mode Switching .................................................................................................................. 99 21. POWER SAVING OPERATION .............................................................................................................. 101 21.1 Sleep Mode ....................................................................................................................................... 101 21.2 Stop Mode ......................................................................................................................................... 102 21.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode ........................................................... 105 21.4 Minimizing Current Consumption ...................................................................................................... 107 22. OSCILLATOR CIRCUIT .......................................................................................................................... 109 23. RESET ..................................................................................................................................................... 110 24. POWER FAIL PROCESSOR ................................................................................................................... 111 25. FLASH PROGRAMMING ........................................................................................................................ 113 25.1 Lock bit .............................................................................................................................................. 113 25.2 Power Fail Detection level ................................................................................................................ 113 26. Emulator EVA. Board Setting .............................................................................................................. 114 27. IN-SYSTEM PROGRAMMING (ISP) ....................................................................................................... 117 27.1 Getting Started / Installation .............................................................................................................. 117 27.2 Basic ISP S/W Information ................................................................................................................ 117 27.3 Hardware Conditions to Enter the ISP Mode .................................................................................... 119 27.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board .............................................. 120 INSTRUCTION MAP........................................................................................................................................... i INSTRUCTION SET........................................................................................................................................... ii MASK ORDER SHEET................................................................................................................................... viii MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 MC80F0424/0432/0448 MC80C0424/0432/0448 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 10-BIT A/D CONVERTER AND UART 1. OVERVIEW 1.1 Description The MC80F0424/0432/0448 is advanced CMOS 8-bit microcontroller with 48K/32K/24K bytes of ROM(FLASH). This is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following standard features : 24K/32K/48K bytes of ROM(FLASH), 1.5K bytes of RAM, 8/16-bit timer/counter, watchdog timer, watch timer, 10-bit A/D converter, 8-bit Serial Input/Output, UART, 6-bit buzzer driving port, 10-bit PWM output and on-chip oscillator and clock circuitry. It also has 8 high current I/O pins with typical 20mA. In addition, the MC80F0424/0432/0448 supports power saving modes to reduce power consumption. FLASH MCU MASK MCU ROM RAM MC80F0424 MC80C0424 24KB 1.5KB MC80F0432 MC80C0432 32KB 1.5KB MC80F0448 MC80C0448 48KB 1.5KB ADC PWM I/O PORT Package 16 channel 2 channel 57 port 64SDIP, 64MQFP 64LQFP 1.2 Features • 24/32K/48K Bytes On-chip ROM • 16 channel 10-bit A/D converter • FLASH memory - Endurance : 100 cycles - Data retention time : 10 years • Four External Interrupt input ports • 1.5K Bytes of On-chip Data RAM (Included stack memory) • Minimum Instruction Execution Time - 333ns at 12MHz (NOP instruction) • 57 I/O Ports at 64 pin • One 8-bit Basic Interval Timer • Four 8-bit and one 16-bit Timer/Event counter (or three 16-bit Timer/Event counter) • Fifteen Interrupt sources - Basic Interval Timer(1), External input(4) - Timer/Event counter(5), ADC(1) - Serial Interface(3), WDT and Watch Timer(1) • Built in Noise Immunity Circuit - Noise filter - 3-level Power fail detector [3.0V, 2.7V, 2.4V] • Power Down Mode - Stop, Sleep, Sub active, Sub sleep mode • One Watchdog timer • Wide Operating Voltage Range - 2.7V to 5.5V @ (0.4~4MHz) - 4.5V to 5.5V @ (0.4~12MHz) • One Watch timer • 0.4 ~ 12MHz Wide Operating Frequency Range • Two 10-bit PWM • 64SDIP, 64MQFP, 64LQFP type • Three 8-bit Serial Communication Interface - One SIO and two UART • Operating Temperature : -40°C ~ 85°C • One Buzzer Driving port - 488Hz ~ 250kHz@4MHz MAR. 2005 Ver 0.2 • Oscillator Type - Crystal, Ceramic resonator, External clock • Sub-clock : 32.768kHz crystal oscillator 1 MC80F0424/0432/0448 Preliminary 1.3 Development Tools The MC80F0424/0432/0448 is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM and OTP programmers. There are two different type of programmers such as single type and gang type. For mode detail, Refer to “25. FLASH PROGRAMMING” on page 113. Macro assembler operates under the MS-Windows 95 and upversioned Windows OS. Please contact sales part of MagnaChip semiconductor. Software - MS-Windows based assembler - MS-Windows based Debugger - HMS800 C compiler Hardware (Emulator) - CHOICE-Dr. - CHOICE-Dr. EVA 80C0x B/D FLASH Writer - CHOICE - SIGMA I/II(Single writer) - PGM Plus I/II/III(Single writer) - Standalone GANG4 I/II(Gang writer) Figure 1-2 PGM-Plus (Single writer) Figure 1-1 Choice-Dr (Emulator) Figure 1-3 Standalone GANG4 (Gang writer) 2 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 1.4 Ordering Information Mask version FLASH version Device name ROM Size MC80C0424K MC80C0424Q MC80C0424L 24K bytes MC80C0432K MC80C0432Q MC80C0432L 32K bytes MC80C0448K MC80C0448Q MC80C0448L 48K bytes MC80F0424K MC80F0424Q MC80F0424L 24K bytes MC80F0432K MC80F0432Q MC80F0432L 32K bytes MC80F0448K MC80F0448Q MC80F0448L 48K bytes RAM size Package 1.5K bytes K : 64SDIP Q : 64QFP L : 64LQFP Table 1-1 Ordering Information of MC80F0424/0432/0448 MAR. 2005 Ver 0.2 3 MC80F0424/0432/0448 Preliminary 2. BLOCK DIAGRAM R30 R31 / ACLK1 R32 / RxD1 R33 / TxD1 R34 R35 R36 R37 Power Supply VDD VSS AVDD AVSS ADC Power Supply PSW ALU R00~R07 R20~R23 R0 R2 A X Y R3 SP Data Memory (1.5K bytes) PC UART1 Program Memory Interrupt Controller Data Table System controller System Clock Controller Sub System Clock Controller 8-bit Basic Interval Timer Watch/ Watchdog Timer 8-bit Timer/ Counter 10-bit PWM Driver Buzzer R1 R5 8-bit serial Interface SIO/UART0 Instruction Decoder 10-bit ADC Timing Generator 4 R21 / SXIN R22 / SXOUT XIN XOUT RESET Clock Generator R10 / INT0 R11 / INT1 R12 / INT2 R13 / BUZO R14 / T0O R15 / EC0 R16 R17 R50 / INT3 R51 / EC1 R52 / T2O R53 / PWM1O / T1O R54 / PWM3O / T3O R4 R40 R41 R42 / SCK R43 / SI R44 / SO R45 / ACLK0 R46 / RxD0 R47 / TxD0 R6 R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7 R7 R70 / AN8 R71 / AN9 R72 / AN10 R73 / AN11 R74 / AN12 R75 / AN13 R76 / AN14 R77 / AN15 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 3. PIN ASSIGNMENT 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD R67 / AN7 R66 / AN6 R65 / AN5 R64 / AN4 R63 / AN3 R62 / AN2 R61 / AN1 R60 / AN0 AVDD AVSS R54 / PWM3O / T3O R53 / PWM1O / T1O R52 / T2O R51 / EC1 R50 / INT3 R47 / TxD0 R46 / RxD0 R45 / ACLK0 R44 / SO R43 / SI R42 / SCK R41 R40 R37 R36 R35 R34 R33 / TxD1 R32 / RxD1 R31 / ACLK1 R30 64MQFP (Top View) MC80F0424/0432/0448Q 32 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 52 53 54 55 56 57 58 59 60 61 62 63 64 R35 R34 R33 / TxD1 R32 / RxD1 R31 / ACLK1 R30 VSS XOUT XIN RESET R23 R22 / SXOUT R21 / SXIN AN14 / R76 AN15 / R77 R00 R01 R02 R03 R04 R05 R06 R07 INT0 / R10 INT1 / R11 INT2 / R12 BUZO / R13 T0O / R14 EC0 / R15 R16 R17 R20 AN2 / R62 AN3 / R63 AN4 / R64 AN5 / R65 AN6 / R66 AN7 / R67 VDD AN8 / R70 AN9 / R71 AN10 / R72 AN11 / R73 AN12 / R74 AN13 / R75 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R61 / AN1 R60 / AN0 AVDD AVSS R54 / PWM3O / T3O R53 / PWM1O / T1O R52 / T2O R51 / EC1 R50 / INT3 R47 / Tx0D R46 / RxD0 R45 / ACLK0 R44 / SO R43 / SI R42 / SCK R41 R40 R37 R36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MC80F0424/0432/0448K AN8 / R70 AN9 / R71 AN10 / R72 AN11 / R73 AN12 / R74 AN13 / R75 AN14 / R76 AN15 / R77 R00 R01 R02 R03 R04 R05 R06 R07 INT0 / R10 INT1 / R11 INT2 / R12 BUZO / R13 T0O /R14 EC0 / R15 R16 R17 R20 SXIN / R21 SXOUT / R22 R23 RESET XIN XOUT VSS 64SDIP (Top View) MAR. 2005 Ver 0.2 5 Preliminary R60 / AN0 AVDD AVSS R54 / PWM3O / T3O R53 / PWM1O / T1O R52 / T2O R51 / EC0 R50 / INT3 R47 / TxD0 R46 / RxD0 R45 / ACLK0 R44 / SO R43 / SI R42 / SCK R41 R40 MC80F0424/0432/0448 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64LQFP (Top View) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 MC80F0424/0432/0448L 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 R37 R36 R35 R34 R33 / TxD1 R32 / RxD1 R31 / ACLK1 R30 VSS XOUT XIN RESET R23 R22 / SXOUT R21/ SXIN R20 R00 R01 R02 R03 R04 R05 R06 R07 NT0 / R10 INT1 / R11 INT2 / R12 BUZO / R13 T0O / R14 EC0 / R15 R16 R17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AN1 / R61 AN2 / R62 AN3 / R63 AN4 / R64 AN5 / R65 AN7 / R67 AN7 / R67 VDD AN8 / R70 AN9 / R71 AN10 / R72 AN11 / R73 AN12 / R74 AN13 / R75 AN14 / R76 AN15 / R77 6 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 4. PACKAGE DIAGRAM 64SDIP UNIT: INCH 0.750 Typ. min. 0.015 0.205 max. 2.280 2.260 0.070 BSC 0.140 0.120 0.050 0.030 0.022 0.016 0.680 0.660 0.012 0.008 0-15° 64MQFP 24.15 23.65 20.10 19.90 18.15 17.65 14.10 13.90 UNIT: MM 0.36 0.10 SEE DETAIL “A” 3.18 max. 1.95 REF 0.50 0.35 MAR. 2005 Ver 0.2 1.03 0.73 0.23 0.13 0-7° 1.00 BSC DETAIL “A” 7 MC80F0424/0432/0448 Preliminary 64LQFP 12.00 BSC 10.00 BSC 1.45 1.35 10.00 BSC 12.00 BSC UNIT: MM 0-7° 0.15 0.05 SEE DETAIL "A" 1.60 max. 0.38 0.22 8 0.50 BSC 0.75 0.45 1.00 REF DETAIL "A" MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 5. PIN FUNCTION VDD: Supply voltage. VSS: Circuit ground. AVDD: Supply voltage to the ladder resistor of ADC circuit. AVSS: ADC circuit ground. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins with 1 or 0 written to the R0 Port Direction Register R0IO can be used as outputs or inputs. The internal pull-up resistor can be connected by using the pull-up selection register 0 (PU0). R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins with 1 or 0 written to the R1 Port Direction Register R1IO can be used as outputs or inputs. The internal pull-up resistor can be connected by using the pull-up selection register 1 (PU1). In addition, R1 serves the functions of the various following special features such as INT0 (External interrupt 0), INT1 (External interrupt 1), INT2 (External interrupt 2), BUZO (Buzzer driver output), T0O (Timer 0 output), EC0 (Event counter input 0). R20~R23: R2 is an 4-bit CMOS bidirectional I/O port. R2 pins with 1 or 0 written to the R2 Port Direction Register R2IO can be used as outputs or inputs. In addition, R2 serves the functions of the various following special features such as SXIN (Sub clock input), SXOUT (Sub clock output). R30~R37: R3 is an 8-bit CMOS bidirectional I/O port. R3 pins with 1 or 0 written to the R3 Port Direction Register R3IO can be used as outputs or inputs. R3 operates as the high current output MAR. 2005 Ver 0.2 port with typical 20mA at low level output. In addition, R3 serves the functions of the various following special features such as ACLK1 (UART1 Asynchronous serial clock input), RxD1 (UART1 data input), TxD1 (UART1 data output) R40~R47: R4 is an 8-bit CMOS bidirectional I/O port. R4 pins with 1 or 0 written to the R4 Port Direction Register R4IO can be used as outputs or inputs. The internal pull-up resistor can be connected by using the pull-up selection register 4 (PU4). In addition, R4 serves the functions of the various following special features such as SCK (Serial clock), SI (Serial data input), SO (Serial data output), ACLK0 (UART0 Asynchronous serial clock input), RxD0 (UART0 data input), TxD0 (UART0 data output). R50~R54: R5 is an 5-bit CMOS bidirectional I/O port. R5 pins with 1 or 0 written to the R5 Port Direction Register R5IO can be used as outputs or inputs. In addition, R5 serves the functions of the various following special features such as INT3 (External interrupt 3), EC1 (Event counter input 1), T2O (Timer 2 output), PWM1O (PWM 1 output) / T1O (Timer 1 compare output), PWM3O (PWM 3 output) / T3O (Timer 3 compare output). R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins with 1 or 0 written to the R6 Port Direction Register R6IO can be used as outputs or inputs. In addition, R6 serves the functions of the ADC analog input port AN[7:0]. R70~R77: R7 is an 8-bit CMOS bidirectional I/O port. R7 pins with 1 or 0 written to the R7 Port Direction Register R7IO can be used as outputs or inputs. The internal pull-up resistor can be connected by using the pull-up selection register 7 (PU7). In addition, R7 serves the functions of the ADC analog input port AN[15:8]. 9 MC80F0424/0432/0448 Preliminary 5.1 MC80F0424/0432/0448 Pin Description 5.1.1 MC80F0424/0432/0448 Pin Description PIN NAME R00~R07 In/Out I/O Function Port 0. 8-bit I/O port. Can be set as input or output mode in 1-bit units. Internal pull-up resistor PU0 can be used via software. Initial state Alternate Function Input - R10 INT0 R11 INT1 R12 R13 R14 I/O R15 Port 1. 8-bit I/O port. Can be set as input or output mode in 1-bit units. Internal pull-up resistor PU1 can be used via software. INT2 Input BUZO T0O EC0 R16 - R17 - R20 R21 R22 I/O R23 Port 2. 4-bit I/O port. Can be set in input or output mode in 1-bit units. Crystal(32.768KHz) connecting pins(R21,R22) Input SXIN SXOUT - P30 P31 ACLK1 P32 P33 P34 I/O P35 Port 3. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Operates as high current output port with typical 20mA at low level output. RxD1 Input TxD1 P36 P37 - R40 - R41 - R42 SCK R43 R44 I/O R45 Port 4. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Internal pull-up resistor PU4 can be used via software. Input SI SO ACLK0 R46 RxD0 R47 TxD0 R50 INT3 R51 R52 R53 I/O Port 5. 5-bit I/O port. Can be set in input or output mode in 1-bit units. R54 EC1 Input T2O PWM1O/T1O PWM3O/T3O Table 5-1 MC80F0424/0432/0448 Pin Description 10 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 Initial state Alternate Function Port 6. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Input AN0~AN7 Port 7. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Internal pull-up resistor PU7 can be used via software. Input AN8~AN15 System reset input. Input - Input - Output - Analog power/reference voltage input to A/D converter. Set the same potential as VDD. - - - Ground potential for A/D converter. Set the same potential as VSS. - - VDD - Positive power supply. - - VSS - Ground potential. - - PIN NAME In/Out R60~R67 I/O R70~R77 I/O RESET I XIN I XOUT O AVDD - AVSS Function Crystal connection for main system clock oscillation. Table 5-1 MC80F0424/0432/0448 Pin Description MAR. 2005 Ver 0.2 11 MC80F0424/0432/0448 Preliminary 5.1.2 MC80F0424/0432/0448 Alternate Function Pin Description PIN NAME In/Out Function Initial state INT0 INT1 INT2 Shared Pin R10 Valid edges(rising, falling, or both rising and falling) can be specified. External Interrupt request Input. I Input INT3 R11 R12 R50 BUZO O Buzzer Output Input R13 T0O O Timer0 Output Input R14 T2O O Timer2 Output Input R52 EC0 I Timer0 Event Counter Input Input R15 Timer2 Event Counter Input Input R51 Input R21 Input R22 Input R31 EC1 I SXIN I SXOUT O ACLK1 I UART1 Asynchronous serial interface serial clock input. RxD1 I UART1 Asynchronous serial interface serial data input. Input R32 TxD1 O UART1 Asynchronous serial interface serial data output. Input R33 SCK I/O Serial clock input/output of serial interface. Input R42 SI I Serial data input of serial interface. Input R43 SO O Serial data output of serial interface. Input R44 ACLK0 I UART0 Asynchronous serial interface serial clock input. Input R45 RxD0 I UART0 Asynchronous serial interface serial data input. Input R46 TxD0 O UART0 Asynchronous serial interface serial data output. Input R47 PWM1O/T1O O Timer1 PWM Output / Timer 1 Compare Output Input R53 PWM3O/T3O O Timer3 PWM Output / Timer 1 Compare Output Input R54 AN0~AN7 I Analog input Channel 0 ~ 7 for A/D converter. Input R60~R67 AN8~AN15 I Analog input Channel 8 ~ 15 for A/D converter. Input R70~R77 Resonator connecting pins (32.768KHz) Table 5-2 MC80F0424/0432/0448 Alternate Function Pin Description 12 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 6. PORT STRUCTURES R00~R07, R16, R17, R40, R41 R50(INT3),R51(EC1) VDD VDD Data Reg. VDD Direction Reg. Pull-up Tr. Pull-up Reg. VDD Pin VSS VDD Data Reg. Data Bus MUX Pin Direction Reg. RD VSS VSS Noise Filter INT3,EC1 Data Bus MUX INT3_EN,EC1_EN RD R33(TxD1) TxD1 VDD R10(INT0), R11(INT1), R12(INT2), R15(EC0), Data Reg. R43(SI),R45(ACLK0),R46(RxD0) VDD Pull-up Tr. Pull-up Reg. MUX Pin Direction Reg. VSS TxD1_EN VDD VDD VSS VDD Data Reg. Data Bus Direction Reg. MUX Pin RD VSS VSS Data Bus MUX RD INT,EC,SI, ACLK0,RxD0 Noise Filter INT_EN,SI_EN,ACLK0_EN, EC_EN,RxD_EN MAR. 2005 Ver 0.2 13 MC80F0424/0432/0448 Preliminary R31(ACLK1), R32(RxD1) R52(T2O), R53(PWM1O), R54(PWM3O) VDD VDD T2O,PWM1O,PWM3O VDD Data Reg. Data Reg. Direction Reg. VDD MUX Pin Pin Direction Reg. VSS VSS PWM1_EN,T2O_EN PWM3_EN Data Bus MUX RD Data Bus MUX RD Noise Filter ACLK1,RxD1 VSS ACLK1_EN, RxD1_EN R13(BUZO), R14(T0O), R47(TxD0) R20, R23, R30~R37 VDD VDD Pull-up Tr. Pull-up Reg. VDD BUZO,T0O,TxD0 Data Reg. Data Reg. Pin Direction Reg. VDD VSS MUX Pin Direction Reg. VSS BUZO_EN, T0O_EN TxD0_EN VDD VSS Data Bus MUX VSS RD MUX Data Bus RD 14 MAR. 2005 Ver 0.2 Preliminary R42(SCK) MC80F0424/0432/0448 R60~R67(AN0~AN7) VDD VDD Pull-up Tr. Pull-up Reg. VDD SCK Data Reg. VDD Data Reg. Direction Reg. VDD Pin MUX VSS VSS Direction Reg. Pin Data Bus SCKO_EN MUX VSS VSS RD Data Bus MUX AN[7:0] RD ADC_EN & CH_SEL SCKI_EN SCK Noise Filter R70~R77(AN8~AN15) VDD R44(SO, IOSWIN(SI)) Pull-up Tr. Pull-up Reg. VDD VDD Pull-up Reg. VDD SO Data Reg. Pull-up Tr. Data Reg. VDD Direction Reg. VDD Pin MUX VSS Direction Reg. VSS Pin Data Bus VSS SO_EN MUX VSS RD Data Bus MUX IOSWIN_EN SI AN[15:0] RD ADC_EN & CH_SEL Noise Filter IOSWIN_EN(SI) MAR. 2005 Ver 0.2 15 MC80F0424/0432/0448 Preliminary RESET XIN, XOUT VDD VDD Mask only XIN Internal Reset STOP VSS Pin VSS VSS VDD MAIN CLOCK XOUT R21(SXIN), R22(SXOUT) VDD VSS VDD Data Reg. Direction Reg. SXIN VSS Data Bus VSS MUX RD XT_EN VDD VDD Data Reg. Direction Reg. SXOUT VSS Data Bus VSS MUX RD 16 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage........................................................ -0.3 to +6.5 V Maximum current (ΣIOL) .................................................160 mA Storage Temperature .............................................-40 to +125 °C Maximum current (ΣIOH)...................................................80 mA Voltage on any pin with respect to Ground (VSS) ..........................................................................-0.3 to VDD+0.3V Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum current out of VSS pin.....................................200 mA Maximum current into VDD pin .......................................100 mA Maximum current sunk by (IOL per I/O Pin) .....................20 mA Maximum output current sourced by (IOH per I/O Pin) ............................................................................................10 mA 7.2 Recommended Operating Conditions Specifications Parameter Symbol Condition Unit Min. Max. Supply Voltage VDD fXIN=0.4~12MHz fXIN=0.4~4MHz 4.5 2.7 5.5 5.5 V Operating Frequency fXIN VDD=4.5~5.5V VDD=2.7~5.5V 0.4 0.4 12 4 MHz -40 85 °C Operating Temperature TOPR 7.3 A/D Converter Characteristics (Ta=-40~85°C, VSS=0V, VDD=2.7~5.5V @Conversion Clock of 1MHz) Parameter Symbol Resolution Conditions Min. Typ. Max. Unit - - ±10 - BIT Overall Accuracy NACC - - - ±3 LSB Non Linearity Error NNLE - - - ±3 LSB Differential Non Linearity Error NDNLE - - - ±3 LSB Full Scale Error NFSE - - - ±3 LSB Zero Offset Error NZOE - - - ±3 LSB Gain Error NNLE - - - ±3 LSB TCONV fXIN 13 - - µS Analog Input Voltage VAIN - AVSS - AVDD V Analog Power Supply AVDD - - - VDD V Analog Ground AVSS - VSS - VSS+0.3 V Analog Block Current IAVDD AVDD=VDD=5.12V - 2.5 3 mA Conversion Time MAR. 2005 Ver 0.2 17 MC80F0424/0432/0448 Preliminary 7.4 DC Electrical Characteristics (TA=-40~85°C, VDD=5.0V±10%, VSS=0V, fXIN=8MHz) Parameter Symbol Typ. Max. Unit INT0, INT1, INT2, INT3, EC0, EC1, SI, SCK, ACLK0, RxD0, ACLK1, RxD1, RESET 0.8VDD - VDD+0.3 V VIH2 R0, R1, R2, R3, R4, R5, R6, R7 0.7VDD - VDD+0.3 V VIH3 XIN, SXIN 0.8VDD - VDD+0.3 V VIL1 INT0, INT1, INT2, INT3, EC0, EC1, SI, SCK, ACLK0, RxD0, ACLK1, RxD1, RESET -0.3 - 0.2VDD V VIL2 R0, R1, R2, R3, R4, R5, R6, R7 -0.3 - 0.3VDD V VIL3 XIN, SXIN -0.3 - 0.2VDD V VOH1 R0, R1, R2, R3, R4, R5, R6, R7 (IOH=-0.7mA) VDD-0.4 - - V VOH2 XOUT (IOH=-50µA) VDD-0.5 - - V VOH3 SXOUT (IOH=-5µA) VDD-0.5 - - V VOL1 R0, R1, R2, R3, R4, R5, R6, R7 (IOL=1.6mA) - - 0.4 V VOL2 XOUT (IOL=50µA) - - 0.5 V VOL3 SXOUT (IOL=5µA) - - 0.5 V Input Low Voltage Output Low Voltage Min. VIH1 Input High Voltage Output High Voltage Pin/Condition High Current IOL R3 (VOL=1V) - - 20 mA Input High Leakage Current IIH R0, R1, R2, R3, R4, R5, R6, R7 - - 1 µA Input Low Leakage Current IIL R0, R1, R2, R3, R4, R5, R6, R7 -1 - - µA Pull-up Resistor RPU R0, R1, R4, R7 10 - 100 kΩ 0.45 - 4.5 MΩ OSC Feedback Resistor RX XIN, XOUT RSX SXIN, SXOUT 8 - 18 MΩ Internal RC WDT Period (RCWDT) IIL VDD=4.5V 33 - 100 µS Hysteresis VT INT0, INT1, INT2, INT3, EC0, EC1, SI, SCK, ACLK, RxD 0.3 - 0.8 V 2.2 2.7 3.2 V 2.5 3.0 3.5 V 1.9 2.4 2.9 V - - 15 mA - 160 µA Power Fail Detect Voltage Power Supply Current VPFD IDD1 Active Mode, XIN=8MHz IDD2 Sub_Active Mode, SXIN=0.32MHz ISLEEP1 Sleep Mode, XIN=8MHz - - 6 mA ISLEEP2 Sub_Sleep Mode, SXIN=0.32MHz - - 20 µA Stop Mode, Oscillator Stop, XIN=4MHz - - 5 µA ISTOP 18 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 7.5 AC Characteristics (TA=-40~85°C, VDD=5V±10%, VSS=0V) Parameter Symbol Pins Operating Frequency fXIN System Clock Cycle Time Specifications Unit Min. Typ. Max. XIN 0.4 - 12 MHz tSYS - 166 - 5000 nS Oscillation Stabilizing Time (4MHz) tST XIN, XOUT - - 20 mS External Clock Pulse Width tCPW XIN 35 - - nS External Clock Transition Time tRCP,tFCP XIN - - 20 nS Interrupt Pulse Width tIW INT0, INT1, INT2, INT3 2 - - tSYS RESET Input Width tRST RESET 8 - - tSYS Event Counter Input Pulse Width tECW EC0, EC1 2 - - tSYS tREC,tFEC EC0, EC1 - - 20 nS Event Counter Transition Time tSYS = 1/fXIN tCPW tCPW 0.9VDD XIN 0.1VDD tRCP tIW INT0~INT3 tFCP tIW 0.8VDD 0.2VDD tRST RESET 0.2VDD tECW tECW 0.8VDD EC0, EC1 0.2VDD tREC tFEC Figure 7-1 Timing Chart MAR. 2005 Ver 0.2 19 MC80F0424/0432/0448 Preliminary 7.6 Serial Interface Timing Characteristics (TA=-40~+85°C, VDD=5V±10%, VSS=0V, fXIN=8MHz) Specifications Parameter Symbol Pins Unit Min. Typ. Max. Serial Input Clock Pulse tSCYC SCK 2tSYS+200 - - nS Serial Input Clock Pulse Width tSCKW SCK tSYS+70 - - nS Serial Input Clock Pulse Transition Time tFSCK tRSCK SCK - - 30 nS Serial Input Pulse Transition Time tFSIN tRSIN SI - - 30 nS Serial Input Setup Time (External SCK) tSUS SI 100 - - nS Serial Input Setup Time (Internal SCK) tSUS SI 200 - nS Serial Input Hold Time tHS SI tSYS+70 - nS Serial Output Clock Cycle Time tSCYC SCK 4tSYS - Serial Output Clock Pulse Width tSCKW SCK tSYS-30 Serial Output Clock Pulse Transition Time tFSCK tRSCK SCK 30 nS Serial Output Delay Time sOUT SO 100 nS tSCKW nS tSCKW 0.8VDD 0.2VDD tSUS tHS 0.8VDD 0.2VDD SI tDS SO nS tSCYC tRSCK tFSCK SCLK 16tSYS tFSIN tRSIN 0.8VDD 0.2VDD Figure 7-2 Serial I/O Timing Chart 20 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 7.7 Typical Characteristic Curves This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. IOH−VOH R0~R7 pins IOH (mA) VDD=5.0V TA=25°C -12 The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation IOH−VOH IOH (mA) VDD=3.0V TA=25°C -12 -9 -9 -6 -6 -3 -3 0 R0~R7 pins 0 0.5 1.0 1.5 IOL−VOL1 2.0 2.5 VDD-VOH (V) R0~R2, R4~R7 pins IOL (mA) VDD=5.0V TA=25°C 40 0.5 1.0 IOL−VOL1 IOL (mA) VDD=3.0V TA=25°C 20 30 15 20 10 10 5 1.5 2.0 VDD-VOH (V) R0~R2, R4~R7 pins 0 0 0.5 1.0 1.5 2.0 IOL−VOL2 2.5 R3 pin IOL (mA) VDD=5.0V TA=25°C 40 0.5 VOL (V) IOL−VOL2 IOL (mA) VDD=3.0V TA=25°C 20 30 15 20 10 10 5 1.5 2.0 VOL (V) R3 pin 0 0 0.5 MAR. 2005 Ver 0.2 1.0 1.0 1.5 2.0 2.5 VOL (V) 0.5 1.0 1.5 2.0 VOL (V) 21 MC80F0424/0432/0448 IDD−VDD IDD (mA) Preliminary ISLEEP−VDD Main Active Mode IDD (mA) TA=25°C 10 7.5 fXIN = 12MHz 5 8MHz IDD (µA) TA=25°C 4 4 3 3 2 1 4MHz 2 3 4 5 4MHz 0 VDD 6 (V) 2 IDD−VDD IDD (mA) 3 4 5 IDD (mA) T A=25°C TA =25°C 2 3 4 5 VDD 6 (V) Sub Active Mode1 TA=25°C 2 fXIN = 12MHz, 8MHz, 4MHz 1.5 2 1 1 0.5 0 2 3 IDD−VDD IDD (µA) 0 VDD 6 (V) ISLEEP−VDD Sub Active Mode1 4 3 TA=25°C fXIN = 12MHz, 8MHz, 4MHz 1 0 Main Active Mode 2 8MHz fXIN = 12MHz 2.5 ISTOP−VDD Main Active Mode 4 5 VDD 6 (V) Sub Active Mode2 TA=25°C fXIN = 12MHz, 8MHz, 4MHz 0 2 3 4 ISLEEP−VDD IDD (µA) 500 20 175 15 250 10 125 5 5 VDD 6 (V) Sub Active Mode2 TA=25°C fXIN = 12MHz, 8MHz, 4MHz 0 2 3 4 5 VDD 6 (V) 0 2 3 4 5 VDD 6 (V) * Main Active mode : System clock(Main) * Sub Active mode1 : System clock(Sub) (at main clock ON, sub clock ON) * Sub Active mode2 : System clock(Sub) (at main clock OFF, sub clock ON) 22 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 fXIN Operating Area (MHz) TA= -40~85°C 16 Actual Operating Area 2.2~6.5V @ (0.1~8MHz) 3.0~6.5V @ (0.1~16MHz) 14 12 10 8 Spec Operating Area 2.7~5.5V @ (0.4~8MHz) 4.5~5.5V @ (0.4~12MHz) 6 4 2 0 1 MAR. 2005 Ver 0.2 2 3 4 5 6 7 VDD (V) 23 MC80F0424/0432/0448 Preliminary 8. MEMORY ORGANIZATION The MC80F0424/0432/0448 has separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 48K bytes of Program memo- ry. Data memory can be read and written to up to 1024 bytes including the stack area. 8.1 Registers This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. PCH A ACCUMULATOR X X REGISTER Y Y REGISTER SP STACK POINTER PCL PROGRAM COUNTER PSW PROGRAM STATUS WORD executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 100H to 1FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “FFH” is used. Bit 15 Stack Address (100H ~ 1FFH) 8 7 Bit 0 01H SP 00H~FFH Hardware fixed Figure 8-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Y Y A A Two 8-bit Registers can be used as a “YA” 16-bit Register Figure 8-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore). Note: The Stack Pointer must be initialized by software because its value is undefined after Reset. Example: To initialize the SP LDX #0FFH TXSP ; SP ← FFH Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is “0” and is cleared by any other result. Generally, SP is automatically updated when a subroutine call is 24 MAR. 2005 Ver 0.2 Preliminary PSW MSB N V G B H NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when G=1, page is selected to “page 1” BRK FLAG I Z MC80F0424/0432/0448 LSB C RESET VALUE: 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] MAR. 2005 Ver 0.2 This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned 100H to 1FFH. It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to “1” when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or 128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag. 25 MC80F0424/0432/0448 Preliminary At acceptance of interrupt At execution of a CALL/TCALL/PCALL 01FF Push down 01FF PCH 01FE PCL 01FD 01FD PSW 01FC 01FC 01FE PCH PCL At execution of RET instruction Push down 01FF PCH 01FE PCL At execution of RET instruction 01FF PCH 01FE PCL 01FD 01FD PSW 01FC 01FC Pop up SP before execution 01FF 01FF 01FD 01FC SP after execution 01FD 01FC 01FF 01FF At execution of PUSH instruction PUSH A (X,Y,PSW) 01FF A 01FE Push down Pop up At execution of POP instruction POP A (X,Y,PSW) 01FF A 01FE 01FD 01FD 01FC 01FC Pop up 0100H Stack depth 01FFH SP before execution 01FF 01FE SP after execution 01FE 01FF Figure 8-4 Stack Operation 8.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 24/32/48K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5, shows a map of Program Memory. After reset, the 26 CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6. As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program MAR. 2005 Ver 0.2 Preliminary . MC80F0424/0432/0448 Example: Usage of TCALL LDA 4000H FFC0H FFDFH FFE0H FFFFH TCALL area Interrupt Vector Area MC80F0448, 48K ROM MC80F0424, 24K ROM FEFFH FF00H PCALL area A000H MC80F0432, 32K ROM 8000H Figure 8-5 Program Memory Map Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7. #5 TCALL 0FH : : ;1BYTE INSTRUCTION ;INSTEAD OF 3 BYTES ;NORMAL CALL ; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B 1 ;TCALL ADDRESS AREA The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFCH. The interrupt service locations spaces 2-byte interval: 0FFFAH and 0FFFBH for External Interrupt 1, 0FFFCH and 0FFFDH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory. Address 0FFE0H E2 Vector Area Memory Basic Interval Timer Watch / Watchdog Timer Interrupt E4 A/D Converter E6 Timer/Counter 4 Interrupt E8 Timer/Counter 3 Interrupt EA Timer/Counter 2 Interrupt EC Timer/Counter 1 Interrupt EE Timer/Counter 0 Interrupt F0 Serial Input/Output (SIO) F2 UART1 F4 UART0 F6 External Interrupt 3 F8 External Interrupt 2 FA External Interrupt 1 FC External Interrupt 0 FE RESET Figure 8-6 Interrupt Vector Area MAR. 2005 Ver 0.2 27 MC80F0424/0432/0448 Address 0FF00H Preliminary PCALL Area Memory Address PCALL Area (256 Bytes) 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF 0FFFFH Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * NOTE: * means that the BRK software interrupt is using same address with TCALL0. Figure 8-7 PCALL and TCALL Memory Area PCALL→ rel TCALL→ n 4F35 4A PCALL 35H TCALL 4 4A 4F 01001010 35 ~ ~ ~ ~ ~ ~ 0D125H ➊ ~ ~ NEXT Reverse PC: 11111111 11010110 FH FH DH 6H 0FF00H 0FF35H 0FFFFH 28 NEXT ➌ 0FF00H 0FFD6H 25 0FFD7H D1 ➋ 0FFFFH MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 Example: The usage software example of Vector address for MC80F0448. ;Interrupt Vector Table ORG 0FFE0H DW BIT_TIMER DW WATCH_WDT DW ADC DW TIMER4 DW TIMER3 DW TIMER2 DW TIMER1 DW TIMER0 DW SIO DW UART1 DW UART0 DW INT3 DW INT2 DW INT1 DW INT0 DW RESET ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; BIT WDT & WT AD Converter Timer-4 Timer-3 Timer-2 Timer-1 Timer-0 Serial Interface UART1 Rx/Tx UART0 Rx/Tx Ext Int.3 Ext Int.2 Ext Int.1 Ext Int.0 Reset ORG 04000H ; 48K bytes ROM Start address ;******************************************* ; MAIN PROGRAM * ;******************************************* RESET: DI ;Disable All Interrupt RAMCLEAR: LDX #00H ;USER RAM START ADDRESS LOAD ! LDY #0 RAMCLR1: LDA #00H ;Page0 Ram Clear(0000h ~ 00BFh) STA {X}+ ; CMPX #0C0H ; BNE RAMCLR1 ; INC STY SETG Y !RPR LDX #00H LDA STA CMPX BNE #00H {X}+ #00H RAMCLR2 INC CMPY BCS Y #6 RAMCLR3 ; ;Page1 Ram Select ;G-FLAG SET ! RAMCLR2: STY SETG ;Page1 ~ Page5 Clear(0100h ~ 04FFh) !RPR BRA RAMCLR2 RAMCLR3: STY SETG LDA STA CMPX BNE !RPR #00H {X}+ #40H RAMCLR3 CLRG LDX TXSP ;Page6 Clear(0600h ~ 063Fh) ;A <-- #0 ; ;G-FLAG CLEAR ! #0FFH MAR. 2005 Ver 0.2 ;Initial Stack Point (01FFh) 29 MC80F0424/0432/0448 Preliminary 8.3 Data Memory Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into three groups, a user RAM, control registers, and Stack memory. Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. 0000H User Memory (192Bytes) 00BFH 00C0H 00FFH 0100H PAGE0 (When “G-flag=0”, this page0 is selected) Control Registers (64Bytes) 01FFH 0200H 02FFH 0300H 03FFH 0400H 04FFH 0500H 05FFH 0600H 063FH 0640H User Memory or Stack Area (256Bytes) PAGE1 User Memory User Memory (256Bytes) (256Bytes) PAGE2 User Memory (256Bytes) PAGE3 User Memory (256Bytes) PAGE4 User Memory (256Bytes) PAGE5 User Memory (64Bytes) PAGE6 Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction, for example “LDM”. Example; To write at CKCTLR LDM CLCTLR,#0AH ;Divide ratio(÷32) Stack Area Not Used 0EBFH 0EC0H The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. Extended SFR (64Bytes) 0EFFH When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. Figure 8-8 Data Memory Map User Memory The MC80F0424/0432/0448 has 1.5kbytes for the user memory (RAM). RAM pages are selected by RPR (See Figure 8-9). The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 26. Note: After setting RPR(RAM Page Select Register), be sure to execute SETG instruction. When executing CLRG instruction, be selected PAGE0 regardless of RPR. RPR 7 6 5 4 3 R/W 2 R/W 1 R/W 0 - - - - - RPR2 RPR1 RPR0 ADDRESS: 0E1H INITIAL VALUE: -----000B RAM page select 000 : PAGE0 001 : PAGE1 010 : PAGE2 011 : PAGE3 100 : PAGE4 101 : PAGE5 110 : PAGE6 Figure 8-9 RPR(RAM Page Select Register) 30 MAR. 2005 Ver 0.2 Preliminary Address Register Name Symbol MC80F0424/0432/0448 R/W Initial Value Addressing mode 7 6 5 4 3 2 1 0 R0 R/W 0 0 0 0 0 0 0 0 byte, bit1 R0IO W 0 0 0 0 0 0 0 0 byte2 R1 R/W 0 0 0 0 0 0 0 0 byte, bit R1IO W 0 0 0 0 0 0 0 0 byte R2 R/W - - - - 0 0 0 0 byte, bit R2IO W - - - - 0 0 0 0 byte R3 R/W 0 0 0 0 0 0 0 0 byte, bit R3IO W 0 0 0 0 0 0 0 0 byte R4 R/W 0 0 0 0 0 0 0 0 byte, bit R4IO W 0 0 0 0 0 0 0 0 byte R5 R/W - - - 0 0 0 0 0 byte, bit R5IO W - - - 0 0 0 0 0 byte R6 R/W 0 0 0 0 0 0 0 0 byte, bit R6IO W 0 0 0 0 0 0 0 0 byte R7 R/W 0 0 0 0 0 0 0 0 byte, bit R7 port I/O direction register R7IO W 0 0 0 0 0 0 0 0 byte Timer 0 mode control register TM0 R/W - - 0 0 0 0 0 0 byte, bit T0 R 0 0 0 0 0 0 0 0 Timer 0 data register TDR0 W 1 1 1 1 1 1 1 1 Timer 0 capture data register CDR0 R 0 0 0 0 0 0 0 0 Timer 1 mode control register TM1 R/W 0 0 0 0 0 0 0 0 TDR1 W 1 1 1 1 1 1 1 1 T1PPR W 1 1 1 1 1 1 1 1 T1 R 0 0 0 0 0 0 0 0 Timer 1 PWM duty register T1PDR R/W 0 0 0 0 0 0 0 0 Timer 1 capture data register CDR1 R 0 0 0 0 0 0 0 0 T1PWHR W - - - - 0 0 0 0 byte TM2 R/W - - 0 0 0 0 0 0 byte, bit T2 R 0 0 0 0 0 0 0 0 Timer 2 data register TDR2 W 1 1 1 1 1 1 1 1 Timer 2 capture data register CDR2 R 0 0 0 0 0 0 0 0 Timer 3 mode control register TM3 R/W 0 0 0 0 0 0 0 0 00C0 R0 port data register 00C1 R0 port I/O direction register 00C2 R1 port data register 00C3 R1 port I/O direction register 00C4 R2 port data register 00C5 R2 port I/O direction register 00C6 R3 port data register 00C7 R3 port I/O direction register 00C8 R4 port data register 00C9 R4 port I/O direction register 00CA R5 port data register 00CB R5 port I/O direction register 00CC R6 port data register 00CD R6 port I/O direction register 00CE R7 port data register 00CF 00D0 Timer 0 register 00D1 00D2 Timer 1 data register 00D3 Timer 1 register 00D5 Timer 1 PWM high register 00D6 Timer 2 mode control register Timer 2 register 00D7 00D8 byte, bit byte Timer 1 PWM period register 00D4 byte byte byte byte, bit Table 8-1 Control Registers MAR. 2005 Ver 0.2 31 MC80F0424/0432/0448 Address Preliminary Register Name Symbol R/W Initial Value Addressing mode 7 6 5 4 3 2 1 0 Timer 3 data register TDR3 W 1 1 1 1 1 1 1 1 T3PPR W 1 1 1 1 1 1 1 1 T3 R 0 0 0 0 0 0 0 0 Timer 3 PWM duty register T3PDR R/W 0 0 0 0 0 0 0 0 Timer 3 capture data register CDR3 R 0 0 0 0 0 0 0 0 T3PWHR W - - - - 0 0 0 0 byte byte, bit 00D9 byte Timer 3 PWM period register Timer 3 register 00DA 00DB Timer 3 PWM high register 00DC Timer 4 mode control register TM4 R/W - - 0 0 0 0 0 0 Timer 4 low register T4L R 0 0 0 0 0 0 0 0 Timer 4 low data register TDR4L W 1 1 1 1 1 1 1 1 Timer 4 capture low data register CDR4L R 0 0 0 0 0 0 0 0 T4H R 0 0 0 0 0 0 0 0 Timer 4 high data register TDR4H W 1 1 1 1 1 1 1 1 Timer 4 capture high data register CDR4H R 0 0 0 0 0 0 0 0 00DD Timer 4 high register 00DE byte byte byte 00DF Interrupt flag register IFR R/W - - 0 0 0 0 0 0 byte, bit 00E0 Buzzer driver register BUZR W 1 1 1 1 1 1 1 1 byte 00E1 RAM page selection register RPR R/W - - - - - 0 0 0 byte, bit 00E2 SIO mode control register SIOM R/W 0 0 0 0 0 0 0 1 byte, bit 00E3 SIO data shift register SIOR R/W Undefined byte, bit 00E4 Reserved 00E5 Reserved 00E6 UART0 mode register ASIMR R/W 0 0 0 0 - 0 0 - byte, bit 00E7 UART0 status register ASISR R - - - - - 0 0 0 byte 00E8 UART0 Baud rate generator control register BRGCR R/W - 0 0 1 0 0 0 0 byte, bit UART0 Receive buffer register RXR R 0 0 0 0 0 0 0 0 UART0 Transmit shift register TXR W 1 1 1 1 1 1 1 1 00EA Interrupt enable register high IENH R/W 0 0 0 0 0 0 0 0 byte, bit 00EB Interrupt enable register low IENL R/W 0 0 0 0 0 0 0 0 byte, bit 00EC Interrupt request register high IRQH R/W 0 0 0 0 0 0 0 0 byte, bit 00ED Interrupt request register low IRQL R/W 0 0 0 0 0 0 0 0 byte, bit 00EE Interrupt edge selection register IEDS R/W 0 0 0 0 0 0 0 0 byte, bit 00EF A/D converter mode control register ADCM R/W 0 0 0 0 0 0 0 1 byte, bit 00F0 A/D converter result high register ADCRH R 00F1 A/D converter result low register ADCRL R 00E9 byte 0 1 1 Undefined Undefined byte byte Table 8-1 Control Registers 32 MAR. 2005 Ver 0.2 Preliminary Address Register Name Symbol MC80F0424/0432/0448 R/W Initial Value Addressing mode 7 6 5 4 3 2 1 0 Basic interval timer register BITR R Undefined CKCTLR W 0 - 0 1 0 1 1 1 System clock mode register SCMR R/W - - - - - 0 0 0 Watch dog timer register WDTR W 0 1 1 1 1 1 1 1 WDTDR R Undefined 00F2 byte Clock control register 00F3 00F4 byte, bit byte Watch dog timer data register 00F5 Stop & sleep mode control register SSCR W 0 0 0 0 0 0 0 0 byte 00F6 Watch timer mode register WTMR R/W 0 - - 0 0 0 0 0 byte, bit 00F7 PFD control register PFDR R/W - - - - - 0 0 0 byte, bit 00F8 Port selection register 0 PSR0 W 0 0 0 0 0 0 0 0 byte 00F9 Port selection register 1 PSR1 W - - - - 0 0 0 0 byte 00FA Reserved 00FB Reserved 00FC Pull-up selection register 0 PU0 W 0 0 0 0 0 0 0 0 byte 00FD Pull-up selection register 1 PU1 W 0 0 0 0 0 0 0 0 byte 00FE Pull-up selection register 4 PU4 W 0 0 0 0 0 0 0 0 byte 00FF Pull-up selection register 7 PU7 W 0 0 0 0 0 0 0 0 byte 0EE6 UART1 mode register ASIMR1 R/W 0 0 0 0 - 0 0 - byte, bit 0EE7 UART1 status register ASISR1 R - - - - - 0 0 0 byte 0EE8 UART1 Baud rate generator control register BRGCR1 R/W - 0 0 1 0 0 0 0 byte, bit UART1 Receive buffer register RXR1 R 0 0 0 0 0 0 0 0 UART1 Transmit shift register TXR1 W 1 1 1 1 1 1 1 1 0EE9 byte Table 8-1 Control Registers 1. The ‘byte, bit’ means registers are controlled by both bit and byte manipulation instruction. Caution) The R/W register except T1PDR and T3PDR are both can be byte and bit manipulated. 2. The ‘byte’ means registers are controlled by only byte manipulation instruction. Do not use bit manipulation instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. *The mark of ‘-’ means this bit location is reserved. MAR. 2005 Ver 0.2 33 MC80F0424/0432/0448 Address Name Preliminary Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T0CN T0ST T1CN T1ST C0H R0 R0 Port Data Register C1H R0IO R0 Port Direction Register C2H R1 R1 Port Data Register C3H R1IO R1 Port Direction Register C4H R2 - - - - R2 Port Data Register C5H R2IO - - - - R2 Port Direction Register C6H R3 R3 Port Data Register C7H R3IO R3 Port Direction Register C8H R4 R4 Port Data Register C9H R4IO R4 Port Direction Register CAH R5 - - - R5 Port Data Register CBH R5IO - - - R5 Port Direction Register CCH R6 R6 Port Data Register CDH R6IO R6 Port Direction Register CEH R7 R7 Port Data Register CFH R7IO R7 Port Direction Register D0H TM0 D1H T0/TDR0/ CDR0 D2H TM1 D3H TDR1/ T1PPR D4H T1/CDR1/ Timer1 Register / Timer1 Capture Data Register / Timer1 PWM Duty Register T1PDR D5H PWM1HR - - - - D6H TM2 - - CAP2 T2CK2 D7H T2/TDR2/ CDR2 D8H TM3 D9H TDR3/ T3PPR DAH T3/CDR3/ Timer3 Register / Timer3 Capture Data Register / Timer3 PWM Duty Register T3PDR DBH PWM3HR - - - - DCH TM4 - - CAP4 T4CK2 DDH T4L/ TDR4L/ CDR4L - - CAP0 T0CK2 T0CK1 T0CK0 Timer0 Register / Timer0 Data Register / Timer0 Capture Data Register POL 16BIT PWM1E CAP1 T1CK1 T1CK0 Timer1 Data Register / Timer1 PWM Period Register Timer1 PWM High Register T2CK1 T2CK0 T2CN T2ST T3CN T3ST Timer2 Register / Timer2 Data Register / Timer2 Capture Data Register POL 16BIT PWM3E CAP3 T3CK1 T3CK0 Timer3 Data Register / Timer3 PWM Period Register Timer3 PWM High Register T4CK1 T4CK0 T4CN T4ST Timer4 Register Low / Timer4 Data Register Low / Timer4 Capture Data Register Low Table 8-2 Control Register Function Description 34 MAR. 2005 Ver 0.2 Preliminary Address Bit 7 Name DEH T4H/ TDR4H/ CDR4H DFH IFR E0H BUZR E1H Bit 6 Bit 5 Bit 4 MC80F0424/0432/0448 Bit 3 Bit 2 Bit 1 Bit 0 Timer4 Register High / Timer4 Data Register High / Timer4 Capture Data Register High - - IFRX0 IFTX0 IFRX1 IFTX1 IFWT IFWDT BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 RPR - - - - - RPR2 RPR1 RPR0 E2H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E3H SIOR SIO Data Shift Register E4H Reserved E5H Reserved E6H ASIMR TXE RXE PS1 PS0 - SL ISRM - E7H ASISR - - - - - PE FE OVE E8H BRGCR - TPS2 TPS1 TPS0 MLD3 MLD2 MLD1 MLD0 E9H RXR UART0 Receive Buffer Register TXR UART0 Transmit Shift Register EAH IENH INT0E INT1E INT2E INT3E UART0E UART1E SIOE T0E EBH IENL T1E T2E T3E T4E ADCE WDTE WTE BITE ECH IRQH INT0IF INT1IF INT2IF INT3IF UART0IF UART1IF SIOIF T0IF EDH IRQL T1IF T2IF T3IF T4IF ADCIF WDTIF WTIF BITIF EEH IEDS IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L EFH ADCM ADEN ADCK ADS3 ADS2 ADS1 ADS0 ADST ADSF F0H ADCRH PSSEL1 PSSEL0 ADC8 - - - F1H ADCRL ADC Result Register Low BITR1 Basic Interval Timer Data Register F2H F3H F4H CKCTLR1 ADC Result Reg. High ADRST - RCWDT WDTON BTCL BTS2 BTS1 BTS0 SCMR - - - - - MCC CS1 CS0 WDTR WDTCL 7-bit Watchdog Timer Register WDTDR Watchdog Timer Data Register (Counter Register) F5H SSCR Stop & Sleep Mode Control Register F6H WTMR WTEN - - WTIN2 WTIN1 WTIN0 WTCK1 WTCK0 F7H PFDR - - - - - PFDEN PFDM PFDS F8H PSR0 PWM3O PWM1O EC1E EC0E INT3E INT2E INT1E INT0E F9H PSR1 - - - - XTEN BUZO T2O T0O FAH Reserved FBH Reserved FCH PU0 R0 Pull-up Selection Register FDH PU1 R1 Pull-up Selection Register FEH PU4 R4 Pull-up Selection Register Table 8-2 Control Register Function Description MAR. 2005 Ver 0.2 35 MC80F0424/0432/0448 Address FEH Bit 7 Name PU4 Preliminary Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R4 Pull-up Selection Register EE6H ASIMR1 TXE RXE PS1 PS0 - SL ISRM - EE7H ASISR1 - - - - - PE FE OVE EE8H BRGCR1 - TPS2 TPS1 TPS0 MLD3 MLD2 MLD1 MLD0 EE9H RXR1 UART1 Receive Buffer Register TXR1 UART1 Transmit Shift Register Table 8-2 Control Register Function Description 1. The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be accessed by register operation instruction such as "LDM dp,#imm". 8.4 Addressing Mode The MC800 series MCU uses six addressing modes; • Register addressing When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. • Immediate addressing Example: G=1 • Direct page addressing E45535 LDM 35H,#55H • Absolute addressing • Indexed addressing • Register-indirect addressing 8.4.1 Register Addressing ➊ Register addressing accesses the A, X, Y, C and PSW. 8.4.2 Immediate Addressing → #imm data ← 55H data 0135H ~ ~ 0F100H ~ ~ ➋ E4 0F101H 55 0F102H 35 In this mode, second byte (operand) is accessed as a data immediately. Example: 0435 ADC 8.4.3 Direct Page Addressing → dp #35H In this mode, a address is specified within direct page. MEMORY 04 35 36 Example; G=0 A+35H+C → A MAR. 2005 Ver 0.2 Preliminary C535 LDA 35H ;A ←RAM[35H] 35H data 983501 ~ ~ ;A ←ROM[135H] !0135H ➌ ~ ~ data → A ➊ INC data 135H ➋ ~ ~ MC80F0424/0432/0448 ➋ ~ ~ data+1 → data 0E550H C5 0F100H 98 0E551H 35 ➊ 0F101H 35 address: 0135 0F102H 01 8.4.4 Absolute Addressing → !abs 8.4.5 Indexed Addressing Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. X indexed direct page (no offset) → {X} ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1 D4 LDA {X} ;ACC←RAM[X]. Example; 0735F0 ADC ;A ←ROM[0F035H] !0F035H 115H data 0F035H ~ ~ 0F100H ➊ A+data+C → A ➋ ~ ~ ➋ ~ ~ data ~ ~ data → A ➊ D4 0E550H 07 0F101H 35 0F102H F0 address: 0F035 X indexed direct page, auto increment→ {X}+ The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag. In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H DB MAR. 2005 Ver 0.2 LDA {X}+ 37 MC80F0424/0432/0448 Preliminary D500FA 35H LDA !0FA00H+Y ➋ data ~ ~ ~ ~ data → A ➊ 36H → X 0F100H D5 0F101H 00 0F102H FA ➊ 0FA00H+55H=0FA55H DB ~ ~ ~ ~ ➋ data 0FA55H data → A ➌ X indexed direct page (8 bit offset) → dp+X This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H C645 LDA 8.4.6 Indirect Addressing Direct page indirect → [dp] Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y. 45H+X JMP, CALL Example; G=0 3F35 3AH JMP [35H] data ➌ ~ ~ ➋ ~ ~ 0E550H C6 0E551H 45 data → A ➊ 35H 0A 36H E3 ~ ~ 45H+0F5H=13AH 0E30AH ~ ~ 0FA00H ➊ NEXT ~ ~ Y indexed direct page (8 bit offset) → dp+Y ➋ jump to address 0E30AH ~ ~ 3F 35 This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. X indexed indirect → [dp+X] Y indexed absolute → !abs+Y Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. Sets the value of 16-bit absolute address plus Y-register data as Memory.This addressing mode can specify memory in whole area. Example; Y=55H 38 ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H MAR. 2005 Ver 0.2 Preliminary 1625 ADC MC80F0424/0432/0448 Absolute indirect → [!abs] [25H+X] The program jumps to address specified by 16-bit absolute address. 35H 05 36H E0 JMP 0E005H Example; G=0 ➋ 0E005H ~ ~ ~ ~ 1F25E0 JMP [!0C025H] ➊ 25 + X(10) = 35H data ~ ~ ~ ~ PROGRAM MEMORY 0FA00H 16 25 ➌ A + data + C → A 0E025H 25 0E026H E7 ~ ~ Y indexed indirect → [dp]+Y þ Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Yregister data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H 1725 ADC 05 26H E0 ~ ~ ~ ~ 0FA00H jump to address 0E30AH ~ ~ 1F 25 E0 ~ ~ ➋ ➊ 0E005H + Y(10) = 0E015H data ~ ~ 0FA00H NEXT ➋ [25H]+Y 25H 0E015H 0E725H ~ ~ ~ ~ 17 25 ➌ A + data + C → A MAR. 2005 Ver 0.2 39 MC80F0424/0432/0448 Preliminary 9. I/O PORTS The MC80F0424/0432/0448 has eight ports (R0, R1, R2, R3, R4, R5, R6 and R7). These ports pins may be multiplexed with an alternate function for the peripheral features on the device. R3 port can drive maximum 20mA of high current in output low state, so it can directly drive LED device. All pins have data direction registers which can define these ports as output or input. A “1” in the port direction register configure the corresponding port pin as output. Conversely, write “0” to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write “55H” to address 0C1H (R0 port direction register) during initial setting as shown in Figure 9-1. R0 R07 R06 R05 R04 R03 R02 R01 R00 Input / Output data R0 Direction Register ADDRESS: 0C1H RESET VALUE: 00H R0IO All the port direction registers in the MC80F0424/0432/0448 have 0 written to them by reset function. On the other hand, its initial status is input. WRITE “55H” TO PORT R0 DIRECTION REGISTER ADDRESS: 0C0H RESET VALUE: 00H R0 Data Register Port Direction 0: Input 1: Output R0 Pull-up Selection Register ADDRESS: 0FCH RESET VALUE: 00H PU0 0C0H R0 data 0C1H R0 direction 0C2H R1 data 0C3H R1 direction 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 BIT Pull-up Resister Selection 0: Disable 1: Enable I O I O I O I O PORT 7 6 5 4 3 2 1 0 I: INPUT PORT O: OUTPUT PORT Figure 9-1 Example of port I/O assignment R0 and R0IO register: R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0IO register (address 0C1H). The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 0 (PU0). 40 R1 and R1IO register: R1 is an 8-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R1IO register (address 0C3H). The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 1 (PU1). In addition, Port R1 is multiplexed with various special features. The control register PSR0 (address 0F8H) and PSR1 (address 0F9H) controls the selection of alternate function. After reset, this value is “0”, port may be used as normal I/O port. To use alternate function such as external interrupt, event counter input or timer clock output, write “1” in the corresponding bit of PSR0 or PSR1. Regardless of the direction register R1IO, PSR0 or PSR1 is selected to use as alternate functions, port pin can be used as a corresponding alternate features. Port Pin Alternate Function R10 R11 R12 R13 R14 R15 R16 R17 INT0 (External Interrupt 0) INT1 (External Interrupt 1) INT2 (External Interrupt 2) BUZO (Square-wave output for buzzer) T0O (Timer 0 Clock-out) EC0 (Event counter input to Counter 0) - MAR. 2005 Ver 0.2 Preliminary ADDRESS: 0C2H RESET VALUE: 00H R1 Data Register R1 R17 R16 R15 R14 R13 R12 R11 R10 Input / Output data R1 Direction Register MC80F0424/0432/0448 R2 and R2IO register: R2 is an 4-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R2IO register (address 0C5H). In addition, Port R2 is multiplexed with various special features. The control register PSR1 (address 0F9H) controls the selection of alternate function. After reset, this value is “0”, port may be used as normal I/O port. To use alternate function such as sub clock input and sub clock output, write “1” in the corresponding bit of PSR1. ADDRESS: 0C3H RESET VALUE: 00H Port Pin R1IO Port Direction 0: Input 1: Output R1 Pull-up Selection Register Alternate Function SXIN (sub clock input) SXOUT (sub clock output) - R20 R21 R22 R23 ADDRESS: 0FDH RESET VALUE: 00H PU1 ADDRESS: 0C4H RESET VALUE: ----0000B R2 Data Register Pull-up Resister Selection 0: Disable 1: Enable R2 - - - - R23 R22 R21 R20 Input / Output data ADDRESS: 0F8H RESET VALUE: 0000 0000B PSR0 PWM3 PWM1 EC1E EC0E INT3E INT2E INT1E INT0E Port / INT Selection 0: R10, R11,R12, R50 1: INT0, INT1,INT2, INT3 R2 Direction Register R2IO ADDRESS: 0F9H RESET VALUE: ---- 0000B PSR1 - - - - XTEN BUZO T2O T0O Timer2/0 Output 0 : R52/R514 Port 1 : Timer2/0 Output R13/BUZO Selection 0: R13 port (Turn off buzzer) 1: BUZO port (Turn on buzzer) Sub Clock Selection 0: R21,R22 Port 1: SXin, SXout Port MAR. 2005 Ver 0.2 - - - Port Direction 0: Input 1: Output Port / EC Selection 0: R15, R51 1: EC0, EC1 Port / PWM3(1) Selection 0: R54 (P53) 1: PWM3O/T3O port (PWM1O/T1O port) - ADDRESS: 0C5H RESET VALUE: ----0000B R3 and R3IO register: R3 is an 8-bit CMOS bidirectional I/O port (address 0C6H). Each I/O pin can independently used as an input or an output through the R3IO register (address 0C7H). In addition, Port R3 is multiplexed with various special features. After reset, this value is "0", port may be used as normal I/O port. To use alternate function, write “1” in the corresponding bit of ASIMR1 and BRGCR1 register. Port Pin R30 R31 R32 R33 R33 R33 R33 R37 Alternate Function ACLK1 (UART1 clock input) RxD1 (UART1 data input) TxD1(UART1 data output)- 41 MC80F0424/0432/0448 ADDRESS: 0C6H RESET VALUE: 00H R3 Data Register R3 Preliminary R37 R36 R35 R34 R33 R32 R31 R30 ADDRESS: 0C8H RESET VALUE: 00H R4 Data Register R4 R47 R46 R45 R44 R43 R42 R41 R40 Input / Output data Input / Output data R3 Direction Register ADDRESS: 0C7H RESET VALUE: 00H ADDRESS: 0C9H RESET VALUE: 00H R4 Direction Register R4IO R3IO Port Direction 0: Input 1: Output Port Direction 0: Input 1: Output R4 and R4IO register: R4 is an 8-bit CMOS bidirectional I/O port (address 0C8H). Each I/O pin can independently used as an input or an output through the R4IO register (address 0C9H). The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 4 (PU4). R4 Pull-up Selection Register ADDRESS: 0FEH RESET VALUE: 00H PU4 Pull-up Resister Selection 0: Disable 1: Enable In addition, Port R4 is multiplexed with various special features. After reset, this value is “0”, port may be used as normal I/O port. To use alternate function, write “1” in the corresponding bit of ASIMR and BRGCR register. Port Pin Alternate Function R40 R41 R42 R43 R44 R45 R46 R47 SCK (SIO clock input/output) SI (SIO data input) SO (Serial1 data output) ACLK (Asynchronous serial clock input) RxD (Asynchronous serialdata input) TxD (Asynchronous serial data output) Port Pin Alternate Function R50 R51 R52 R53 R54 INT3 (External Interrupt 3) EC1 (Event counter input to Counter 2) T2O (Timer 2 Clock-out) PWM1O (PWM1 output) / T1O PWM3O (PWM3 output) / T3O ADDRESS: 0CAH RESET VALUE: ---00000B R5 Data Register R5 - - - R54 R53 R52 R51 R50 R5 and R5IO register: R5 is an 5-bit CMOS bidirectional I/O port (address 0CAH). Each I/O pin can independently used as an input or an output through the R5IO register (address 0CBH). In addition, Port R5 is multiplexed with various special features. The control register PSR0 (address 0F8H) and PSR1 (address 0F9H) controls the selection of alternate function. After reset, this value is “0”, port may be used as normal I/O port. To use alternate function such as external interrupt, event counter input, timer clock output or PWM output, write “1” in the corresponding bit of PSR0 or PSR1. Regardless of the direction register R5IO, PSR0 or PSR1 is selected to use as alternate functions, port pin can be used as a corresponding alternate features. 42 Input / Output data R5 Direction Register R5IO - - ADDRESS: 0CBH RESET VALUE: ---00000B - Port Direction 0: Input 1: Output MAR. 2005 Ver 0.2 Preliminary R6 and R6IO register: R6 is an 8-bit CMOS bidirectional I/O port (address 0CCH). Each I/O pin can independently used as an input or an output through the R6IO register (address 0CDH). MC80F0424/0432/0448 Port Pin In addition, Port R6 is multiplexed with AD converter analog input AN0~AN7. Port Pin R60 R61 R62 R63 R64 R65 R66 R67 R70 R71 R72 R73 R74 R75 R76 R77 Alternate Function AN0 (ADC input channel 0) AN1 (ADC input channel 1) AN2 (ADC input channel 2) AN3 (ADC input channel 3) AN4 (ADC input channel 4) AN5 (ADC input channel 5) AN6 (ADC input channel 6) AN7 (ADC input channel 7) R6IO (address CDH) controls the direction of the R6 pins, except when they are being used as analog input channels. The user don’t have to keep the pins configured as inputs when using them as analog input channels, because the analog input mode is activated by the setting of ADC enable bit of ADCM register and ADC channel selection. Alternate Function AN8 (ADC input channel 8) AN9 (ADC input channel 9) AN10 (ADC input channel 10) AN11 (ADC input channel 11) AN12 (ADC input channel 12) AN13 (ADC input channel 13) AN14 (ADC input channel 14) AN15 (ADC input channel 15) R7IO (address CFH) controls the direction of the R7 pins, except when they are being used as analog input channels. The user don’t have to keep the pins configured as inputs when using them as analog input channels, because the analog input mode is activated by the setting of ADC enable bit of ADCM register and ADC channel selection. R7 Data Register R6 Data Register R6 ADDRESS: 0CCH RESET VALUE: 00H R7 ADDRESS: 0CEH RESET VALUE: 00H R77 R76 R75 R74 R73 R72 R71 R70 R67 R66 R65 R64 R63 R62 R61 R60 Input / Output data Input / Output data R7 Direction Register R6 Direction Register ADDRESS: 0CDH RESET VALUE: 00H R7IO R6IO Port Direction 0: Input 1: Output Port Direction 0: Input 1: Output R7 Pull-up Selection Register R7 and R7IO register: R7 is an 8-bit CMOS bidirectional I/O port (address 0CEH). Each I/O pin can independently used as an input or an output through the R7IO register (address 0CFH). The on-chip pull-up resistor can be connected to them in 1-bit units with a R7 pull-up selection register (PU7). ADDRESS: 0CFH RESET VALUE: 00H ADDRESS: 0FFH RESET VALUE: 00H PU7 Pull-up Resister Selection 0: Disable 1: Enable In addition, Port R7 is multiplexed with AD converter analog input channel AN8~AN15. MAR. 2005 Ver 0.2 43 MC80F0424/0432/0448 Preliminary 10. CLOCK GENERATOR As shown in Figure 10-1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains two oscillators which are main-frequency clock oscillator and a sub-frequency clock oscillator. The system clock operation can be easily obtained by attaching a crystal or a ceramic resonator between the XIN and XOUT pin and the SXIN and SXOUT pin, respectively. The system clock can also be obtained from the external oscillator. In this case, it is necessary to input a external clock signal to the XIN pin and open the XOUT pin. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. system clock control register (SCMR). The registers are shown in Figure 10-2. In case of selecting sub clock, to oscillate or stop the main clock is decided by MCC bit (SCMR.2). On the initial reset, internal system clock is PS1 which is the fastest and other clock can be provided by bit0 and bit1 of SCMR. The clock among the not-divided original clock and clocks divided by 1, 2, 4,..., up to 4096 can be provided to the peripheral block, Peripheral clock is enabled or disabled by STOP instruction. The peripheral clock is controlled by clock control register (CKCTLR). See "11. BASIC INTERVAL TIMER" on page 46 for details. The subclock oscillation connected to SXIN and SXOUT pin is enabled by the set of corresponding XTEN bit of PSR1 register (See Figure 10-3). The internal system clock can be selected by bit0 and bit1 of the STOP MCC SLEEP Main OSC Stop CS1 CS0 XIN XOUT OSC Circuit SXIN SXOUT Sub OSC Circuit Clock Pulse Generator (÷2) fEX MUX Sub OSC Run Internal system clock PRESCALER XTEN (PSR1 reg.) PS0 ÷1 PS1 ÷2 PS2 ÷4 PS3 ÷8 PS4 ÷16 PS5 ÷32 PS6 ÷64 PS7 ÷128 PS8 ÷256 PS9 PS10 PS11 PS12 ÷512 ÷1024 ÷2048 ÷4096 *MCC, CS1, CS0 are described in next figure. Peripheral clock fEX (Hz) PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 Frequency 4M 2M 1M 500K 250K 125K 62.5K 31.25K 15.63K 7.183K 3.906K 1.953K 976 period 250n 500n 1u 2u 4u 8u 16u 32u 64u 128u 256u 512u 1.024m 4M Figure 10-1 Block Diagram of Clock Generator 44 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 SCMR (System Clock Mode Register) - - - - - R/W R/W R/W MCC CS1 CS0 ADDRESS: 0F3H INITIAL VALUE: ----_-000B CS[1:0] (System clock control) 00: main clock on 01: main clock on 10: sub clock on 11: Setting prohibited MCC (Main System Clock Oscillation Control) 0: Oscillation possible 1: Oscillation stop Note 1. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system oscillation. A STOP instruction should not be used. Figure 10-2 System Clock Mode Registers ADDRESS: 0F9H RESET VALUE: ----_0000B W PSR1 - - - - W XTEN BUZO W W T2O T0O R14/T0O Selection 0: R14 port (Timer0 output disable) 1: T0O port (Timer0 output enable) R52/T2O Selection 0: R52 port (Timer2 output disable) 1: T2O port (Timer2 output enable) R13/BUZO Selection 0: R13 port (Turn off buzzer) 1: BUZO port (Turn on buzzer) R21,R22/Sub Clock Selection 0: Sub clock (SXIN, SXOUT) oscillation stop 1: Sub clock (SXIN, SXOUT) oscillation enable Figure 10-3 Port Selection Register PSR1 MAR. 2005 Ver 0.2 45 MC80F0424/0432/0448 Preliminary 11. BASIC INTERVAL TIMER The MC80F0424/0432/0448 has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 11-1. In addition, the Basic Interval Timer generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITIF). The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 10-2. When write "1" to bit BTCL of CKCTLR, BITR register is cleared to "0" and restart to count-up. The bit BTCL becomes "0" after one machine cycle by hardware. If the STOP instruction executed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and RC Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7bit timer. Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and address 0F2H is read as a BITR, and written to CKCTLR. Internal RC OSC RCWDT ÷8 ÷16 1 XIN PIN Prescaler ÷32 source clock 8-bit up-counter overflow BITR ÷64 ÷128 Basic Interval Timer Interrupt BITIF 0 MUX [0F2H] ÷256 clear ÷512 ÷1024 0 Select Input clock 3 BTS[2:0] [0F2H] RCWDT Watchdog timer (WDTCK) 1 BTCL CKCTLR Basic Interval Timer clock control register Read RCWDT Internal bus line Figure 11-1 Block Diagram of Basic Interval Timer CKCTLR [2:0] 000 001 010 011 100 101 110 111 Source clock fXIN÷8 fXIN÷16 fXIN÷32 fXIN÷64 fXIN÷128 fXIN÷256 fXIN÷512 fXIN÷1024 Interrupt (overflow) Period (ms) @ fXIN = 8MHz 0.256 0.512 1.024 2.048 4.096 8.192 16.384 32.768 Table 11-1 Basic Interval Timer Interrupt Period 46 MAR. 2005 Ver 0.2 Preliminary 7 CKCTLR 6 - ADRST 5 4 RCWDT WDTON 3 2 1 0 BTCL BTCL BTS2 BTS1 BTS0 MC80F0424/0432/0448 ADDRESS: 0F2H INITIAL VALUE: 0-010111B Basic Interval Timer source clock select 000: fXIN ÷ 8 001: fXIN ÷ 16 010: fXIN ÷ 32 011: fXIN ÷ 64 100: fXIN ÷ 128 101: fXIN ÷ 256 110: fXIN ÷ 512 111: fXIN ÷ 1024 Caution: Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR. Clear bit 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically after one machine cycle, and starts counting. Watchdog timer Enable bit 0: Operate as 7-bit Timer 1: Enable Watchdog Timer operation See the section “Watchdog Timer”. RC Watchdog Selection bit 0: Disable Internal RC Watchdog Timer 1: Enable Internal RC Watchdog Timer Address Fail Reset Selection 0: Enable Address Fail Reset 1: Disable Address Fail Reset 7 6 BITR 5 4 3 BTCL 2 1 0 ADDRESS: 0F2H INITIAL VALUE: Undefined 8-BIT FREE-RUN BINARY COUNTER Figure 11-2 BITR: Basic Interval Timer Mode Register Example 1: Interrupt request flag is generated every 8.192ms at 4MHz. : LDM SET1 EI : CKCTLR,#1BH BITE Example 2: Interrupt request flag is generated every 8.192ms at 8MHz. : LDM SET1 EI : CKCTLR,#1CH BITE MAR. 2005 Ver 0.2 47 MC80F0424/0432/0448 Preliminary 12. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below. LDM LDM LDM STOP NOP NOP : When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is separated from the external oscillator of the XIN pin. It means that the watchdog timer will run, even if the clock on the XIN pin of the device has been stopped, for example, by entering the STOP mode. The other type is a prescaler system clock. CKCTLR,#3FH; enable the RC-OSC WDT WDTR,#0FFH ; set the WDT period SSCR, #5AH ;ready for STOP mode ; enter the STOP mode ; RC-OSC WDT running The RC-WDT oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 33~100uS). The following equation shows the RCWDT oscillated watchdog timer time-out. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as Watchdog timer interrupt or reset the CPU in accordance with the bit WDTON. TRCWDT=CLKRCWDT×28×WDTR + (CLKRCWDT×28)/2 where, CLKRCWDT = 33~100uS In addition, this watchdog timer can be used as a simple 7-bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer, after the bit WDTON set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 machine cycle. TWDT = (WDTR+1) × Interval of BIT clear BASIC INTERVAL TIMER OVERFLOW Watchdog Counter (7-bit) Count source clear “0” WDTCL WDTON in CKCTLR [0F2H] 7-bit compare data WDTIF 7 WDTR to reset CPU “1” enable comparator Watchdog Timer interrupt Watchdog Timer Register [0F4H] Internal bus line Figure 12-1 Block Diagram of Watchdog Timer 48 MAR. 2005 Ver 0.2 Preliminary Watchdog Timer Control counters unless the binary counter is cleared. At this time, when WDTON=1, a reset is generated, which drives the RESET pin to low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (WDTIF) is generated. The WDTON bit is in register CLKCTLR. Figure 12-2 shows the watchdog timer control register. The watchdog timer is automatically disabled after reset. The CPU malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary counter. Clearing the binary counter is repeated within the detection time. The watchdog timer temporarily stops counting in the STOP mode, and when the STOP mode is released, it automatically restarts (continues counting). If the malfunction occurs for any cause, the watchdog timer output will become active at the rising overflow from the binary W 7 WDTR W 6 W 5 W 4 W 3 MC80F0424/0432/0448 W 2 W 1 W 0 ADDRESS: 0F4H INITIAL VALUE: 0111_1111B WDTCL 7-bit compare data Clear count flag 0: Free-run count 1: When the WDTCL is set to “1”, binary counter is cleared to “0”. And the WDTCL becomes “0” automatically after one machine cycle. Counter count up again. Figure 12-2 WDTR: Watchdog Timer Control Register Example: Sets the watchdog timer detection time to 1 sec. at 4.194304MHz Within WDT detection time Within WDT detection time LDM LDM CKCTLR,#3FH WDTR,#08FH ;Select 1/1024 clock source, WDTON ← 1, Clear Counter LDM : : : : LDM : : : : LDM WDTR,#08FH ;Clear counter WDTR,#08FH ;Clear counter WDTR,#08FH ;Clear counter Enable and Disable Watchdog Watchdog Timer Interrupt Watchdog timer is enabled by setting WDTON (bit 4 in CKCTLR) to “1”. WDTON is initialized to “0” during reset and it should be set to “1” to operate after reset is released. The watchdog timer can be also used as a simple 7-bit timer by clearing bit4 of CKCTLR to “0”. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below. Example: Enables watchdog timer for Reset : LDM : : TWDT = (WDTR+1) × Interval of BIT CKCTLR,#xxx1_xxxxB;WDTON ← 1 The watchdog timer is disabled by clearing bit 4 (WDTON) of CKCTLR. The watchdog timer is halted in STOP mode and restarts automatically after STOP mode is released. The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source. Example: 7-bit timer interrupt set up. LDM LDM CKCTLR,#xxx0_xxxxB;WDTON ←0 WDTR,#8FH ;WDTCL ←1 : MAR. 2005 Ver 0.2 49 MC80F0424/0432/0448 Preliminary Source clock BIT overflow Binary-counter 3 2 1 0 1 2 3 Counter Clear WDTR 0 Counter Clear 3 n Match Detect WDTIF interrupt WDTR ← “1000_0011B” WDT reset reset Figure 12-3 Watchdog timer Timing If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware. reset is generated in sub clock mode. The IFWDT bit of IFR register is set when watchdog timer interrupt is generated. (Refer to Figure 12-4) The main clock oscillator also turns on when a watchdog timer IFR MSB - R/W R/W R/W R/W R/W R/W IFRX0 IFTX0 IFRX1 IFTX1 IFWT IFWDT - - - - ADDRESS: 0DFH INITIAL VALUE: --00_0000B LSB WDT interrupt occurred flagNOTE1 WT interrupt occurred flagNOTE1 UART1 Tx interrupt occurred flagNOTE2 UART1 Rx interrupt occurred flagNOTE2 UART0 Tx interrupt occurred flagNOTE3 UART0 Rx interrupt occurred flagNOTE3 NOTE1 : In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE2 : In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE3 : In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. Figure 12-4 IFR : Interrupt Flag Register 50 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 13. WATCH TIMER The watch timer generates interrupt for watch operation. The watch timer consists of the clock selector, 15-bit binary counter, interval selector and watch timer mode register. It is a multi-purpose timer. It is generally used for watch design. into stop mode, the main-clock is stopped and then watch timer is also stopped. If the sub clock’s oscillation is enabled by XTEN bit(PSR1 register), the watch timer by sub clock continues to operate even when the CPU is in the STOP mode. The watch timer counter can output with period of max 1 seconds at sub-clock. The bit 2, 3, 4 of WTMR select the interrupt interval divide ratio selection of watch timer among 16, 64, 256, 1024, 4096, 8192, 16384 or 32768. The bit 0,1 of WTMR select the clock source of watch timer among sub-clock(32.768kHz), f XIN÷2, f XIN ÷128 and mainclock(fXIN). The fXIN of main-clock is used usually for watch timer test, so generally it is not used for the clock source of watch timer. The fXIN÷128 of main-clock is used when the single clock system is organized. In fXIN÷128 clock source, if the CPU enters The IFWT bit of IFR register is set when watch timer interrupt is generated. (Refer to Figure 12-4) WTMR (Watch Timer Mode Register) W 7 6 5 R/W 4 WTEN - - WTIN2 Bit : R/W 3 WTIN1 R/W 2 WTIN0 R/W 1 R/W 0 WTCK1 WTCK0 ADDRESS: 0F6H INITIAL VALUE:0--00000B Watch Timer Clock Source selection 00: fSUB 01: fXIN ÷ 128 10: fXIN 11: fXIN ÷ 2 WTEN (Watch Timer Enable) 0: Watch Timer disable 1: Watch Timer Enable Watch Timer Interrupt Interval selection 000: Clock Source ÷ 32768 001: Clock Source ÷ 16384 010: Clock Source ÷ 8192 011: Clock Source ÷ 4096 100: Clock Source ÷ 1024 101: Clock Source ÷ 256 110: Clock Source ÷ 64 111: Clock Source ÷ 16 Figure 13-1 Watch Timer Mode Register WTIN[2:0] ÷32768 15-bit binary counter WTCK[1:0] fSUB fXIN÷128 fXIN MUX fXIN÷2 Clock Source Selector WTEN Clear If WTEN=0 ÷16384 ÷8192 ÷4096 ÷1024 Watch Timer interrupt MUX ÷256 ÷64 ÷16 interval selector Figure 13-2 Watch Timer Block Diagram MAR. 2005 Ver 0.2 51 MC80F0424/0432/0448 Preliminary 14. TIMER/EVENT COUNTER The MC80F0424/0432/0448 has five Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 are can be used either two 8-bit Timer/ Counter or one 16-bit Timer/Counter with combine them. Also Timer 2 and Timer 3 are same. Timer 4 is 16-bit Timer/Counter. In the “timer” function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency. In the “counter” function, the register is increased in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, EC0(Timer 0) or EC1(Timer 2). In addition the “capture” function, the register is increased in response external or internal clock sources same with timer or counter function. When external interrupt edge input, the count register is captured into capture data register CDRx. It has seven operating modes: "8-bit timer/counter", "16-bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", "16-bit compare output" and "10-bit PWM" which are selected by bit in Timer mode register TMx as shown in Table 141, Table 14-2, Table 14-3, Figure 14-10, Figure 14-2 and Figure 14-3. In 8/16 Timer mode, pin R14/T0O and R52/T2O can output Timer0 or Timer2 output by setting "1" respectively to bit T0O and T2O in PSR0 register. In operation of Timer 2 and Timer 3, their operations are same as Timer 0 and Timer 1, respectively as shown in Table 14-2. 16BIT CAP0 CAP1 PWM1E T0CK [2:0] T1CK [1:0] PWM1O 0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event counter 8-bit Capture 0 X1 0 0 XXX XX 1 8-bit Capture 8-bit Compare Output 0 0 0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM 1 0 0 0 XXX 11 0 16-bit Timer 1 0 0 0 111 11 0 16-bit Event counter 1 1 1 0 XXX 11 0 16-bit Capture 1 0 0 0 XXX 11 1 16-bit Compare Output TIMER 0 TIMER 1 Table 14-1 Operating Modes of Timer 0, 1 1. X: The value “0” or “1” corresponding to user operation. 16BIT CAP2 CAP3 PWM3E T2CK [2:0] T3CK [1:0] PWM3O 0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event counter 8-bit Capture 0 1 0 0 XXX XX 1 8-bit Capture 8-bit Compare Output 0 X1 0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM 1 0 0 0 XXX 11 0 16-bit Timer 1 0 0 0 111 11 0 16-bit Event counter 1 1 1 0 XXX 11 0 16-bit Capture 1 0 0 0 XXX 11 1 16-bit Compare Output TIMER 2 TIMER 3 Table 14-2 Operating Modes of Timer 2, 3 1. X: The value “0” or “1” corresponding to user operation. 52 MAR. 2005 Ver 0.2 Preliminary CAP4 T4CK[2:0] 0 XXX1 16-bit Timer 1 XXX 16-bit Capture MC80F0424/0432/0448 TIMER 4 Table 14-3 Operating Modes of Timer 4 1. X: The value “0” or “1” corresponding to user operation. MAR. 2005 Ver 0.2 53 MC80F0424/0432/0448 Preliminary R/W 5 TM0 - - R/W 3 R/W 2 R/W 1 R/W 0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST ADDRESS: 0D0H INITIAL VALUE: --000000B Bit Name Bit Position Description CAP0 TM0.5 0: Timer/Counter mode 1: Capture mode selection flag T0CK2 T0CK1 T0CK0 TM0.4 TM0.3 TM0.2 000: 8-bit Timer, Clock source is fXIN ÷ 2 001: 8-bit Timer, Clock source is fXIN ÷ 4 010: 8-bit Timer, Clock source is fXIN ÷ 8 011: 8-bit Timer, Clock source is fXIN ÷ 32 100: 8-bit Timer, Clock source is fXIN ÷ 128 101: 8-bit Timer, Clock source is fXIN ÷ 512 110: 8-bit Timer, Clock source is fXIN ÷ 2048 111: EC0 (External clock) T0CN TM0.1 0: Timer count pause 1: Timer count start T0ST TM0.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. R/W 7 TM1 R/W 4 POL R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 16BIT PWM1E CAP1 T1CK1 BTCL T1CK0 T1CN T1ST ADDRESS: 0D2H INITIAL VALUE: 00H Bit Name Bit Position Description POL TM1.7 0: PWM Duty Active Low 1: PWM Duty Active High 16BIT TM1.6 0: 8-bit Mode 1: 16-bit Mode PWMIE TM1.5 0: Disable PWM 1: Enable PWM CAP1 TM1.4 0: Timer/Counter mode 1: Capture mode selection flag T1CK1 T1CK0 TM1.3 TM1.2 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN ÷ 2 10: 8-bit Timer, Clock source is fXIN ÷ 8 11: 8-bit Timer, Clock source is Using the Timer 0 Clock T1CN TM1.1 0: Timer count pause 1: Timer count start T1ST TM1.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TDR0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TDR1 ADDRESS: 0D1H INITIAL VALUE: 0FFH ADDRESS: 0D3H INITIAL VALUE: 0FFH Read: Count value read Write: Compare data write Figure 14-1 TM0, TM1 Registers 54 MAR. 2005 Ver 0.2 Preliminary R/W 5 TM2 - - R/W 3 R/W 2 R/W 1 R/W 0 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST ADDRESS: 0D6H INITIAL VALUE: --000000B Bit Name Bit Position Description CAP2 TM2.5 0: Timer/Counter mode 1: Capture mode selection flag T2CK2 T2CK1 T2CK0 TM2.4 TM2.3 TM2.2 000: 8-bit Timer, Clock source is fXIN ÷ 2 001: 8-bit Timer, Clock source is fXIN ÷ 4 010: 8-bit Timer, Clock source is fXIN ÷ 8 011: 8-bit Timer, Clock source is fXIN ÷ 16 100: 8-bit Timer, Clock source is fXIN ÷ 64 101: 8-bit Timer, Clock source is fXIN ÷ 256 110: 8-bit Timer, Clock source is fXIN ÷ 1024 111: EC1 (External clock) T2CN TM2.1 0: Timer count pause 1: Timer count start T2ST TM2.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. R/W 7 TM3 R/W 4 MC80F0424/0432/0448 POL R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 16BIT PWM3E CAP3 T3CK1 BTCL T3CK0 T3CN T3ST ADDRESS: 0D8H INITIAL VALUE: 00H Bit Name Bit Position Description POL TM3.7 0: PWM Duty Active Low 1: PWM Duty Active High 16BIT TM3.6 0: 8-bit Mode 1: 16-bit Mode PWM3E TM3.5 0: Disable PWM 1: Enable PWM CAP3 TM3.4 0: Timer/Counter mode 1: Capture mode selection flag T3CK1 T3CK0 TM3.3 TM3.2 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN ÷ 4 10: 8-bit Timer, Clock source is fXIN ÷ 16 11: 8-bit Timer, Clock source is Using the Timer 2 Clock T3CN TM3.1 0: Timer count pause 1: Timer count start T3ST TM3.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TDR2 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TDR3 ADDRESS: 0D7H INITIAL VALUE: 0FFH ADDRESS: 0D9H INITIAL VALUE: 0FFH Read: Count value read Write: Compare data write Figure 14-2 TM2, TM3 Registers MAR. 2005 Ver 0.2 55 MC80F0424/0432/0448 Preliminary R/W 5 TM4 - - R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 CAP4 T4CK2 T4CK1 BTCL T4CK0 T4CN T4ST ADDRESS: 0DCH INITIAL VALUE: --000000B Bit Name Bit Position Description CAP4 TM4.5 0: Timer/Counter mode 1: Capture mode selection flag T4CK2 T4CK1 T4CK0 TM4.4 TM4.3 TM4.2 000: 8-bit Timer, Clock source is fXIN ÷ 2 001: 8-bit Timer, Clock source is fXIN ÷ 4 010: 8-bit Timer, Clock source is fXIN ÷ 8 011: 8-bit Timer, Clock source is fXIN ÷ 16 100: 8-bit Timer, Clock source is fXIN ÷ 64 101: 8-bit Timer, Clock source is fXIN ÷ 256 110: 8-bit Timer, Clock source is fXIN ÷ 1024 111: 8-bit Timer, Clock source is fXIN ÷ 2048 T4CN TM4.1 0: Timer count pause 1: Timer count start T4ST TM4.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TDR4H R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TDR4L ADDRESS: 0DDH INITIAL VALUE: 0FFH ADDRESS: 0DEH INITIAL VALUE: 0FFH Figure 14-3 TM4 Registers 14.1 8-bit Timer / Counter Mode The MC80F0424/0432/0448 has four 8-bit Timer/Counters, Timer 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 are shown in Figure 14-4 and Timer 2, Timer 3 are shown in Figure 14-5. The “timer” or “counter” function is selected by control registers TM0, TM1, TM2, TM3 as shown in Figure 14-1. To use as an 8bit timer/counter mode, bit CAP0, CAP1, CAP2, or CAP3 of TMx should be cleared to “0” and 16BIT of TM1 or TM3 should 56 be cleared to "0"(Figure 14-4). These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 or external clock (selected by control bits TxCK0, TxCK1, TxCK2 of register TMx). MAR. 2005 Ver 0.2 Preliminary TM0 7 6 - - - - 5 4 3 2 1 MC80F0424/0432/0448 0 ADDRESS: 0D0H INITIAL VALUE: --000000B CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST 0 X X X X X X means the value of "0" or "1" corresponding to user operation 7 TM1 6 5 4 3 2 1 0 POL 16BIT PWM1E CAP1 T1CK1 BTCL T1CK0 T1CN T1ST X 0 0 0 X X X ADDRESS: 0D2H INITIAL VALUE: 00H X T0CK[2:0] RISING EDGE DETECTOR EC0 PIN 111 T0ST ÷2 000 ÷4 Prescaler ÷8 XIN PIN 0: Stop 1: Clear and start 001 010 ÷ 32 T0 (8-bit) clear 011 ÷ 128 100 ÷ 512 ÷ 2048 101 T0CN T0IF Comparator TIMER 0 INTERRUPT 110 MUX TIMER 0 TDR0 (8-bit) F/F R14/T0O T1CK[1:0] T1ST ÷1 ÷2 ÷8 0: Stop 1: Clear and start 11 00 T1 (8-bit) 01 clear 10 T1CN T1IF MUX Comparator TIMER 1 TDR1 (8-bit) TIMER 1 INTERRUPT F/F R53/PWM1O/T1O Figure 14-4 8-bit Timer/Counter 0, 1 MAR. 2005 Ver 0.2 57 MC80F0424/0432/0448 TM2 Preliminary 7 6 - - - - 5 4 3 2 1 0 ADDRESS: 0D6H INITIAL VALUE: --000000B CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST 0 X X X X X X means the value of "0" or "1" corresponding to user operation 7 TM3 6 5 4 3 2 1 0 POL 16BIT PWM3E CAP3 T3CK1 BTCL T3CK0 T3CN T3ST X 0 0 0 X X X ADDRESS: 0D8H INITIAL VALUE: 00H X T2CK[2:0] RISING EDGE DETECTOR EC1 PIN 111 T2ST ÷2 000 XIN PIN Prescaler ÷4 0: Stop 1: Clear and start 001 ÷8 010 ÷ 16 T2 (8-bit) clear 011 ÷ 64 100 ÷ 256 ÷ 1024 101 T2CN T2IF Comparator TIMER 2 INTERRUPT 110 MUX TIMER 2 TDR2 (8-bit) F/F R52/T2O T3CK[1:0] T3ST ÷1 ÷4 ÷ 16 0: Stop 1: Clear and start 11 00 T3 (8-bit) 01 clear 10 T3CN T3IF MUX Comparator TIMER 3 TDR3 (8-bit) TIMER 3 INTERRUPT F/F R54/PWM3O/T3O Figure 14-5 8-bit Timer/Counter 2, 3 58 MAR. 2005 Ver 0.2 Preliminary These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32, 128, 512, 2048 selected by control bits T0CK[2:0] of register TM0 or 1, 2, 8 selected by control bits T1CK[1:0] of register TM1, or 2, 4, 8, 16, 64, 256, 1024 selected by control bits T2CK[2:0] of register TM2, or 1, 4, 16 selected by control bits T3CK[1:0] of register TM3. In the Timer 0, timer register T0 increases from 00H until it matches TDR0 and then reset to 00H. The match output of Timer 0 generates Timer 0 interrupt (latched in T0IF bit). Example 1: Timer0 = 2ms 8-bit timer mode at 4MHz Timer1 = 0.5ms 8-bit timer mode at 4MHz Timer2 = 1ms 8-bit timer mode at 4MHz Timer3 = 1ms 8-bit timer mode at 4MHz LDM LDM LDM LDM LDM LDM LDM LDM SET1 SET1 SET1 SET1 EI TDR0,#249 TDR1,#249 TDR2,#249 TDR3,#249 TM0,#0000_1111B TM1,#0000_1011B TM2,#0000_1111B TM3,#0000_1011B T0E T1E T2E T3E In counter function, the counter is increased every 0-to-1(1-to-0) (rising & falling edge) transition of EC0 pin. In order to use counter function, the bit EC0 of the Port Selection Register(PSR0.4) is set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not. Likewise, In order to use Timer2 as counter function, the bit EC1 of the Port Selection Register(PSR0.5) is set to "1". The Timer 2 can be used as a counter by pin EC1 input, but Timer 3 can not. Example 2: Timer0 = 8-bit event counter mode Timer1 = 0.5ms 8-bit timer mode at 4MHz Timer2 = 8-bit event counter mode Timer3 = 1ms 8-bit timer mode at 4MHz LDM LDM LDM LDM LDM LDM LDM LDM SET1 SET1 SET1 SET1 EI MC80F0424/0432/0448 14.1.1 8-bit Timer Mode TDR0,#249 TDR1,#249 TDR2,#249 TDR3,#249 TM0,#0001_1111B TM1,#0000_1011B TM2,#0001_1111B TM3,#0000_1011B T0E T1E T2E T3E In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn are compared with the contents of up-counter, Tn. If match is found, a timer n interrupt (TnIF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. As the value of TDRn is changeable by software, time interval is set as you want. Start count ~ ~ Source clock ~ ~ Up-counter 0 1 2 n-2 3 n-1 n 0 1 2 3 4 ~ ~ Match Detect Counter Clear ~ ~ T1IF interrupt n ~ ~ TDR1 Figure 14-6 Timer Mode Timing Chart MAR. 2005 Ver 0.2 59 MC80F0424/0432/0448 Preliminary Example: Make 1ms interrupt using by Timer0 at 4MHz LDM LDM SET1 EI TM0,#0FH TDR0,#124 T0E ; ; ; ; divide by 32 8us x (124+1)= 1ms Enable Timer 0 Interrupt Enable Master Interrupt When TM0 = 0000 1111B (8-bit Timer mode, Prescaler divide ratio = 32) TDR0 = 124D = 7CH fXIN = 4 MHz 1 INTERRUPT PERIOD = × 32 × (124+1) = 1 ms 4 × 106 Hz TDR0 MATCH (TDR0 = T0) Count Pulse Period 7C 7C 8 µs 6 ~~ ~~ up -c ou nt ~~ 7B 7A 5 4 3 2 1 0 0 TIME Interrupt period = 8 µs x (124+1) Timer 0 (T0IF) Interrupt Occur interrupt Occur interrupt Occur interrupt Figure 14-7 Timer Count Example 14.1.2 8-bit Event Counter Mode In order to use event counter function, the bit 4, 5 of the Port Selection Register PSR0(address 0F8H) is required to be set to “1”. In this mode, counting up is started by an external trigger. This trigger means rising edge of the EC0 or EC1 pin input. Source clock is used as an internal clock selected with timer mode register TM0 or TM2. The contents of timer data register TDRn (n = 0,1,2,3) are compared with the contents of the up-counter Tn. If a match is found, an timer interrupt request flag TnIF is generated, and the counter is cleared to “0”. The counter is restart and count up continuously by every rising edge of the EC0 or EC1 pin input. The maximum frequency applied to the EC0 or EC1 pin is fXIN/ 2 [Hz]. After reset, the value of timer data register TDRn is initialized to "0", The interval period of Timer is calculated as below equation. 1 Period (sec) = ----------- × 2 × Divide Ratio × (TDRn+1) f XIN Start count ~ ~ ECn pin input ~ ~ 1 0 2 ~ ~ Up-counter n-1 n 0 1 2 ~ ~ ~ ~ T1IF interrupt n ~ ~ TDR1 Figure 14-8 Event Counter Mode Timing Chart 60 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 TDR1 disable ~~ clear & start enable up -c ou nt stop ~~ TIME Timer 1 (T1IF) Interrupt Occur interrupt Occur interrupt T1ST Start & Stop T1ST = 1 T1ST = 0 T1CN Control count T1CN = 1 T1CN = 0 Figure 14-9 Count Operation of Timer / Event counter MAR. 2005 Ver 0.2 61 MC80F0424/0432/0448 Preliminary 14.2 16-bit Timer / Counter Mode The Timer register is being run with all 16 bits. A 16-bit timer/ counter register T0, T1 are incremented from 0000H until it matches TDR0, TDR1 and then resets to 0000H. The match output generates Timer 0 interrupt. T3CK[1:0] and 16BIT of TM3 should be set to "1" respectively as shown in Figure 14-11. Even if the Timer 0 (including Timer 1) is used as a 16-bit timer, the Timer 2 and Timer 3 can still be used as either two 8-bit timer or one 16-bit timer by setting the TM2. Reversely, even if the Timer 2 (including Timer 3) is used as a 16-bit timer, the Timer 0 and Timer 1 can still be used as 8-bit timer independently. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK[1:0] and 16BIT of TM1 should be set to "1" respectively as shown in Figure 14-10. A 16-bit timer/counter 4 register T4H, T4L are increased from 0000H until it matches TDR4H, TDR4L and then resets to 0000H. The match output generates Timer 4 interrupt. Timer/Counter 4 is 16 bit mode as shown in Figure 14-12. Likewise, A 16-bit timer/counter register T2, T3 are incremented from 0000H until it matches TDR2, TDR3 and then resets to 0000H. The match output generates Timer 2 interrupt. The clock source of the Timer 2 is selected either internal or external clock by bit T2CK[2:0]. In 16-bit mode, the bits TM0 7 6 - - - - 5 4 3 2 1 0 ADDRESS: 0D0H INITIAL VALUE: --000000B BTCL T0CK0 T0CN T0ST CAP0 T0CK2 T0CK1 0 X X X X X X means the value of "0" or "1" corresponding to user operation 7 TM1 6 5 4 3 2 1 0 ADDRESS: 0D2H INITIAL VALUE: 00H POL 16BIT PWM1E CAP1 T1CK1 BTCL T1CK0 T1CN T1ST X 1 0 0 1 1 X X T0CK[2:0] RISING EDGE DETECTOR EC0 PIN 111 ÷2 ÷4 Prescaler XIN PIN ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 T0ST 0: Stop 1: Clear and start 000 001 T1 + T0 (16-bit) 010 clear 011 100 101 T0CN T0IF Comparator 110 MUX TDR1 + TDR0 (16-bit) F/F TIMER 0 INTERRUPT (Not Timer 1 interrupt) R14/T0O Higher byte Lower byte COMPARE DATA TIMER 0 + TIMER 1 → TIMER 0 (16-bit) Figure 14-10 16-bit Timer/Counter for Timer 0, 1 62 MAR. 2005 Ver 0.2 Preliminary TM2 7 6 - - - - 5 4 3 2 1 MC80F0424/0432/0448 0 ADDRESS: 0D6H INITIAL VALUE: --000000B CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST 0 X X X X X X means the value of "0" or "1" corresponding to user operation 7 TM3 6 5 4 3 2 1 0 ADDRESS: 0D8H INITIAL VALUE: 00H POL 16BIT PWM3E CAP3 T3CK1 BTCL T3CK0 T3CN T3ST X 1 0 0 1 1 X X T2CK[2:0] RISING EDGE DETECTOR EC1 PIN 111 ÷2 ÷4 Prescaler XIN PIN ÷8 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 T2ST 0: Stop 1: Clear and start 000 001 T3 + T2 (16-bit) 010 clear 011 100 101 T2CN T2IF Comparator 110 TDR3 + TDR2 (16-bit) MUX F/F TIMER 2 INTERRUPT (Not Timer 3 interrupt) R52/T2O Higher byte Lower byte COMPARE DATA TIMER 2 + TIMER 3 → TIMER 2 (16-bit) Figure 14-11 16-bit Timer/Counter for Timer 2, 3 14.3 8-bit Compare Output (16-bit) The MC80F0424/0432/0448 has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin(T0O, PWM1O, T2O, PWM3O) as shown in Figure 14-4, Figure 14-5 and Figure 14-12. In this mode, the bit PWM1O and PWM3O of PSR0 register should be set to “1”, and the bit PWM1E/PWM3E of timer1/timer3 mode register (TM1/TM3) should be set to “0”. MAR. 2005 Ver 0.2 These Compare output pins output the signal having a 50:50 duty square wave, and output frequency is same as below equation. Oscillation Frequency f COMP = --------------------------------------------------------------------------------2 × Prescaler Value × ( TDR + 1 ) 63 MC80F0424/0432/0448 Preliminary In addition, 16-bit Compare output mode is available, also. TM4 7 6 - - X X 5 4 3 2 1 0 ADDRESS: 0DCH INITIAL VALUE: 00H CAP4 T4CK2 T4CK1 BTCL T4CK0 T4CN T4ST 0 X X X X X X means the value of "0" or "1" corresponding to user operation T4CK[2:0] ÷2 ÷4 Prescaler XIN PIN ÷8 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 ÷ 2048 000 T4ST 0: Stop 1: Clear and start 001 010 011 T4H + T4L (16-bit) 100 clear 101 110 T4CN T4IF 111 TIMER 4 INTERRUPT Comparator TDR4H + TDR4L (16-bit) MUX Higher byte Lower byte COMPARE DATA Figure 14-12 Timer 4 for only 16 bit mode 14.4 8-bit Capture Mode The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 14-13. Likewise, the Timer 2 capture mode is set by bit CAP2 of timer mode register TM2 (bit CAP3 of timer mode register TM3 for Timer 3) as shown in Figure 14-14. The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when timer register T0 (T1, T2, T3) increases and matches TDR0 (TDR1, TDR2, TDR3). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 14-16, the pulse width of captured signal is wider than the timer data value (FFH) over 2 times. When external interrupt is occurred, the captured value (13H) is more little 64 than wanted value. It can be obtained correct value by counting the number of timer overflow occurrence. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1,T2,T3), to be captured into registers CDRx (CDR0, CDR1, CDR2, CDR3), respectively. After captured, Timer x register is cleared and restarts by hardware. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS. Refer to “19.5 External Interrupt” on page 96. In addition, the transition at INTn pin generate an interrupt. Note: The CDRn and TDRn are in same address.In the capture mode, reading operation is read the CDRn, not TDRn because path is opened to the CDRn. MAR. 2005 Ver 0.2 Preliminary TM0 7 6 - - - - 5 4 3 2 MC80F0424/0432/0448 1 0 ADDRESS: 0D0H INITIAL VALUE: --000000B CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST 1 X X X X X X means the value of "0" or "1" corresponding to user operation 7 TM1 6 5 4 3 2 1 0 ADDRESS: 0D2H INITIAL VALUE: 00H POL 16BIT PWM1E CAP1 T1CK1 BTCL T1CK0 T1CN T1ST X 0 0 1 X X X X T0CK[2:0] Rising Edge Detector EC0 PIN 111 T0ST ÷2 000 ÷4 Prescaler XIN PIN 0: Stop 1: Clear and start 001 ÷8 T0 (8-bit) 010 ÷ 32 011 ÷ 128 100 ÷ 512 ÷ 2048 101 clear T0CN Capture 110 CDR0 (8-bit) MUX IEDS[1:0] “01” “10” INT0 PIN INT0IF T1CK[1:0] INT0 INTERRUPT “11” T1ST ÷1 ÷2 ÷8 0: Stop 1: Clear and start 11 00 T1 (8-bit) 01 clear 10 MUX T1CN Capture CDR1 (8-bit) IEDS[3:2] “01” INT1 PIN “10” INT1IF INT1 INTERRUPT “11” Figure 14-13 8-bit Capture Mode for Timer 0, 1 MAR. 2005 Ver 0.2 65 MC80F0424/0432/0448 Preliminary TM2 7 6 - - - - 5 4 3 2 1 0 ADDRESS: 0D6H INITIAL VALUE: --000000B CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST 1 X X X X X X means the value of "0" or "1" corresponding to user operation 7 TM3 6 5 4 3 2 1 0 ADDRESS: 0D8H INITIAL VALUE: 00H POL 16BIT PWM3E CAP3 T3CK1 BTCL T3CK0 T3CN T3ST X 0 0 1 X X X X T2CK[2:0] Rising Edge Detector EC1 PIN 111 T2ST ÷2 000 ÷4 Prescaler XIN PIN 0: Stop 1: Clear and start 001 ÷8 T2 (8-bit) 010 ÷ 16 011 ÷ 64 100 ÷ 256 ÷ 1024 101 clear T2CN Capture 110 CDR2 (8-bit) MUX IEDS[5:4] “01” “10” INT2 PIN INT2IF T3CK[1:0] INT2 INTERRUPT “11” T3ST ÷1 ÷4 ÷ 16 0: Stop 1: Clear and start 11 00 T3 (8-bit) 01 clear 10 MUX T3CN Capture CDR3 (8-bit) IEDS[7:6] “01” INT3 PIN “10” INT3IF INT3 INTERRUPT “11” Figure 14-14 8-bit Capture Mode for Timer 2, 3 66 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 This value is loaded to CDR0 n T0 n-1 t -c ou n ~~ ~~ 9 8 up 7 6 5 4 ~~ 3 2 1 0 TIME Ext. INT0 Pin Interrupt Request ( INT0IF ) Interrupt Interval Period Ext. INT0 Pin Interrupt Request ( INT0IF ) 20nS Capture ( Timer Stop ) 5nS Delay Clear & Start Figure 14-15 Input Capture Operation of Timer 0 Capture mode Ext. INT0 Pin Interrupt Request ( INT0IF ) Interrupt Interval Period=01H+FFH +01H+FFH +01H+13H=214H Interrupt Request ( T0IF ) FFH FFH T0 13H 00H 00H Figure 14-16 Excess Timer Overflow in Capture Mode MAR. 2005 Ver 0.2 67 MC80F0424/0432/0448 Preliminary 14.5 16-bit Capture Mode ternal clock by bit T2CK[2:0]. In 16-bit mode, the bits T3CK1,T3CK0, CAP3 and 16BIT of TM3 should be set to "1" respectively as shown in Figure 14-18. 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK1, T1CK0, CAP1 and 16BIT of TM1 should be set to "1" respectively as shown in Figure 14-17. The clock source of the Timer 4 is selected either internal or external clock by bit T4CK[2:0] as shown in Figure 14-18. The clock source of the Timer 2 is selected either internal or ex- 7 6 - - - - TM0 5 4 3 2 1 0 ADDRESS: 0D0H INITIAL VALUE: --000000B CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST 1 X X X X X X means the value of "0" or "1" corresponding to user operation 7 TM1 6 5 4 3 2 1 0 ADDRESS: 0D2H INITIAL VALUE: 00H POL 16BIT PWM1E CAP1 T1CK1 BTCL T1CK0 T1CN T1ST X 1 0 1 1 1 X X T0CK[2:0] Rising Edge Detector EC0 PIN 111 T0ST ÷2 ÷4 Prescaler XIN PIN ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 0: Stop 1: Clear and start 000 001 TDR1 + TDR0 (16-bit) 010 011 100 clear T0CN 101 Capture 110 CDR1 + CDR0 (16-bit) MUX IEDS[1:0] Higher byte Lower byte CAPTURE DATA “01” INT0 PIN “10” INT0IF INT0 INTERRUPT “11” Figure 14-17 16-bit Capture Mode of Timer 0, 1 68 MAR. 2005 Ver 0.2 Preliminary TM2 7 6 - - - - 5 4 3 2 MC80F0424/0432/0448 1 0 ADDRESS: 0D6H INITIAL VALUE: --000000B CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST 1 X X X X X X means the value of "0" or "1" corresponding to user operation 7 TM3 6 5 4 3 2 1 0 ADDRESS: 0D8H INITIAL VALUE: 00H POL 16BIT PWM3E CAP3 T3CK1 BTCL T3CK0 T3CN T3ST X 1 0 X 1 1 X X T2CK[2:0] Rising Edge Detector EC1 PIN 111 T2ST ÷2 ÷4 Prescaler XIN PIN ÷8 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 0: Stop 1: Clear and start 000 001 TDR3 + TDR2 (16-bit) 010 011 100 clear T2CN 101 Capture 110 CDR3 + CDR2 (16-bit) MUX IEDS[5:4] Higher byte Lower byte CAPTURE DATA “01” INT2 PIN “10” INT2IF INT2 INTERRUPT “11” Figure 14-18 16-bit Capture Mode of Timer 2, 3 MAR. 2005 Ver 0.2 69 MC80F0424/0432/0448 Preliminary TM4 7 6 - - X X 5 4 3 2 1 0 ADDRESS: 0DCH INITIAL VALUE: 00H CAP4 T4CK2 T4CK1 BTCL T4CK0 T4CN T4ST 1 X X X X X X means the value of "0" or "1" corresponding to user operation T4CK[2:0] ÷2 ÷4 Prescaler XIN PIN ÷8 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 ÷ 2048 000 T4ST 001 0: Stop 1: Clear and start 010 011 TDR4H + TDR4L (16-bit) 100 101 clear T4CN 110 Capture 111 CDR4H + CDR4L (16-bit) MUX IEDS[1:0] Higher byte Lower byte CAPTURE DATA “01” “10” INT3 PIN INT3IF INT3 INTERRUPT “11” Figure 14-19 16-bit Capture Mode of Timer 4 Example 1: EI : : Timer0 = 16-bit timer mode, 0.5s at 4MHz LDM LDM LDM LDM SET1 EI : : TM0,#0000_1111B;8uS TM1,#0100_1100B;16bit Mode TDR0,#<62499 ;8uS X 62500 TDR1,#>62499 ;=0.5s T0E Example 2: Timer0 = 16-bit event counter mode LDM LDM LDM LDM LDM SET1 70 PSR0,#0001_0000B;EC0 Set TM0,#0001_1111B;CounterMode TM1,#0100_1100B;16bit Mode TDR0,#<0FFFFH ; TDR1,#>0FFFFH ; T0E Example 3: Timer0 = 16-bit capture mode LDM LDM LDM LDM LDM LDM SET1 SET1 EI : : PSR0,#0000_0001B;INT0 set TM0,#0010_1111B;CaptureMode TM1,#0100_1100B;16bit Mode TDR0,#<0FFFFH ; TDR1,#>0FFFFH ; IEDS,#01H ;Falling Edge T0E INT0E MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 14.6 PWM Mode The MC80F0424/0432/0448 has a high speed PWM (Pulse Width Modulation) functions which shared with Timer1 and Timer3. In PWM mode, pin R53/PWM1O and R54/PWM3O outputs up to a 10-bit resolution PWM output. This pin should be configured as a PWM output by setting "1" to bit PWM1O and PWM3O in PSR0 register. The period of the PWM1 output is determined by the T1PPR (T1 PWM Period Register) and T1PWHR[3:2] (bit3,2 of T1 PWM High Register) and the duty of the PWM1 output is determined by the T1PDR (T1 PWM Duty Register) and T1PWHR[1:0] (bit1,0 of T1 PWM High Register). The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the T1PWHR[3:2]. And writes duty value to the T1PDR and the T1PWHR[1:0] same way. The T1PDR is configured as a double buffering for glitch less PWM output. In Figure 14-1, the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) PWM1 Period = [PWM1HR[3:2]T1PPR] X Source Clock PWM1 Duty = [PWM1HR[1:0]T1PDR] X Source Clock Likewise, the period of the PWM3 output is determined by the T3PPR (T3 PWM Period Register) and T3PWHR[3:2] (bit3,2 of T3 PWM High Register) and the duty of the PWM output is determined by the T3PDR (T3 PWM Duty Register) and T3PWHR[1:0] (bit1,0 of T3 PWM High Register). The user writes the lower 8-bit period value to the T3PPR and the higher 2-bit period value to the T3PWHR[3:2]. And writes duty value to the T3PDR and the T3PWHR[1:0] same way. The T3PDR is configured as a double buffering for glitch less PWM output. In Figure 14-21, the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) PWM3 Period = [PWM3HR[3:2]T3PPR] X Source Clock PWM3 Duty = [PWM3HR[1:0]T3PDR] X Source Clock Table 14-4 shows the relation of PWM frequency vs. resolution. If it needed more higher frequency of PWM, it should be reduced resolution. Frequency Resolution T1CK[1:0] = 00(250nS) T1CK[1:0] = 01(500nS) T1CK[1:0] = 10(2uS) 10-bit 3.9kHz 0.98kHz 0.49kHz 9-bit 7.8kHz 1.95kHz 0.97kHz 8-bit 15.6kHz 3.90kHz 1.95kHz 7-bit 31.2kHz 7.81kHz 3.90kHz Table 14-4 PWM Frequency vs. Resolution at 4MHz The bit POL of TM1 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00H", the PWM output is determined by the bit POL (1: Low, 0: High). It can be changed duty value when the PWM output. However the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 14-23. As it were, the absolute duty time is not changed in varying frequency. But the changed period value must greater than the duty value. Note: If changing the Timer1 to PWM function, it should be stopped with the timer clock uncounted firstly, and then set period and duty register value. If user writes register values while timer is in operation, these register could be set with certain values. Ex) Sample Program @4MHz 2uS LDM LDM LDM LDM LDM TM1,#1010_1000b ; Set Clock & PWM1E T1PPR,#199 ; Period :400uS=2uSX(199+1) T1PDR,#99 ; Duty:200uS=2uSX(99+1) PWM1HR,00H TM1,#1010_1011b ; Start timer1 The relation of frequency and resolution is in inverse proportion. MAR. 2005 Ver 0.2 71 MC80F0424/0432/0448 R/W 7 TM1 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 0 1 0 X X X X W 1 W 0 6 5 - - - - - - - - 7 T1PWHR Preliminary 4 W 3 W 2 ADDRESS : D2H RESET VALUE : 00000000 ADDRESS : D5H RESET VALUE : ----0000B Bit Manipulation Not Available T1PWHR3 T1PWHR2 T1PWHR1 T1PWHR0 X X X Period High X Duty High X : The value "0" or "1" corresponding to user operation. W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 ADDRESS : D3H RESET VALUE : 0FFH T1PPR R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 ADDRESS : D4H RESET VALUE : 00H T1PDR T1PWHR[3:2] T1ST T0 clock source [T0CK] T1PPR(8-bit) 0 : Stop 1 : Clear and Start R53/PWM1O COMPARATOR S Q CLEAR 1 XIN ÷1 ÷2 ÷8 MUX (2-bit) R T1 ( 8-bit ) POL PWM1O [PSR0.6] COMPARATOR T1CK[1:0] T1CN Slave T1PDR(8-bit) T1PWHR[1:0] Master T1PDR(8-bit) Figure 14-20 PWM1 Mode 72 MAR. 2005 Ver 0.2 Preliminary R/W 7 TM3 R/W 6 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST X 0 1 0 X X X X 7 T3PWHR R/W 5 MC80F0424/0432/0448 5 6 4 - - - - - - - - W 3 W 2 W 1 ADDRESS : D8H RESET VALUE : 00000000 W 0 ADDRESS : DBH RESET VALUE : ----0000 Bit Manipulation Not Available T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0 X X X Period High X Duty High X : The value "0" or "1" corresponding to user operation. W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 ADDRESS : D9H RESET VALUE : 0FFH T3PPR R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 ADDRESS : DAH RESET VALUE : 00H T3PDR T3PWHR[3:2] T3ST T2 clock source [T2CK] T3PPR(8-bit) 0 : Stop 1 : Clear and Start R54/PWM3O COMPARATOR S Q CLEAR 1 XIN ÷1 ÷4 ÷ 16 MUX (2-bit) R T3 ( 8-bit ) POL PWM3O [PSR0.7] COMPARATOR T3CK[1:0] T3CN Slave T3PDR(8-bit) T1PWHR[1:0] Master T3PDR(8-bit) Figure 14-21 PWM3 Mode MAR. 2005 Ver 0.2 73 MC80F0424/0432/0448 Preliminary ~ ~ ~ ~ Source clock 01 02 03 04 PWM1E 7E 7F ~ ~ ~ ~ 00 ~ ~ ~ ~ ~ ~ T1 80 00 3FF 01 02 ~ ~ T1ST ~ ~ T1CN ~ ~ ~ ~ ~ ~ PWM1O [POL=1] ~ ~ PWM1O [POL=0] Duty Cycle [ (1+7Fh) x 250nS = 32uS ] Period Cycle [ (3FFh+1) x 250nS = 256uS, 3.9KHz ] T1CK[1:0] = 00 ( XIN ) T1PWHR = 0CH Period T1PWHR3 1 T1PWHR2 T1PPR (8-bit) 1 FFH T1PWHR0 T1PDR (8-bit) 0 7FH T1PPR = FFH T1PDR = 7FH Duty T1PWHR1 0 Figure 14-22 Example of PWM at 4MHz T1CK[1:0] = 10 ( 2us ) PWM1HR = 00H T1PPR = 0DH Write T1PPR to 09H T1PDR = 04H Source clock T1 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04 PWM1O POL=1 Duty Cycle [ (04h+1) x 2uS = 10uS ] Period Cycle [ (1+0Dh) x 2uS = 28uS, 35.5KHz ] Duty Cycle [ (04h+1) x 2uS = 10uS ] Duty Cycle [ (04h+1) x 2uS = 10uS ] Period Cycle [ (1+09h) x 2uS = 20uS, 50KHz ] Figure 14-23 Example of Changing the Period in Absolute Duty Cycle (@4MHz) 74 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 15. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 10-bit digital value. The A/ D module has sixteen analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to AVDD of Sample & Hold logic of A/D module. The AVDD was separated with VDD in order to minimize the degradation of operation characteristic by power supply noise. The A/D module has three registers which are the control register ADCM and A/D result register ADCRH and ADCRL. The ADCRH[7:6] is used as ADC clock source selection bits too. The register ADCM, shown in Figure 15-4, controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O. It is selected for the corresponding channel to be converted by setting ADS[3:0]. The A/D port is set to analog input port by ADEN and ADS[3:0] regardless of port I/O direction register. The port deselected by ADS[3:0] operates as normal port. ADCRH and ADCRL contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCRH and ADCRL, the A/D conversion status bit ADSF is set to “1”, and the A/D interrupt flag ADCIF is set. See Figure 15-1 for operation flow. The block diagram of the A/D module is shown in Figure 15-3. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes 12 times of conversion source clock. The period of actual A/D conversion clock should be minimally 1µs Analog Input AN0~AN15 0~1000pF User Selectable Figure 15-2 Analog Input Pin Connecting Capacitor Enable A/D Converter A/D Converter Cautions A/D Input Channel Select (1) Input range of AN0 to AN15 The input voltage of AN0 to AN15 should be within the specification range. In particular, if a voltage above AVDD or below AVSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also be affected. Conversion Source Clock Select A/D Start (ADST = 1) (2) Noise countermeasures NOP ADSF = 1 NO YES Read ADCRH, ADCRL Figure 15-1 A/D Converter Operation Flow How to Use A/D Converter The processing of conversion is start when the start bit ADST is set to “1”. After one cycle, it is cleared by hardware. The register MAR. 2005 Ver 0.2 In order to maintain 10-bit resolution, attention must be paid to noise on pins AVDD and AN0 to AN15. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended in some cases that a capacitor be connected externally as shown in Figure 15-2 in order to reduce noise. The capacitance is user-selectable and appropriately determined according to the target system. (3) Pins AN0/R60 to AN15/R77 The analog input pins AN0 to AN15 also function as input/output port (PORT R6 and R7) pins. When A/D conversion is performed with any of pins AN0 to AN15 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. 75 MC80F0424/0432/0448 Preliminary (4) AVDD pin input impedance parallel connection to the series resistor string between the AVDD pin and the AVSS pin, and there will be a large analog supply voltage error. A series resistor string of approximately 5KΩ is connected between the AVDD pin and the AVSS pin. Therefore, if the output impedance of the analog power source is high, this will result in ADEN AVDD Resistor Ladder Circuit AVSS 8-bit ADC R60/AN0 R61/AN1 Successive MUX Sample & Hold ADC INTERRUPT ADCIF Approximation Circuit R76/AN14 R77/AN15 ADC8 0 1 10-bit Mode 8-bit Mode ADS[5:2] 9 8 ... 9 8 ... ... 1 0 ADCR (10-bit) 10-bit ADCR ... 3 2 10-bit ADCR 0 0 ADCRH ADCRL (8-bit) 1 0 ADC Result Register ADCRH ADCRL (8-bit) 1 0 ADC Result Register Figure 15-3 A/D Block Diagram 76 MAR. 2005 Ver 0.2 Preliminary R/W R/W R/W R 3 2 1 0 ADS1 ADS0 ADST ADSF ADEN ADCK ADS2 ADS2 BTCL R/W 7 ADCM R/W 6 5 R/W 4 MC80F0424/0432/0448 ADDRESS: 0EFH INITIAL VALUE: 00-0 0001B A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to “0” by hardware. Analog input channel select 0000: Channel 0 (AN0) 0001: Channel 1 (AN1) 0010: Channel 2 (AN2) 0011: Channel 3 (AN3) 0100: Channel 4 (AN4) 0101: Channel 5 (AN5) 0110: Channel 6 (AN6) 0111: Channel 7 (AN7) 1000: Channel 8 (AN8) 1001: Channel 9 (AN9) 1010: Channel 10 (AN10) 1011: Channel 11 (AN11) 1100: Channel 12 (AN12) 1101: Channel 13 (AN13) 1110: Channel 14 (AN14) 1111: Channel 15 (AN15) A/D converter Clock Source Divide Ratio Selection bit 0: Clock Source fPS ÷ 4 1: Clock Source fPS ÷ 8 A/D converter Enable bit 0: A/D converter module turn off and current is not flow. 1: Enable A/D converter ADCRH W W 7 6 W 5 PSSEL1 PSSEL0 ADC8 4 - 3 BTCL - 2 R R 1 0 ADDRESS: 0F0H INITIAL VALUE: 010- ----B - A/D Conversion High Data (for 10-bit mode) ADC 8-bit Mode select bit 0: 10-bit Mode 1: 8-bit Mode A/D Conversion Clock (fPS) Source Selection 00: fXIN 01: fXIN ÷ 2 10: fXIN ÷ 4 11: fXIN ÷ 8 R 7 ADCRL R 6 R 5 R 4 R 3 BTCL R 2 R 1 R 0 ADDRESS: 0F1H INITIAL VALUE: Undefined A/D Conversion Low Data Figure 15-4 A/D Converter Control & Result Register MAR. 2005 Ver 0.2 77 MC80F0424/0432/0448 Preliminary 16. SERIAL INPUT/OUTPUT (SIO) The serial Input/Output is used to transmit/receive 8-bit data serially. The Serial Input/Output(SIO) module is a serial interface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. This SIO is 8bit clock synchronous type and consists of serial I/O data register, serial I/O mode register, clock selection circuit, octal counter and control circuit as illustrated in Figure 16-1. The SO pin is designed to input and output. So the Serial I/O(SIO) can be operated with minimum two pin. Pin R42/SCK, R43/SI, and R44/SO pins are controlled by the Serial Mode Register. The contents of the Serial I/O data register can be written into or read out by software. The data in the Serial Data Register can be shifted synchronously with the transfer clock signal. SIOST SIOSF clear XIN PIN Prescaler SCK[1:0] ÷4 ÷ 16 Timer0 Overflow POL Complete Start 00 01 “0” 10 “1” Clock SIO CONTROL CIRCUIT Clock 11 SCK PIN “11” overflow Octal Counter (3-bit) SIOIF Serial communication Interrupt MUX not “11” SCK[1:0] IOSW SM0 SO PIN SOUT IOSW 1 Input shift register SI PIN 0 Shift SIOR Internal Bus Figure 16-1 SIO Block Diagram 78 MAR. 2005 Ver 0.2 Preliminary Serial I/O Mode Register(SIOM) controls serial I/O function. According to SCK1 and SCK0, the internal clock or external clock can be selected. R/W 7 SIOM R/W 6 R/W 5 POL IOSW SM1 R/W 4 MC80F0424/0432/0448 Serial I/O Data Register(SIOR) is an 8-bit shift register. First LSB is send or is received. R/W R/W R/W R 3 2 1 0 SM0 BTCL SCK1 SCK0 SIOST SIOSF ADDRESS: 0E2H INITIAL VALUE: 0000 0001B Serial transmission status bit 0: Serial transmission is in progress 1: Serial transmission is completed Serial transmission start bit Setting this bit starts an Serial transmission. After one cycle, bit is cleared to “0” by hardware. Serial transmission Clock selection 00: fXIN ÷ 4 01: fXIN ÷ 16 10: TMR0OV(Timer0 Overflow) 11: External Clock Serial transmission Operation Mode 00: Normal Port(R42,R43,R44) 01: Sending Mode(SCK,R43,SO) 10: Receiving Mode(SCK,SI,R44) 11: Sending & Receiving Mode(SCK,SI,SO) Serial Input Pin Selection bit 0: SI Pin Selection 1: SO Pin Selection Serial Clock Polarity Selection bit 0: Data Transmission at Falling Edge Received Data Latch at Rising Edge 1: Data Transmission at Rising Edge Received Data Latch at Falling Edge SIOR R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BTCL ADDRESS: 0E3H INITIAL VALUE: Undefined Sending Data at Sending Mode Receiving Data at Receiving Mode Figure 16-2 SIO Control Register 16.1 Transmission/Receiving Timing The serial transmission is started by setting SIOST(bit1 of SIOM) to “1”. After one cycle of SCK, SIOST is cleared automatically to “0”. At the default state of POL bit clear, the serial output data from 8-bit shift register is output at falling edge of SCLK, and in- MAR. 2005 Ver 0.2 put data is latched at rising edge of SCLK pin (Refer to Figure 163). When transmission clock is counted 8 times, serial I/O counter is cleared as ‘0”. Transmission clock is halted in “H” state and serial I/O interrupt(SIOIF) occurred. 79 MC80F0424/0432/0448 Preliminary SIOST SCK [R42] (POL=0) SO [P44] D0 D1 D2 D3 D4 D5 D6 D7 SI [R43] (IOSW=0) D0 D1 D2 D3 D4 D5 D6 D7 IOSWIN [P44] (IOSW=1) D0 D1 D2 D3 D4 D5 D6 D7 SIOSF (SIO Status) SIOIF (SIO Int. Req) Figure 16-3 Serial I/O Timing Diagram at POL=0 SIOST SCK [R42] (POL=1) SO [R44] D0 D1 D2 D3 D4 D5 D6 D7 SI [R43] (IOSW=0) D0 D1 D2 D3 D4 D5 D6 D7 IOSWIN [R44] (IOSW=1) D0 D1 D2 D3 D4 D5 D6 D7 SIOSF (SIO Status) SIOIF (SIO Int. Req) Figure 16-4 Serial I/O Timing Diagram at POL=1 80 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 16.2 The method of Serial I/O 1. Select transmission/receiving mode. LDM LDM NOP LDM 2. In case of sending mode, write data to be send to SIOR. 3. Set SIOST to “1” to start serial transmission. 4. The SIO interrupt is generated at the completion of SIO and SIOIF is set to “1”. In SIO interrupt service routine, correct transmission should be tested. SIOR,#0AAh SIOM,#0011_1100b ;set tx data ;set SIO mode SIOM,#0011_1110b ;SIO Start Note: When external clock is used, the frequency should be less than 1MHz and recommended duty is 50%. If both transmission mode is selected and transmission is performed simultaneously, error will be made. 5. In case of receiving mode, the received data is acquired by reading the SIOR. 16.3 The Method to Test Correct Transmission Serial I/O Interrupt Service Routine SIOSF 0 1 Abnormal SIOE = 0 Write SIOM SIOIF 0 1 Normal Operation Overrun Error - SIOE: Interrupt Enable Register High IENH(Bit3) - SIOIF: Interrupt Request Flag Register High IRQH(Bit3) Figure 16-5 Serial IO Method to Test Transmission MAR. 2005 Ver 0.2 81 MC80F0424/0432/0448 Preliminary 17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) 17.1 UART Serial Interface Functions The Universal Asynchronous Receiver/Transmitter(UART) enables full-duplex operation wherein one byte of data after the start bit is transmitted and received. The on-chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates. In addition, a baud rate can also be defined by dividing clocks input to the ACLK pin. The UART driver consists of RXR, TXR, ASIMR, ASISR and BRGCR register. Clock asynchronous serial I/O mode (UART) can be selected by ASIMR register. Figure 17-1 shows a block diagram of the UART driver. In operation of UART0 and UART1, their operations are same as UART0 and UART1 Note: The UART1 control register ASIMR1,ASISR1, BRGCR1, RXR1 and TXR1 are located at EE6H ~ EE9H address. These address must be controlled (read and written) by absolute addressing manipulation instruction. Internal Data Bus Receive Buffer Register (RXR / RXR1) RXE RxD0 PIN / RxD1 PIN Receive Shift Register (RXSR) TXE 2 1 0 PE FE OVE TxD0 PIN / TxD1 PIN Transmit Shift Register (TXR / TXR1) (ASISR / ASISR1) Transmit Controller (Parity Addition) IFTX0 / IFTX1 Receive Controller (Parity Check) IFRX0 / IFRX1 UART0IF / UART1IF (UART0/1 interrupt) ACLK0 PIN / ACLK1 PIN fXIN/2 ~ fXIN/128 Baud Rate Generator Figure 17-1 UART Block Diagram 82 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 RECEIVE RXE ACLK0 PIN / ACLK1 PIN MUX 5-bit counter fXIN/2 ~ fXIN/128 match 1/2 (Divider) Tx_Clock 1/2 (Divider) Rx_Clock Decoder match - TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 (BRGCR / BRGCR1) 5-bit counter TXE Internal Data Bus SEND Figure 17-2 Baud Rate Generator Block Diagram 17.2 Serial Interface Configuration The UART interface consists of the following hardware. Item Configuration Register Transmit shift register (TXR) Receive buffer register (RXR) Receive shift register Control register Serial interface mode register (ASIMR) Serial interface status register (ASISR) Baudrate generator control register (BRGCR) Table 17-1 Serial Interface Configuration Transmit shift register (TXR) This is the register for setting transmit data. Data written to TXR is transmitted as serial data. When the data length is set as 7 bit, bit 0 to 6 of the data written to TX are transferred as transmit data. Writing data to TXR starts the transmit operation. TXR can be written by an 8 bit memory manipulation instruction. It cannot be read. The RESET input sets TXR to 0FFH. same address is assigned to TXR and the receive buffer register (RXR). A read operation reads values from RXR. Receive buffer register (RXR) This register is used to hold receive data. When one byte of data is received, one byte of new receive data is transferred from the receive shift register (RXSR). When the data length is set as 7 bits, receive data is sent to bits 0 to 6 of RXR. In this case, the MSB of RXR always becomes 0. RXR can be read by an 8 bit memory manipulation instruction. It cannot be written. The RESET input sets RXR to 00H. Note: The same address is assigned to RXR and the transmit shift register (TXR). During a write operation, values are written to TXR. Receive shift register This register converts serial data input via the RxD pin to paralleled data. When one byte of data is received at this register cannot be manipulated directly by a program. Note: Do not write to TXR during a transmit operation. The MAR. 2005 Ver 0.2 83 MC80F0424/0432/0448 Preliminary Asynchronous serial interface mode register (ASIMR) Asynchronous serial interface status register (ASISR) This is an 8 bit register that controls UART serial transfer operation. ASIMR is set by a 1 bit or 8 bit memory manipulation intruction. The RESET input sets ASIMR to 0000_-00-B. Table 172 shows the format of ASIMR. When a receive error occurs during UART mode, this register indicates the type of error. ASISR can be read by an 8 bit memory manipulation instruction. The RESET input sets ASISR to ----000B. Table 17-3 shows the format of ASISR. Address : 0E6H / EE6H Reset value : 0000-00-B ASIMR / ASIMR1 TXE RXE PS1 RXE Operation Mode TXE PS0 - RxD Pin Func. 0 0 Operation stop Port function(R46) 0 1 UART mode (Receive only) Serial function (RxD0) 1 0 UART mode (Transmit only) Port function (R46) UART mode ( RX & TX ) Serial function (RxD0) 1 1 PS1 PS0 SL TxD Pin Func. Serial function (TxD0) No parity 0 1 1 0 1 1 Zero parity always added during transmission. No parity detection during reception (parity errors do not occur) Odd parity Even parity Stop Bit Length for Specification for Transmit Data 1 bit 1 2 bit ISRM Receive interrupt request is issued when an error occurs 0 Receive Completion Interrupt Control When Error Occurs 1 Receive completion interrupt request is not issued when an error occurs Table 17-2 Asynchronous Serial Interface Mode register (ASIMR) format Note: Do not switch the operation mode until the current serial transmit/receive operation has stopped. 84 - - - - - PE FE OVE Parity Error Flag 0 No parity error 1 Parity error (Transmit data parity not matched) Frame Error Flag FE 0 No Frame error 1 Framing errorNote1 (stop bit not detected) Parity Bit Specification 0 0 ASISR / ASISR1 PE Port function(R47) 0 SL Address : 0E7H / EE7H Reset value : -----000B ISRM OVE Overrun Error Flag 0 No overrun error 1 Overrun errorNote2 (Next receive operation was completed before data was read from receive buffer register (RXR) Note 1. Even if a stop bit length is set to 2 bits by setting bit2(SL) in ASIMR, stop bit detection during a recive operation only applies to a stop bit length of 1bit. 2. Be sure to read the contents of the receive buffer register(RXR) when an overrun error has occurred. Until the contents of RXR are read, futher overrun errors will occur when receiving data. Table 17-3 Asynchronous Serial Interface Status Register (ASISR) Format Baud rate generator control register (BRGCR) This register sets the serial clock for serial interface. BRGCR is set by an 8 bit memory manipulation instruction. The RESET input sets BRGCR to -001_0000B. Table 17-4 shows the format of BRGCR. MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 Address : 0E8H / EE8H Reset value : -0010000B BRGCR / BRGCR1 - TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 TPS2 TPS1 TPS0 Source Clock Selection for 5 Bit count n MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 ACLK0 / ACLK1 0 0 1 fXIN / 2 0 1 0 0 0 0 1 0 fXIN / 4 2 0 0 1 0 1 1 fXIN / 8 0 0 1 0 0 fXIN / 16 3 4 0 1 0 1 fXIN / 32 5 1 1 0 fXIN / 64 1 1 1 fXIN / 128 Caution Input Clock Selection k fSCK / 16 0 1 fSCK / 17 1 0 fSCK / 18 2 1 1 fSCK / 19 3 1 0 0 fSCK / 20 4 0 1 0 1 fSCK / 21 5 6 0 1 1 0 fSCK / 22 6 7 0 1 1 1 fSCK / 23 7 1 0 0 0 fSCK / 24 8 1 0 0 1 fSCK / 25 9 1 0 1 0 10 1 0 1 1 fSCK / 26 fSCK / 27 1 1 0 0 fSCK / 28 12 1 1 0 1 fSCK / 29 13 1 1 1 0 fSCK / 30 1 1 1 1 Setting prohibited 14 - Writing to BRGCR/BRGXR1 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. Therefore, do not write to BRGCR/BRGCR1 during a communication operation. Remarks 1. fSCK : Source clock for 5 bit counter 2. n : Value set via TPS0 to TPS2 ( 0 ≤ n ≤ 7 ) 3. k : Source clock for 5 bit counter ( 0 ≤ k ≤ 14 ) 11 Table 17-4 Baud Rate Generator Control Register (BRGCR / BRGCR1) Format 17.3 Communication operation 1 data frame TxD RxD Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop character bits TX INTERRUPT (In case of 1 stop bit) RX INTERRUPT (In case of 1 stop bit) 1 data frame consists of following bits. - Start bit : 1 bit - Character bits : 8 bits - Parity bit : Even parity, Odd parity, Zero parity, No parity - Stop bit(s) : 1 bit or 2 bits Figure 17-3 UART data format and interrupt timing diagram The transmit operation is enabled when bit 7 (TXE) of the asynchronous serial interface mode register (ASIMR/ASIMR1) is set to 1. The transmit operation is started when transmit data is written to the transmit shift register (TXR). The timing of the transmit completion interrupt request is shown in Figure 17-3. The receive operation is enabled when bit 6 (RXE) of the asyn- MAR. 2005 Ver 0.2 chronous serial interface mode register (ASIMR/ASIMR1) is set to 1, and input via the RxD0 pin is sampled. The serial clock specified by ASIMR/ASIMR1 is used to sample the RxD0/RxD1 pin. Once reception of one data frame is completed, a receive completion interrupt request (UART0IF/UART1IF) occurs. Even if an error has occurred, the receive data in which the error occurred is 85 MC80F0424/0432/0448 Preliminary still transferred to RXR. When bit 1 (ISRM) of ASIMR(ASIMR1) is cleared to 0 upon occurrence of an error, interrupt by Rx occurs. When ISRM bit is set to 1, interrupt by Rx does not occur in case of error occurrence. Figure 17-3 shows the timing of the asynchronous serial interface receive completion interrupt request. 17.4 Relationship between main clock and baud rate Baud Rate = fXIN / ( 2n+1(k+16) ) The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock or ACLK0/ACLK1 pin clock. The baud rate generated from the main system clock or ACLK0/ACLK1 pin clock is determined according to the following formula. If the high 4 bits of BRGCR/BRGCR1 is 0, ACLK0/ ACLK1 pin clock is used for source clock of baud rate generator. fXIN=12M Baud Rate (bps) fXIN=11.0592M fXIN=10.0M - fXIN : Main system clock oscillation frequency When ACLK0/ACLK1 is selected as the source clock of the 5-bit counter, substitute the input clock frequency to ACLK0/ACLK1 pin clock for in the above expression. - n : Value set via TPS0 to TPS2 (0 ≤ n ≤ 7) - k : Value set via MDL0 to MDL3 (0 ≤ k ≤ 14) fXIN=8.0M fXIN=6.0M fXIN=5.0M fXIN=4.0M BRGCR ERR (%) BRGCR ERR (%) BRGCR ERR (%) BRGCR ERR (%) BRGCR ERR (%) BRGCR ERR (%) BRGCR ERR (%) 600 - - - - - - - - - - - - 7AH 0.16 1200 - - - - - - 7AH 0.16 74H 2.34 70H 1.73 6AH 0.16 2400 74H 2.34 72H 0.00 70H 1.73 6AH 0.16 64H 2.34 60H 1.73 5AH 0.16 4800 64H 2.34 62H 0.00 60H 1.73 5AH 0.16 54H 2.34 50H 1.73 4AH 0.16 9600 54H 2.34 52H 0.00 50H 1.73 4AH 0.16 44H 2.34 40H 1.73 3AH 0.16 19200 44H 2.34 42H 0.00 40H 1.73 3AH 0.16 34H 2.34 30H 1.73 2AH 0.16 31250 38H 0.00 36H 0.53 34H 0.00 30H 0.00 28H 0.00 24H 0.00 20H 0.00 38400 34H 2.34 32H 0.00 30H 1.73 2AH 0.16 24H 2.34 20H 1.73 1AH 0.16 57600 2AH 0.16 28H 0.00 26H 1.35 21H 2.11 1AH 0.16 16H 1.36 11H 2.12 76800 24H 2.34 22H 0.00 20H 1.73 1AH 0.16 14H 2.34 10H 1.73 - - 115200 1AH 0.16 18H 0.00 16H 1.36 11H 2.12 - - - - - - Table 17-5 Relationship between main clock and Baud Rate 86 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 17.5 Communication operation The transmit operation is enabled when bit 7 (TXE) of the asynchronous serial interface mode register (ASIMR/ASIMR1) is set to 1. The transmit operation is started when transmit data is written to the transmit shift register (TXR/TXR1). The timing of the transmit completion interrupt request is shown in Figure 17-3. The receive operation is enabled when bit 6 (RXE) of the asynchronous serial interface mode register (ASIMR/ASIMR1) is set to 1, and input via the RxD0/RxD1 pin is sampled. The serial clock specified by ASIMR/ASIMR1 is used to sample the RxD0/ RxD1 pin. Once reception of one data frame is completed, a receive completion interrupt request (UART0IF/UART1IF) occurs. Even if an error has occurred, the receive data in which the error occurred is still transferred to RXR/RXR1. When ASIMR bit 1 (ISRM) is cleared to 0 upon occurrence of an error, UART0/ UART1 interrupt occurs. When ISRM bit is set to 1, UART0/ UART1 interrupt does not occur in case of error occurrence. Figure 17-3 shows the timing of the asynchronous serial interface receive completion interrupt request. In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. These flag bits must be cleared by software after reading this register. Each processing step is determined by IFR as shown MAR. 2005 Ver 0.2 in Figure 17-1. UART0(UART1) Interrupt Request IFTX0(IFTX1) =0 =1 TX0(TX1) Interrupt Routine Clear IFTX0(IFTX1) IFRX0(IFRX1) =0 =1 RX0(RX1) Interrupt Routine Clear IFRX0(IFRX1) RETI Figure 17-1 Shared Interrupt Vector of UART 87 MC80F0424/0432/0448 Preliminary 18. BUZZER FUNCTION The buzzer driver block consists of 6-bit binary counter, buzzer register BUZR, and clock source selector. It generates squarewave which has very wide range frequency (488Hz ~ 250kHz at fXIN= 4MHz) by user software. The bit 0 to 5 of BUZR determines output frequency for buzzer driving. A 50% duty pulse can be output to R13/BUZO pin to use for piezo-electric buzzer drive. Pin R13 is assigned for output port of Buzzer driver by setting the bit 2 of PSR1(address 0F9H) to “1”. For PSR1 register, refer to Figure 10-3. f XIN f BUZ = --------------------------------------------------------------------------2 × DivideRatio × ( BUR + 1 ) Equation of frequency calculation is shown below. fBUZ: Buzzer frequency fXIN: Oscillator frequency Example: 5kHz output at 4MHz. LDM LDM Divide Ratio: Prescaler divide ratio by BUCK[1:0] BUR: Lower 6-bit value of BUZR. Buzzer period value. BUZR,#0011_0001B PSR1,#XXXX_X1XXB The frequency of output signal is controlled by the buzzer control register BUZR. The bit 0 to bit 5 of BUZR determine output frequency for buzzer driving. X means don’t care R13 port data XIN PIN Prescaler ÷8 ÷ 16 ÷ 32 ÷ 64 6-BIT BINARY COUNTER 00 MUX 01 0 10 F/F 11 1 R13/BUZO PIN Comparator MUX 2 Compare data BUZO 6 PSR1 BUR Port selection register 1 [0F9H] [0E0H] Internal bus line Figure 18-1 Block Diagram of Buzzer Driver ADDRESS: 0E0H Reset VALUE: 0FFH W BUZR W W W W W W W BUCK1 BUCK0 BUR[5:0] Buzzer Period Data Source clock select 00: fXIN ÷ 8 01: fXIN ÷ 16 10: fXIN ÷ 32 11: fXIN ÷ 64 Figure 18-2 Buzzer Register 88 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 The 6-bit counter is cleared and starts the counting by writing signal at BUZR register. It is incremental from 00H until it matches 6-bit BUR value. When main-frequency is 4MHz, buzzer frequency is shown as below Table 18-1. BUR [5:0] BUR[7:6] 00 01 10 11 BUR [5:0] BUR[7:6] 00 01 10 11 00 01 02 03 04 05 06 07 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 20 21 22 23 24 25 26 27 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 08 09 0A 0B 0C 0D 0E 0F 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 28 29 2A 2B 2C 2D 2E 2F 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 10 11 12 13 14 15 16 17 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 30 31 32 33 34 35 36 37 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 18 19 1A 1B 1C 1D 1E 1F 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977 38 39 3A 3B 3C 3D 3E 3F 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.907 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488 Table 18-1 buzzer frequency (kHz unit) MAR. 2005 Ver 0.2 89 MC80F0424/0432/0448 Preliminary 19. INTERRUPTS The MC80F0424/0432/0448 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit, and Master enable flag (“I” flag of PSW). Fifteen interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 19-1 and interrupt priority is shown in Table 19-1. T2IF, T3IF and T4IF which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register. The AD converter Interrupt is generated by ADCIF which is set by finishing the analog to digital conversion. The External Interrupts INT0 ~ INT3 each can be transition-activated (1-to-0 or 0-to-1 transition) by selection IEDS register. The flags that actually generate these interrupts are bit INT0IF, INT1IF, INT2IF and INT3IF in register IRQH. When an external interrupt is generated, the generated flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Watchdog timer and Watch Timer Interrupt is generated by WDTIF and WTIF which is set by a match in Watchdog timer register or Watch timer register. The IFR(Interrupt Flag Register) is used for discrimination of the interrupt source among these two Watchdog timer and Watch Timer Interrupt. The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflow in the timer counter register. The Timer 0 ~ Timer 4 Interrupts are generated by T0IF, T1IF, Internal bus line [0EAH] IENH Interrupt Enable Register (Higher byte) IRQH [0ECH] INT0 INT0IF INT1 INT2 INT1IF I-flag is in PSW, it is cleared by “DI”, set by “EI” instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by “RETI” instruction, I-flag is set to “1” by hardware. Release STOP/SLEEP INT2IF INT3 UART0IF UART1 Tx/Rxt UART1IF Serial Communication Timer 0 Priority Control INT3IF UART0 Tx/Rx SIOIF T0IF IRQL [0EDH] Timer 1 T1IF Timer 2 T2IF Timer 3 T3IF Timer 3 T4IF A/D Converter ADCIF Watchdog Timer WDTIF Watch Timer WTIF BIT BITIF To CPU I-flag Interrupt Master Enable Flag Interrupt Vector Address Generator [0EBH] IENL Interrupt Enable Register (Lower byte) Internal bus line Figure 19-1 Block Diagram of Interrupt 90 MAR. 2005 Ver 0.2 Preliminary The UART receive/transmit interrupt is generated by UART0IF and UART1IF which are set by completion of UART data reception or transmission. MC80F0424/0432/0448 Reset/Interrupt The SIO interrupt is generated by SIOIF which is set by completion of SIO data reception or transmission. Hardware Reset External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 UART0 Rx/Tx Interrupt UART1 Rx/Tx Interrupt Serial Input/Output Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 Timer/Counter 4 ADC Interrupt Watchdog/Watch Timer Basic Interval Timer The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on Figure 8-3), the interrupt enable register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except Power-on reset and software BRK interrupt. The Table 19-1 shows the Interrupt priority. Vector addresses are shown in Figure 8-6. Interrupt enable registers are shown in Figure 19-2. These registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. Symbol Priority RESET INT0 INT1 INT2 INT3 UART0 UART1 SIO Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 ADC WDT_WT BIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Table 19-1 Interrupt Priority R/W IENH INT0E R/W R/W R/W R/W R/W R/W INT1E INT2E INT3E UART0E UART1E SIOE R/W ADDRESS: 0EAH INITIAL VALUE: 0000 0000B T0E MSB LSB Timer/Counter 0 interrupt enable flag Serial Communication interrupt enable flag UART1 Tx/Rx interrupt enable flag UART0 Tx/Rx interrupt enable flag External interrupt 0 enable flag External interrupt 1 enable flag External interrupt 2 enable flag External interrupt 3 enable flag IENL R/W R/W R/W R/W R/W R/W T1E T2E T3E T4E ADCE WDTE WTE BITE MSB R/W R/W ADDRESS: 0EBH INITIAL VALUE: 0000 0000B LSB Basic Interval Timer interrupt enable flag Watch timer interrupt enable flag Watchdog timer interrupt enable flag A/D Converter interrupt enable flag Timer/Counter 4 interrupt enable flag Timer/Counter 3 interrupt enable flag Timer/Counter 2 interrupt enable flag Timer/Counter 1 interrupt enable flag Figure 19-2 Interrupt Enable Flag Register MAR. 2005 Ver 0.2 91 MC80F0424/0432/0448 R/W IRQH Preliminary R/W R/W R/W R/W R/W R/W INT0IF INT1IF INT2IF INT3IF UART0IF UART1IF SIOIF R/W T0IF MSB ADDRESS: 0ECH INITIAL VALUE: 0000 0000B LSB Timer/Counter 0 interrupt request flag Serial Communication interrupt request flag UART1Tx/Rx interrupt request flag UART0 Tx/Rx interrupt request flag External interrupt 3 request flag External interrupt 2 request flag External interrupt 1 request flag External interrupt 0 request flag IRQL R/W R/W R/W R/W T1IF T2IF T3IF T4IF ADCIF WDTIF WTIF BITIF R/W R/W R/W R/W ADDRESS: 0EDH INITIAL VALUE: 0000 0000B LSB MSB Basic Interval Timer interrupt request flag Watch timer interrupt request flag Watchdog timer interrupt request flag A/D Converter interrupt request flag Timer/Counter 4 interrupt request flag Timer/Counter 3 interrupt request flag Timer/Counter 2 interrupt request flag Timer/Counter 1 interrupt request flag IFR - - R/W R/W R/W R/W R/W R/W IFRX0 IFTX0 IFRX1 IFTX1 IFWT IFWDT ADDRESS: 0DFH INITIAL VALUE: --00 0000B LSB MSB WDT interrupt occurred flagNOTE1 WT interrupt occurred flagNOTE1 UART1 Tx interrupt occurred flagNOTE2 UART1 Rx interrupt occurred flagNOTE2 UART0 Tx interrupt occurred flagNOTE3 UART0 Rx interrupt occurred flagNOTE3 NOTE1 : In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE2 : In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE3 : In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. Figure 19-3 Interrupt Request Flag Register 19.1 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 8 cycles of fXIN (2µs at fX- 92 IN =4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI]. MAR. 2005 Ver 0.2 Preliminary 19.1.1 Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to “0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to “0”. MC80F0424/0432/0448 and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed. 3. The contents of the program counter (return address) System clock Instruction Fetch SP Address Bus PC Data Bus Not used SP-1 PCH PCL SP-2 PSW V.L. V.L. V.H. ADL New PC ADH OP code Internal Read Internal Write Interrupt Processing Step Interrupt Service Task V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents. Figure 19-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction Basic Interval Timer Vector Table Address Entry Address 19.1.2 Saving/Restoring General-purpose Register 0EH 2EH During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. The following method is used to save/restore the general-purpose registers. 0FFE0H 0FFE1H 012H 0E3H 0E312H 0E313H A interrupt request is not accepted until the I-flag is set to “1” even if a requested interrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to “1” by “EI” instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. MAR. 2005 Ver 0.2 Example: Register save using push and pop instructions INTxx: PUSH PUSH PUSH A X Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG. interrupt processing 93 MC80F0424/0432/0448 POP POP POP RETI Y X A Preliminary ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN main task acceptance of interrupt interrupt service task saving registers General-purpose register save/restore using push and pop instructions; restoring registers interrupt return 19.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 19-5. B-FLAG BRK or TCALL0 =0 =1 BRK INTERRUPT ROUTINE TCALL0 ROUTINE RETI RET Figure 19-5 Execution of BRK/TCALL0 19.3 Shared Interrupt Vector In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and 94 UART0 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. Each processing step is determined by IFR as shown in Figure 19-6. MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 UART0(UART1) Interrupt Request WDT or WT Interrupt Request IFTX0(IFTX1) =0 =1 IFWDT =0 IFWT =1 =0 =1 WDT Interrupt Routine TX0(TX1) Interrupt Routine Clear IFTX0(IFTX1) WT Interrupt Routine IFRX0(IFRX1) Clear IFWDT =0 Clear IFWT =1 RX0(RX1) Interrupt Routine RETI Clear IFRX0(IFRX1) RETI Figure 19-6 Software Flowchart of Shared Interrupt Vector 19.4 Multi Interrupt If two interrupt requests of different priority level are received simultaneously, the request of higher priority level is serviced. If interrupt requests of of equal priority level are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the Iflag is cleared to disable any further interrupt. But as user sets Iflag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. Refer to Figure 19-7. Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER1: PUSH PUSH A X MAR. 2005 Ver 0.2 PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI Y IENH,#80H IENL,#0 ;Enable INT0 only ;Disable other int. ;Enable Interrupt IENH,#0FFH ;Enable all interrupts IENL,#0FFH Y X A 95 MC80F0424/0432/0448 Main Program service Preliminary TIMER 1 service enable INT0 disable other INT0 service EI Occur TIMER1 interrupt Occur INT0 enable INT0 enable other In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable “EI” in the TIMER1 routine. Figure 19-7 Execution of Multi Interrupt 19.5 External Interrupt The external interrupt on INT0, INT1, INT2 and INT3 pins are edge triggered depending on the edge selection register IEDS (address 0EEH) as shown in Figure 19-8. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. INT0 ~ INT3 are multiplexed with general I/O ports (R10, R11, R12, R50). To use as an external interrupt pin, the bit of port selection register PSR0 should be set to “1” correspondingly. INT0 pin INT0IF INT0 INTERRUPT INT1 pin INT1IF Example: To use as an INT0 and INT2 : ;**** Set external interrupt port as pull-up state. LDM PU1,#0000_0101B ; ;**** Set port as an external interrupt port LDM PSR0,#0000_0101B ; ;**** Set Falling-edge Detection LDM IEDS,#0001_0001B : INT1 INTERRUPT INT2 pin INT2IF INT2 INTERRUPT INT3 pin INT3IF INT3 INTERRUPT 2 2 IEDS 2 2 Edge selection Register [0EEH] Figure 19-8 External Interrupt Block Diagram 96 MAR. 2005 Ver 0.2 Preliminary Response Time twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. The INT0 ~ INT3 edge are latched into INT0IF ~ INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of max. 12 fXIN MC80F0424/0432/0448 Figure 19-9 shows interrupt response timings. 8 fXIN Interrupt Interrupt goes latched active Interrupt processing Interrupt routine Figure 19-9 Interrupt Response Timing Diagram MSB W IEDS W W W W W W LSB W IED3H IED3L IED2H IED2L IED1H BTCL IED1L IED0H IED0L INT3 INT2 INT1 ADDRESS: 0EEH INITIAL VALUE: 00H INT0 Edge selection register 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling) W PSR0 W W PWM3O PWM1O EC1E MSB W W W W W EC0E INT3E BTCL INT2E INT1E INT0E ADDRESS: 0F8H INITIAL VALUE: 00H 0: R54 1: PWM3O LSB 0: R10 1: INT0 0: R53 1: PWM1O 0: R11 1: INT1 0: R51 1: EC1 0: R12 1: INT2 0: R15 1: EC0 0: R50 1: INT3 Figure 19-10 IEDS register and Port Selection Register PSR0 MAR. 2005 Ver 0.2 97 MC80F0424/0432/0448 Preliminary 20. OPERATION MODE Sub Active mode The system clock controller starts or stops the main-frequency clock oscillator and switches between the main and sub frequency clock. The operating mode is generally divided into the main active mode, the sub active mode 1 and sub active mode 2, which are controlled by System clock control register (SCMR). Figure 20-1 shows the operating mode transition diagram. This mode is low-frequency operating mode. In this mode, the CPU and the peripheral hardware clock are provided by low-frequency clock oscillation, so power consumption can be reduced. SLEEP mode System clock control is performed by the system clock mode register, SCMR. During reset, this register is initialized to “0” so that the main-clock operating mode is selected. In this mode, the CPU clock stops while peripherals and the oscillation source continues to operate normally. Main Active mode STOP mode This mode is fast-frequency operating mode. The CPU and the peripheral hardware are operated on the high-frequency clock. At reset release, this mode is invoked. In this mode, the system operations are all stopped, holding the internal states valid immediately before the stop at the low power consumption level. The main oscillation source stops, but the sub clock oscillation and watch timer by sub clock and RC-oscillated watchdog timer don’t stop. Main : Oscillation Sub : Oscillation System Clock : Sub Main : Oscillation Sub : Oscillation or stop System Clock : Main LDM SCMR, #02H Sub Active Main Active Mode Mode 1 LDM SCMR, #01H ot e4 *N CLR1 SCMR.2 * Note4 * Note2 : Sleep released by Reset, or All interrupts SET1 SCMR.2 * Note1 / * Note2 *N ot e1 /N e3 ot e 2 ot *N * Note1 : Stop released by Reset, Watch Timer, Watchdog Timer Timer(event counter), SIO (External clock), UART External interrupt LD M * Note3 : List of instruction is CLR1 SCMR.2 ;Main OSC ON NOP ;for Oscillation stabilization time NOP ;for Oscillation stabilization time LDM SCMR, #01H SC R M ,# H 06 Stop / Sleep * Note1 / Note2 Sub Active Mode 2 Mode * Note4 Stop : System Clock Oscillation stop Sleep : System Clock Oscillation run (CPU stops, Peripherals operate) Main : Stop Sub : Oscillation System Clock : Sub * Note4 : 1) Stop mode Admission LDM SSCR, #5AH STOP NOP NOP 2) Sleep mode Admission LDM SSCR, #0FH - Sub clock cannot be stopped by STOP instruction. Figure 20-1 Operating Mode 98 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 20.1 Operation Mode Switching In the Main active mode, only the high-frequency clock oscillator is used. In the Sub active mode, the low-frequency clock oscillation is used, so the low power voltage operation or the low power consumption operation can be enabled. Instruction execution does not stop during the change of operation mode. In this case, some peripheral hardware capabilities may be affected. For details, refer to the description of the relevant operation. The following describes the switching between the Main active mode and the Sub active mode. During reset, the system clock mode register is initialized at the Main active mode. It must be set to the Sub active mode for reducing the power consumption. with the length of two or more NOP instruction. Sub active mode can also be released by setting the RESET pin to low, which immediately performs the reset operation. After reset, the MC80F0424/0432/0448 is placed in Main active mode. Example: CLR1 SCMR.2 ;Turn on main-clock NOP ;for OSC stabilization time NOP ;for OSC stabilization time LDM SCMR,#01h ;Move to main active Returning from Sub active 2 to Sub active 1 Switching from Main active to Sub active 1 First, write “02H” into SCMR to switch the main system clock to the sub-frequency clock of Sub Active mode 1. Example: LDM First, write “06H” into SCMR to switch the main system clock to the sub-frequency clock of Sub Active mode 2. Example: SCMR,#06H ;Switch to sub active2 Returning from Sub active 1 to Main active First, write “01H” into SCMR to turn on the main-frequency oscillation. Sub active mode can also be released by setting the RESET pin to low, which immediately performs the reset operation. After reset, the MC80F0424/0432/0448 is placed in Main active mode. Example: LDM SCMR,#01H ;Switch to main-clock Switching from Sub active 1 to Sub active 2 First, set SCMR.2 to switch the main system clock to the sub-frequency clock of Sub Active mode 2. Example: SET1 CLR1 SCMR.2 ;Switch to sub active1 SCMR,#02H ;Switch to sub active1 Switching from Main active to Sub active 2 LDM First, clear SCMR.2 to switch the main system clock to the subfrequency clock of Sub Active mode 2. Example: SCMR.2 ;Switch to sub active2 Returning from Sub active 2 to Main active First, set the SCMR.2 bit clear, and wait for a while for oscillation stabilization time. Secondly, write “01H” into the SCMR to turn on the main-frequency oscillation. This time, the stabilization (warm-up) time needs to be taken by the software delay routine MAR. 2005 Ver 0.2 Shifting from the Normal operation to the SLEEP mode If the SLEEP mode is invoked, the external clock oscillation does not stops but the CPU clock stops while other peripherals are operate normally. The ways of release from this mode are by setting the RESET pin to low and all available interrupts. For more detail, See "21. POWER SAVING OPERATION" on page 101. Shifting from the Normal operation to the STOP mode If the STOP mode is invoked, the main-frequency clock oscillation stops and the CPU clock stops and other peripherals are stop too. But sub-frequency clock oscillation operate continuously if enabled previously. After the STOP operation is released by reset, the operation mode is changed to Main active mode. The methods of release from this mode are Reset, Watch Timer, RC watchdog timer, Event counter, SIO(External clock), UART, and External Interrupt. For more details, see "21. POWER SAVING OPERATION" on page 101. Note: In the STOP and SLEEP operating modes, the power consumption by the oscillator and the internal hardware is reduced. However, the power for the pin interface (depending on external circuitry and program) is not directly associated with the low-power consumption operation. This must be considered in system design as well as interface circuit design. 99 MC80F0424/0432/0448 Preliminary ~ ~ Sub freq. clock (SXIN pin) ~ ~ ~ ~ Main freq. clock (XIN pin) ~ ~ ~ ~ Operation clock Main-clock operation Sub-clock operation Changed to the Sub-clock SCMR ← XXXX X010B Turn off main clock SCMR.2 bit HIGH (a) Main active mode → Sub active mode 1 → Sub active mode 2 ~ ~ ~ ~ Main freq. clock (XIN pin) Stabilizing Time > 20ms ~ ~ Sub freq. clock (SXIN pin) Operation clock ~ ~ Sub-clock operation Changed to the Transition SCMR.2 bit LOW Main-clock operation Changed to the Main-clock SCMR ← XXXX X000B or XXXX X001B (b) Sub active mode 2 → Sub active mode 1 → Main active mode Figure 20-2 System Clock Switching Timing 100 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 21. POWER SAVING OPERATION The MC80F0424/0432/0448 has two power-down modes. In power-down mode, power consumption is reduced considerably. For applications where power consumption is a critical factor, device provides two kinds of power saving functions, STOP mode and SLEEP mode. Table 21-1 shows the status of each Power Saving Mode. SLEEP mode is entered by the SSCR register to “0Fh”., and STOP mode is entered by STOP instruction after the SSCR register to “5Ah”. 21.1 Sleep Mode In this mode, the internal oscillation circuits remain active and oscillation continues and peripherals are operate normally, but CPU stops. Movement of all peripherals is shown in Table 21-1. SLEEP mode is entered by setting the SSCR register to “0Fh”. It W 7 W 6 W 5 W 4 W 3 is released by Reset or interrupt. To be released by interrupt, interrupt should be enabled before SLEEP mode. W 2 W 1 W 0 ADDRESS: 0F5H INITIAL VALUE: 0000 0000B SSCR Power Down Control 5AH: STOP mode 0FH: SLEEP mode 1. To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution. At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released. 2. To get into SLEEP mode, SSCR must be set to 0FH. Figure 21-1 STOP and SLEEP Control Register Release the SLEEP mode The exit from SLEEP mode is hardware reset or all interrupts. Reset re-defines all the Control registers but does not change the on-chip RAM. Interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction following the SLEEP instruction. It will not vector to interrupt service routine. (refer to Figure 21-4) MAR. 2005 Ver 0.2 When exit from SLEEP mode by reset, enough oscillation stabilization time is required to normal operation. Figure 21-3 shows the timing diagram. his guarantees that oscillator has started and stabilized. By interrupts, exit from SLEEP mode is shown in Figure 21-2. By reset, exit from SLEEP mode is shown in Figure 213. 101 MC80F0424/0432/0448 Preliminary . ~ ~ ~ ~ ~ ~ CPU Clock ~ ~ ~ ~ ~ ~ ~ ~ Oscillator (XIN pin) SLEEP Instruction Executed Normal Operation SLEEP Operation ~ ~ External Interrupt Normal Operation Figure 21-2 SLEEP Mode Release Timing by External Interrupt ~ ~ ~ ~ Oscillator (XIN pin) ~ ~ CPU Clock ~ ~ Internal RESET ~ ~ ~ ~ RESET ~ ~ SLEEP Instruction Execution Normal Operation Stabilization Time tST = 65.5mS @4MHz Normal Operation SLEEP Operation Figure 21-3 Timing of SLEEP Mode Release by Reset 21.2 Stop Mode In the Stop mode, the main oscillator, system clock and peripheral clock is stopped, but the sub clock oscillation and Watch Timer by sub clock and RC-oscillated watchdog timer continue to operate. With the clock frozen, all functions are stopped, but the onchip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up. • The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held. • The program counter stop the address of the instruction to be executed after the instruction 102 "STOP" which starts the STOP operating mode. Note: The Stop mode is activated by execution of STOP instruction after setting the SSCR to “5AH”. (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. MAR. 2005 Ver 0.2 Preliminary The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. Note: After STOP instruction, at least two or more NOP instruction should be written. Ex) LDM CKCTLR,#0FH ;more than 20ms LDM SSCR,#5AH STOP NOP ;for stabilization time NOP ;for stabilization time MC80F0424/0432/0448 with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. In the STOP operation, the dissipation of the power associated Peripheral STOP Mode SLEEP Mode CPU Stop Stop RAM Retain Retain Basic Interval Timer Halted (Only operates in RC-WDT mode) Operates Continuously Watchdog Timer Stop (Only operates in RC-WDT mode) Stop Watch Timer Stop (Only operates in Subclock mode) Stop Timer/Counter Halted(Only when the event counter mode is enabled, timer operates normally) Operates Continuously Buzzer, ADC Stop Stop SIO Only operate with external clock Only operate with external clock UART Only operate with external clock Only operate with external clock Oscillator Stop(XIN=L, XOUT=H) Oscillation Sub Oscillator Oscillation Oscillation I/O Ports Retain Retain Control Registers Retain Retain Internal Circuit Stop mode Sleep mode Prescaler Retain Active Address Data Bus Retain Retain Release Source Reset, Timer(EC0, EC1), RC WDT Timer, Watch Timer(Subclock), SIO(ext. clock), UART, External Interrupt Reset, All Interrupts Table 21-1 Peripheral Operation During Power Saving Mode Release the STOP mode The source for exit from STOP mode is hardware reset, external interrupt, Timer(Event Counter), Watchdog Timer(RCWDT), Watch Timer(by subclock), SIO(by external clock) or UART. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction fol- MAR. 2005 Ver 0.2 lowing the STOP instruction. It will not vector to interrupt service routine. (refer to Figure 21-4) When exit from Stop mode by external interrupt, enough oscillation stabilization time is required to normal operation. Figure 215 shows the timing diagram. When released from the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must set its relevant prescaler divide ratio to have long enough time (more than 103 MC80F0424/0432/0448 Preliminary 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure 21-6. STOP INSTRUCTION STOP Mode Interrupt Request Corresponding Interrupt Enable Bit (IENH, IENL) =0 IENH or IENL ? =1 STOP Mode Release Master Interrupt Enable Bit PSW[2] I-FLAG =0 =1 Interrupt Service Routine Next INSTRUCTION Figure 21-4 STOP Releasing Flow by Interrupts . ~ ~ ~ ~ ~ ~ Oscillator (XIN pin) ~ ~ ~ ~ internal system Clock ~ ~ STOP Instruction Executed n+1 n+2 n+3 0 1 ~ ~ ~ ~ n ~ ~ ~ ~ BIT Counter ~ ~ External Interrupt FE FF 0 1 2 Clear Normal Operation Stop Operation Stabilization Time tST > 20ms by software Normal Operation Before executing Stop instruction, Basic Interval Timer must be set properly by software to get stabilization time which is longer than 20ms. Figure 21-5 STOP Mode Release Timing by External Interrupt 104 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 STOP Mode ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Internal RESET ~ ~ RESET ~ ~ Internal Clock ~ ~ ~ ~ Oscillator (XI pin) STOP Instruction Execution Time can not be control by software Stabilization Time tST = 65.5mS @4MHz Figure 21-6 Timing of STOP Mode Release by Reset 21.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after setting the bit RCWDT of CKCTLR to "1". (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) Note: Caution: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM WDTR,#1111_1111B LDM CKCTLR,#0010_1110B LDM SSCR,#0101_1010B STOP NOP ;for stabilization time NOP ;for stabilization time The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt including RC watchdog tim- MAR. 2005 Ver 0.2 er. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine(Figure 8-6). However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal Reset signal and execute the reset processing(Figure 21-8). If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.(refer to Figure 21-4) When exit from Stop mode at Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to normal operation. Figure 21-7 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from internal RC-Oscillated Watchdog Timer mode is shown in Figure 21-8. 105 MC80F0424/0432/0448 Preliminary ~ ~ ~ ~ ~ ~ Oscillator (XIN pin) Internal RC Clock ~ ~ ~ ~ Internal Clock ~ ~ External Interrupt ( or WDT Interrupt ) ~ ~ STOP Instruction Execution ~ ~ N-2 N-1 N N+1 N+2 00 01 FE FF 00 00 ~ ~ BIT Counter Clear Basic Interval Timer Normal Operation STOP mode at RC-WDT Mode Stabilization Time tST > 20mS Normal Operation Figure 21-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt RCWDT Mode ~ ~ ~ ~ ~ ~ Oscillator (XIN pin) Internal RC Clock ~ ~ ~ ~ ~ ~ RESET ~ ~ Internal Clock RESET by WDT ~ ~ STOP Instruction Execution Time can not be control by software ~ ~ Internal RESET Stabilization Time tST = 65.5mS @4MHz Figure 21-8 Internal RC-WDT Mode Releasing by Reset 106 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 21.4 Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn- off output drivers that are sourcing or sinking current, if it is practical. VDD INPUT PIN INPUT PIN VDD VDD internal pull-up VDD i=0 O OPEN O i i GND Very weak current flows VDD X X i=0 O OPEN Weak pull-up current flows GND O When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption. Figure 21-9 Application Example of Unused Input Port OUTPUT PIN OUTPUT PIN VDD ON OPEN OFF ON OFF ON O OFF i VDD GND X ON OFF L OFF ON i GND X O VDD L i=0 GND O In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port . In the left case, much current flows from port to GND. Figure 21-10 Application Example of Unused Output Port Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher MAR. 2005 Ver 0.2 than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means. It should be set properly in order that current flow through port doesn't exist. First consider the port setting to input mode. Be sure that there is 107 MC80F0424/0432/0448 Preliminary no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn’t flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if uncertain voltage level (not VSS or VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. 108 If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. The port setting to High or Low is decided by considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pulldown register, it is set to low. MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 22. OSCILLATOR CIRCUIT The MC80F0424/0432/0448 has two oscillation circuits internally. XIN and XOUT are input and output for frequency, and SXIN and SXOUT are input and output for sub frequency, respectively, inverting amplifier which can be configured for being used as an on-chip oscillator, as shown in Figure 22-1. Note: When using the sub clock oscillation, connect a resistor in series with R which is shown as below Figure 221. In order to reduce the power consumption, the sub clock oscillator employs a low amplification factor circuit. Because of this, the sub clock oscillator is more sensitive to noise than the main system clock oscillator. C1 C1 XOUT C2 8MHz R C2 XIN 32.768kHz SXOUT SXIN VSS VSS Recommend C1,C2 = 30pF ~ 90pF R = 5.7kΩ (if necessary) Recommended Crystal Oscillator C1,C2 = 20pF ± 10pF Ceramic Resonator C1,C2 = 20pF ± 10pF Crystal or Ceramic Oscillator Open External Clock XOUT XIN External Oscillator Figure 22-1 Oscillation Circuit Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. In addition, see Figure 22-2 for the layout of the crystal. XOUT Note: Minimize the wiring length. Do not allow the wiring to intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator. XIN Figure 22-2 Layout of Oscillator PCB circuit MAR. 2005 Ver 0.2 109 MC80F0424/0432/0448 Preliminary 23. RESET The MC80F0424/0432/0448 have four types of reset generation procedures; they are an external reset input, a watch-dog timer reOn-chip Hardware Initial Value On-chip Hardware Initial Value (FFFFH) - (FFFEH) Peripheral clock Off (RPR) 0 Watchdog timer Disable (G) 0 Control registers Refer to Table 8-1 Program counter RAM page register set, power fail processor reset, and address fail reset. Table 23-1 shows on-chip hardware initialization by reset action. (PC) G-flag Operation mode Main-frequency clock Power fail detector Disable Table 23-1 Initializing Internal Status by Reset Action External Reset Input The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. After reset, 65.5ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 23-2. VCC 10kΩ to the RESET pin 7036P + Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before read or tested it. 10uF When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. Figure 23-1 Simple Power-on-Reset Circuit A connection for simple power-on-reset is shown in Figure 23-1. 1 ? ? 4 5 6 7 ~ ~ ? FFFE FFFF Start ? ~ ~ ~ ~ ? ? ? ? FE ADL ADH OP ~ ~ DATA BUS 3 ~ ~ RESET ADDRESS BUS 2 ~ ~ Oscillator (XIN pin) Stabilization Time tST =65.5mS at 4MHz Reset Process Step tST = 1 fXIN ÷1024 MAIN PROGRAM x 256 Figure 23-2 Timing Diagram after Reset Address Fail Reset The Address Fail Reset is the function to reset the system by checking code access of abnormal and unwished address caused by erroneous program code itself or external noise, which could 110 not be returned to normal operation and would become malfunction state. If the CPU tries to fetch the instruction from ineffective code area or RAM area, the address fail reset is occurred. Please refer to Figure 11-2 for setting address fail option. MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 24. POWER FAIL PROCESSOR The MC80F0424/0432/0448 has an on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable or disable the power fail detect circuitry. Whenever VDD falls close to or below power fail voltage for 100ns, the power fail situation may reset or freeze MCU according to PFDM bit of PFDR. Refer to “Figure 24-1 Power Fail Voltage Detector Register” on page 111. In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Therefore, after final development of user program, this function may be experimented or evaluated. Note: If power fail voltage is selected to 2.4V or 2.7V on below 3V operation, MCU is freezed at all the times. Power Fail Function OTP MASK Enable/Disable PFDEN flag PFDEN flag Level Selection PFS0 bit PFS1 bit Mask option Note: User can select power fail voltage level according to CONFIG register(20FFH) at the FLASH MCU(MC80F0424/ 0432/0448) but must select the power fail voltage level to define PFD option of "Mask Order & Verification Sheet" at the mask chip(MC80C0424/0432/0448), because the power fail voltage level of mask chip is determined according to mask option. PFDR 7 - 6 - 5 - 4 - 3 - R/W R/W 1 0 PFDEN PFDM PFDS Table 24-1 Power fail processor R/W 2 ADDRESS: 0F7H INITIAL VALUE: -----000B Power Fail Status 0: Normal operate 1: Set to “1” if power fail is detected PFD Operation Mode 0 : MCU will be freezed by power fail detection 1 : MCU will be reset by power fail detection * Cautions : Be sure to set bits 3 through 7 to “0”. PFD Enable Bit 0: Power fail detection disable 1: Power fail detection enable Figure 24-1 Power Fail Voltage Detector Register MAR. 2005 Ver 0.2 111 MC80F0424/0432/0448 Preliminary RESET VECTOR PFDS =1 YES NO RAM Clear Initialize RAM Data PFDS = 0 Skip the initial routine Initialize All Ports Initialize Registers Function Execution Figure 24-2 Example S/W of Reset flow by Power fail VDD Internal RESET VPFDMAX VPFDMIN 65.5mS VDD When PFDM = 1 Internal RESET 65.5mS t <65.5mS VDD Internal RESET VPFDMAX VPFDMIN 65.5mS VPFDMAX VPFDMIN Figure 24-3 Power Fail Processor Situations (at 4MHz operation) 112 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 25. FLASH PROGRAMMING The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as security bit. This area is not accessible during normal execution but is reada- CONFIG 7 - 6 - 5 - 4 - 3 - ble and writable during FLASH program / verify mode. The Device Configuration Area register is located at the address 20FFH. 2 1 0 PFS1 PFS0 LOCK ADDRESS: 20FFH INITIAL VALUE: 00H Code Protect (Available FLASH version) 0 : Lock Disable 1 : Lock Enable (main cell read protection) PFD Level Selection 00: PFD = 2.7V 01: PFD = 2.7V 10: PFD = 3.0V 11: PFD = 2.4V Figure 25-1 Device Configuration Area Register 25.1 Lock bit The lock bit exists in Device Configuration Area register. If lock bit is programmed and user tries to read FLASH memory cell, the output data from the data port is 5AH that means the normal pro- tection operation of user program data. Once the lock bit is programmed, the user can’t modify and read the data of user program area. 25.2 Power Fail Detection level The power fail detection provides 3 level of detection, 2.4V, 2.7V and 3.0V. The default level of detection is 2.7V and this level is applied if user does not select the specific level in FLASH pro- MAR. 2005 Ver 0.2 gramming S/W tools. For more information, refer to "24. POWER FAIL PROCESSOR" on page 111 113 ➋ ➎ VDD AVDD GND R67 R65 R63 R61 GND R57 R55 R53 R51 GND R47 R45 R43 R41 GND R37 R35 R33 R31 GND U_Reset GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 J_USERB 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VCC AVDD GND R66 R64 R62 R60 GND R56 R54 R52 R50 GND R46 R44 R42 R40 GND R36 R34 R32 R30 GND U_XOUT GND VDD R70 R72 R74 R76 GND R80 R82 R84 R86 GND R00 R02 R04 R06 GND R10 R12 R14 R16 GND R20 R22 R24 R26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 J_USERA 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VDD R71 R73 R75 R77 GND R81 R83 R85 R87 GND R01 R03 R05 R07 GND R11 R13 R15 R17 GND R21 R23 R25 R27 MAR. 2005 Ver 0.2 114 þ“ à ÃÕŒœ–— ➍ Preliminary MC80F0424/0432/0448 26. Emulator EVA. Board Setting ➏ ➐ ➌ ➊ Preliminary MC80F0424/0432/0448 DIP Switch and VR Setting Before executing the user program, set up the EVA board according to the below configuration. DIP S/W ➊ ➋ Description ON/OFF Setting - This connector is only used for a device over 32 PIN. Used for the MC80F0424/0432/0448. - This connector is only used for a device under 32 PIN. Not used for the MC80F0424/0432/0448. Must be ON position. ON 1 ON : MC80F0424/0432/0448 selection OFF : other MCU selection Eva. select switch 2 3 ON OFF OFF ON Use Eva. VDD ➌ Use User’s AVDD These switches select the AVDD source. ON & OFF : Use Eva. VDD OFF & ON : Use User AVDD AVDD pin select switch This switch select the /Reset source. Normally OFF. EVA. chip can be reset by external user target board. ON : Reset is available by either user target system board or Emulator RESET switch. OFF : Reset the MCU by Emulator RESET switch. Does not work from user target board. This switch select the XOUT signal on/off. Normally OFF. MCU XOUT pin is disconnected internally in the Emulator. Some circumstance user may connect this circuit. ON : Output XOUT signal OFF : Disconnect circuit SW2 4 5 This switch select Eva. B/D Power supply source. MDS MDS ➍ SW3 Normally MDS. This switch select Eva. B/D Power supply source. 1 USER Use MDS Power ➎ SW4 1 2 USER Use User’s Power This switch select the R22 or SXOUT. This switch select the R21 or SXIN. MAR. 2005 Ver 0.2 These switchs select the Normal I/O port(off) or Sub-Clock (on). ON : SXOUT, SXIN selection OFF : R22, R21 selection 115 MC80F0424/0432/0448 DIP S/W ➏ SW5 ➐ 116 Preliminary Description 1 2 These switches select the R33 or XIN 3 4 These switches select the R34 or XOUT 5 6 These switches select the R35 or /Reset - This is External oscillation socket(CAN Type. OSC) ON/OFF Setting This switch select the Normal I/O port(on&off) or special function select(off&on). It is not used for the MC80F0424/0432/ 0448. This is for External Clock(CAN Type. OSC). MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 27. IN-SYSTEM PROGRAMMING (ISP) 27.1 Getting Started / Installation The following section details the procedure for accomplishing the installation procedure. 3. Turn your target B/D power switch ON. Your target B/ D must be configured to enter the ISP mode. 1. Connect the serial(RS-232C) cable between a target board and the COM port of your PC. 4. Run the MagnaChip ISP software. 2. Configure the COM port of your PC as following. Baudrate Data bit Parity Stop bit Flow control 5. Press the Reset Button in the ISP S/W. If the status windows shows a message as "Connected", all the conditions for ISP are provided. 115,200 8 No 1 No 27.2 Basic ISP S/W Information MAR. 2005 Ver 0.2 117 MC80F0424/0432/0448 Preliminary Function Description Load HEX File Load the data from the selected file storage into the memory buffer. Save HEX File Save the current data in your memory buffer to a disk storage by using the Intel Motorolla HEX format. Erase Erase the data in your target MCU before programming it. Blank Check Verify whether or not a device is in an erased or unprogrammed state. Program This button enables you to place new data from the memory buffer into the target device. Read Read the data in the target MCU into the buffer for examination. The checksum will be displayed on the checksum box. Verify Assures that data in the device matches data in the memory buffer. If your device is secured, a verification error is detected. Option Write Progam the configuration data of target MCU. The security locking is performed with this button. Option Set the configuration data of target MCU. The security locking is set with this button. AUTO Erase & Program & Verify. Auto Option Write If selected with check mark, the option write is performed after erasure and write. Edit Buffer Modify the data in the selected address in your buffer memory Fill Buffer Fill the selected area with a data. Goto Display the selected page. OSC. ______ MHz Enter your target system’s oscillator value with discarding below point. Start ______ Starting address End ______ End address Checksum Display the checksum(Hexdecimal) after reading the target device. Com Port Select serial port. Baud Rate Select UART baud rate. Select Device Select target device. Page Up Key Display the previous page of your memory buffer. Page Down Key Display the higher page than the current location. Table 27-1 ISP Function Description 118 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 27.3 Hardware Conditions to Enter the ISP Mode The In-System Programming (ISP) is performed without removing the microcontroller from the target system. The In-System Programming(ISP) facility consists of a series of internal hardware resources coupled with internal firmware through the serial port. The In-System Programming (ISP) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The boot loader can be executed by holding ALEB high, RST/VPP as +9V, and ACLK0 with the OSC. 1.8432MHz. The ISP function uses five pins: TxD0, RxD0, ALEB, ACLK0 and RST/VPP. VDD(+5V) VDD RST/VPP RESET XIN XOUT MC80F0424/0432/0448 +9V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 R47 / TxD0 R46 / RxD0 R45 / ACLK0 R30 ALE VSS Tx Data Rx Data 1.8432MHz VDD X-TAL 2MHz~12MHz Figure 27-1 ISP Configuration Note: Considerations to implement ISP function in a user target board • The ACLK0 must be connected to the specifed oscillator. • Connect the +9V to RESET/Vpp pin directly. • The ALEB pin must be pulled high. • The main clk must be higher than 2MHz. MAR. 2005 Ver 0.2 119 MC80F0424/0432/0448 Preliminary 27.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board partment. The following circuit diagram is for reference use.. 2N2907 1uF DTR + GND VSS VSS + 10kΩ 8.2kΩ + VSS 22Ω 22Ω VSS VDD(+5V) 0.1uF J3 10uF/16V VDD(+5V) VDD VSS VSS 100pF 1uF VDD(+5V) 1 2 3 4 5 6 VSS VSS X1 Vcc J2 RESET/VPP VDD VSS ACLK_CLK MCU_TxD MCU_RxD To MCU + TxD 100Ω 10uF/35V RxD T1IN 11 T2IN 10 12 R1OUT R2OUT 9 1 C1+ + 1uF 3 C14 C2+ + 1uF 5 C2- 22Ω 1 6 2 7 3 8 4 9 5 14 T1OUT 7 T2OUT 13 R1IN 8 R2IN 2 V+ 16 VCC 6 V15 GND 0.1uF From PC CON1 Female DB9 MAX232 1kΩ VDD(+5V) 100pF The ISP software and hardware circuit diagram are provided at www.magnachipmcu.com . To get a ISP B/D, contact to sales de- 22Ω Out * VDD : +4.5 ~ +5.5V * VPP : VDD + 4V Gnd OSC 1.8432MHz VSS VSS VSS External VDD The ragne of VDD must be from 4.5 to 5.5V and ISP function is not supported under 2MHz system clock. If the user supplied VDD is out of range, the external power is needed instead of the target system VDD. For the ISP operation, power consumption required is minimum 30mA. Figure 27-2 Reference ISP Circuit Diagram Figure 27-3 MagnaChip supplied ISP Board 120 MAR. 2005 Ver 0.2 Preliminary MC80F0424/0432/0448 APPENDIX MAR. 2005 Ver 0.2 MC80F0424/0432/0448 A. INSTRUCTION MAP LOW 00000 HIGH 00 00001 01 00010 02 00011 03 00101 05 00110 06 00111 07 01000 08 01001 09 ADC #imm ADC dp ADC dp+X ADC !abs ASL A ASL dp 01010 0A 01011 0B 01100 0C 01101 0D 01110 0E 01111 0F TCALL SETA1 0 .bit BIT dp POP A PUSH A BRK 000 - SET1 dp.bit 001 CLRC “ “ “ SBC #imm SBC dp SBC dp+X SBC !abs ROL A ROL dp TCALL CLRA1 2 .bit COM dp POP X PUSH X BRA rel 010 CLRG “ “ “ CMP #imm CMP dp CMP dp+X CMP !abs LSR A LSR dp TCALL 4 NOT1 M.bit TST dp POP Y PUSH Y PCALL Upage 011 DI “ “ “ OR #imm OR dp OR dp+X OR !abs ROR A ROR dp TCALL 6 OR1 OR1B CMPX dp POP PSW PUSH PSW RET 100 CLRV “ “ “ AND #imm AND dp AND dp+X AND !abs INC A INC dp TCALL AND1 8 AND1B CMPY dp CBNE dp+X TXSP INC X 101 SETC “ “ “ EOR #imm EOR dp EOR dp+X EOR !abs DEC A DEC dp TCALL EOR1 10 EOR1B DBNE dp XMA dp+X TSPX DEC X 110 SETG “ “ “ LDA #imm LDA dp LDA dp+X LDA !abs TXA LDY dp TCALL 12 LDC LDCB LDX dp LDX dp+Y XCN DAS STA dp STA dp+X STA !abs TAX STY dp TCALL 14 STC M.bit STX dp STX dp+Y XAX STOP 111 EI LOW 10000 HIGH 10 BBS BBS A.bit,rel dp.bit,rel 00100 04 “ “ “ LDM dp,#imm 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1A 11011 1B 11100 1C 11101 1D 11110 1E 11111 1F ADC {X} ADC !abs+Y ADC [dp+X] ADC [dp]+Y ASL !abs ASL dp+X TCALL 1 JMP !abs BIT !abs ADDW dp LDX #imm JMP [!abs] TEST !abs SUBW dp LDY #imm JMP [dp] TCLR1 CMPW !abs dp CMPX #imm CALL [dp] 000 BPL rel CLR1 BBC BBC dp.bit A.bit,rel dp.bit,rel 001 BVC rel “ “ “ SBC {X} SBC !abs+Y SBC [dp+X] SBC [dp]+Y ROL !abs ROL dp+X TCALL 3 CALL !abs 010 BCC rel “ “ “ CMP {X} CMP !abs+Y CMP [dp+X] CMP [dp]+Y LSR !abs LSR dp+X TCALL 5 MUL 011 BNE rel “ “ “ OR {X} OR !abs+Y OR [dp+X] OR [dp]+Y ROR !abs ROR dp+X TCALL 7 DBNE Y CMPX !abs LDYA dp CMPY #imm RETI 100 BMI rel “ “ “ AND {X} AND !abs+Y AND [dp+X] AND [dp]+Y INC !abs INC dp+X TCALL 9 DIV CMPY !abs INCW dp INC Y TAY 101 BVS rel “ “ “ EOR {X} EOR !abs+Y EOR [dp+X] EOR [dp]+Y DEC !abs DEC dp+X TCALL 11 XMA {X} XMA dp DECW dp DEC Y TYA 110 BCS rel “ “ “ LDA {X} LDA !abs+Y LDA [dp+X] LDA [dp]+Y LDY !abs LDY dp+X TCALL 13 LDA {X}+ LDX !abs STYA dp XAY DAA 111 BEQ rel “ “ “ STA {X} STA !abs+Y STA [dp+X] STA [dp]+Y STY !abs STY dp+X TCALL 15 STA {X}+ STX !abs CBNE dp XYX NOP MAR. 2005 Ver 0.2 i MC80F0424/0432/0448 B. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION NO. 1 ii MNEMONIC ADC #imm OP BYTE CYCLE CODE NO NO 04 2 2 Add with carry. 2 ADC dp 05 2 3 3 ADC dp + X 06 2 4 4 ADC !abs 07 3 4 5 ADC !abs + Y 15 3 5 6 ADC [ dp + X ] 16 2 6 7 ADC [ dp ] + Y 17 2 6 8 ADC { X } 14 1 3 9 AND #imm AND dp 84 2 2 10 85 2 3 11 AND dp + X 86 2 4 12 AND !abs 87 3 4 13 AND !abs + Y 95 3 5 14 AND [ dp + X ] 96 2 6 15 AND [ dp ] + Y 97 2 6 16 AND { X } 94 1 3 17 ASL A 08 1 2 18 19 ASL dp ASL dp + X 09 19 2 2 4 5 20 ASL !abs 18 3 5 21 CMP #imm 44 2 2 22 CMP dp 45 2 3 23 CMP dp + X 46 2 4 24 CMP !abs 47 3 4 25 CMP !abs + Y 55 3 5 26 CMP [ dp + X ] 56 2 6 27 CMP [ dp ] + Y 57 2 6 28 CMP { X } 54 1 3 29 CMPX #imm 5E 2 2 30 CMPX dp 6C 2 3 31 CMPX !abs 7C 3 4 FLAG NVGBHIZC OPERATION A←(A)+(M)+C NV--H-ZC Logical AND A← (A)∧(M) N-----Z- Arithmetic shift C 7 6 left5 4 3 2 1 0 N-----ZC “0” Compare accumulator contents with memory contents (A) -(M) N-----ZC Compare X contents with memory contents (X)-(M) N-----ZC 32 CMPY #imm 7E 2 2 33 CMPY dp 8C 2 3 34 CMPY !abs 9C 3 4 35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z- 36 DAA DF 1 3 Decimal adjust for addition N-----ZC 37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC 38 DEC A A8 1 2 Decrement N-----Z- 39 DEC dp A9 2 4 40 DEC dp + X B9 2 5 5 41 DEC !abs B8 3 42 DEC X AF 1 2 43 DEC Y BE 1 2 44 DIV 9B 1 12 Compare Y contents with memory contents (Y)-(M) N-----ZC M← (M)-1 N-----Z- Divide : YA / X Q: A, R: Y NV--H-Z- MAR. 2005 Ver 0.2 MC80F0424/0432/0448 NO. MNEMONIC FLAG NVGBHIZC OP BYTE CYCLE OPERATION CODE NO NO A4 2 2 Exclusive OR A5 2 3 A← (A)⊕(M) 45 EOR #imm 46 EOR dp 47 EOR dp + X A6 2 4 48 EOR !abs A7 3 4 49 EOR !abs + Y B5 3 5 50 EOR [ dp + X ] B6 2 6 51 EOR [ dp ] + Y B7 2 6 52 EOR { X } B4 1 3 53 INC A 88 1 2 54 INC dp 89 2 4 N-----Z- Increment N-----ZC M← (M)+1 55 INC dp + X 99 2 5 56 INC !abs 98 3 5 57 INC X 8F 1 2 58 INC Y 9E 1 2 59 LSR A 48 1 2 60 LSR dp 49 2 4 61 LSR dp + X 59 2 5 62 LSR !abs 58 3 5 63 MUL 5B 1 9 Multiply : YA ← Y × A 64 OR #imm 64 2 2 Logical OR N-----Z- Logical shift right 7 6 5 4 3 2 1 0 C N-----ZC “0” N-----Z- A ← (A)∨(M) 65 OR dp 65 2 3 66 OR dp + X 66 2 4 67 OR !abs 67 3 4 68 OR !abs + Y 75 3 5 69 OR [ dp + X ] 76 2 6 70 OR [ dp ] + Y 77 2 6 71 OR { X } 74 1 3 72 ROL A 28 1 2 73 ROL dp 29 2 4 74 ROL dp + X 39 2 5 75 ROL !abs 38 3 5 76 ROR A 68 1 2 77 ROR dp 69 2 4 78 ROR dp + X 79 2 5 79 ROR !abs 78 3 5 80 SBC #imm 24 2 2 81 SBC dp 25 2 3 82 SBC dp + X 26 2 4 83 SBC !abs 27 3 4 84 SBC !abs + Y 35 3 5 85 SBC [ dp + X ] 36 2 6 86 SBC [ dp ] + Y 37 2 6 87 SBC { X } 34 1 3 88 TST dp 4C 2 3 Test memory contents for negative or zero ( dp ) - 00H N-----Z- 89 XCN CE 1 5 Exchange nibbles within the accumulator A7~A4 ↔ A3~A0 N-----Z- MAR. 2005 Ver 0.2 N-----Z- Rotate left through carry C 7 6 5 4 3 2 1 0 N-----ZC Rotate right through carry 7 6 5 4 3 2 1 0 C N-----ZC Subtract with carry A ← ( A ) - ( M ) - ~( C ) NV--HZC iii MC80F0424/0432/0448 2. REGISTER / MEMORY OPERATION NO. iv MNEMONIC OP BYTE CYCLE CODE NO NO C4 2 2 1 LDA #imm 2 LDA dp C5 2 3 3 LDA dp + X C6 2 4 4 LDA !abs C7 3 4 FLAG NVGBHIZC OPERATION Load accumulator A←(M) 5 LDA !abs + Y D5 3 5 6 LDA [ dp + X ] D6 2 6 7 LDA [ dp ] + Y D7 2 6 8 LDA { X } D4 1 3 9 LDA { X }+ DB 1 4 X- register auto-increment : A ← ( M ) , X ← X + 1 10 LDM dp,#imm E4 3 5 Load memory with immediate data : ( M ) ← imm 11 LDX #imm 1E 2 2 Load X-register 12 LDX dp CC 2 3 13 LDX dp + Y CD 2 4 14 LDX !abs DC 3 4 15 LDY #imm 3E 2 2 16 LDY dp C9 2 3 17 LDY dp + X D9 2 4 18 LDY !abs D8 3 4 19 STA dp E5 2 4 20 STA dp + X E6 2 5 21 STA !abs E7 3 5 22 STA !abs + Y F5 3 6 23 STA [ dp + X ] F6 2 7 24 STA [ dp ] + Y F7 2 7 25 STA { X } F4 1 4 N-----Z- X ←(M) -------N-----Z- Load Y-register Y←(M) N-----Z- Store accumulator contents in memory (M)←A -------- 26 STA { X }+ FB 1 4 X- register auto-increment : ( M ) ← A, X ← X + 1 27 STX dp EC 2 4 Store X-register contents in memory 28 STX dp + Y ED 2 5 29 STX !abs FC 3 5 30 STY dp E9 2 4 31 STY dp + X F9 2 5 32 STY !abs F8 3 5 33 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z- 34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z- 35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← sp N-----Z- 36 TXA C8 1 2 Transfer X-register contents to accumulator: A ← X N-----Z- 37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer: sp ← X N-----Z- 38 TYA BF 1 2 Transfer Y-register contents to accumulator: A ← Y N-----Z- 39 XAX EE 1 4 (M)← X -------- Store Y-register contents in memory (M)← Y -------- 40 XAY DE 1 4 Exchange X-register contents with accumulator :X ↔ A -------Exchange Y-register contents with accumulator :Y ↔ A -------- 41 XMA dp BC 2 5 Exchange memory contents with accumulator 42 XMA dp+X AD 2 6 43 XMA {X} BB 1 5 44 XYX FE 1 4 (M)↔A N-----Z- Exchange X-register contents with Y-register : X ↔ Y -------- MAR. 2005 Ver 0.2 MC80F0424/0432/0448 3. 16-BIT OPERATION NO. MNEMONIC OP BYTE CYCLE CODE NO NO OPERATION FLAG NVGBHIZC 1 ADDW dp 1D 2 5 16-Bits add without carry YA ← ( YA ) + ( dp +1 ) ( dp ) NV--H-ZC 2 CMPW dp 5D 2 4 Compare YA contents with memory pair contents : (YA) − (dp+1)(dp) N-----ZC 3 DECW dp BD 2 6 Decrement memory pair ( dp+1)( dp) ← ( dp+1) ( dp) - 1 N-----Z- 4 INCW dp 9D 2 6 Increment memory pair ( dp+1) ( dp) ← ( dp+1) ( dp ) + 1 N-----Z- 5 LDYA dp 7D 2 5 Load YA YA ← ( dp +1 ) ( dp ) N-----Z- 6 STYA dp DD 2 5 Store YA ( dp +1 ) ( dp ) ← YA -------- 7 SUBW dp 3D 2 5 16-Bits substact without carry YA ← ( YA ) - ( dp +1) ( dp) NV--H-ZC 4. BIT MANIPULATION NO. MNEMONIC OP BYTE CYCLE OPERATION CODE NO NO 8B 3 4 Bit AND C-flag : C ← ( C ) ∧ ( M .bit ) FLAG NVGBHIZC -------C 1 AND1 M.bit 2 AND1B M.bit 8B 3 4 Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit ) -------C 3 BIT dp 0C 2 4 Bit test A with memory : MM----Z- 4 BIT !abs 1C 3 5 Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M 6 ) 2 4 Clear bit : ( M.bit ) ← “0” 5 CLR1 dp.bit y1 6 CLRA1 A.bit 2B 2 2 Clear A bit : ( A.bit )← “0” -------- 7 CLRC 20 1 2 Clear C-flag : C ← “0” -------0 -------- 8 CLRG 40 1 2 Clear G-flag : G ← “0” --0----- 9 CLRV 80 1 2 Clear V-flag : V ← “0” -0--0--- 10 -------C EOR1 M.bit AB 3 5 Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit ) 11 EOR1B M.bit AB 3 5 12 LDC M.bit CB 3 4 Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit) -------C Load C-flag : C ← ( M .bit ) -------C 13 LDCB M.bit CB 3 4 Load C-flag with NOT : C ← ~( M .bit ) -------C 14 NOT1 M.bit 4B 3 5 Bit complement : ( M .bit ) ← ~( M .bit ) -------- 15 OR1 M.bit 6B 3 5 Bit OR C-flag : C ← ( C ) ∨ ( M .bit ) -------C 16 OR1B M.bit 6B 3 5 Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit ) -------C 17 SET1 dp.bit x1 2 4 Set bit : ( M.bit ) ← “1” -------- 18 SETA1 A.bit 0B 2 2 Set A bit : ( A.bit ) ← “1” -------- 19 SETC A0 1 2 Set C-flag : C ← “1” -------1 20 SETG C0 1 2 Set G-flag : G ← “1” --1----- 21 STC M.bit EB 3 6 Store C-flag : ( M .bit ) ← C -------- 22 TCLR1 !abs 5C 3 6 Test and clear bits with A : A - ( M ) , ( M ) ← ( M ) ∧ ~( A ) N-----Z- 23 TSET1 !abs 3C 3 6 Test and set bits with A : A-(M), (M)← (M)∨(A) N-----Z- MAR. 2005 Ver 0.2 v MC80F0424/0432/0448 5. BRANCH / JUMP OPERATION NO. OP BYTE CYCLE OPERATION CODE NO NO y2 2 4/6 Branch if bit clear : y3 3 5/7 if ( bit ) = 0 , then pc ← ( pc ) + rel FLAG NVGBHIZC -------- 1 BBC A.bit,rel 2 BBC dp.bit,rel 3 BBS A.bit,rel x2 2 4/6 BBS dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ← ( pc ) + rel -------- 4 vi MNEMONIC Branch if bit set : -------- 5 BCC rel 50 2 2/4 Branch if carry bit clear if ( C ) = 0 , then pc ← ( pc ) + rel 6 BCS rel D0 2 2/4 Branch if carry bit set if ( C ) = 1 , then pc ← ( pc ) + rel -------- 7 BEQ rel F0 2 2/4 Branch if equal if ( Z ) = 1 , then pc ← ( pc ) + rel -------- 8 BMI rel 90 2 2/4 Branch if minus if ( N ) = 1 , then pc ← ( pc ) + rel -------- 9 BNE rel 70 2 2/4 Branch if not equal if ( Z ) = 0 , then pc ← ( pc ) + rel -------- 10 BPL rel 10 2 2/4 Branch if minus if ( N ) = 0 , then pc ← ( pc ) + rel -------- 11 BRA rel 2F 2 4 Branch always pc ← ( pc ) + rel -------- 12 BVC rel 30 2 2/4 Branch if overflow bit clear if (V) = 0 , then pc ← ( pc) + rel -------- 13 BVS rel B0 2 2/4 Branch if overflow bit set if (V) = 1 , then pc ← ( pc ) + rel -------- 14 CALL !abs 3B 3 8 15 CALL [dp] 5F 2 8 16 CBNE dp,rel FD 3 5/7 17 CBNE dp+X,rel 8D 3 6/8 18 DBNE dp,rel AC 3 5/7 Decrement and branch if not equal : 19 DBNE Y,rel 7B 2 4/6 if ( M ) ≠ 0 , then pc ← ( pc ) + rel. 20 Subroutine call M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1, -------if !abs, pc← abs ; if [dp], pcL← ( dp ), pcH← ( dp+1 ) . -------Compare and branch if not equal : if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel. -------- JMP !abs 1B 3 3 21 JMP [!abs] 1F 3 5 22 JMP [dp] 3F 2 4 23 PCALL upage 4F 2 6 U-page call M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ), sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” . -------- 24 TCALL n nA 1 8 Table call : (sp) ←( pcH ), sp ← sp - 1, M(sp) ← ( pcL ),sp ← sp - 1, pcL ← (Table vector L), pcH ← (Table vector H) -------- Unconditional jump pc ← jump address -------- MAR. 2005 Ver 0.2 MC80F0424/0432/0448 6. CONTROL OPERATION & etc. NO. MNEMONIC OP BYTE CYCLE CODE NO NO OPERATION FLAG NVGBHIZC 1 BRK 0F 1 8 Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1, M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0-pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) . 2 DI 60 1 3 Disable interrupts : I ← “0” -----0-- 3 EI E0 1 3 Enable interrupts : I ← “1” -----1-- 4 NOP FF 1 2 No operation -------- 5 POP A 0D 1 4 sp ← sp + 1, A ← M( sp ) 6 sp ← sp + 1, X ← M( sp ) POP X 2D 1 4 7 POP Y 4D 1 4 sp ← sp + 1, Y ← M( sp ) 8 POP PSW 6D 1 4 sp ← sp + 1, PSW ← M( sp ) 9 PUSH A 0E 1 4 M( sp ) ← A , sp ← sp - 1 10 PUSH X 2E 1 4 M( sp ) ← X , sp ← sp - 1 11 PUSH Y 4E 1 4 M( sp ) ← Y , sp ← sp - 1 12 PUSH PSW 6E 1 4 M( sp ) ← PSW , sp ← sp - 1 -------restored -------- 13 RET 6F 1 5 Return from subroutine -------sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( sp ) 14 RETI 7F 1 6 Return from interrupt sp ← sp +1, PSW ← M( sp ), sp ← sp + 1, pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp ) restored 15 STOP EF 1 3 Stop mode ( halt CPU, stop oscillator ) -------- MAR. 2005 Ver 0.2 vii MC80F0424/0432/0448 C. MASK ORDER SHEET Refer to next page. viii MAR. 2005 Ver 0.2 Mask Order & Verification Sheet MC80C04 - MD K : 64SDIP Q : 64MQFP L : 64LQFP 48 : 48K 32 : 32K 24 : 24K Customer should write inside thick line box. 2. Device Information 1. Customer Information Company Name Package 64LQFP MM ) .OTP ROM Size (bytes) DD Mask Data YYYY Order Date Fax: E-mail address: Check Sum 64SDIP ( File Name Application Tel: 64MQFP 24K 32K ( 48K ) Set “00H” in blanked area * PFD Option (48K) 4000 H (32K) 8000 H (24K) C000 H .OTP file 2.7V 2.7V 3.0V Name & Signature: FFFFH 2.4V (Please check mark√ into 3. Marking Specification 24 or 32 or 48 Customer’s logo Customer logo is not required. MC80C04XXX-MD MC80C04XXX-MD YYWW KOREA YYWW KOREA If the customer logo must be used in the special mark, please submit a clean original of the logo. Customer’s part number 4. Delivery Schedule Date Customer sample Risk order Quantity YYYY MM DD YYYY MM DD MagnaChip Confirmation pcs pcs 5. ROM Code Verification Please confirm out verification data. YYYY Verification date: Check sum: Tel: E-mail address: Name & Signature: MM DD YYYY Approval date: MM DD I agree with your verification data and confirm you to make mask set. Fax: Tel: E-mail address: Name & Signature: Fax: )